1 /* $NetBSD: mace.c,v 1.25 2021/08/07 16:19:04 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 2003 Christopher Sekiya
5 * Copyright (c) 2002,2003 Rafal K. Boni
6 * Copyright (c) 2000 Soren S. Jorvang
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the
20 * NetBSD Project. See http://www.NetBSD.org/ for
21 * information about NetBSD.
22 * 4. The name of the author may not be used to endorse or promote products
23 * derived from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37 /*
38 * O2 MACE
39 *
40 * The MACE is weird -- although it is a 32-bit device, writes only seem to
41 * work properly if they are 64-bit-at-once writes (at least, out in ISA
42 * space and probably MEC space -- the PCI stuff seems to be okay with _4).
43 * Therefore, the _8* routines are used even though the top 32 bits are
44 * thrown away.
45 */
46
47 #include <sys/cdefs.h>
48 __KERNEL_RCSID(0, "$NetBSD: mace.c,v 1.25 2021/08/07 16:19:04 thorpej Exp $");
49
50 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <sys/device.h>
53 #include <sys/callout.h>
54 #include <sys/mbuf.h>
55 #include <sys/malloc.h>
56 #include <sys/kernel.h>
57 #include <sys/socket.h>
58 #include <sys/ioctl.h>
59 #include <sys/errno.h>
60 #include <sys/syslog.h>
61
62 #include <uvm/uvm_extern.h>
63
64 #include <sys/bus.h>
65 #include <machine/cpu.h>
66 #include <machine/locore.h>
67 #include <machine/autoconf.h>
68 #include <machine/machtype.h>
69
70 #include <sgimips/mace/macevar.h>
71 #include <sgimips/mace/macereg.h>
72 #include <sgimips/dev/crimevar.h>
73 #include <sgimips/dev/crimereg.h>
74
75 #include "locators.h"
76
77 #define MACE_NINTR 32 /* actually only 8, but interrupts are shared */
78
79 struct {
80 unsigned int irq;
81 unsigned int intrmask;
82 int (*func)(void *);
83 void *arg;
84 struct evcnt evcnt;
85 char evname[32];
86 } maceintrtab[MACE_NINTR];
87
88 struct mace_softc {
89 device_t sc_dev;
90
91 bus_space_tag_t iot;
92 bus_space_handle_t ioh;
93 bus_dma_tag_t dmat; /* 32KB ring buffers, 4KB segments, for ISA */
94 int nsegs;
95 bus_dma_segment_t seg;
96 bus_dmamap_t map;
97
98 void *isa_ringbuffer;
99 };
100
101 static int mace_match(device_t, cfdata_t, void *);
102 static void mace_attach(device_t, device_t, void *);
103 static int mace_print(void *, const char *);
104 static int mace_search(device_t, cfdata_t, const int *, void *);
105
106 CFATTACH_DECL_NEW(mace, sizeof(struct mace_softc),
107 mace_match, mace_attach, NULL, NULL);
108
109 static void mace_isa_bus_mem_init(bus_space_tag_t, void *);
110
111 static struct mips_bus_space mace_isa_mbst;
112 bus_space_tag_t mace_isa_memt = NULL;
113 static int mace_isa_init = 0;
114
115 #if defined(BLINK)
116 static callout_t mace_blink_ch;
117 static void mace_blink(void *);
118 #endif
119
120 static int
mace_match(device_t parent,struct cfdata * match,void * aux)121 mace_match(device_t parent, struct cfdata *match, void *aux)
122 {
123
124 /*
125 * The MACE is in the O2.
126 */
127 if (mach_type == MACH_SGI_IP32)
128 return 1;
129
130 return 0;
131 }
132
133 void
mace_init_bus(void)134 mace_init_bus(void)
135 {
136 if (mace_isa_init == 1)
137 return;
138 mace_isa_init = 1;
139 mace_isa_bus_mem_init(&mace_isa_mbst, NULL);
140 mace_isa_memt = &mace_isa_mbst;
141 }
142
143 static void
mace_attach(device_t parent,device_t self,void * aux)144 mace_attach(device_t parent, device_t self, void *aux)
145 {
146 struct mace_softc *sc = device_private(self);
147 struct mainbus_attach_args *ma = aux;
148 uint32_t scratch;
149
150 sc->sc_dev = self;
151 #ifdef BLINK
152 callout_init(&mace_blink_ch, 0);
153 #endif
154
155 sc->iot = normal_memt; /* for mace registers */
156 sc->dmat = &sgimips_default_bus_dma_tag;
157
158 if (bus_space_map(sc->iot, ma->ma_addr, 0,
159 BUS_SPACE_MAP_LINEAR, &sc->ioh))
160 panic("mace_attach: could not allocate memory\n");
161
162 aprint_normal("\n");
163
164 aprint_debug("%s: isa sts %#"PRIx64"\n", device_xname(self),
165 bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_INT_STATUS));
166 aprint_debug("%s: isa msk %#"PRIx64"\n", device_xname(self),
167 bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_INT_MASK));
168
169 mace_init_bus();
170
171 /*
172 * Turn on most ISA interrupts. These are actually masked and
173 * registered via the CRIME, as the MACE ISA interrupt mask is
174 * really whacky and nigh on impossible to map to a sane autoconfig
175 * scheme. We do, however, turn off the count/compare timer and RTC
176 * interrupts as they are unused and conflict with the PS/2
177 * keyboard and mouse interrupts.
178 */
179
180 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_INT_MASK, 0xffff0aff);
181 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_INT_STATUS, 0);
182
183 /* set up LED for solid green or blink, if that's your fancy */
184 scratch = bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG);
185 scratch |= MACE_ISA_LED_RED;
186 scratch &= ~(MACE_ISA_LED_GREEN);
187 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG, scratch);
188
189 #if defined(BLINK)
190 mace_blink(sc);
191 #endif
192
193 /* Initialize the maceintr elements to sane values */
194 for (scratch = 0; scratch < MACE_NINTR; scratch++) {
195 maceintrtab[scratch].func = NULL;
196 maceintrtab[scratch].irq = 0;
197 }
198
199 config_search(self, NULL,
200 CFARGS(.search = mace_search));
201 }
202
203
204 static int
mace_print(void * aux,const char * pnp)205 mace_print(void *aux, const char *pnp)
206 {
207 struct mace_attach_args *maa = aux;
208
209 if (pnp != 0)
210 return QUIET;
211
212 if (maa->maa_offset != MACECF_OFFSET_DEFAULT)
213 aprint_normal(" offset 0x%lx", maa->maa_offset);
214 if (maa->maa_intr != MACECF_INTR_DEFAULT)
215 aprint_normal(" intr %d", maa->maa_intr);
216 if (maa->maa_offset != MACECF_INTRMASK_DEFAULT)
217 aprint_normal(" intrmask 0x%x", maa->maa_intrmask);
218
219 return UNCONF;
220 }
221
222 static int
mace_search(device_t parent,struct cfdata * cf,const int * ldesc,void * aux)223 mace_search(device_t parent, struct cfdata *cf, const int *ldesc, void *aux)
224 {
225 struct mace_softc *sc = device_private(parent);
226 struct mace_attach_args maa;
227 int tryagain;
228
229 do {
230 maa.maa_offset = cf->cf_loc[MACECF_OFFSET];
231 maa.maa_intr = cf->cf_loc[MACECF_INTR];
232 maa.maa_intrmask = cf->cf_loc[MACECF_INTRMASK];
233 maa.maa_st = normal_memt;
234 maa.maa_sh = sc->ioh; /* XXX */
235 maa.maa_dmat = &sgimips_default_bus_dma_tag;
236 maa.isa_ringbuffer = sc->isa_ringbuffer;
237
238 tryagain = 0;
239 if (config_probe(parent, cf, &maa)) {
240 config_attach(parent, cf, &maa, mace_print, CFARGS_NONE);
241 tryagain = (cf->cf_fstate == FSTATE_STAR);
242 }
243
244 } while (tryagain);
245
246 return 0;
247 }
248
249 void *
mace_intr_establish(int intr,int level,int (* func)(void *),void * arg)250 mace_intr_establish(int intr, int level, int (*func)(void *), void *arg)
251 {
252 int i;
253
254 if (intr < 0 || intr >= 16)
255 panic("invalid interrupt number");
256
257 for (i = 0; i < MACE_NINTR; i++)
258 if (maceintrtab[i].func == NULL) {
259 maceintrtab[i].func = func;
260 maceintrtab[i].arg = arg;
261 maceintrtab[i].irq = (1 << intr);
262 maceintrtab[i].intrmask = level;
263 snprintf(maceintrtab[i].evname,
264 sizeof(maceintrtab[i].evname),
265 "intr %d lv 0x%x", intr, level);
266 evcnt_attach_dynamic(&maceintrtab[i].evcnt,
267 EVCNT_TYPE_INTR, NULL,
268 "mace", maceintrtab[i].evname);
269 break;
270 }
271
272 crime_intr_mask(intr);
273 aprint_debug("mace: established interrupt %d (level %x)\n",
274 intr, level);
275 return (void *)&maceintrtab[i];
276 }
277
278 void
mace_intr_disestablish(void * cookie)279 mace_intr_disestablish(void *cookie)
280 {
281 int intr = -1, level = 0, irq = 0, i;
282
283 for (i = 0; i < MACE_NINTR; i++)
284 if (&maceintrtab[i] == cookie) {
285 evcnt_detach(&maceintrtab[i].evcnt);
286 for (intr = 0;
287 maceintrtab[i].irq == (1 << intr); intr++);
288 level = maceintrtab[i].intrmask;
289 irq = maceintrtab[i].irq;
290
291 maceintrtab[i].irq = 0;
292 maceintrtab[i].intrmask = 0;
293 maceintrtab[i].func = NULL;
294 maceintrtab[i].arg = NULL;
295 memset(&maceintrtab[i].evcnt, 0, sizeof (struct evcnt));
296 memset(&maceintrtab[i].evname, 0,
297 sizeof (maceintrtab[i].evname));
298 break;
299 }
300 if (intr == -1)
301 panic("mace: lost maceintrtab");
302
303 /* do not do an unmask when irq is shared. */
304 for (i = 0; i < MACE_NINTR; i++)
305 if (&maceintrtab[i].func != NULL && maceintrtab[i].irq == irq)
306 break;
307 if (i == MACE_NINTR)
308 crime_intr_unmask(intr);
309 aprint_debug("mace: disestablished interrupt %d (level %x)\n",
310 intr, level);
311 }
312
313 void
mace_intr(int irqs)314 mace_intr(int irqs)
315 {
316 uint64_t isa_irq;
317 int i;
318
319 /* irq 4 is the ISA cascade interrupt. Must handle with care. */
320 if (irqs & (1 << 4)) {
321 isa_irq = mips3_ld(MIPS_PHYS_TO_KSEG1(MACE_BASE
322 + MACE_ISA_INT_STATUS));
323 for (i = 0; i < MACE_NINTR; i++) {
324 if ((maceintrtab[i].irq == (1 << 4)) &&
325 (isa_irq & maceintrtab[i].intrmask)) {
326 (maceintrtab[i].func)(maceintrtab[i].arg);
327 maceintrtab[i].evcnt.ev_count++;
328 }
329 }
330 irqs &= ~(1 << 4);
331 }
332
333 for (i = 0; i < MACE_NINTR; i++)
334 if ((irqs & maceintrtab[i].irq)) {
335 (maceintrtab[i].func)(maceintrtab[i].arg);
336 maceintrtab[i].evcnt.ev_count++;
337 }
338 }
339
340 #if defined(BLINK)
341 static void
mace_blink(void * self)342 mace_blink(void *self)
343 {
344 struct mace_softc *sc = device_private(self);
345 register int s;
346 int value;
347
348 s = splhigh();
349 value = bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG);
350 value ^= MACE_ISA_LED_GREEN;
351 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG, value);
352 splx(s);
353 /*
354 * Blink rate is:
355 * full cycle every second if completely idle (loadav = 0)
356 * full cycle every 2 seconds if loadav = 1
357 * full cycle every 3 seconds if loadav = 2
358 * etc.
359 */
360 s = (((averunnable.ldavg[0] + FSCALE) * hz) >> (FSHIFT + 1));
361 callout_reset(&mace_blink_ch, s, mace_blink, sc);
362
363 }
364 #endif
365
366 #define CHIP mace_isa
367 #define CHIP_MEM /* defined */
368 #define CHIP_ALIGN_STRIDE 8
369 #define CHIP_ACCESS_SIZE 8
370 #define CHIP_W1_BUS_START(v) 0x00000000UL
371 #define CHIP_W1_BUS_END(v) 0xffffffffUL
372 #define CHIP_W1_SYS_START(v) 0x00000000UL
373 #define CHIP_W1_SYS_END(v) 0xffffffffUL
374
375 #include <mips/mips/bus_space_alignstride_chipdep.c>
376