1 /* $NetBSD: display_mode_structs.h,v 1.2 2021/12/18 23:45:04 riastradh Exp $ */ 2 3 /* 4 * Copyright 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 #ifndef __DISPLAY_MODE_STRUCTS_H__ 28 #define __DISPLAY_MODE_STRUCTS_H__ 29 30 #define MAX_CLOCK_LIMIT_STATES 8 31 32 typedef struct _vcs_dpi_voltage_scaling_st voltage_scaling_st; 33 typedef struct _vcs_dpi_soc_bounding_box_st soc_bounding_box_st; 34 typedef struct _vcs_dpi_ip_params_st ip_params_st; 35 typedef struct _vcs_dpi_display_pipe_source_params_st display_pipe_source_params_st; 36 typedef struct _vcs_dpi_display_output_params_st display_output_params_st; 37 typedef struct _vcs_dpi_scaler_ratio_depth_st scaler_ratio_depth_st; 38 typedef struct _vcs_dpi_scaler_taps_st scaler_taps_st; 39 typedef struct _vcs_dpi_display_pipe_dest_params_st display_pipe_dest_params_st; 40 typedef struct _vcs_dpi_display_pipe_params_st display_pipe_params_st; 41 typedef struct _vcs_dpi_display_clocks_and_cfg_st display_clocks_and_cfg_st; 42 typedef struct _vcs_dpi_display_e2e_pipe_params_st display_e2e_pipe_params_st; 43 typedef struct _vcs_dpi_display_data_rq_misc_params_st display_data_rq_misc_params_st; 44 typedef struct _vcs_dpi_display_data_rq_sizing_params_st display_data_rq_sizing_params_st; 45 typedef struct _vcs_dpi_display_data_rq_dlg_params_st display_data_rq_dlg_params_st; 46 typedef struct _vcs_dpi_display_rq_dlg_params_st display_rq_dlg_params_st; 47 typedef struct _vcs_dpi_display_rq_sizing_params_st display_rq_sizing_params_st; 48 typedef struct _vcs_dpi_display_rq_misc_params_st display_rq_misc_params_st; 49 typedef struct _vcs_dpi_display_rq_params_st display_rq_params_st; 50 typedef struct _vcs_dpi_display_dlg_regs_st display_dlg_regs_st; 51 typedef struct _vcs_dpi_display_ttu_regs_st display_ttu_regs_st; 52 typedef struct _vcs_dpi_display_data_rq_regs_st display_data_rq_regs_st; 53 typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st; 54 typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st; 55 typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st; 56 57 struct _vcs_dpi_voltage_scaling_st { 58 int state; 59 double dscclk_mhz; 60 double dcfclk_mhz; 61 double socclk_mhz; 62 double phyclk_d18_mhz; 63 double dram_speed_mts; 64 double fabricclk_mhz; 65 double dispclk_mhz; 66 double phyclk_mhz; 67 double dppclk_mhz; 68 double dtbclk_mhz; 69 }; 70 71 struct _vcs_dpi_soc_bounding_box_st { 72 double sr_exit_time_us; 73 double sr_enter_plus_exit_time_us; 74 double urgent_latency_us; 75 double urgent_latency_pixel_data_only_us; 76 double urgent_latency_pixel_mixed_with_vm_data_us; 77 double urgent_latency_vm_data_only_us; 78 double writeback_latency_us; 79 double ideal_dram_bw_after_urgent_percent; 80 double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly 81 double pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm; 82 double pct_ideal_dram_sdp_bw_after_urgent_vm_only; 83 double max_avg_sdp_bw_use_normal_percent; 84 double max_avg_dram_bw_use_normal_percent; 85 unsigned int max_request_size_bytes; 86 double downspread_percent; 87 double dram_page_open_time_ns; 88 double dram_rw_turnaround_time_ns; 89 double dram_return_buffer_per_channel_bytes; 90 double dram_channel_width_bytes; 91 double fabric_datapath_to_dcn_data_return_bytes; 92 double dcn_downspread_percent; 93 double dispclk_dppclk_vco_speed_mhz; 94 double dfs_vco_period_ps; 95 unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes; 96 unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes; 97 unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes; 98 unsigned int round_trip_ping_latency_dcfclk_cycles; 99 unsigned int urgent_out_of_order_return_per_channel_bytes; 100 unsigned int channel_interleave_bytes; 101 unsigned int num_banks; 102 unsigned int num_chans; 103 unsigned int vmm_page_size_bytes; 104 unsigned int hostvm_min_page_size_bytes; 105 unsigned int gpuvm_min_page_size_bytes; 106 double dram_clock_change_latency_us; 107 double dummy_pstate_latency_us; 108 double writeback_dram_clock_change_latency_us; 109 unsigned int return_bus_width_bytes; 110 unsigned int voltage_override; 111 double xfc_bus_transport_time_us; 112 double xfc_xbuf_latency_tolerance_us; 113 int use_urgent_burst_bw; 114 unsigned int num_states; 115 struct _vcs_dpi_voltage_scaling_st clock_limits[MAX_CLOCK_LIMIT_STATES]; 116 bool do_urgent_latency_adjustment; 117 double urgent_latency_adjustment_fabric_clock_component_us; 118 double urgent_latency_adjustment_fabric_clock_reference_mhz; 119 bool disable_dram_clock_change_vactive_support; 120 }; 121 122 struct _vcs_dpi_ip_params_st { 123 bool gpuvm_enable; 124 bool hostvm_enable; 125 unsigned int gpuvm_max_page_table_levels; 126 unsigned int hostvm_max_page_table_levels; 127 unsigned int hostvm_cached_page_table_levels; 128 unsigned int pte_group_size_bytes; 129 unsigned int max_inter_dcn_tile_repeaters; 130 unsigned int num_dsc; 131 unsigned int odm_capable; 132 unsigned int rob_buffer_size_kbytes; 133 unsigned int det_buffer_size_kbytes; 134 unsigned int dpte_buffer_size_in_pte_reqs_luma; 135 unsigned int dpte_buffer_size_in_pte_reqs_chroma; 136 unsigned int pde_proc_buffer_size_64k_reqs; 137 unsigned int dpp_output_buffer_pixels; 138 unsigned int opp_output_buffer_lines; 139 unsigned int pixel_chunk_size_kbytes; 140 unsigned char pte_enable; 141 unsigned int pte_chunk_size_kbytes; 142 unsigned int meta_chunk_size_kbytes; 143 unsigned int writeback_chunk_size_kbytes; 144 unsigned int line_buffer_size_bits; 145 unsigned int max_line_buffer_lines; 146 unsigned int writeback_luma_buffer_size_kbytes; 147 unsigned int writeback_chroma_buffer_size_kbytes; 148 unsigned int writeback_chroma_line_buffer_width_pixels; 149 150 unsigned int writeback_interface_buffer_size_kbytes; 151 unsigned int writeback_line_buffer_buffer_size; 152 153 unsigned int writeback_10bpc420_supported; 154 double writeback_max_hscl_ratio; 155 double writeback_max_vscl_ratio; 156 double writeback_min_hscl_ratio; 157 double writeback_min_vscl_ratio; 158 unsigned int writeback_max_hscl_taps; 159 unsigned int writeback_max_vscl_taps; 160 unsigned int writeback_line_buffer_luma_buffer_size; 161 unsigned int writeback_line_buffer_chroma_buffer_size; 162 163 unsigned int max_page_table_levels; 164 unsigned int max_num_dpp; 165 unsigned int max_num_otg; 166 unsigned int cursor_chunk_size; 167 unsigned int cursor_buffer_size; 168 unsigned int max_num_wb; 169 unsigned int max_dchub_pscl_bw_pix_per_clk; 170 unsigned int max_pscl_lb_bw_pix_per_clk; 171 unsigned int max_lb_vscl_bw_pix_per_clk; 172 unsigned int max_vscl_hscl_bw_pix_per_clk; 173 double max_hscl_ratio; 174 double max_vscl_ratio; 175 unsigned int hscl_mults; 176 unsigned int vscl_mults; 177 unsigned int max_hscl_taps; 178 unsigned int max_vscl_taps; 179 unsigned int xfc_supported; 180 unsigned int ptoi_supported; 181 unsigned int gfx7_compat_tiling_supported; 182 183 bool odm_combine_4to1_supported; 184 bool dynamic_metadata_vm_enabled; 185 unsigned int max_num_hdmi_frl_outputs; 186 187 unsigned int xfc_fill_constant_bytes; 188 double dispclk_ramp_margin_percent; 189 double xfc_fill_bw_overhead_percent; 190 double underscan_factor; 191 unsigned int min_vblank_lines; 192 unsigned int dppclk_delay_subtotal; 193 unsigned int dispclk_delay_subtotal; 194 unsigned int dcfclk_cstate_latency; 195 unsigned int dppclk_delay_scl; 196 unsigned int dppclk_delay_scl_lb_only; 197 unsigned int dppclk_delay_cnvc_formatter; 198 unsigned int dppclk_delay_cnvc_cursor; 199 unsigned int is_line_buffer_bpp_fixed; 200 unsigned int line_buffer_fixed_bpp; 201 unsigned int dcc_supported; 202 203 unsigned int IsLineBufferBppFixed; 204 unsigned int LineBufferFixedBpp; 205 unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one; 206 unsigned int bug_forcing_LC_req_same_size_fixed; 207 }; 208 209 struct _vcs_dpi_display_xfc_params_st { 210 double xfc_tslv_vready_offset_us; 211 double xfc_tslv_vupdate_width_us; 212 double xfc_tslv_vupdate_offset_us; 213 int xfc_slv_chunk_size_bytes; 214 }; 215 216 struct _vcs_dpi_display_pipe_source_params_st { 217 int source_format; 218 unsigned char dcc; 219 unsigned int dcc_rate; 220 unsigned int dcc_rate_chroma; 221 unsigned char dcc_use_global; 222 unsigned char vm; 223 bool gpuvm; // gpuvm enabled 224 bool hostvm; // hostvm enabled 225 bool gpuvm_levels_force_en; 226 unsigned int gpuvm_levels_force; 227 bool hostvm_levels_force_en; 228 unsigned int hostvm_levels_force; 229 int source_scan; 230 int sw_mode; 231 int macro_tile_size; 232 unsigned int surface_width_y; 233 unsigned int surface_height_y; 234 unsigned int surface_width_c; 235 unsigned int surface_height_c; 236 unsigned int viewport_width; 237 unsigned int viewport_height; 238 unsigned int viewport_y_y; 239 unsigned int viewport_y_c; 240 unsigned int viewport_width_c; 241 unsigned int viewport_height_c; 242 unsigned int data_pitch; 243 unsigned int data_pitch_c; 244 unsigned int meta_pitch; 245 unsigned int meta_pitch_c; 246 unsigned int cur0_src_width; 247 int cur0_bpp; 248 unsigned int cur1_src_width; 249 int cur1_bpp; 250 int num_cursors; 251 unsigned char is_hsplit; 252 unsigned char dynamic_metadata_enable; 253 unsigned int dynamic_metadata_lines_before_active; 254 unsigned int dynamic_metadata_xmit_bytes; 255 unsigned int hsplit_grp; 256 unsigned char xfc_enable; 257 unsigned char xfc_slave; 258 unsigned char immediate_flip; 259 struct _vcs_dpi_display_xfc_params_st xfc_params; 260 //for vstartuplines calculation freesync 261 unsigned char v_total_min; 262 unsigned char v_total_max; 263 }; 264 struct writeback_st { 265 int wb_src_height; 266 int wb_src_width; 267 int wb_dst_width; 268 int wb_dst_height; 269 int wb_pixel_format; 270 int wb_htaps_luma; 271 int wb_vtaps_luma; 272 int wb_htaps_chroma; 273 int wb_vtaps_chroma; 274 double wb_hratio; 275 double wb_vratio; 276 }; 277 278 struct _vcs_dpi_display_output_params_st { 279 int dp_lanes; 280 double output_bpp; 281 int dsc_enable; 282 int wb_enable; 283 int num_active_wb; 284 int output_bpc; 285 int output_type; 286 int output_format; 287 int dsc_slices; 288 int max_audio_sample_rate; 289 struct writeback_st wb; 290 }; 291 292 struct _vcs_dpi_scaler_ratio_depth_st { 293 double hscl_ratio; 294 double vscl_ratio; 295 double hscl_ratio_c; 296 double vscl_ratio_c; 297 double vinit; 298 double vinit_c; 299 double vinit_bot; 300 double vinit_bot_c; 301 int lb_depth; 302 int scl_enable; 303 }; 304 305 struct _vcs_dpi_scaler_taps_st { 306 unsigned int htaps; 307 unsigned int vtaps; 308 unsigned int htaps_c; 309 unsigned int vtaps_c; 310 }; 311 312 struct _vcs_dpi_display_pipe_dest_params_st { 313 unsigned int recout_width; 314 unsigned int recout_height; 315 unsigned int full_recout_width; 316 unsigned int full_recout_height; 317 unsigned int hblank_start; 318 unsigned int hblank_end; 319 unsigned int vblank_start; 320 unsigned int vblank_end; 321 unsigned int htotal; 322 unsigned int vtotal; 323 unsigned int vactive; 324 unsigned int hactive; 325 unsigned int vstartup_start; 326 unsigned int vupdate_offset; 327 unsigned int vupdate_width; 328 unsigned int vready_offset; 329 unsigned char interlaced; 330 unsigned char embedded; 331 double pixel_rate_mhz; 332 unsigned char synchronized_vblank_all_planes; 333 unsigned char otg_inst; 334 unsigned int odm_combine; 335 unsigned char use_maximum_vstartup; 336 unsigned int vtotal_max; 337 unsigned int vtotal_min; 338 }; 339 340 struct _vcs_dpi_display_pipe_params_st { 341 display_pipe_source_params_st src; 342 display_pipe_dest_params_st dest; 343 scaler_ratio_depth_st scale_ratio_depth; 344 scaler_taps_st scale_taps; 345 }; 346 347 struct _vcs_dpi_display_clocks_and_cfg_st { 348 int voltage; 349 double dppclk_mhz; 350 double refclk_mhz; 351 double dispclk_mhz; 352 double dcfclk_mhz; 353 double socclk_mhz; 354 }; 355 356 struct _vcs_dpi_display_e2e_pipe_params_st { 357 display_pipe_params_st pipe; 358 display_output_params_st dout; 359 display_clocks_and_cfg_st clks_cfg; 360 }; 361 362 struct _vcs_dpi_display_data_rq_misc_params_st { 363 unsigned int full_swath_bytes; 364 unsigned int stored_swath_bytes; 365 unsigned int blk256_height; 366 unsigned int blk256_width; 367 unsigned int req_height; 368 unsigned int req_width; 369 }; 370 371 struct _vcs_dpi_display_data_rq_sizing_params_st { 372 unsigned int chunk_bytes; 373 unsigned int min_chunk_bytes; 374 unsigned int meta_chunk_bytes; 375 unsigned int min_meta_chunk_bytes; 376 unsigned int mpte_group_bytes; 377 unsigned int dpte_group_bytes; 378 }; 379 380 struct _vcs_dpi_display_data_rq_dlg_params_st { 381 unsigned int swath_width_ub; 382 unsigned int swath_height; 383 unsigned int req_per_swath_ub; 384 unsigned int meta_pte_bytes_per_frame_ub; 385 unsigned int dpte_req_per_row_ub; 386 unsigned int dpte_groups_per_row_ub; 387 unsigned int dpte_row_height; 388 unsigned int dpte_bytes_per_row_ub; 389 unsigned int meta_chunks_per_row_ub; 390 unsigned int meta_req_per_row_ub; 391 unsigned int meta_row_height; 392 unsigned int meta_bytes_per_row_ub; 393 }; 394 395 struct _vcs_dpi_display_rq_dlg_params_st { 396 display_data_rq_dlg_params_st rq_l; 397 display_data_rq_dlg_params_st rq_c; 398 }; 399 400 struct _vcs_dpi_display_rq_sizing_params_st { 401 display_data_rq_sizing_params_st rq_l; 402 display_data_rq_sizing_params_st rq_c; 403 }; 404 405 struct _vcs_dpi_display_rq_misc_params_st { 406 display_data_rq_misc_params_st rq_l; 407 display_data_rq_misc_params_st rq_c; 408 }; 409 410 struct _vcs_dpi_display_rq_params_st { 411 unsigned char yuv420; 412 unsigned char yuv420_10bpc; 413 unsigned char rgbe_alpha; 414 display_rq_misc_params_st misc; 415 display_rq_sizing_params_st sizing; 416 display_rq_dlg_params_st dlg; 417 }; 418 419 struct _vcs_dpi_display_dlg_regs_st { 420 unsigned int refcyc_h_blank_end; 421 unsigned int dlg_vblank_end; 422 unsigned int min_dst_y_next_start; 423 unsigned int refcyc_per_htotal; 424 unsigned int refcyc_x_after_scaler; 425 unsigned int dst_y_after_scaler; 426 unsigned int dst_y_prefetch; 427 unsigned int dst_y_per_vm_vblank; 428 unsigned int dst_y_per_row_vblank; 429 unsigned int dst_y_per_vm_flip; 430 unsigned int dst_y_per_row_flip; 431 unsigned int ref_freq_to_pix_freq; 432 unsigned int vratio_prefetch; 433 unsigned int vratio_prefetch_c; 434 unsigned int refcyc_per_pte_group_vblank_l; 435 unsigned int refcyc_per_pte_group_vblank_c; 436 unsigned int refcyc_per_meta_chunk_vblank_l; 437 unsigned int refcyc_per_meta_chunk_vblank_c; 438 unsigned int refcyc_per_pte_group_flip_l; 439 unsigned int refcyc_per_pte_group_flip_c; 440 unsigned int refcyc_per_meta_chunk_flip_l; 441 unsigned int refcyc_per_meta_chunk_flip_c; 442 unsigned int dst_y_per_pte_row_nom_l; 443 unsigned int dst_y_per_pte_row_nom_c; 444 unsigned int refcyc_per_pte_group_nom_l; 445 unsigned int refcyc_per_pte_group_nom_c; 446 unsigned int dst_y_per_meta_row_nom_l; 447 unsigned int dst_y_per_meta_row_nom_c; 448 unsigned int refcyc_per_meta_chunk_nom_l; 449 unsigned int refcyc_per_meta_chunk_nom_c; 450 unsigned int refcyc_per_line_delivery_pre_l; 451 unsigned int refcyc_per_line_delivery_pre_c; 452 unsigned int refcyc_per_line_delivery_l; 453 unsigned int refcyc_per_line_delivery_c; 454 unsigned int chunk_hdl_adjust_cur0; 455 unsigned int chunk_hdl_adjust_cur1; 456 unsigned int vready_after_vcount0; 457 unsigned int dst_y_offset_cur0; 458 unsigned int dst_y_offset_cur1; 459 unsigned int xfc_reg_transfer_delay; 460 unsigned int xfc_reg_precharge_delay; 461 unsigned int xfc_reg_remote_surface_flip_latency; 462 unsigned int xfc_reg_prefetch_margin; 463 unsigned int dst_y_delta_drq_limit; 464 unsigned int refcyc_per_vm_group_vblank; 465 unsigned int refcyc_per_vm_group_flip; 466 unsigned int refcyc_per_vm_req_vblank; 467 unsigned int refcyc_per_vm_req_flip; 468 unsigned int refcyc_per_vm_dmdata; 469 }; 470 471 struct _vcs_dpi_display_ttu_regs_st { 472 unsigned int qos_level_low_wm; 473 unsigned int qos_level_high_wm; 474 unsigned int min_ttu_vblank; 475 unsigned int qos_level_flip; 476 unsigned int refcyc_per_req_delivery_l; 477 unsigned int refcyc_per_req_delivery_c; 478 unsigned int refcyc_per_req_delivery_cur0; 479 unsigned int refcyc_per_req_delivery_cur1; 480 unsigned int refcyc_per_req_delivery_pre_l; 481 unsigned int refcyc_per_req_delivery_pre_c; 482 unsigned int refcyc_per_req_delivery_pre_cur0; 483 unsigned int refcyc_per_req_delivery_pre_cur1; 484 unsigned int qos_level_fixed_l; 485 unsigned int qos_level_fixed_c; 486 unsigned int qos_level_fixed_cur0; 487 unsigned int qos_level_fixed_cur1; 488 unsigned int qos_ramp_disable_l; 489 unsigned int qos_ramp_disable_c; 490 unsigned int qos_ramp_disable_cur0; 491 unsigned int qos_ramp_disable_cur1; 492 }; 493 494 struct _vcs_dpi_display_data_rq_regs_st { 495 unsigned int chunk_size; 496 unsigned int min_chunk_size; 497 unsigned int meta_chunk_size; 498 unsigned int min_meta_chunk_size; 499 unsigned int dpte_group_size; 500 unsigned int mpte_group_size; 501 unsigned int swath_height; 502 unsigned int pte_row_height_linear; 503 }; 504 505 struct _vcs_dpi_display_rq_regs_st { 506 display_data_rq_regs_st rq_regs_l; 507 display_data_rq_regs_st rq_regs_c; 508 unsigned int drq_expansion_mode; 509 unsigned int prq_expansion_mode; 510 unsigned int mrq_expansion_mode; 511 unsigned int crq_expansion_mode; 512 unsigned int plane1_base_address; 513 }; 514 515 struct _vcs_dpi_display_dlg_sys_params_st { 516 double t_mclk_wm_us; 517 double t_urg_wm_us; 518 double t_sr_wm_us; 519 double t_extra_us; 520 double mem_trip_us; 521 double t_srx_delay_us; 522 double deepsleep_dcfclk_mhz; 523 double total_flip_bw; 524 unsigned int total_flip_bytes; 525 }; 526 527 struct _vcs_dpi_display_arb_params_st { 528 int max_req_outstanding; 529 int min_req_outstanding; 530 int sat_level_us; 531 }; 532 533 #endif /*__DISPLAY_MODE_STRUCTS_H__*/ 534