1 /* $NetBSD: mha.c,v 1.58 2022/05/26 14:33:29 tsutsui Exp $ */
2
3 /*-
4 * Copyright (c) 1996-1999 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Charles M. Hannum, Masaru Oki, Takumi Nakamura, Masanobu Saitoh and
9 * Minoura Makoto.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*-
34 * Copyright (c) 1994 Jarle Greipsland
35 * All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 * 1. Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * 2. Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in the
44 * documentation and/or other materials provided with the distribution.
45 * 3. The name of the author may not be used to endorse or promote products
46 * derived from this software without specific prior written permission.
47 *
48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
50 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
51 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
52 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
53 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
54 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
56 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
57 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
58 * POSSIBILITY OF SUCH DAMAGE.
59 */
60
61 #include <sys/cdefs.h>
62 __KERNEL_RCSID(0, "$NetBSD: mha.c,v 1.58 2022/05/26 14:33:29 tsutsui Exp $");
63
64 #include "opt_ddb.h"
65
66 /* Synchronous data transfers? */
67 #define SPC_USE_SYNCHRONOUS 0
68 #define SPC_SYNC_REQ_ACK_OFS 8
69
70 /* Default DMA mode? */
71 #define MHA_DMA_LIMIT_XFER 1
72 #define MHA_DMA_BURST_XFER 1
73 #define MHA_DMA_SHORT_BUS_CYCLE 1
74
75 #define MHA_DMA_DATAIN (0 | (MHA_DMA_LIMIT_XFER << 1) \
76 | (MHA_DMA_BURST_XFER << 2) \
77 | (MHA_DMA_SHORT_BUS_CYCLE << 3))
78 #define MHA_DMA_DATAOUT (1 | (MHA_DMA_LIMIT_XFER << 1) \
79 | (MHA_DMA_BURST_XFER << 2) \
80 | (MHA_DMA_SHORT_BUS_CYCLE << 3))
81
82 /* Include debug functions? At the end of this file there are a bunch of
83 * functions that will print out various information regarding queued SCSI
84 * commands, driver state and chip contents. You can call them from the
85 * kernel debugger. If you set SPC_DEBUG to 0 they are not included (the
86 * kernel uses less memory) but you lose the debugging facilities.
87 */
88 #define SPC_DEBUG 0
89
90 /* End of customizable parameters */
91
92 /*
93 * MB86601A SCSI Protocol Controller (SPC) routines for MANKAI Mach-2
94 */
95
96 #include <sys/types.h>
97 #include <sys/param.h>
98 #include <sys/systm.h>
99 #include <sys/kernel.h>
100 #include <sys/errno.h>
101 #include <sys/ioctl.h>
102 #include <sys/device.h>
103 #include <sys/buf.h>
104 #include <sys/proc.h>
105 #include <sys/queue.h>
106
107 #include <machine/bus.h>
108
109 #include <dev/scsipi/scsi_spc.h>
110 #include <dev/scsipi/scsi_all.h>
111 #include <dev/scsipi/scsipi_all.h>
112 #include <dev/scsipi/scsi_message.h>
113 #include <dev/scsipi/scsiconf.h>
114
115 #include <x68k/x68k/iodevice.h>
116 #include <x68k/dev/mb86601reg.h>
117 #include <x68k/dev/mhavar.h>
118 #include <x68k/dev/intiovar.h>
119 #include <x68k/dev/scsiromvar.h>
120
121 #include "ioconf.h"
122
123 #if 0
124 #define WAIT {if (sc->sc_pc[2]) {printf("[W_%d", __LINE__); while (sc->sc_pc[2] & 0x40);printf("]");}}
125 #else
126 #define WAIT {while (sc->sc_pc[2] & 0x40);}
127 #endif
128
129 #define SSR (sc->sc_pc[2])
130 #define SS_IREQUEST 0x80
131 #define SS_BUSY 0x40
132 #define SS_DREG_FULL 0x02
133
134 #define NSR (sc->sc_pc[3])
135
136 #define SIR (sc->sc_pc[4])
137
138 #define CMR (sc->sc_pc[5])
139 #define CMD_SEL_AND_CMD 0x00
140 #define CMD_SELECT 0x09
141 #define CMD_SET_ATN 0x0a
142 #define CMD_RESET_ATN 0x0b
143 #define CMD_RESET_ACK 0x0d
144 #define CMD_SEND_FROM_MPU 0x10
145 #define CMD_SEND_FROM_DMA 0x11
146 #define CMD_RECEIVE_TO_MPU 0x12
147 #define CMD_RECEIVE_TO_DMA 0x13
148 #define CMD_RECEIVE_MSG 0x1a
149 #define CMD_RECEIVE_STS 0x1c
150 #define CMD_SOFT_RESET 0x40
151 #define CMD_SCSI_RESET 0x42
152 #define CMD_SET_UP_REG 0x43
153
154 #define SCR (sc->sc_pc[11])
155
156 #define TMR (sc->sc_pc[12])
157 #define TM_SYNC 0x80
158 #define TM_ASYNC 0x00
159
160 #define WAR (sc->sc_pc[15])
161 #define WA_MCSBUFWIN 0x00
162 #define WA_UPMWIN 0x80
163 #define WA_INITWIN 0xc0
164
165 #define MBR (sc->sc_pc[15])
166
167 #define ISCSR (sc->sc_ps[2])
168
169 #define CCR (sc->sc_pcx[0])
170 #define OIR (sc->sc_pcx[1])
171 #define AMR (sc->sc_pcx[2])
172 #define SMR (sc->sc_pcx[3])
173 #define SRR (sc->sc_pcx[4])
174 #define STR (sc->sc_pcx[5])
175 #define RTR (sc->sc_pcx[6])
176 #define ATR (sc->sc_pcx[7])
177 #define PER (sc->sc_pcx[8])
178 #define IER (sc->sc_pcx[9])
179 #define IE_ALL 0xBF
180
181 #define GLR (sc->sc_pcx[10])
182 #define DMR (sc->sc_pcx[11])
183 #define IMR (sc->sc_pcx[12])
184
185 #ifndef DDB
186 #define Debugger() panic("should call debugger here (mha.c)")
187 #endif /* ! DDB */
188
189
190 #if SPC_DEBUG
191 #define SPC_SHOWACBS 0x01
192 #define SPC_SHOWINTS 0x02
193 #define SPC_SHOWCMDS 0x04
194 #define SPC_SHOWMISC 0x08
195 #define SPC_SHOWTRAC 0x10
196 #define SPC_SHOWSTART 0x20
197 #define SPC_SHOWPHASE 0x40
198 #define SPC_SHOWDMA 0x80
199 #define SPC_SHOWCCMDS 0x100
200 #define SPC_SHOWMSGS 0x200
201 #define SPC_DOBREAK 0x400
202
203 int mha_debug =
204 #if 0
205 0x7FF;
206 #else
207 SPC_SHOWSTART|SPC_SHOWTRAC;
208 #endif
209
210
211 #define SPC_ACBS(str) do {if (mha_debug & SPC_SHOWACBS) printf str;} while (0)
212 #define SPC_MISC(str) do {if (mha_debug & SPC_SHOWMISC) printf str;} while (0)
213 #define SPC_INTS(str) do {if (mha_debug & SPC_SHOWINTS) printf str;} while (0)
214 #define SPC_TRACE(str) do {if (mha_debug & SPC_SHOWTRAC) printf str;} while (0)
215 #define SPC_CMDS(str) do {if (mha_debug & SPC_SHOWCMDS) printf str;} while (0)
216 #define SPC_START(str) do {if (mha_debug & SPC_SHOWSTART) printf str;}while (0)
217 #define SPC_PHASE(str) do {if (mha_debug & SPC_SHOWPHASE) printf str;}while (0)
218 #define SPC_DMA(str) do {if (mha_debug & SPC_SHOWDMA) printf str;}while (0)
219 #define SPC_MSGS(str) do {if (mha_debug & SPC_SHOWMSGS) printf str;}while (0)
220 #define SPC_BREAK() do {if ((mha_debug & SPC_DOBREAK) != 0) Debugger();} while (0)
221 #define SPC_ASSERT(x) do {if (x) {} else {printf("%s at line %d: assertion failed\n", device_xname(sc->sc_dev), __LINE__); Debugger();}} while (0)
222 #else
223 #define SPC_ACBS(str)
224 #define SPC_MISC(str)
225 #define SPC_INTS(str)
226 #define SPC_TRACE(str)
227 #define SPC_CMDS(str)
228 #define SPC_START(str)
229 #define SPC_PHASE(str)
230 #define SPC_DMA(str)
231 #define SPC_MSGS(str)
232 #define SPC_BREAK()
233 #define SPC_ASSERT(x)
234 #endif
235
236 int mhamatch(device_t, cfdata_t, void *);
237 void mhaattach(device_t, device_t, void *);
238 void mhaselect(struct mha_softc *, u_char, u_char, u_char *, u_char);
239 void mha_scsi_reset(struct mha_softc *);
240 void mha_reset(struct mha_softc *);
241 void mha_free_acb(struct mha_softc *, struct acb *, int);
242 void mha_sense(struct mha_softc *, struct acb *);
243 void mha_msgin(struct mha_softc *);
244 void mha_msgout(struct mha_softc *);
245 int mha_dataout_pio(struct mha_softc *, u_char *, int);
246 int mha_datain_pio(struct mha_softc *, u_char *, int);
247 int mha_dataout(struct mha_softc *, u_char *, int);
248 int mha_datain(struct mha_softc *, u_char *, int);
249 void mha_abort(struct mha_softc *, struct acb *);
250 void mha_init(struct mha_softc *);
251 void mha_scsi_request(struct scsipi_channel *, scsipi_adapter_req_t, void *);
252 void mha_poll(struct mha_softc *, struct acb *);
253 void mha_sched(struct mha_softc *);
254 void mha_done(struct mha_softc *, struct acb *);
255 int mhaintr(void *);
256 void mha_timeout(void *);
257 void mha_minphys(struct buf *);
258 void mha_dequeue(struct mha_softc *, struct acb *);
259 inline void mha_setsync(struct mha_softc *, struct spc_tinfo *);
260 #if SPC_DEBUG
261 void mha_print_acb(struct acb *);
262 void mha_show_scsi_cmd(struct acb *);
263 void mha_print_active_acb(void);
264 void mha_dump_driver(struct mha_softc *);
265 #endif
266
267 static int mha_dataio_dma(int, int, struct mha_softc *, u_char *, int);
268
269 CFATTACH_DECL_NEW(mha, sizeof(struct mha_softc),
270 mhamatch, mhaattach, NULL, NULL);
271
272 /*
273 * returns non-zero value if a controller is found.
274 */
275 int
mhamatch(device_t parent,cfdata_t cf,void * aux)276 mhamatch(device_t parent, cfdata_t cf, void *aux)
277 {
278 struct intio_attach_args *ia = aux;
279 bus_space_tag_t iot = ia->ia_bst;
280 bus_space_handle_t ioh;
281
282 ia->ia_size=0x20;
283 if (ia->ia_addr != 0xea0000)
284 return 0;
285
286 if (intio_map_allocate_region(device_parent(parent), ia,
287 INTIO_MAP_TESTONLY) < 0) /* FAKE */
288 return 0;
289
290 if (bus_space_map(iot, ia->ia_addr, 0x20, BUS_SPACE_MAP_SHIFTED,
291 &ioh) < 0)
292 return 0;
293 if (!badaddr((void *)IIOV(ia->ia_addr + 0)))
294 return 0;
295 bus_space_unmap(iot, ioh, 0x20);
296
297 return 1;
298 }
299
300 /*
301 */
302
303 struct mha_softc *tmpsc;
304
305 void
mhaattach(device_t parent,device_t self,void * aux)306 mhaattach(device_t parent, device_t self, void *aux)
307 {
308 struct mha_softc *sc = device_private(self);
309 struct intio_attach_args *ia = aux;
310
311 tmpsc = sc; /* XXX */
312 sc->sc_dev = self;
313
314 aprint_normal(": Mankai Mach-2 Fast SCSI Host Adaptor\n");
315
316 SPC_TRACE(("mhaattach "));
317 sc->sc_state = SPC_INIT;
318 sc->sc_iobase = (void *)IIOV(ia->ia_addr + 0x80); /* XXX */
319 intio_map_allocate_region(device_parent(parent), ia, INTIO_MAP_ALLOCATE);
320 /* XXX: FAKE */
321 sc->sc_dmat = ia->ia_dmat;
322
323 sc->sc_pc = (volatile u_char *)sc->sc_iobase;
324 sc->sc_ps = (volatile u_short *)sc->sc_iobase;
325 sc->sc_pcx = &sc->sc_pc[0x10];
326
327 sc->sc_id = IODEVbase->io_sram[0x70] & 0x7; /* XXX */
328
329 intio_intr_establish(ia->ia_intr, "mha", mhaintr, sc);
330
331 mha_init(sc); /* Init chip and driver */
332
333 mha_scsi_reset(sc); /* XXX: some devices need this. */
334
335 sc->sc_phase = BUSFREE_PHASE;
336
337 /*
338 * Fill in the adapter.
339 */
340 sc->sc_adapter.adapt_dev = self;
341 sc->sc_adapter.adapt_nchannels = 1;
342 sc->sc_adapter.adapt_openings = 7;
343 sc->sc_adapter.adapt_max_periph = 1;
344 sc->sc_adapter.adapt_ioctl = NULL;
345 sc->sc_adapter.adapt_minphys = mha_minphys;
346 sc->sc_adapter.adapt_request = mha_scsi_request;
347
348 sc->sc_channel.chan_adapter = &sc->sc_adapter;
349 sc->sc_channel.chan_bustype = &scsi_bustype;
350 sc->sc_channel.chan_channel = 0;
351 sc->sc_channel.chan_ntargets = 8;
352 sc->sc_channel.chan_nluns = 8;
353 sc->sc_channel.chan_id = sc->sc_id;
354
355 sc->sc_spcinitialized = 0;
356 WAR = WA_INITWIN;
357 #if 1
358 CCR = 0x14;
359 OIR = sc->sc_id;
360 AMR = 0x00;
361 SMR = 0x00;
362 SRR = 0x00;
363 STR = 0x20;
364 RTR = 0x40;
365 ATR = 0x01;
366 PER = 0xc9;
367 #endif
368 IER = IE_ALL; /* $B$9$Y$F$N3d$j9~$_$r5v2D(B */
369 #if 1
370 GLR = 0x00;
371 DMR = 0x30;
372 IMR = 0x00;
373 #endif
374 WAR = WA_MCSBUFWIN;
375
376 /* drop off */
377 while (SSR & SS_IREQUEST) {
378 (void) ISCSR;
379 }
380
381 CMR = CMD_SET_UP_REG; /* setup reg cmd. */
382
383 SPC_TRACE(("waiting for intr..."));
384 while (!(SSR & SS_IREQUEST))
385 delay(10);
386 mhaintr(sc);
387
388 tmpsc = NULL;
389
390 config_found(self, &sc->sc_channel, scsiprint, CFARGS_NONE);
391 }
392
393 #if 0
394 void
395 mha_reset(struct mha_softc *sc)
396 {
397 u_short dummy;
398 printf("reset...");
399 CMR = CMD_SOFT_RESET;
400 __asm volatile ("nop"); /* XXX wait (4clk in 20 MHz) ??? */
401 dummy = sc->sc_ps[-1];
402 dummy = sc->sc_ps[-1];
403 dummy = sc->sc_ps[-1];
404 dummy = sc->sc_ps[-1];
405 __asm volatile ("nop");
406 CMR = CMD_SOFT_RESET;
407 sc->sc_spcinitialized = 0;
408 CMR = CMD_SET_UP_REG; /* setup reg cmd. */
409 while(!sc->sc_spcinitialized);
410
411 sc->sc_id = IODEVbase->io_sram[0x70] & 0x7; /* XXX */
412 printf("done.\n");
413 }
414 #endif
415
416 /*
417 * Pull the SCSI RST line for 500us.
418 */
419 void
mha_scsi_reset(struct mha_softc * sc)420 mha_scsi_reset(struct mha_softc *sc)
421 {
422
423 CMR = CMD_SCSI_RESET; /* SCSI RESET */
424 while (!(SSR&SS_IREQUEST))
425 delay(10);
426 }
427
428 /*
429 * Initialize mha SCSI driver.
430 */
431 void
mha_init(struct mha_softc * sc)432 mha_init(struct mha_softc *sc)
433 {
434 struct acb *acb;
435 int r;
436
437 if (sc->sc_state == SPC_INIT) {
438 /* First time through; initialize. */
439 TAILQ_INIT(&sc->ready_list);
440 TAILQ_INIT(&sc->nexus_list);
441 TAILQ_INIT(&sc->free_list);
442 sc->sc_nexus = NULL;
443 acb = sc->sc_acb;
444 memset(acb, 0, sizeof(sc->sc_acb));
445 for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) {
446 TAILQ_INSERT_TAIL(&sc->free_list, acb, chain);
447 acb++;
448 }
449 memset(&sc->sc_tinfo, 0, sizeof(sc->sc_tinfo));
450
451 r = bus_dmamem_alloc(sc->sc_dmat, MAXBSIZE, 0, 0,
452 sc->sc_dmaseg, 1, &sc->sc_ndmasegs,
453 BUS_DMA_NOWAIT);
454 if (r)
455 panic("mha_init: cannot allocate DMA memory");
456 if (sc->sc_ndmasegs != 1)
457 panic("mha_init: number of segment > 1??");
458 r = bus_dmamem_map(sc->sc_dmat, sc->sc_dmaseg, sc->sc_ndmasegs,
459 MAXBSIZE, &sc->sc_dmabuf, BUS_DMA_NOWAIT);
460 if (r)
461 panic("mha_init: cannot map DMA memory");
462 r = bus_dmamap_create(sc->sc_dmat, MAXBSIZE, 1,
463 MAXBSIZE, 0, BUS_DMA_NOWAIT,
464 &sc->sc_dmamap);
465 if (r)
466 panic("mha_init: cannot create dmamap structure");
467 r = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap,
468 sc->sc_dmabuf, MAXBSIZE, NULL,
469 BUS_DMA_NOWAIT);
470 if (r)
471 panic("mha_init: cannot load DMA buffer into dmamap");
472 sc->sc_p = 0;
473 } else {
474 /* Cancel any active commands. */
475 sc->sc_flags |= SPC_ABORTING;
476 sc->sc_state = SPC_IDLE;
477 if ((acb = sc->sc_nexus) != NULL) {
478 acb->xs->error = XS_DRIVER_STUFFUP;
479 mha_done(sc, acb);
480 }
481 while ((acb = TAILQ_FIRST(&sc->nexus_list)) != NULL) {
482 acb->xs->error = XS_DRIVER_STUFFUP;
483 mha_done(sc, acb);
484 }
485 }
486
487 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE;
488 for (r = 0; r < 8; r++) {
489 struct spc_tinfo *ti = &sc->sc_tinfo[r];
490
491 ti->flags = 0;
492 #if SPC_USE_SYNCHRONOUS
493 ti->flags |= T_SYNCMODE;
494 ti->period = sc->sc_minsync;
495 ti->offset = SPC_SYNC_REQ_ACK_OFS;
496 #else
497 ti->period = ti->offset = 0;
498 #endif
499 ti->width = 0;
500 }
501
502 sc->sc_state = SPC_IDLE;
503 }
504
505 void
mha_free_acb(struct mha_softc * sc,struct acb * acb,int flags)506 mha_free_acb(struct mha_softc *sc, struct acb *acb, int flags)
507 {
508 int s;
509
510 s = splbio();
511
512 acb->flags = 0;
513 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain);
514
515 /*
516 * If there were none, wake anybody waiting for one to come free,
517 * starting with queued entries.
518 */
519 if (TAILQ_NEXT(acb, chain) == NULL)
520 wakeup(&sc->free_list);
521
522 splx(s);
523 }
524
525 /*
526 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS
527 */
528
529 /*
530 * Expected sequence:
531 * 1) Command inserted into ready list
532 * 2) Command selected for execution
533 * 3) Command won arbitration and has selected target device
534 * 4) Send message out (identify message, eventually also sync.negotiations)
535 * 5) Send command
536 * 5a) Receive disconnect message, disconnect.
537 * 5b) Reselected by target
538 * 5c) Receive identify message from target.
539 * 6) Send or receive data
540 * 7) Receive status
541 * 8) Receive message (command complete etc.)
542 * 9) If status == SCSI_CHECK construct a synthetic request sense SCSI cmd.
543 * Repeat 2-8 (no disconnects please...)
544 */
545
546 /*
547 * Start a selection. This is used by mha_sched() to select an idle target,
548 * and by mha_done() to immediately reselect a target to get sense information.
549 */
550 void
mhaselect(struct mha_softc * sc,u_char target,u_char lun,u_char * cmd,u_char clen)551 mhaselect(struct mha_softc *sc, u_char target, u_char lun, u_char *cmd,
552 u_char clen)
553 {
554 int i;
555 int s;
556
557 s = splbio(); /* XXX */
558
559 SPC_TRACE(("[mhaselect(t%d,l%d,cmd:%x)] ", target, lun, *(u_char *)cmd));
560
561 /* CDB $B$r(B SPC $B$N(B MCS REG $B$K%;%C%H$9$k(B */
562 /* Now the command into the FIFO */
563 WAIT;
564 #if 1
565 SPC_MISC(("[cmd:"));
566 for (i = 0; i < clen; i++) {
567 unsigned c = cmd[i];
568 if (i == 1)
569 c |= lun << 5;
570 SPC_MISC((" %02x", c));
571 sc->sc_pcx[i] = c;
572 }
573 SPC_MISC(("], target=%d\n", target));
574 #else
575 memcpy(sc->sc_pcx, cmd, clen);
576 #endif
577 if (NSR & 0x80)
578 panic("scsistart: already selected...");
579 sc->sc_phase = COMMAND_PHASE;
580
581 /* new state ASP_SELECTING */
582 sc->sc_state = SPC_SELECTING;
583
584 SIR = target;
585 #if 0
586 CMR = CMD_SELECT;
587 #else
588 CMR = CMD_SEL_AND_CMD; /* select & cmd */
589 #endif
590 splx(s);
591 }
592
593 #if 0
594 int
595 mha_reselect(struct mha_softc *sc, u_char message)
596 {
597 u_char selid, target, lun;
598 struct acb *acb;
599 struct scsipi_periph *periph;
600 struct spc_tinfo *ti;
601
602 /*
603 * The SCSI chip made a snapshot of the data bus while the reselection
604 * was being negotiated. This enables us to determine which target did
605 * the reselect.
606 */
607 selid = sc->sc_selid & ~(1 << sc->sc_id);
608 if (selid & (selid - 1)) {
609 printf("%s: reselect with invalid selid %02x; sending DEVICE RESET\n",
610 device_xname(sc->sc_dev), selid);
611 SPC_BREAK();
612 goto reset;
613 }
614
615 /*
616 * Search wait queue for disconnected cmd
617 * The list should be short, so I haven't bothered with
618 * any more sophisticated structures than a simple
619 * singly linked list.
620 */
621 target = ffs(selid) - 1;
622 lun = message & 0x07;
623 TAILQ_FOREACH(acb, &sc->nexus_list, chain) {
624 periph = acb->xs->xs_periph;
625 if (periph->periph_target == target &&
626 periph->periph_lun == lun)
627 break;
628 }
629 if (acb == NULL) {
630 printf("%s: reselect from target %d lun %d with no nexus; sending ABORT\n",
631 device_xname(sc->sc_dev), target, lun);
632 SPC_BREAK();
633 goto abort;
634 }
635
636 /* Make this nexus active again. */
637 TAILQ_REMOVE(&sc->nexus_list, acb, chain);
638 sc->sc_state = SPC_HASNEXUS;
639 sc->sc_nexus = acb;
640 ti = &sc->sc_tinfo[target];
641 ti->lubusy |= (1 << lun);
642 mha_setsync(sc, ti);
643
644 if (acb->flags & ACB_RESET)
645 mha_sched_msgout(sc, SEND_DEV_RESET);
646 else if (acb->flags & ACB_ABORTED)
647 mha_sched_msgout(sc, SEND_ABORT);
648
649 /* Do an implicit RESTORE POINTERS. */
650 sc->sc_dp = acb->daddr;
651 sc->sc_dleft = acb->dleft;
652 sc->sc_cp = (u_char *)&acb->cmd;
653 sc->sc_cleft = acb->clen;
654
655 return (0);
656
657 reset:
658 mha_sched_msgout(sc, SEND_DEV_RESET);
659 return (1);
660
661 abort:
662 mha_sched_msgout(sc, SEND_ABORT);
663 return (1);
664 }
665 #endif
666 /*
667 * Start a SCSI-command
668 * This function is called by the higher level SCSI-driver to queue/run
669 * SCSI-commands.
670 */
671 void
mha_scsi_request(struct scsipi_channel * chan,scsipi_adapter_req_t req,void * arg)672 mha_scsi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req,
673 void *arg)
674 {
675 struct scsipi_xfer *xs;
676 struct mha_softc *sc = device_private(chan->chan_adapter->adapt_dev);
677 struct acb *acb;
678 int s, flags;
679
680 switch (req) {
681 case ADAPTER_REQ_RUN_XFER:
682 xs = arg;
683
684 SPC_TRACE(("[mha_scsi_cmd] "));
685 SPC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen,
686 periph->periph_target));
687
688 flags = xs->xs_control;
689
690 /* Get a mha command block */
691 s = splbio();
692 acb = TAILQ_FIRST(&sc->free_list);
693 if (acb) {
694 TAILQ_REMOVE(&sc->free_list, acb, chain);
695 ACB_SETQ(acb, ACB_QNONE);
696 }
697
698 if (acb == NULL) {
699 xs->error = XS_RESOURCE_SHORTAGE;
700 scsipi_done(xs);
701 splx(s);
702 return;
703 }
704 splx(s);
705
706 /* Initialize acb */
707 acb->xs = xs;
708 memcpy(&acb->cmd, xs->cmd, xs->cmdlen);
709 acb->clen = xs->cmdlen;
710 acb->daddr = xs->data;
711 acb->dleft = xs->datalen;
712 acb->stat = 0;
713
714 s = splbio();
715 ACB_SETQ(acb, ACB_QREADY);
716 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain);
717 #if 1
718 callout_reset(&acb->xs->xs_callout,
719 mstohz(xs->timeout), mha_timeout, acb);
720 #endif
721
722 /*
723 * $B%-%e!<$N=hM}Cf$G$J$1$l$P!"%9%1%8%e!<%j%s%03+;O$9$k(B
724 */
725 if (sc->sc_state == SPC_IDLE)
726 mha_sched(sc);
727
728 splx(s);
729
730 if (flags & XS_CTL_POLL) {
731 /* Not allowed to use interrupts, use polling instead */
732 mha_poll(sc, acb);
733 }
734
735 SPC_MISC(("SUCCESSFULLY_QUEUED"));
736 return;
737
738 case ADAPTER_REQ_GROW_RESOURCES:
739 /* XXX Not supported. */
740 return;
741
742 case ADAPTER_REQ_SET_XFER_MODE:
743 /* XXX Not supported. */
744 return;
745 }
746 }
747
748 /*
749 * Adjust transfer size in buffer structure
750 */
751 void
mha_minphys(struct buf * bp)752 mha_minphys(struct buf *bp)
753 {
754
755 SPC_TRACE(("mha_minphys "));
756 minphys(bp);
757 }
758
759 /*
760 * Used when interrupt driven I/O isn't allowed, e.g. during boot.
761 */
762 void
mha_poll(struct mha_softc * sc,struct acb * acb)763 mha_poll(struct mha_softc *sc, struct acb *acb)
764 {
765 struct scsipi_xfer *xs = acb->xs;
766 int count = xs->timeout * 100;
767 int s;
768
769 s = splbio();
770
771 SPC_TRACE(("[mha_poll] "));
772
773 while (count) {
774 /*
775 * If we had interrupts enabled, would we
776 * have got an interrupt?
777 */
778 if (SSR & SS_IREQUEST)
779 mhaintr(sc);
780 if ((xs->xs_status & XS_STS_DONE) != 0)
781 break;
782 DELAY(10);
783 #if 1
784 if (sc->sc_state == SPC_IDLE) {
785 SPC_TRACE(("[mha_poll: rescheduling] "));
786 mha_sched(sc);
787 }
788 #endif
789 count--;
790 }
791
792 if (count == 0) {
793 SPC_MISC(("mha_poll: timeout"));
794 mha_timeout((void *)acb);
795 }
796 splx(s);
797 scsipi_done(xs);
798 }
799
800 /*
801 * LOW LEVEL SCSI UTILITIES
802 */
803
804 /*
805 * Set synchronous transfer offset and period.
806 */
807 inline void
mha_setsync(struct mha_softc * sc,struct spc_tinfo * ti)808 mha_setsync(struct mha_softc *sc, struct spc_tinfo *ti)
809 {
810 }
811
812 /*
813 * Schedule a SCSI operation. This has now been pulled out of the interrupt
814 * handler so that we may call it from mha_scsi_cmd and mha_done. This may
815 * save us an unnecessary interrupt just to get things going. Should only be
816 * called when state == SPC_IDLE and at bio pl.
817 */
818 void
mha_sched(struct mha_softc * sc)819 mha_sched(struct mha_softc *sc)
820 {
821 struct scsipi_periph *periph;
822 struct acb *acb;
823 int t;
824
825 SPC_TRACE(("[mha_sched] "));
826 if (sc->sc_state != SPC_IDLE)
827 panic("mha_sched: not IDLE (state=%d)", sc->sc_state);
828
829 if (sc->sc_flags & SPC_ABORTING)
830 return;
831
832 /*
833 * Find first acb in ready queue that is for a target/lunit
834 * combinations that is not busy.
835 */
836 TAILQ_FOREACH(acb, &sc->ready_list, chain) {
837 struct spc_tinfo *ti;
838 periph = acb->xs->xs_periph;
839 t = periph->periph_target;
840 ti = &sc->sc_tinfo[t];
841 if (!(ti->lubusy & (1 << periph->periph_lun))) {
842 if ((acb->flags & ACB_QBITS) != ACB_QREADY)
843 panic("mha: busy entry on ready list");
844 TAILQ_REMOVE(&sc->ready_list, acb, chain);
845 ACB_SETQ(acb, ACB_QNONE);
846 sc->sc_nexus = acb;
847 sc->sc_flags = 0;
848 sc->sc_prevphase = INVALID_PHASE;
849 sc->sc_dp = acb->daddr;
850 sc->sc_dleft = acb->dleft;
851 ti->lubusy |= (1<<periph->periph_lun);
852 mhaselect(sc, t, periph->periph_lun,
853 (u_char *)&acb->cmd, acb->clen);
854 break;
855 } else {
856 SPC_MISC(("%d:%d busy\n",
857 periph->periph_target,
858 periph->periph_lun));
859 }
860 }
861 }
862
863 /*
864 * POST PROCESSING OF SCSI_CMD (usually current)
865 */
866 void
mha_done(struct mha_softc * sc,struct acb * acb)867 mha_done(struct mha_softc *sc, struct acb *acb)
868 {
869 struct scsipi_xfer *xs = acb->xs;
870 struct scsipi_periph *periph = xs->xs_periph;
871 struct spc_tinfo *ti = &sc->sc_tinfo[periph->periph_target];
872
873 SPC_TRACE(("[mha_done(error:%x)] ", xs->error));
874
875 #if 1
876 callout_stop(&acb->xs->xs_callout);
877 #endif
878
879 /*
880 * Now, if we've come here with no error code, i.e. we've kept the
881 * initial XS_NOERROR, and the status code signals that we should
882 * check sense, we'll need to set up a request sense cmd block and
883 * push the command back into the ready queue *before* any other
884 * commands for this target/lunit, else we lose the sense info.
885 * We don't support chk sense conditions for the request sense cmd.
886 */
887 if (xs->error == XS_NOERROR) {
888 if ((acb->flags & ACB_ABORTED) != 0) {
889 xs->error = XS_TIMEOUT;
890 } else if (acb->flags & ACB_CHKSENSE) {
891 xs->error = XS_SENSE;
892 } else {
893 xs->status = acb->stat & ST_MASK;
894 switch (xs->status) {
895 case SCSI_CHECK:
896 xs->resid = acb->dleft;
897 /* FALLTHROUGH */
898 case SCSI_BUSY:
899 xs->error = XS_BUSY;
900 break;
901 case SCSI_OK:
902 xs->resid = acb->dleft;
903 break;
904 default:
905 xs->error = XS_DRIVER_STUFFUP;
906 #if SPC_DEBUG
907 printf("%s: mha_done: bad stat 0x%x\n",
908 device_xname(sc->sc_dev), acb->stat);
909 #endif
910 break;
911 }
912 }
913 }
914
915 #if SPC_DEBUG
916 if ((mha_debug & SPC_SHOWMISC) != 0) {
917 if (xs->resid != 0)
918 printf("resid=%d ", xs->resid);
919 if (xs->error == XS_SENSE)
920 printf("sense=0x%02x\n", xs->sense.scsi_sense.response_code);
921 else
922 printf("error=%d\n", xs->error);
923 }
924 #endif
925
926 /*
927 * Remove the ACB from whatever queue it's on.
928 */
929 switch (acb->flags & ACB_QBITS) {
930 case ACB_QNONE:
931 if (acb != sc->sc_nexus) {
932 panic("%s: floating acb", device_xname(sc->sc_dev));
933 }
934 sc->sc_nexus = NULL;
935 sc->sc_state = SPC_IDLE;
936 ti->lubusy &= ~(1<<periph->periph_lun);
937 mha_sched(sc);
938 break;
939 case ACB_QREADY:
940 TAILQ_REMOVE(&sc->ready_list, acb, chain);
941 break;
942 case ACB_QNEXUS:
943 TAILQ_REMOVE(&sc->nexus_list, acb, chain);
944 ti->lubusy &= ~(1<<periph->periph_lun);
945 break;
946 case ACB_QFREE:
947 panic("%s: dequeue: busy acb on free list",
948 device_xname(sc->sc_dev));
949 break;
950 default:
951 panic("%s: dequeue: unknown queue %d",
952 device_xname(sc->sc_dev), acb->flags & ACB_QBITS);
953 }
954
955 /* Put it on the free list, and clear flags. */
956 #if 0
957 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain);
958 acb->flags = ACB_QFREE;
959 #else
960 mha_free_acb(sc, acb, xs->xs_control);
961 #endif
962
963 ti->cmds++;
964 scsipi_done(xs);
965 }
966
967 void
mha_dequeue(struct mha_softc * sc,struct acb * acb)968 mha_dequeue(struct mha_softc *sc, struct acb *acb)
969 {
970
971 if (acb->flags & ACB_QNEXUS) {
972 TAILQ_REMOVE(&sc->nexus_list, acb, chain);
973 } else {
974 TAILQ_REMOVE(&sc->ready_list, acb, chain);
975 }
976 }
977
978 /*
979 * INTERRUPT/PROTOCOL ENGINE
980 */
981
982 /*
983 * Schedule an outgoing message by prioritizing it, and asserting
984 * attention on the bus. We can only do this when we are the initiator
985 * else there will be an illegal command interrupt.
986 */
987 #define mha_sched_msgout(m) \
988 do { \
989 SPC_MISC(("mha_sched_msgout %d ", m)); \
990 CMR = CMD_SET_ATN; \
991 sc->sc_msgpriq |= (m); \
992 } while (0)
993
994 /*
995 * Precondition:
996 * The SCSI bus is already in the MSGI phase and there is a message byte
997 * on the bus, along with an asserted REQ signal.
998 */
999 void
mha_msgin(struct mha_softc * sc)1000 mha_msgin(struct mha_softc *sc)
1001 {
1002 int v;
1003
1004 SPC_TRACE(("[mha_msgin(curmsglen:%d)] ", sc->sc_imlen));
1005
1006 /*
1007 * Prepare for a new message. A message should (according
1008 * to the SCSI standard) be transmitted in one single
1009 * MESSAGE_IN_PHASE. If we have been in some other phase,
1010 * then this is a new message.
1011 */
1012 if (sc->sc_prevphase != MESSAGE_IN_PHASE) {
1013 sc->sc_flags &= ~SPC_DROP_MSGI;
1014 sc->sc_imlen = 0;
1015 }
1016
1017 WAIT;
1018
1019 v = MBR; /* modified byte */
1020 v = sc->sc_pcx[0];
1021
1022 sc->sc_imess[sc->sc_imlen] = v;
1023
1024 /*
1025 * If we're going to reject the message, don't bother storing
1026 * the incoming bytes. But still, we need to ACK them.
1027 */
1028
1029 if ((sc->sc_flags & SPC_DROP_MSGI)) {
1030 CMR = CMD_SET_ATN;
1031 /* ESPCMD(sc, ESPCMD_MSGOK);*/
1032 printf("<dropping msg byte %x>",
1033 sc->sc_imess[sc->sc_imlen]);
1034 return;
1035 }
1036
1037 if (sc->sc_imlen >= SPC_MAX_MSG_LEN) {
1038 mha_sched_msgout(SEND_REJECT);
1039 sc->sc_flags |= SPC_DROP_MSGI;
1040 } else {
1041 sc->sc_imlen++;
1042 /*
1043 * This testing is suboptimal, but most
1044 * messages will be of the one byte variety, so
1045 * it should not effect performance
1046 * significantly.
1047 */
1048 if (sc->sc_imlen == 1 && MSG_IS1BYTE(sc->sc_imess[0]))
1049 goto gotit;
1050 if (sc->sc_imlen == 2 && MSG_IS2BYTE(sc->sc_imess[0]))
1051 goto gotit;
1052 if (sc->sc_imlen >= 3 && MSG_ISEXTENDED(sc->sc_imess[0]) &&
1053 sc->sc_imlen == sc->sc_imess[1] + 2)
1054 goto gotit;
1055 }
1056 #if 0
1057 /* Ack what we have so far */
1058 ESPCMD(sc, ESPCMD_MSGOK);
1059 #endif
1060 return;
1061
1062 gotit:
1063 SPC_MSGS(("gotmsg(%x)", sc->sc_imess[0]));
1064 /*
1065 * Now we should have a complete message (1 byte, 2 byte
1066 * and moderately long extended messages). We only handle
1067 * extended messages which total length is shorter than
1068 * SPC_MAX_MSG_LEN. Longer messages will be amputated.
1069 */
1070 if (sc->sc_state == SPC_HASNEXUS) {
1071 struct acb *acb = sc->sc_nexus;
1072 struct spc_tinfo *ti =
1073 &sc->sc_tinfo[acb->xs->xs_periph->periph_target];
1074
1075 switch (sc->sc_imess[0]) {
1076 case MSG_CMDCOMPLETE:
1077 SPC_MSGS(("cmdcomplete "));
1078 if (sc->sc_dleft < 0) {
1079 struct scsipi_periph *periph = acb->xs->xs_periph;
1080 printf("mha: %d extra bytes from %d:%d\n",
1081 -sc->sc_dleft,
1082 periph->periph_target,
1083 periph->periph_lun);
1084 sc->sc_dleft = 0;
1085 }
1086 acb->xs->resid = acb->dleft = sc->sc_dleft;
1087 sc->sc_flags |= SPC_BUSFREE_OK;
1088 break;
1089
1090 case MSG_MESSAGE_REJECT:
1091 #if SPC_DEBUG
1092 if (mha_debug & SPC_SHOWMSGS)
1093 printf("%s: our msg rejected by target\n",
1094 device_xname(sc->sc_dev));
1095 #endif
1096 #if 1 /* XXX - must remember last message */
1097 scsipi_printaddr(acb->xs->xs_periph);
1098 printf("MSG_MESSAGE_REJECT>>");
1099 #endif
1100 if (sc->sc_flags & SPC_SYNCHNEGO) {
1101 ti->period = ti->offset = 0;
1102 sc->sc_flags &= ~SPC_SYNCHNEGO;
1103 ti->flags &= ~T_NEGOTIATE;
1104 }
1105 /* Not all targets understand INITIATOR_DETECTED_ERR */
1106 if (sc->sc_msgout == SEND_INIT_DET_ERR)
1107 mha_sched_msgout(SEND_ABORT);
1108 break;
1109 case MSG_NOOP:
1110 SPC_MSGS(("noop "));
1111 break;
1112 case MSG_DISCONNECT:
1113 SPC_MSGS(("disconnect "));
1114 ti->dconns++;
1115 sc->sc_flags |= SPC_DISCON;
1116 sc->sc_flags |= SPC_BUSFREE_OK;
1117 if ((acb->xs->xs_periph->periph_quirks & PQUIRK_AUTOSAVE) == 0)
1118 break;
1119 /*FALLTHROUGH*/
1120 case MSG_SAVEDATAPOINTER:
1121 SPC_MSGS(("save datapointer "));
1122 acb->dleft = sc->sc_dleft;
1123 acb->daddr = sc->sc_dp;
1124 break;
1125 case MSG_RESTOREPOINTERS:
1126 SPC_MSGS(("restore datapointer "));
1127 if (!acb) {
1128 mha_sched_msgout(SEND_ABORT);
1129 printf("%s: no DATAPOINTERs to restore\n",
1130 device_xname(sc->sc_dev));
1131 break;
1132 }
1133 sc->sc_dp = acb->daddr;
1134 sc->sc_dleft = acb->dleft;
1135 break;
1136 case MSG_PARITY_ERROR:
1137 printf("%s:target%d: MSG_PARITY_ERROR\n",
1138 device_xname(sc->sc_dev),
1139 acb->xs->xs_periph->periph_target);
1140 break;
1141 case MSG_EXTENDED:
1142 SPC_MSGS(("extended(%x) ", sc->sc_imess[2]));
1143 switch (sc->sc_imess[2]) {
1144 case MSG_EXT_SDTR:
1145 SPC_MSGS(("SDTR period %d, offset %d ",
1146 sc->sc_imess[3], sc->sc_imess[4]));
1147 ti->period = sc->sc_imess[3];
1148 ti->offset = sc->sc_imess[4];
1149 if (sc->sc_minsync == 0) {
1150 /* We won't do synch */
1151 ti->offset = 0;
1152 mha_sched_msgout(SEND_SDTR);
1153 } else if (ti->offset == 0) {
1154 printf("%s:%d: async\n", "mha",
1155 acb->xs->xs_periph->periph_target);
1156 ti->offset = 0;
1157 sc->sc_flags &= ~SPC_SYNCHNEGO;
1158 } else if (ti->period > 124) {
1159 printf("%s:%d: async\n", "mha",
1160 acb->xs->xs_periph->periph_target);
1161 ti->offset = 0;
1162 mha_sched_msgout(SEND_SDTR);
1163 } else {
1164 #if 0
1165 int p;
1166 p = mha_stp2cpb(sc, ti->period);
1167 ti->period = mha_cpb2stp(sc, p);
1168 #endif
1169
1170 #if SPC_DEBUG
1171 scsipi_printaddr(acb->xs->xs_periph);
1172 #endif
1173 if ((sc->sc_flags&SPC_SYNCHNEGO) == 0) {
1174 /* Target initiated negotiation */
1175 if (ti->flags & T_SYNCMODE) {
1176 ti->flags &= ~T_SYNCMODE;
1177 #if SPC_DEBUG
1178 printf("renegotiated ");
1179 #endif
1180 }
1181 TMR=TM_ASYNC;
1182 /* Clamp to our maxima */
1183 if (ti->period < sc->sc_minsync)
1184 ti->period = sc->sc_minsync;
1185 if (ti->offset > 15)
1186 ti->offset = 15;
1187 mha_sched_msgout(SEND_SDTR);
1188 } else {
1189 /* we are sync */
1190 sc->sc_flags &= ~SPC_SYNCHNEGO;
1191 TMR = TM_SYNC;
1192 ti->flags |= T_SYNCMODE;
1193 }
1194 }
1195 ti->flags &= ~T_NEGOTIATE;
1196 break;
1197 default: /* Extended messages we don't handle */
1198 CMR = CMD_SET_ATN; /* XXX? */
1199 break;
1200 }
1201 break;
1202 default:
1203 SPC_MSGS(("ident "));
1204 /* thanks for that ident... */
1205 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) {
1206 SPC_MISC(("unknown "));
1207 printf("%s: unimplemented message: %d\n", device_xname(sc->sc_dev), sc->sc_imess[0]);
1208 CMR = CMD_SET_ATN; /* XXX? */
1209 }
1210 break;
1211 }
1212 } else if (sc->sc_state == SPC_RESELECTED) {
1213 struct scsipi_periph *periph = NULL;
1214 struct acb *acb;
1215 struct spc_tinfo *ti;
1216 u_char lunit;
1217
1218 if (MSG_ISIDENTIFY(sc->sc_imess[0])) { /* Identify? */
1219 SPC_MISC(("searching "));
1220 /*
1221 * Search wait queue for disconnected cmd
1222 * The list should be short, so I haven't bothered with
1223 * any more sophisticated structures than a simple
1224 * singly linked list.
1225 */
1226 lunit = sc->sc_imess[0] & 0x07;
1227 TAILQ_FOREACH(acb, &sc->nexus_list, chain) {
1228 periph = acb->xs->xs_periph;
1229 if (periph->periph_lun == lunit &&
1230 sc->sc_selid == (1<<periph->periph_target)) {
1231 TAILQ_REMOVE(&sc->nexus_list, acb,
1232 chain);
1233 ACB_SETQ(acb, ACB_QNONE);
1234 break;
1235 }
1236 }
1237
1238 if (!acb) { /* Invalid reselection! */
1239 mha_sched_msgout(SEND_ABORT);
1240 printf("mha: invalid reselect (idbit=0x%2x)\n",
1241 sc->sc_selid);
1242 } else { /* Reestablish nexus */
1243 /*
1244 * Setup driver data structures and
1245 * do an implicit RESTORE POINTERS
1246 */
1247 ti = &sc->sc_tinfo[periph->periph_target];
1248 sc->sc_nexus = acb;
1249 sc->sc_dp = acb->daddr;
1250 sc->sc_dleft = acb->dleft;
1251 sc->sc_tinfo[periph->periph_target].lubusy
1252 |= (1<<periph->periph_lun);
1253 if (ti->flags & T_SYNCMODE) {
1254 TMR = TM_SYNC; /* XXX */
1255 } else {
1256 TMR = TM_ASYNC;
1257 }
1258 SPC_MISC(("... found acb"));
1259 sc->sc_state = SPC_HASNEXUS;
1260 }
1261 } else {
1262 printf("%s: bogus reselect (no IDENTIFY) %0x2x\n",
1263 device_xname(sc->sc_dev), sc->sc_selid);
1264 mha_sched_msgout(SEND_DEV_RESET);
1265 }
1266 } else { /* Neither SPC_HASNEXUS nor SPC_RESELECTED! */
1267 printf("%s: unexpected message in; will send DEV_RESET\n",
1268 device_xname(sc->sc_dev));
1269 mha_sched_msgout(SEND_DEV_RESET);
1270 }
1271
1272 /* Ack last message byte */
1273 #if 0
1274 ESPCMD(sc, ESPCMD_MSGOK);
1275 #endif
1276
1277 /* Done, reset message pointer. */
1278 sc->sc_flags &= ~SPC_DROP_MSGI;
1279 sc->sc_imlen = 0;
1280 }
1281
1282 /*
1283 * Send the highest priority, scheduled message.
1284 */
1285 void
mha_msgout(struct mha_softc * sc)1286 mha_msgout(struct mha_softc *sc)
1287 {
1288 #if (SPC_USE_SYNCHRONOUS || SPC_USE_WIDE)
1289 struct spc_tinfo *ti;
1290 #endif
1291 int n;
1292
1293 SPC_TRACE(("mha_msgout "));
1294
1295 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) {
1296 if (sc->sc_omp == sc->sc_omess) {
1297 /*
1298 * This is a retransmission.
1299 *
1300 * We get here if the target stayed in MESSAGE OUT
1301 * phase. Section 5.1.9.2 of the SCSI 2 spec indicates
1302 * that all of the previously transmitted messages must
1303 * be sent again, in the same order. Therefore, we
1304 * requeue all the previously transmitted messages, and
1305 * start again from the top. Our simple priority
1306 * scheme keeps the messages in the right order.
1307 */
1308 SPC_MISC(("retransmitting "));
1309 sc->sc_msgpriq |= sc->sc_msgoutq;
1310 /*
1311 * Set ATN. If we're just sending a trivial 1-byte
1312 * message, we'll clear ATN later on anyway.
1313 */
1314 CMR = CMD_SET_ATN; /* XXX? */
1315 } else {
1316 /* This is a continuation of the previous message. */
1317 n = sc->sc_omp - sc->sc_omess;
1318 goto nextbyte;
1319 }
1320 }
1321
1322 /* No messages transmitted so far. */
1323 sc->sc_msgoutq = 0;
1324 sc->sc_lastmsg = 0;
1325
1326 nextmsg:
1327 /* Pick up highest priority message. */
1328 sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq;
1329 sc->sc_msgpriq &= ~sc->sc_currmsg;
1330 sc->sc_msgoutq |= sc->sc_currmsg;
1331
1332 /* Build the outgoing message data. */
1333 switch (sc->sc_currmsg) {
1334 case SEND_IDENTIFY:
1335 SPC_ASSERT(sc->sc_nexus != NULL);
1336 sc->sc_omess[0] =
1337 MSG_IDENTIFY(sc->sc_nexus->xs->xs_periph->periph_lun, 1);
1338 n = 1;
1339 break;
1340
1341 #if SPC_USE_SYNCHRONOUS
1342 case SEND_SDTR:
1343 SPC_ASSERT(sc->sc_nexus != NULL);
1344 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target];
1345 sc->sc_omess[4] = MSG_EXTENDED;
1346 sc->sc_omess[3] = 3;
1347 sc->sc_omess[2] = MSG_EXT_SDTR;
1348 sc->sc_omess[1] = ti->period >> 2;
1349 sc->sc_omess[0] = ti->offset;
1350 n = 5;
1351 break;
1352 #endif
1353
1354 #if SPC_USE_WIDE
1355 case SEND_WDTR:
1356 SPC_ASSERT(sc->sc_nexus != NULL);
1357 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target];
1358 sc->sc_omess[3] = MSG_EXTENDED;
1359 sc->sc_omess[2] = 2;
1360 sc->sc_omess[1] = MSG_EXT_WDTR;
1361 sc->sc_omess[0] = ti->width;
1362 n = 4;
1363 break;
1364 #endif
1365
1366 case SEND_DEV_RESET:
1367 sc->sc_flags |= SPC_ABORTING;
1368 sc->sc_omess[0] = MSG_BUS_DEV_RESET;
1369 n = 1;
1370 break;
1371
1372 case SEND_REJECT:
1373 sc->sc_omess[0] = MSG_MESSAGE_REJECT;
1374 n = 1;
1375 break;
1376
1377 case SEND_PARITY_ERROR:
1378 sc->sc_omess[0] = MSG_PARITY_ERROR;
1379 n = 1;
1380 break;
1381
1382 case SEND_INIT_DET_ERR:
1383 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR;
1384 n = 1;
1385 break;
1386
1387 case SEND_ABORT:
1388 sc->sc_flags |= SPC_ABORTING;
1389 sc->sc_omess[0] = MSG_ABORT;
1390 n = 1;
1391 break;
1392
1393 default:
1394 printf("%s: unexpected MESSAGE OUT; sending NOOP\n",
1395 device_xname(sc->sc_dev));
1396 SPC_BREAK();
1397 sc->sc_omess[0] = MSG_NOOP;
1398 n = 1;
1399 break;
1400 }
1401 sc->sc_omp = &sc->sc_omess[n];
1402
1403 nextbyte:
1404 /* Send message bytes. */
1405 /* send TRANSFER command. */
1406 sc->sc_ps[3] = 1;
1407 sc->sc_ps[4] = n >> 8;
1408 sc->sc_pc[10] = n;
1409 sc->sc_ps[-1] = 0x000F; /* burst */
1410 __asm volatile ("nop");
1411 CMR = CMD_SEND_FROM_DMA; /* send from DMA */
1412 for (;;) {
1413 if ((SSR & SS_BUSY) != 0)
1414 break;
1415 if (SSR & SS_IREQUEST)
1416 goto out;
1417 }
1418 for (;;) {
1419 #if 0
1420 for (;;) {
1421 if ((PSNS & PSNS_REQ) != 0)
1422 break;
1423 /* Wait for REQINIT. XXX Need timeout. */
1424 }
1425 #endif
1426 if (SSR & SS_IREQUEST) {
1427 /*
1428 * Target left MESSAGE OUT, possibly to reject
1429 * our message.
1430 *
1431 * If this is the last message being sent, then we
1432 * deassert ATN, since either the target is going to
1433 * ignore this message, or it's going to ask for a
1434 * retransmission via MESSAGE PARITY ERROR (in which
1435 * case we reassert ATN anyway).
1436 */
1437 #if 0
1438 if (sc->sc_msgpriq == 0)
1439 CMR = CMD_RESET_ATN;
1440 #endif
1441 goto out;
1442 }
1443
1444 #if 0
1445 /* Clear ATN before last byte if this is the last message. */
1446 if (n == 1 && sc->sc_msgpriq == 0)
1447 CMR = CMD_RESET_ATN;
1448 #endif
1449
1450 while ((SSR & SS_DREG_FULL) != 0)
1451 ;
1452 /* Send message byte. */
1453 sc->sc_pc[0] = *--sc->sc_omp;
1454 --n;
1455 /* Keep track of the last message we've sent any bytes of. */
1456 sc->sc_lastmsg = sc->sc_currmsg;
1457
1458 if (n == 0)
1459 break;
1460 }
1461
1462 /* We get here only if the entire message has been transmitted. */
1463 if (sc->sc_msgpriq != 0) {
1464 /* There are more outgoing messages. */
1465 goto nextmsg;
1466 }
1467
1468 /*
1469 * The last message has been transmitted. We need to remember the last
1470 * message transmitted (in case the target switches to MESSAGE IN phase
1471 * and sends a MESSAGE REJECT), and the list of messages transmitted
1472 * this time around (in case the target stays in MESSAGE OUT phase to
1473 * request a retransmit).
1474 */
1475
1476 out:
1477 /* Disable REQ/ACK protocol. */
1478 return;
1479 }
1480
1481 /***************************************************************
1482 *
1483 * datain/dataout
1484 *
1485 */
1486
1487 int
mha_datain_pio(struct mha_softc * sc,u_char * p,int n)1488 mha_datain_pio(struct mha_softc *sc, u_char *p, int n)
1489 {
1490 u_short d;
1491 int a;
1492 int total_n = n;
1493
1494 SPC_TRACE(("[mha_datain_pio(%p,%d)", p, n));
1495
1496 WAIT;
1497 sc->sc_ps[3] = 1;
1498 sc->sc_ps[4] = n >> 8;
1499 sc->sc_pc[10] = n;
1500 /* $BHa$7$-%=%U%HE>Aw(B */
1501 CMR = CMD_RECEIVE_TO_MPU;
1502 for (;;) {
1503 a = SSR;
1504 if (a & 0x04) {
1505 d = sc->sc_ps[0];
1506 *p++ = d >> 8;
1507 if (--n > 0) {
1508 *p++ = d;
1509 --n;
1510 }
1511 a = SSR;
1512 }
1513 if (a & 0x40)
1514 continue;
1515 if (a & 0x80)
1516 break;
1517 }
1518 SPC_TRACE(("...%d resd]", n));
1519 return total_n - n;
1520 }
1521
1522 int
mha_dataout_pio(struct mha_softc * sc,u_char * p,int n)1523 mha_dataout_pio(struct mha_softc *sc, u_char *p, int n)
1524 {
1525 u_short d;
1526 int a;
1527 int total_n = n;
1528
1529 SPC_TRACE(("[mha_dataout_pio(%p,%d)", p, n));
1530
1531 WAIT;
1532 sc->sc_ps[3] = 1;
1533 sc->sc_ps[4] = n >> 8;
1534 sc->sc_pc[10] = n;
1535 /* $BHa$7$-%=%U%HE>Aw(B */
1536 CMR = CMD_SEND_FROM_MPU;
1537 for (;;) {
1538 a = SSR;
1539 if (a & 0x04) {
1540 d = *p++ << 8;
1541 if (--n > 0) {
1542 d |= *p++;
1543 --n;
1544 }
1545 sc->sc_ps[0] = d;
1546 a = SSR;
1547 }
1548 if (a & 0x40)
1549 continue;
1550 if (a & 0x80)
1551 break;
1552 }
1553 SPC_TRACE(("...%d resd]", n));
1554 return total_n - n;
1555 }
1556
1557 /*
1558 * dw: DMA word
1559 * cw: CMR word
1560 */
1561 static int
mha_dataio_dma(int dw,int cw,struct mha_softc * sc,u_char * p,int n)1562 mha_dataio_dma(int dw, int cw, struct mha_softc *sc, u_char *p, int n)
1563 {
1564 char *paddr;
1565
1566 if (n > MAXBSIZE)
1567 panic("transfer size exceeds MAXBSIZE");
1568 if (sc->sc_dmasize > 0)
1569 panic("DMA request while another DMA transfer is in pregress");
1570
1571 if (cw == CMD_SEND_FROM_DMA) {
1572 memcpy(sc->sc_dmabuf, p, n);
1573 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, n, BUS_DMASYNC_PREWRITE);
1574 } else {
1575 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, n, BUS_DMASYNC_PREREAD);
1576 }
1577 sc->sc_p = p;
1578 sc->sc_dmasize = n;
1579
1580 paddr = (char *)sc->sc_dmaseg[0].ds_addr;
1581 #if MHA_DMA_SHORT_BUS_CYCLE == 1
1582 if ((*(volatile int *)&IODEVbase->io_sram[0xac]) &
1583 (1 << ((paddr_t)paddr >> 19)))
1584 dw &= ~(1 << 3);
1585 #endif
1586 sc->sc_pc[0x80 + (((long)paddr >> 16) & 0xFF)] = 0;
1587 sc->sc_pc[0x180 + (((long)paddr >> 8) & 0xFF)] = 0;
1588 sc->sc_pc[0x280 + (((long)paddr >> 0) & 0xFF)] = 0;
1589 WAIT;
1590 sc->sc_ps[3] = 1;
1591 sc->sc_ps[4] = n >> 8;
1592 sc->sc_pc[10] = n;
1593 /* DMA $BE>Aw@)8f$O0J2<$NDL$j!#(B
1594 3 ... short bus cycle
1595 2 ... MAXIMUM XFER.
1596 1 ... BURST XFER.
1597 0 ... R/W */
1598 sc->sc_ps[-1] = dw; /* burst */
1599 __asm volatile ("nop");
1600 CMR = cw; /* receive to DMA */
1601 return n;
1602 }
1603
1604 int
mha_dataout(struct mha_softc * sc,u_char * p,int n)1605 mha_dataout(struct mha_softc *sc, u_char *p, int n)
1606 {
1607 if (n == 0)
1608 return n;
1609
1610 if (n & 1)
1611 return mha_dataout_pio(sc, p, n);
1612 return mha_dataio_dma(MHA_DMA_DATAOUT, CMD_SEND_FROM_DMA, sc, p, n);
1613 }
1614
1615 int
mha_datain(struct mha_softc * sc,u_char * p,int n)1616 mha_datain(struct mha_softc *sc, u_char *p, int n)
1617 {
1618 struct acb *acb = sc->sc_nexus;
1619
1620 if (n == 0)
1621 return n;
1622 if (acb->cmd.opcode == SCSI_REQUEST_SENSE || (n & 1))
1623 return mha_datain_pio(sc, p, n);
1624 return mha_dataio_dma(MHA_DMA_DATAIN, CMD_RECEIVE_TO_DMA, sc, p, n);
1625 }
1626
1627 /*
1628 * Catch an interrupt from the adaptor
1629 */
1630 /*
1631 * This is the workhorse routine of the driver.
1632 * Deficiencies (for now):
1633 * 1) always uses programmed I/O
1634 */
1635 int
mhaintr(void * arg)1636 mhaintr(void *arg)
1637 {
1638 struct mha_softc *sc = arg;
1639 #if 0
1640 u_char ints;
1641 #endif
1642 struct acb *acb;
1643 u_char ph;
1644 u_short r;
1645 int n;
1646
1647 #if 1 /* XXX called during attach? */
1648 if (tmpsc != NULL) {
1649 SPC_MISC(("[%p %p]\n", mha_cd.cd_devs, sc));
1650 sc = tmpsc;
1651 } else {
1652 #endif
1653
1654 #if 1 /* XXX */
1655 }
1656 #endif
1657
1658 #if 0
1659 /*
1660 * $B3d$j9~$_6X;_$K$9$k(B
1661 */
1662 SCTL &= ~SCTL_INTR_ENAB;
1663 #endif
1664
1665 SPC_TRACE(("[mhaintr]"));
1666
1667 /*
1668 * $BA4E>Aw$,40A4$K=*N;$9$k$^$G%k!<%W$9$k(B
1669 */
1670 /*
1671 * First check for abnormal conditions, such as reset.
1672 */
1673 #if 0
1674 #if 1 /* XXX? */
1675 while (((ints = SSR) & SS_IREQUEST) == 0)
1676 delay(1);
1677 SPC_MISC(("ints = 0x%x ", ints));
1678 #else /* usually? */
1679 ints = SSR;
1680 #endif
1681 #endif
1682 while (SSR & SS_IREQUEST) {
1683 acb = sc->sc_nexus;
1684 r = ISCSR;
1685 SPC_MISC(("[r=0x%x]", r));
1686 switch (r >> 8) {
1687 default:
1688 printf("[addr=%p\n"
1689 "result=0x%x\n"
1690 "cmd=0x%x\n"
1691 "ph=0x%x(ought to be %d)]\n",
1692 &ISCSR,
1693 r,
1694 acb->xs->cmd->opcode,
1695 SCR, sc->sc_phase);
1696 panic("unexpected result.");
1697 case 0x82: /* selection timeout */
1698 SPC_MISC(("selection timeout "));
1699 sc->sc_phase = BUSFREE_PHASE;
1700 SPC_ASSERT(sc->sc_nexus != NULL);
1701 acb = sc->sc_nexus;
1702 delay(250);
1703 acb->xs->error = XS_SELTIMEOUT;
1704 mha_done(sc, acb);
1705 continue; /* XXX ??? msaitoh */
1706 case 0x60: /* command completed */
1707 sc->sc_spcinitialized++;
1708 if (sc->sc_phase == BUSFREE_PHASE)
1709 continue;
1710 ph = SCR;
1711 if (ph & PSNS_ACK) {
1712 int s;
1713 /* $B$U$D!<$N%3%^%s%I$,=*N;$7$?$i$7$$(B */
1714 SPC_MISC(("0x60)phase = %x(ought to be %x)\n",
1715 ph & PHASE_MASK, sc->sc_phase));
1716 #if 0
1717 /* switch (sc->sc_phase) {*/
1718 #else
1719 switch (ph & PHASE_MASK) {
1720 #endif
1721 case STATUS_PHASE:
1722 if (sc->sc_state != SPC_HASNEXUS)
1723 printf("stsin: !SPC_HASNEXUS->(%d)\n",
1724 sc->sc_state);
1725 SPC_ASSERT(sc->sc_nexus != NULL);
1726 acb = sc->sc_nexus;
1727 WAIT;
1728 s = MBR;
1729 SPC_ASSERT(s == 1);
1730 __USE(s);
1731 acb->stat = sc->sc_pcx[0]; /* XXX */
1732 SPC_MISC(("stat=0x%02x ", acb->stat));
1733 sc->sc_prevphase = STATUS_PHASE;
1734 break;
1735 case MESSAGE_IN_PHASE:
1736 mha_msgin(sc);
1737 sc->sc_prevphase = MESSAGE_IN_PHASE;
1738 /* thru */
1739 case DATA_IN_PHASE:
1740 if (sc->sc_dmasize == 0)
1741 break;
1742 bus_dmamap_sync(sc->sc_dmat,
1743 sc->sc_dmamap,
1744 0, sc->sc_dmasize,
1745 BUS_DMASYNC_POSTREAD);
1746 memcpy(sc->sc_p, sc->sc_dmabuf,
1747 sc->sc_dmasize);
1748 sc->sc_dmasize = 0;
1749 break;
1750 case DATA_OUT_PHASE:
1751 if (sc->sc_dmasize == 0)
1752 break;
1753 bus_dmamap_sync(sc->sc_dmat,
1754 sc->sc_dmamap,
1755 0, sc->sc_dmasize,
1756 BUS_DMASYNC_POSTWRITE);
1757 sc->sc_dmasize = 0;
1758 break;
1759 }
1760 WAIT;
1761 CMR = CMD_RESET_ACK; /* reset ack */
1762 /*mha_done(sc, acb); XXX */
1763 continue;
1764 } else if (NSR & 0x80) { /* nexus */
1765 #if 1
1766 if (sc->sc_state == SPC_SELECTING) /* XXX msaitoh */
1767 sc->sc_state = SPC_HASNEXUS;
1768 /* $B%U%'!<%:$N7h$aBG$A$r$9$k(B
1769 $B30$l$?$i!"(Binitial-phase error(0x54) $B$,(B
1770 $BJV$C$F$/$k$s$GCm0U$7$?$^$(!#(B
1771 $B$G$b$J$<$+(B 0x65 $B$,JV$C$F$-$?$j$7$F$M!<$+(B? */
1772 WAIT;
1773 if (SSR & SS_IREQUEST)
1774 continue;
1775 switch (sc->sc_phase) {
1776 default:
1777 panic("$B8+CN$i$L(B phase $B$,Mh$A$^$C$?$@$h(B");
1778 case MESSAGE_IN_PHASE:
1779 /* $B2?$b$7$J$$(B */
1780 continue;
1781 case STATUS_PHASE:
1782 sc->sc_phase = MESSAGE_IN_PHASE;
1783 CMR = CMD_RECEIVE_MSG; /* receive msg */
1784 continue;
1785 case DATA_IN_PHASE:
1786 sc->sc_prevphase = DATA_IN_PHASE;
1787 if (sc->sc_dleft == 0) {
1788 /* $BE>Aw%G!<%?$O$b$&$J$$$N$G(B
1789 $B%9%F!<%?%9%U%'!<%:$r4|BT$7$h$&(B */
1790 sc->sc_phase = STATUS_PHASE;
1791 CMR = CMD_RECEIVE_STS; /* receive sts */
1792 continue;
1793 }
1794 n = mha_datain(sc, sc->sc_dp,
1795 sc->sc_dleft);
1796 sc->sc_dp += n;
1797 sc->sc_dleft -= n;
1798 continue;
1799 case DATA_OUT_PHASE:
1800 sc->sc_prevphase = DATA_OUT_PHASE;
1801 if (sc->sc_dleft == 0) {
1802 /* $BE>Aw%G!<%?$O$b$&$J$$$N$G(B
1803 $B%9%F!<%?%9%U%'!<%:$r4|BT$7$h$&(B */
1804 sc->sc_phase = STATUS_PHASE;
1805 CMR = CMD_RECEIVE_STS; /* receive sts */
1806 continue;
1807 }
1808 /* data phase $B$NB3$-$r$d$m$&(B */
1809 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft);
1810 sc->sc_dp += n;
1811 sc->sc_dleft -= n;
1812 continue;
1813 case COMMAND_PHASE:
1814 /* $B:G=i$O(B CMD PHASE $B$H$$$&$3$H$i$7$$(B */
1815 if (acb->dleft) {
1816 /* $B%G!<%?E>Aw$,$"$j$&$k>l9g(B */
1817 if (acb->xs->xs_control & XS_CTL_DATA_IN) {
1818 sc->sc_phase = DATA_IN_PHASE;
1819 n = mha_datain(sc, sc->sc_dp, sc->sc_dleft);
1820 sc->sc_dp += n;
1821 sc->sc_dleft -= n;
1822 }
1823 else if (acb->xs->xs_control & XS_CTL_DATA_OUT) {
1824 sc->sc_phase = DATA_OUT_PHASE;
1825 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft);
1826 sc->sc_dp += n;
1827 sc->sc_dleft -= n;
1828 }
1829 continue;
1830 }
1831 else {
1832 /* $B%G!<%?E>Aw$O$J$$$i$7$$(B?! */
1833 WAIT;
1834 sc->sc_phase = STATUS_PHASE;
1835 CMR = CMD_RECEIVE_STS; /* receive sts */
1836 continue;
1837 }
1838 }
1839 #endif
1840 }
1841 continue;
1842 case 0x31: /* disconnected in xfer progress. */
1843 SPC_MISC(("[0x31]"));
1844 case 0x70: /* disconnected. */
1845 SPC_ASSERT(sc->sc_flags & SPC_BUSFREE_OK);
1846 sc->sc_phase = BUSFREE_PHASE;
1847 sc->sc_state = SPC_IDLE;
1848 #if 1
1849 acb = sc->sc_nexus;
1850 SPC_ASSERT(sc->sc_nexus != NULL);
1851 acb->xs->error = XS_NOERROR;
1852 mha_done(sc, acb);
1853 #else
1854 TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain);
1855 mha_sched(sc);
1856 #endif
1857 continue;
1858 case 0x32: /* phase error in xfer progress. */
1859 SPC_MISC(("[0x32]"));
1860 #if 0
1861 case 0x65: /* invalid command.
1862 $B$J$<$3$s$J$b$N$,=P$k$N$+(B
1863 $B26$K$OA4$/M}2r$G$-$J$$(B */
1864 #if 1
1865 SPC_MISC(("[0x%04x]", r));
1866 #endif
1867 #endif
1868 case 0x54: /* initial-phase error. */
1869 SPC_MISC(("[0x54, ns=%x, ph=%x(ought to be %x)]",
1870 NSR,
1871 SCR, sc->sc_phase));
1872 /* thru */
1873 case 0x71: /* assert req */
1874 WAIT;
1875 if (SSR & 0x40) {
1876 printf("SPC sts=%2x, r=%04x, ns=%x, ph=%x\n",
1877 SSR, r, NSR, SCR);
1878 WAIT;
1879 }
1880 ph = SCR;
1881 if (sc->sc_state == SPC_SELECTING) { /* XXX msaitoh */
1882 sc->sc_state = SPC_HASNEXUS;
1883 }
1884 if (ph & 0x80) {
1885 switch (ph & PHASE_MASK) {
1886 default:
1887 printf("phase = %x\n", ph);
1888 panic("assert req: the phase I don't know!");
1889 case DATA_IN_PHASE:
1890 sc->sc_prevphase = DATA_IN_PHASE;
1891 SPC_MISC(("DATAIN(%d)...", sc->sc_dleft));
1892 n = mha_datain(sc, sc->sc_dp, sc->sc_dleft);
1893 sc->sc_dp += n;
1894 sc->sc_dleft -= n;
1895 SPC_MISC(("done\n"));
1896 continue;
1897 case DATA_OUT_PHASE:
1898 sc->sc_prevphase = DATA_OUT_PHASE;
1899 SPC_MISC(("DATAOUT\n"));
1900 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft);
1901 sc->sc_dp += n;
1902 sc->sc_dleft -= n;
1903 continue;
1904 case STATUS_PHASE:
1905 sc->sc_phase = STATUS_PHASE;
1906 SPC_MISC(("[RECV_STS]"));
1907 WAIT;
1908 CMR = CMD_RECEIVE_STS; /* receive sts */
1909 continue;
1910 case MESSAGE_IN_PHASE:
1911 sc->sc_phase = MESSAGE_IN_PHASE;
1912 WAIT;
1913 CMR = CMD_RECEIVE_MSG;
1914 continue;
1915 }
1916 }
1917 continue;
1918 }
1919 }
1920
1921 return 1;
1922 }
1923
1924 void
mha_abort(struct mha_softc * sc,struct acb * acb)1925 mha_abort(struct mha_softc *sc, struct acb *acb)
1926 {
1927 acb->flags |= ACB_ABORTED;
1928
1929 if (acb == sc->sc_nexus) {
1930 /*
1931 * If we're still selecting, the message will be scheduled
1932 * after selection is complete.
1933 */
1934 if (sc->sc_state == SPC_HASNEXUS) {
1935 sc->sc_flags |= SPC_ABORTING;
1936 mha_sched_msgout(SEND_ABORT);
1937 }
1938 } else {
1939 if (sc->sc_state == SPC_IDLE)
1940 mha_sched(sc);
1941 }
1942 }
1943
1944 void
mha_timeout(void * arg)1945 mha_timeout(void *arg)
1946 {
1947 struct acb *acb = (struct acb *)arg;
1948 struct scsipi_xfer *xs = acb->xs;
1949 struct scsipi_periph *periph = xs->xs_periph;
1950 struct mha_softc *sc =
1951 device_private(periph->periph_channel->chan_adapter->adapt_dev);
1952 int s;
1953
1954 s = splbio();
1955
1956 scsipi_printaddr(periph);
1957 printf("%s: timed out [acb %p (flags 0x%x, dleft %x, stat %x)], "
1958 "<state %d, nexus %p, phase(c %x, p %x), resid %x, msg(q %x,o %x) >",
1959 device_xname(sc->sc_dev),
1960 acb, acb->flags, acb->dleft, acb->stat,
1961 sc->sc_state, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase,
1962 sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout
1963 );
1964 printf("[%04x %02x]\n", sc->sc_ps[1], SCR);
1965 panic("timeout, ouch!");
1966
1967 if (acb->flags & ACB_ABORTED) {
1968 /* abort timed out */
1969 printf(" AGAIN\n");
1970 #if 0
1971 mha_init(sc, 1); /* XXX 1?*/
1972 #endif
1973 } else {
1974 /* abort the operation that has timed out */
1975 printf("\n");
1976 xs->error = XS_TIMEOUT;
1977 mha_abort(sc, acb);
1978 }
1979
1980 splx(s);
1981 }
1982
1983 #if SPC_DEBUG
1984 /*
1985 * The following functions are mostly used for debugging purposes, either
1986 * directly called from the driver or from the kernel debugger.
1987 */
1988
1989 void
mha_show_scsi_cmd(struct acb * acb)1990 mha_show_scsi_cmd(struct acb *acb)
1991 {
1992 u_char *b = (u_char *)&acb->cmd;
1993 struct scsipi_periph *periph = acb->xs->xs_periph;
1994 int i;
1995
1996 scsipi_printaddr(periph);
1997 if ((acb->xs->xs_control & XS_CTL_RESET) == 0) {
1998 for (i = 0; i < acb->clen; i++) {
1999 if (i)
2000 printf(",");
2001 printf("%x", b[i]);
2002 }
2003 printf("\n");
2004 } else
2005 printf("RESET\n");
2006 }
2007
2008 void
mha_print_acb(struct acb * acb)2009 mha_print_acb(struct acb *acb)
2010 {
2011
2012 printf("acb@%p xs=%p flags=%x", acb, acb->xs, acb->flags);
2013 printf(" dp=%p dleft=%d stat=%x\n",
2014 acb->daddr, acb->dleft, acb->stat);
2015 mha_show_scsi_cmd(acb);
2016 }
2017
2018 void
mha_print_active_acb(void)2019 mha_print_active_acb(void)
2020 {
2021 struct acb *acb;
2022 struct mha_softc *sc = device_lookup_private(&mha_cd, 0); /* XXX */
2023
2024 printf("ready list:\n");
2025 TAILQ_FOREACH(acb, &sc->ready_list, chain)
2026 mha_print_acb(acb);
2027 printf("nexus:\n");
2028 if (sc->sc_nexus != NULL)
2029 mha_print_acb(sc->sc_nexus);
2030 printf("nexus list:\n");
2031 TAILQ_FOREACH(acb, &sc->nexus_list, chain)
2032 mha_print_acb(acb);
2033 }
2034
2035 void
mha_dump_driver(struct mha_softc * sc)2036 mha_dump_driver(struct mha_softc *sc)
2037 {
2038 struct spc_tinfo *ti;
2039 int i;
2040
2041 printf("nexus=%p prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase);
2042 printf("state=%x msgin=%x msgpriq=%x msgoutq=%x lastmsg=%x currmsg=%x\n",
2043 sc->sc_state, sc->sc_imess[0],
2044 sc->sc_msgpriq, sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg);
2045 for (i = 0; i < 7; i++) {
2046 ti = &sc->sc_tinfo[i];
2047 printf("tinfo%d: %d cmds %d disconnects %d timeouts",
2048 i, ti->cmds, ti->dconns, ti->touts);
2049 printf(" %d senses flags=%x\n", ti->senses, ti->flags);
2050 }
2051 }
2052 #endif
2053