1 #ifndef MIPS_CPU_H
2 #define MIPS_CPU_H
3
4 #include "cpu-qom.h"
5 #include "exec/cpu-defs.h"
6 #include "fpu/softfloat-types.h"
7 #include "mips-defs.h"
8
9 #ifdef TARGET_CHERI
10 #include "cheri_defs.h"
11 #include "cheri-lazy-capregs-types.h"
12 #endif
13
14 #define TCG_GUEST_DEFAULT_MO (0)
15
16 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
17
18 /* MSA Context */
19 #define MSA_WRLEN (128)
20
21 typedef union wr_t wr_t;
22 union wr_t {
23 int8_t b[MSA_WRLEN / 8];
24 int16_t h[MSA_WRLEN / 16];
25 int32_t w[MSA_WRLEN / 32];
26 int64_t d[MSA_WRLEN / 64];
27 };
28
29 typedef union fpr_t fpr_t;
30 union fpr_t {
31 float64 fd; /* ieee double precision */
32 float32 fs[2];/* ieee single precision */
33 uint64_t d; /* binary double fixed-point */
34 uint32_t w[2]; /* binary single fixed-point */
35 /* FPU/MSA register mapping is not tested on big-endian hosts. */
36 wr_t wr; /* vector data */
37 };
38 /*
39 *define FP_ENDIAN_IDX to access the same location
40 * in the fpr_t union regardless of the host endianness
41 */
42 #if defined(HOST_WORDS_BIGENDIAN)
43 # define FP_ENDIAN_IDX 1
44 #else
45 # define FP_ENDIAN_IDX 0
46 #endif
47
48 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
49 struct CPUMIPSFPUContext {
50 /* Floating point registers */
51 fpr_t fpr[32];
52 float_status fp_status;
53 /* fpu implementation/revision register (fir) */
54 uint32_t fcr0;
55 #define FCR0_FREP 29
56 #define FCR0_UFRP 28
57 #define FCR0_HAS2008 23
58 #define FCR0_F64 22
59 #define FCR0_L 21
60 #define FCR0_W 20
61 #define FCR0_3D 19
62 #define FCR0_PS 18
63 #define FCR0_D 17
64 #define FCR0_S 16
65 #define FCR0_PRID 8
66 #define FCR0_REV 0
67 /* fcsr */
68 uint32_t fcr31_rw_bitmask;
69 uint32_t fcr31;
70 #define FCR31_FS 24
71 #define FCR31_ABS2008 19
72 #define FCR31_NAN2008 18
73 #define SET_FP_COND(num, env) do { ((env).fcr31) |= \
74 ((num) ? (1 << ((num) + 24)) : \
75 (1 << 23)); \
76 } while (0)
77 #define CLEAR_FP_COND(num, env) do { ((env).fcr31) &= \
78 ~((num) ? (1 << ((num) + 24)) : \
79 (1 << 23)); \
80 } while (0)
81 #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | \
82 (((env).fcr31 >> 23) & 0x1))
83 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
84 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
85 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
86 #define SET_FP_CAUSE(reg, v) do { (reg) = ((reg) & ~(0x3f << 12)) | \
87 ((v & 0x3f) << 12); \
88 } while (0)
89 #define SET_FP_ENABLE(reg, v) do { (reg) = ((reg) & ~(0x1f << 7)) | \
90 ((v & 0x1f) << 7); \
91 } while (0)
92 #define SET_FP_FLAGS(reg, v) do { (reg) = ((reg) & ~(0x1f << 2)) | \
93 ((v & 0x1f) << 2); \
94 } while (0)
95 #define UPDATE_FP_FLAGS(reg, v) do { (reg) |= ((v & 0x1f) << 2); } while (0)
96 #define FP_INEXACT 1
97 #define FP_UNDERFLOW 2
98 #define FP_OVERFLOW 4
99 #define FP_DIV0 8
100 #define FP_INVALID 16
101 #define FP_UNIMPLEMENTED 32
102 };
103
104 #define TARGET_INSN_START_EXTRA_WORDS 2
105
106 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
107 struct CPUMIPSMVPContext {
108 int32_t CP0_MVPControl;
109 #define CP0MVPCo_CPA 3
110 #define CP0MVPCo_STLB 2
111 #define CP0MVPCo_VPC 1
112 #define CP0MVPCo_EVP 0
113 int32_t CP0_MVPConf0;
114 #define CP0MVPC0_M 31
115 #define CP0MVPC0_TLBS 29
116 #define CP0MVPC0_GS 28
117 #define CP0MVPC0_PCP 27
118 #define CP0MVPC0_PTLBE 16
119 #define CP0MVPC0_TCA 15
120 #define CP0MVPC0_PVPE 10
121 #define CP0MVPC0_PTC 0
122 int32_t CP0_MVPConf1;
123 #define CP0MVPC1_CIM 31
124 #define CP0MVPC1_CIF 30
125 #define CP0MVPC1_PCX 20
126 #define CP0MVPC1_PCP2 10
127 #define CP0MVPC1_PCP1 0
128 };
129
130 typedef struct mips_def_t mips_def_t;
131
132 #define MIPS_SHADOW_SET_MAX 16
133 #define MIPS_TC_MAX 5
134 #define MIPS_FPU_MAX 1
135 #define MIPS_DSP_ACC 4
136 #define MIPS_KSCRATCH_NUM 6
137 #define MIPS_MAAR_MAX 16 /* Must be an even number. */
138
139 #ifdef CONFIG_MIPS_LOG_INSTR
140 struct cvtrace {
141 uint8_t version;
142 #define CVT_GPR 1 /* GPR change (val2) */
143 #define CVT_LD_GPR 2 /* Load into GPR (val2) from address (val1) */
144 #define CVT_ST_GPR 3 /* Store from GPR (val2) to address (val1) */
145 #define CVT_NO_REG 4 /* No register is changed. */
146 #define CVT_CAP 11 /* Cap change (val2,val3,val4,val5) */
147 #define CVT_LD_CAP 12 /* Load Cap (val2,val3,val4,val5) from addr (val1) */
148 #define CVT_ST_CAP 13 /* Store Cap (val2,val3,val4,val5) to addr (val1) */
149 uint8_t exception; /* 0=none, 1=TLB Mod, 2=TLB Load, 3=TLB Store, etc. */
150 uint16_t cycles; /* Currently not used. */
151 uint32_t inst; /* Encoded instruction. */
152 uint64_t pc; /* PC value of instruction. */
153 uint64_t val1; /* val1 is used for memory address. */
154 uint64_t val2; /* val2, val3, val4, val5 are used for reg content. */
155 uint64_t val3;
156 uint64_t val4;
157 uint64_t val5;
158 uint8_t thread; /* Hardware thread/CPU (i.e. cpu->cpu_index ) */
159 uint8_t asid; /* Address Space ID (i.e. CP0_TCStatus & 0xff) */
160 } __attribute__((packed));
161 typedef struct cvtrace cvtrace_t;
162
163 /* Version 3 Cheri Stream Trace header info */
164 #define CVT_QEMU_VERSION (0x80U + 3)
165 #define CVT_QEMU_MAGIC "CheriTraceV03"
166 #endif // CONFIG_MIPS_LOG_INSTR
167
168 #if defined(TARGET_CHERI)
169
170 struct cheri_cap_hwregs {
171 cap_register_t DDC; /* CapHwr 0 */
172 cap_register_t UserTlsCap; /* CapHwr 1 */
173 cap_register_t PrivTlsCap; /* CapHwr 8 */
174 cap_register_t KR1C; /* CapHwr 22 */
175 cap_register_t KR2C; /* CapHwr 23 */
176 cap_register_t ErrorEPCC; /* CapHwr 28 */
177 cap_register_t KCC; /* CapHwr 29 */
178 cap_register_t KDC; /* CapHwr 30 */
179 cap_register_t EPCC; /* CapHwr 31 */
180 };
181
182 #endif /* TARGET_CHERI */
183
184
185 /*
186 * Summary of CP0 registers
187 * ========================
188 *
189 *
190 * Register 0 Register 1 Register 2 Register 3
191 * ---------- ---------- ---------- ----------
192 *
193 * 0 Index Random EntryLo0 EntryLo1
194 * 1 MVPControl VPEControl TCStatus GlobalNumber
195 * 2 MVPConf0 VPEConf0 TCBind
196 * 3 MVPConf1 VPEConf1 TCRestart
197 * 4 VPControl YQMask TCHalt
198 * 5 VPESchedule TCContext
199 * 6 VPEScheFBack TCSchedule
200 * 7 VPEOpt TCScheFBack TCOpt
201 *
202 *
203 * Register 4 Register 5 Register 6 Register 7
204 * ---------- ---------- ---------- ----------
205 *
206 * 0 Context PageMask Wired HWREna
207 * 1 ContextConfig PageGrain SRSConf0
208 * 2 UserLocal SegCtl0 SRSConf1
209 * 3 XContextConfig SegCtl1 SRSConf2
210 * 4 DebugContextID SegCtl2 SRSConf3
211 * 5 MemoryMapID PWBase SRSConf4
212 * 6 PWField PWCtl
213 * 7 PWSize
214 *
215 *
216 * Register 8 Register 9 Register 10 Register 11
217 * ---------- ---------- ----------- -----------
218 *
219 * 0 BadVAddr Count EntryHi Compare
220 * 1 BadInstr
221 * 2 BadInstrP
222 * 3 BadInstrX
223 * 4 GuestCtl1 GuestCtl0Ext
224 * 5 GuestCtl2
225 * 6 SAARI GuestCtl3
226 * 7 SAAR
227 *
228 *
229 * Register 12 Register 13 Register 14 Register 15
230 * ----------- ----------- ----------- -----------
231 *
232 * 0 Status Cause EPC PRId
233 * 1 IntCtl EBase
234 * 2 SRSCtl NestedEPC CDMMBase
235 * 3 SRSMap CMGCRBase
236 * 4 View_IPL View_RIPL BEVVA
237 * 5 SRSMap2 NestedExc
238 * 6 GuestCtl0
239 * 7 GTOffset
240 *
241 *
242 * Register 16 Register 17 Register 18 Register 19
243 * ----------- ----------- ----------- -----------
244 *
245 * 0 Config LLAddr WatchLo0 WatchHi
246 * 1 Config1 MAAR WatchLo1 WatchHi
247 * 2 Config2 MAARI WatchLo2 WatchHi
248 * 3 Config3 WatchLo3 WatchHi
249 * 4 Config4 WatchLo4 WatchHi
250 * 5 Config5 WatchLo5 WatchHi
251 * 6 WatchLo6 WatchHi
252 * 7 WatchLo7 WatchHi
253 *
254 *
255 * Register 20 Register 21 Register 22 Register 23
256 * ----------- ----------- ----------- -----------
257 *
258 * 0 XContext Debug
259 * 1 TraceControl
260 * 2 TraceControl2
261 * 3 UserTraceData1
262 * 4 TraceIBPC
263 * 5 TraceDBPC
264 * 6 Debug2
265 * 7
266 *
267 *
268 * Register 24 Register 25 Register 26 Register 27
269 * ----------- ----------- ----------- -----------
270 *
271 * 0 DEPC PerfCnt ErrCtl CacheErr
272 * 1 PerfCnt
273 * 2 TraceControl3 PerfCnt
274 * 3 UserTraceData2 PerfCnt
275 * 4 PerfCnt
276 * 5 PerfCnt
277 * 6 PerfCnt
278 * 7 PerfCnt
279 *
280 *
281 * Register 28 Register 29 Register 30 Register 31
282 * ----------- ----------- ----------- -----------
283 *
284 * 0 DataLo DataHi ErrorEPC DESAVE
285 * 1 TagLo TagHi
286 * 2 DataLo1 DataHi1 KScratch<n>
287 * 3 TagLo1 TagHi1 KScratch<n>
288 * 4 DataLo2 DataHi2 KScratch<n>
289 * 5 TagLo2 TagHi2 KScratch<n>
290 * 6 DataLo3 DataHi3 KScratch<n>
291 * 7 TagLo3 TagHi3 KScratch<n>
292 *
293 */
294 #define CP0_REGISTER_00 0
295 #define CP0_REGISTER_01 1
296 #define CP0_REGISTER_02 2
297 #define CP0_REGISTER_03 3
298 #define CP0_REGISTER_04 4
299 #define CP0_REGISTER_05 5
300 #define CP0_REGISTER_06 6
301 #define CP0_REGISTER_07 7
302 #define CP0_REGISTER_08 8
303 #define CP0_REGISTER_09 9
304 #define CP0_REGISTER_10 10
305 #define CP0_REGISTER_11 11
306 #define CP0_REGISTER_12 12
307 #define CP0_REGISTER_13 13
308 #define CP0_REGISTER_14 14
309 #define CP0_REGISTER_15 15
310 #define CP0_REGISTER_16 16
311 #define CP0_REGISTER_17 17
312 #define CP0_REGISTER_18 18
313 #define CP0_REGISTER_19 19
314 #define CP0_REGISTER_20 20
315 #define CP0_REGISTER_21 21
316 #define CP0_REGISTER_22 22
317 #define CP0_REGISTER_23 23
318 #define CP0_REGISTER_24 24
319 #define CP0_REGISTER_25 25
320 #define CP0_REGISTER_26 26
321 #define CP0_REGISTER_27 27
322 #define CP0_REGISTER_28 28
323 #define CP0_REGISTER_29 29
324 #define CP0_REGISTER_30 30
325 #define CP0_REGISTER_31 31
326
327
328 /* CP0 Register 00 */
329 #define CP0_REG00__INDEX 0
330 #define CP0_REG00__MVPCONTROL 1
331 #define CP0_REG00__MVPCONF0 2
332 #define CP0_REG00__MVPCONF1 3
333 #define CP0_REG00__VPCONTROL 4
334 /* CP0 Register 01 */
335 #define CP0_REG01__RANDOM 0
336 #define CP0_REG01__VPECONTROL 1
337 #define CP0_REG01__VPECONF0 2
338 #define CP0_REG01__VPECONF1 3
339 #define CP0_REG01__YQMASK 4
340 #define CP0_REG01__VPESCHEDULE 5
341 #define CP0_REG01__VPESCHEFBACK 6
342 #define CP0_REG01__VPEOPT 7
343 /* CP0 Register 02 */
344 #define CP0_REG02__ENTRYLO0 0
345 #define CP0_REG02__TCSTATUS 1
346 #define CP0_REG02__TCBIND 2
347 #define CP0_REG02__TCRESTART 3
348 #define CP0_REG02__TCHALT 4
349 #define CP0_REG02__TCCONTEXT 5
350 #define CP0_REG02__TCSCHEDULE 6
351 #define CP0_REG02__TCSCHEFBACK 7
352 /* CP0 Register 03 */
353 #define CP0_REG03__ENTRYLO1 0
354 #define CP0_REG03__GLOBALNUM 1
355 #define CP0_REG03__TCOPT 7
356 /* CP0 Register 04 */
357 #define CP0_REG04__CONTEXT 0
358 #define CP0_REG04__CONTEXTCONFIG 1
359 #define CP0_REG04__USERLOCAL 2
360 #define CP0_REG04__XCONTEXTCONFIG 3
361 #define CP0_REG04__DBGCONTEXTID 4
362 #define CP0_REG04__MMID 5
363 /* CP0 Register 05 */
364 #define CP0_REG05__PAGEMASK 0
365 #define CP0_REG05__PAGEGRAIN 1
366 #define CP0_REG05__SEGCTL0 2
367 #define CP0_REG05__SEGCTL1 3
368 #define CP0_REG05__SEGCTL2 4
369 #define CP0_REG05__PWBASE 5
370 #define CP0_REG05__PWFIELD 6
371 #define CP0_REG05__PWSIZE 7
372 /* CP0 Register 06 */
373 #define CP0_REG06__WIRED 0
374 #define CP0_REG06__SRSCONF0 1
375 #define CP0_REG06__SRSCONF1 2
376 #define CP0_REG06__SRSCONF2 3
377 #define CP0_REG06__SRSCONF3 4
378 #define CP0_REG06__SRSCONF4 5
379 #define CP0_REG06__PWCTL 6
380 /* CP0 Register 07 */
381 #define CP0_REG07__HWRENA 0
382 /* CP0 Register 08 */
383 #define CP0_REG08__BADVADDR 0
384 #define CP0_REG08__BADINSTR 1
385 #define CP0_REG08__BADINSTRP 2
386 #define CP0_REG08__BADINSTRX 3
387 /* CP0 Register 09 */
388 #define CP0_REG09__COUNT 0
389 #define CP0_REG09__SAARI 6
390 #define CP0_REG09__SAAR 7
391 /* CP0 Register 10 */
392 #define CP0_REG10__ENTRYHI 0
393 #define CP0_REG10__GUESTCTL1 4
394 #define CP0_REG10__GUESTCTL2 5
395 #define CP0_REG10__GUESTCTL3 6
396 /* CP0 Register 11 */
397 #define CP0_REG11__COMPARE 0
398 #define CP0_REG11__GUESTCTL0EXT 4
399 /* CP0 Register 12 */
400 #define CP0_REG12__STATUS 0
401 #define CP0_REG12__INTCTL 1
402 #define CP0_REG12__SRSCTL 2
403 #define CP0_REG12__SRSMAP 3
404 #define CP0_REG12__VIEW_IPL 4
405 #define CP0_REG12__SRSMAP2 5
406 #define CP0_REG12__GUESTCTL0 6
407 #define CP0_REG12__GTOFFSET 7
408 /* CP0 Register 13 */
409 #define CP0_REG13__CAUSE 0
410 #define CP0_REG13__VIEW_RIPL 4
411 #define CP0_REG13__NESTEDEXC 5
412 /* CP0 Register 14 */
413 #define CP0_REG14__EPC 0
414 #define CP0_REG14__NESTEDEPC 2
415 /* CP0 Register 15 */
416 #define CP0_REG15__PRID 0
417 #define CP0_REG15__EBASE 1
418 #define CP0_REG15__CDMMBASE 2
419 #define CP0_REG15__CMGCRBASE 3
420 #define CP0_REG15__BEVVA 4
421 /* CP0 Register 16 */
422 #define CP0_REG16__CONFIG 0
423 #define CP0_REG16__CONFIG1 1
424 #define CP0_REG16__CONFIG2 2
425 #define CP0_REG16__CONFIG3 3
426 #define CP0_REG16__CONFIG4 4
427 #define CP0_REG16__CONFIG5 5
428 #define CP0_REG16__CONFIG6 6
429 #define CP0_REG16__CONFIG7 7
430 /* CP0 Register 17 */
431 #define CP0_REG17__LLADDR 0
432 #define CP0_REG17__MAAR 1
433 #define CP0_REG17__MAARI 2
434 /* CP0 Register 18 */
435 #define CP0_REG18__WATCHLO0 0
436 #define CP0_REG18__WATCHLO1 1
437 #define CP0_REG18__WATCHLO2 2
438 #define CP0_REG18__WATCHLO3 3
439 #define CP0_REG18__WATCHLO4 4
440 #define CP0_REG18__WATCHLO5 5
441 #define CP0_REG18__WATCHLO6 6
442 #define CP0_REG18__WATCHLO7 7
443 /* CP0 Register 19 */
444 #define CP0_REG19__WATCHHI0 0
445 #define CP0_REG19__WATCHHI1 1
446 #define CP0_REG19__WATCHHI2 2
447 #define CP0_REG19__WATCHHI3 3
448 #define CP0_REG19__WATCHHI4 4
449 #define CP0_REG19__WATCHHI5 5
450 #define CP0_REG19__WATCHHI6 6
451 #define CP0_REG19__WATCHHI7 7
452 /* CP0 Register 20 */
453 #define CP0_REG20__XCONTEXT 0
454 /* CP0 Register 21 */
455 /* CP0 Register 22 */
456 /* CP0 Register 23 */
457 #define CP0_REG23__DEBUG 0
458 #define CP0_REG23__TRACECONTROL 1
459 #define CP0_REG23__TRACECONTROL2 2
460 #define CP0_REG23__USERTRACEDATA1 3
461 #define CP0_REG23__TRACEIBPC 4
462 #define CP0_REG23__TRACEDBPC 5
463 #define CP0_REG23__DEBUG2 6
464 /* CP0 Register 24 */
465 #define CP0_REG24__DEPC 0
466 /* CP0 Register 25 */
467 #define CP0_REG25__PERFCTL0 0
468 #define CP0_REG25__PERFCNT0 1
469 #define CP0_REG25__PERFCTL1 2
470 #define CP0_REG25__PERFCNT1 3
471 #define CP0_REG25__PERFCTL2 4
472 #define CP0_REG25__PERFCNT2 5
473 #define CP0_REG25__PERFCTL3 6
474 #define CP0_REG25__PERFCNT3 7
475 /* CP0 Register 26 */
476 #define CP0_REG26__ERRCTL 0
477 /* CP0 Register 27 */
478 #define CP0_REG27__CACHERR 0
479 /* CP0 Register 28 */
480 #define CP0_REG28__TAGLO 0
481 #define CP0_REG28__DATALO 1
482 #define CP0_REG28__TAGLO1 2
483 #define CP0_REG28__DATALO1 3
484 #define CP0_REG28__TAGLO2 4
485 #define CP0_REG28__DATALO2 5
486 #define CP0_REG28__TAGLO3 6
487 #define CP0_REG28__DATALO3 7
488 /* CP0 Register 29 */
489 #define CP0_REG29__TAGHI 0
490 #define CP0_REG29__DATAHI 1
491 #define CP0_REG29__TAGHI1 2
492 #define CP0_REG29__DATAHI1 3
493 #define CP0_REG29__TAGHI2 4
494 #define CP0_REG29__DATAHI2 5
495 #define CP0_REG29__TAGHI3 6
496 #define CP0_REG29__DATAHI3 7
497 /* CP0 Register 30 */
498 #define CP0_REG30__ERROREPC 0
499 /* CP0 Register 31 */
500 #define CP0_REG31__DESAVE 0
501 #define CP0_REG31__KSCRATCH1 2
502 #define CP0_REG31__KSCRATCH2 3
503 #define CP0_REG31__KSCRATCH3 4
504 #define CP0_REG31__KSCRATCH4 5
505 #define CP0_REG31__KSCRATCH5 6
506 #define CP0_REG31__KSCRATCH6 7
507
508
509 typedef struct TCState TCState;
510 struct TCState {
511 target_ulong gpr[32];
512 #ifdef TARGET_CHERI
513 cap_register_t PCC;
514 cap_register_t CapBranchTarget; /* Target of the next cjr/cjalr/ccall */
515 #else
516 target_ulong PC;
517 #endif
518
519 #ifdef CONFIG_DEBUG_TCG
520 target_ulong _pc_is_current;
521 #endif
522 target_ulong HI[MIPS_DSP_ACC];
523 target_ulong LO[MIPS_DSP_ACC];
524 target_ulong ACX[MIPS_DSP_ACC];
525 target_ulong DSPControl;
526
527 #if defined(TARGET_CHERI)
528 struct GPCapRegs gpcapregs;
529 struct cheri_cap_hwregs CHWR;
530 // #define CP2CAP_RCC 24 /* Return Code Capability */
531 #define CP2CAP_IDC 26 /* Invoked Data Capability */
532 // #define CP2CAP_EPCC_FAKE_OFFSET_VALUE 0xe9cce9cce9cce9cc /* cr_offset should not be used for EPCC */
533 #endif /* TARGET_CHERI */
534
535 int32_t CP0_TCStatus;
536 #define CP0TCSt_TCU3 31
537 #define CP0TCSt_TCU2 30
538 #define CP0TCSt_TCU1 29
539 #define CP0TCSt_TCU0 28
540 #define CP0TCSt_TMX 27
541 #define CP0TCSt_RNST 23
542 #define CP0TCSt_TDS 21
543 #define CP0TCSt_DT 20
544 #define CP0TCSt_DA 15
545 #define CP0TCSt_A 13
546 #define CP0TCSt_TKSU 11
547 #define CP0TCSt_IXMT 10
548 #define CP0TCSt_TASID 0
549 int32_t CP0_TCBind;
550 #define CP0TCBd_CurTC 21
551 #define CP0TCBd_TBE 17
552 #define CP0TCBd_CurVPE 0
553 target_ulong CP0_TCHalt;
554 target_ulong CP0_TCContext;
555 target_ulong CP0_TCSchedule;
556 target_ulong CP0_TCScheFBack;
557 int32_t CP0_Debug_tcstatus;
558 target_ulong CP0_UserLocal;
559
560 int32_t msacsr;
561
562 #define MSACSR_FS 24
563 #define MSACSR_FS_MASK (1 << MSACSR_FS)
564 #define MSACSR_NX 18
565 #define MSACSR_NX_MASK (1 << MSACSR_NX)
566 #define MSACSR_CEF 2
567 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)
568 #define MSACSR_RM 0
569 #define MSACSR_RM_MASK (0x3 << MSACSR_RM)
570 #define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \
571 MSACSR_FS_MASK)
572
573 float_status msa_fp_status;
574
575 /* Upper 64-bit MMRs (multimedia registers); the lower 64-bit are GPRs */
576 uint64_t mmr[32];
577
578 #define NUMBER_OF_MXU_REGISTERS 16
579 target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
580 target_ulong mxu_cr;
581 #define MXU_CR_LC 31
582 #define MXU_CR_RC 30
583 #define MXU_CR_BIAS 2
584 #define MXU_CR_RD_EN 1
585 #define MXU_CR_MXU_EN 0
586
587 };
588
589
590 #if defined(TARGET_CHERI)
591 #define CP2HWR_BASE_INDEX 0
592 // TODO: start at 32: #define CP2HWR_BASE_NUM 32
593
594 enum CP2HWR {
595 CP2HWR_DDC = CP2HWR_BASE_INDEX + 0, /* Default Data Capability */
596 CP2HWR_USER_TLS = CP2HWR_BASE_INDEX + 1, /* Unprivileged TLS Cap */
597 CP2HWR_PRIV_TLS = CP2HWR_BASE_INDEX + 8, /* Privileged TLS Cap */
598 CP2HWR_K1RC = CP2HWR_BASE_INDEX + 22, /* Reserved Kernel Cap #1 */
599 CP2HWR_K2RC = CP2HWR_BASE_INDEX + 23, /* Reserved Kernel Cap #2 */
600 CP2HWR_ErrorEPCC = CP2HWR_BASE_INDEX + 28, /* Error Exception PC Capability */
601 CP2HWR_KCC = CP2HWR_BASE_INDEX + 29, /* Kernel Code Capability */
602 CP2HWR_KDC = CP2HWR_BASE_INDEX + 30, /* Kernel Data Capability */
603 CP2HWR_EPCC = CP2HWR_BASE_INDEX + 31, /* Exception PC Capability */
604 };
605
606 #endif
607
608 struct MIPSITUState;
609 typedef struct CPUMIPSState CPUMIPSState;
610 struct CPUMIPSState {
611 TCState active_tc;
612 CPUMIPSFPUContext active_fpu;
613
614 uint32_t current_tc;
615 uint32_t current_fpu;
616
617 uint32_t SEGBITS;
618 uint32_t PABITS;
619 #if defined(TARGET_MIPS64)
620 # define PABITS_BASE 36
621 #else
622 # define PABITS_BASE 32
623 #endif
624 target_ulong SEGMask;
625 uint64_t PAMask;
626 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)
627
628 int32_t msair;
629 #define MSAIR_ProcID 8
630 #define MSAIR_Rev 0
631
632 /*
633 * CP0 Register 0
634 */
635 int32_t CP0_Index;
636 /* CP0_MVP* are per MVP registers. */
637 int32_t CP0_VPControl;
638 #define CP0VPCtl_DIS 0
639 /*
640 * CP0 Register 1
641 */
642 int32_t CP0_Random;
643 int32_t CP0_VPEControl;
644 #define CP0VPECo_YSI 21
645 #define CP0VPECo_GSI 20
646 #define CP0VPECo_EXCPT 16
647 #define CP0VPECo_TE 15
648 #define CP0VPECo_TargTC 0
649 int32_t CP0_VPEConf0;
650 #define CP0VPEC0_M 31
651 #define CP0VPEC0_XTC 21
652 #define CP0VPEC0_TCS 19
653 #define CP0VPEC0_SCS 18
654 #define CP0VPEC0_DSC 17
655 #define CP0VPEC0_ICS 16
656 #define CP0VPEC0_MVP 1
657 #define CP0VPEC0_VPA 0
658 int32_t CP0_VPEConf1;
659 #define CP0VPEC1_NCX 20
660 #define CP0VPEC1_NCP2 10
661 #define CP0VPEC1_NCP1 0
662 target_ulong CP0_YQMask;
663 target_ulong CP0_VPESchedule;
664 target_ulong CP0_VPEScheFBack;
665 int32_t CP0_VPEOpt;
666 #define CP0VPEOpt_IWX7 15
667 #define CP0VPEOpt_IWX6 14
668 #define CP0VPEOpt_IWX5 13
669 #define CP0VPEOpt_IWX4 12
670 #define CP0VPEOpt_IWX3 11
671 #define CP0VPEOpt_IWX2 10
672 #define CP0VPEOpt_IWX1 9
673 #define CP0VPEOpt_IWX0 8
674 #define CP0VPEOpt_DWX7 7
675 #define CP0VPEOpt_DWX6 6
676 #define CP0VPEOpt_DWX5 5
677 #define CP0VPEOpt_DWX4 4
678 #define CP0VPEOpt_DWX3 3
679 #define CP0VPEOpt_DWX2 2
680 #define CP0VPEOpt_DWX1 1
681 #define CP0VPEOpt_DWX0 0
682 /*
683 * CP0 Register 2
684 */
685 uint64_t CP0_EntryLo0;
686 /*
687 * CP0 Register 3
688 */
689 uint64_t CP0_EntryLo1;
690 #if defined(TARGET_MIPS64)
691 #if defined(TARGET_CHERI)
692 # define CP0EnLo_S 63
693 # define CP0EnLo_L 62
694 # define CP0EnLo_CLG 61
695 #else
696 # define CP0EnLo_RI 63
697 # define CP0EnLo_XI 62
698 #endif /* TARGET_CHERI */
699 #else
700 # define CP0EnLo_RI 31
701 # define CP0EnLo_XI 30
702 #endif
703 int32_t CP0_GlobalNumber;
704 #define CP0GN_VPId 0
705 /*
706 * CP0 Register 4
707 */
708 target_ulong CP0_Context;
709 int32_t CP0_MemoryMapID;
710 /*
711 * CP0 Register 5
712 */
713 int32_t CP0_PageMask;
714 int32_t CP0_PageGrain_rw_bitmask;
715 int32_t CP0_PageGrain;
716 #define CP0PG_RIE 31
717 #define CP0PG_XIE 30
718 #define CP0PG_ELPA 29
719 #define CP0PG_IEC 27
720 target_ulong CP0_SegCtl0;
721 target_ulong CP0_SegCtl1;
722 target_ulong CP0_SegCtl2;
723 #define CP0SC_PA 9
724 #define CP0SC_PA_MASK (0x7FULL << CP0SC_PA)
725 #define CP0SC_PA_1GMASK (0x7EULL << CP0SC_PA)
726 #define CP0SC_AM 4
727 #define CP0SC_AM_MASK (0x7ULL << CP0SC_AM)
728 #define CP0SC_AM_UK 0ULL
729 #define CP0SC_AM_MK 1ULL
730 #define CP0SC_AM_MSK 2ULL
731 #define CP0SC_AM_MUSK 3ULL
732 #define CP0SC_AM_MUSUK 4ULL
733 #define CP0SC_AM_USK 5ULL
734 #define CP0SC_AM_UUSK 7ULL
735 #define CP0SC_EU 3
736 #define CP0SC_EU_MASK (1ULL << CP0SC_EU)
737 #define CP0SC_C 0
738 #define CP0SC_C_MASK (0x7ULL << CP0SC_C)
739 #define CP0SC_MASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \
740 CP0SC_PA_MASK)
741 #define CP0SC_1GMASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \
742 CP0SC_PA_1GMASK)
743 #define CP0SC0_MASK (CP0SC_MASK | (CP0SC_MASK << 16))
744 #define CP0SC1_XAM 59
745 #define CP0SC1_XAM_MASK (0x7ULL << CP0SC1_XAM)
746 #define CP0SC1_MASK (CP0SC_MASK | (CP0SC_MASK << 16) | CP0SC1_XAM_MASK)
747 #define CP0SC2_XR 56
748 #define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR)
749 #define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK)
750 target_ulong CP0_PWBase;
751 target_ulong CP0_PWField;
752 #if defined(TARGET_MIPS64)
753 #define CP0PF_BDI 32 /* 37..32 */
754 #define CP0PF_GDI 24 /* 29..24 */
755 #define CP0PF_UDI 18 /* 23..18 */
756 #define CP0PF_MDI 12 /* 17..12 */
757 #define CP0PF_PTI 6 /* 11..6 */
758 #define CP0PF_PTEI 0 /* 5..0 */
759 #else
760 #define CP0PF_GDW 24 /* 29..24 */
761 #define CP0PF_UDW 18 /* 23..18 */
762 #define CP0PF_MDW 12 /* 17..12 */
763 #define CP0PF_PTW 6 /* 11..6 */
764 #define CP0PF_PTEW 0 /* 5..0 */
765 #endif
766 target_ulong CP0_PWSize;
767 #if defined(TARGET_MIPS64)
768 #define CP0PS_BDW 32 /* 37..32 */
769 #endif
770 #define CP0PS_PS 30
771 #define CP0PS_GDW 24 /* 29..24 */
772 #define CP0PS_UDW 18 /* 23..18 */
773 #define CP0PS_MDW 12 /* 17..12 */
774 #define CP0PS_PTW 6 /* 11..6 */
775 #define CP0PS_PTEW 0 /* 5..0 */
776 /*
777 * CP0 Register 6
778 */
779 int32_t CP0_Wired;
780 int32_t CP0_PWCtl;
781 #define CP0PC_PWEN 31
782 #if defined(TARGET_MIPS64)
783 #define CP0PC_PWDIREXT 30
784 #define CP0PC_XK 28
785 #define CP0PC_XS 27
786 #define CP0PC_XU 26
787 #endif
788 #define CP0PC_DPH 7
789 #define CP0PC_HUGEPG 6
790 #define CP0PC_PSN 0 /* 5..0 */
791 int32_t CP0_SRSConf0_rw_bitmask;
792 int32_t CP0_SRSConf0;
793 #define CP0SRSC0_M 31
794 #define CP0SRSC0_SRS3 20
795 #define CP0SRSC0_SRS2 10
796 #define CP0SRSC0_SRS1 0
797 int32_t CP0_SRSConf1_rw_bitmask;
798 int32_t CP0_SRSConf1;
799 #define CP0SRSC1_M 31
800 #define CP0SRSC1_SRS6 20
801 #define CP0SRSC1_SRS5 10
802 #define CP0SRSC1_SRS4 0
803 int32_t CP0_SRSConf2_rw_bitmask;
804 int32_t CP0_SRSConf2;
805 #define CP0SRSC2_M 31
806 #define CP0SRSC2_SRS9 20
807 #define CP0SRSC2_SRS8 10
808 #define CP0SRSC2_SRS7 0
809 int32_t CP0_SRSConf3_rw_bitmask;
810 int32_t CP0_SRSConf3;
811 #define CP0SRSC3_M 31
812 #define CP0SRSC3_SRS12 20
813 #define CP0SRSC3_SRS11 10
814 #define CP0SRSC3_SRS10 0
815 int32_t CP0_SRSConf4_rw_bitmask;
816 int32_t CP0_SRSConf4;
817 #define CP0SRSC4_SRS15 20
818 #define CP0SRSC4_SRS14 10
819 #define CP0SRSC4_SRS13 0
820 /*
821 * CP0 Register 7
822 */
823 int32_t CP0_HWREna;
824 /*
825 * CP0 Register 8
826 */
827 target_ulong CP0_BadVAddr;
828 uint32_t CP0_BadInstr;
829 uint32_t CP0_BadInstrP;
830 uint32_t CP0_BadInstrX;
831 /*
832 * CP0 Register 9
833 */
834 int32_t CP0_Count;
835 uint32_t CP0_SAARI;
836 #define CP0SAARI_TARGET 0 /* 5..0 */
837 uint64_t CP0_SAAR[2];
838 #define CP0SAAR_BASE 12 /* 43..12 */
839 #define CP0SAAR_SIZE 1 /* 5..1 */
840 #define CP0SAAR_EN 0
841 /*
842 * CP0 Register 10
843 */
844 target_ulong CP0_EntryHi;
845 #define CP0EnHi_EHINV 10
846 #if defined(TARGET_CHERI)
847 #define CP0EnHi_CLGK 61
848 #define CP0EnHi_CLGS 60
849 #define CP0EnHi_CLGU 59
850 #endif
851 target_ulong CP0_EntryHi_ASID_mask;
852 /*
853 * CP0 Register 11
854 */
855 int32_t CP0_Compare;
856 /*
857 * CP0 Register 12
858 */
859 int32_t CP0_Status;
860 #define CP0St_CU3 31
861 #define CP0St_CU2 30
862 #define CP0St_CU1 29
863 #define CP0St_CU0 28
864 #define CP0St_RP 27
865 #define CP0St_FR 26
866 #define CP0St_RE 25
867 #define CP0St_MX 24
868 #define CP0St_PX 23
869 #define CP0St_BEV 22
870 #define CP0St_TS 21
871 #define CP0St_SR 20
872 #define CP0St_NMI 19
873 #define CP0St_IM 8
874 #define CP0St_KX 7
875 #define CP0St_SX 6
876 #define CP0St_UX 5
877 #define CP0St_KSU 3
878 #define CP0St_ERL 2
879 #define CP0St_EXL 1
880 #define CP0St_IE 0
881 int32_t CP0_IntCtl;
882 #define CP0IntCtl_IPTI 29
883 #define CP0IntCtl_IPPCI 26
884 #define CP0IntCtl_VS 5
885 int32_t CP0_SRSCtl;
886 #define CP0SRSCtl_HSS 26
887 #define CP0SRSCtl_EICSS 18
888 #define CP0SRSCtl_ESS 12
889 #define CP0SRSCtl_PSS 6
890 #define CP0SRSCtl_CSS 0
891 int32_t CP0_SRSMap;
892 #define CP0SRSMap_SSV7 28
893 #define CP0SRSMap_SSV6 24
894 #define CP0SRSMap_SSV5 20
895 #define CP0SRSMap_SSV4 16
896 #define CP0SRSMap_SSV3 12
897 #define CP0SRSMap_SSV2 8
898 #define CP0SRSMap_SSV1 4
899 #define CP0SRSMap_SSV0 0
900 /*
901 * CP0 Register 13
902 */
903 int32_t CP0_Cause;
904 #define CP0Ca_BD 31
905 #define CP0Ca_TI 30
906 #define CP0Ca_CE 28
907 #define CP0Ca_DC 27
908 #define CP0Ca_PCI 26
909 #define CP0Ca_IV 23
910 #define CP0Ca_WP 22
911 #define CP0Ca_IP 8
912 #define CP0Ca_IP_mask 0x0000FF00
913 #define CP0Ca_EC 2
914 /*
915 * CP0 Register 14
916 */
917 #if !defined(TARGET_CHERI)
918 /* We use EPCC for TARGET_CHERI */
919 target_ulong CP0_EPC;
920 #endif
921 /*
922 * CP0 Register 15
923 */
924 int32_t CP0_PRid;
925 target_ulong CP0_EBase;
926 target_ulong CP0_EBaseWG_rw_bitmask;
927 #define CP0EBase_WG 11
928 target_ulong CP0_CMGCRBase;
929 /*
930 * CP0 Register 16
931 */
932 int32_t CP0_Config0;
933 #define CP0C0_M 31
934 #define CP0C0_K23 28 /* 30..28 */
935 #define CP0C0_KU 25 /* 27..25 */
936 #define CP0C0_MDU 20
937 #define CP0C0_MM 18
938 #define CP0C0_BM 16
939 #define CP0C0_Impl 16 /* 24..16 */
940 #define CP0C0_BE 15
941 #define CP0C0_AT 13 /* 14..13 */
942 #define CP0C0_AR 10 /* 12..10 */
943 #define CP0C0_MT 7 /* 9..7 */
944 #define CP0C0_VI 3
945 #define CP0C0_K0 0 /* 2..0 */
946 int32_t CP0_Config1;
947 #define CP0C1_M 31
948 #define CP0C1_MMU 25 /* 30..25 */
949 #define CP0C1_IS 22 /* 24..22 */
950 #define CP0C1_IL 19 /* 21..19 */
951 #define CP0C1_IA 16 /* 18..16 */
952 #define CP0C1_DS 13 /* 15..13 */
953 #define CP0C1_DL 10 /* 12..10 */
954 #define CP0C1_DA 7 /* 9..7 */
955 #define CP0C1_C2 6
956 #define CP0C1_MD 5
957 #define CP0C1_PC 4
958 #define CP0C1_WR 3
959 #define CP0C1_CA 2
960 #define CP0C1_EP 1
961 #define CP0C1_FP 0
962 int32_t CP0_Config2;
963 #define CP0C2_M 31
964 #define CP0C2_TU 28 /* 30..28 */
965 #define CP0C2_TS 24 /* 27..24 */
966 #define CP0C2_TL 20 /* 23..20 */
967 #define CP0C2_TA 16 /* 19..16 */
968 #define CP0C2_SU 12 /* 15..12 */
969 #define CP0C2_SS 8 /* 11..8 */
970 #define CP0C2_SL 4 /* 7..4 */
971 #define CP0C2_SA 0 /* 3..0 */
972 int32_t CP0_Config3;
973 #define CP0C3_M 31
974 #define CP0C3_BPG 30
975 #define CP0C3_CMGCR 29
976 #define CP0C3_MSAP 28
977 #define CP0C3_BP 27
978 #define CP0C3_BI 26
979 #define CP0C3_SC 25
980 #define CP0C3_PW 24
981 #define CP0C3_VZ 23
982 #define CP0C3_IPLV 21 /* 22..21 */
983 #define CP0C3_MMAR 18 /* 20..18 */
984 #define CP0C3_MCU 17
985 #define CP0C3_ISA_ON_EXC 16
986 #define CP0C3_ISA 14 /* 15..14 */
987 #define CP0C3_ULRI 13
988 #define CP0C3_RXI 12
989 #define CP0C3_DSP2P 11
990 #define CP0C3_DSPP 10
991 #define CP0C3_CTXTC 9
992 #define CP0C3_ITL 8
993 #define CP0C3_LPA 7
994 #define CP0C3_VEIC 6
995 #define CP0C3_VInt 5
996 #define CP0C3_SP 4
997 #define CP0C3_CDMM 3
998 #define CP0C3_MT 2
999 #define CP0C3_SM 1
1000 #define CP0C3_TL 0
1001 int32_t CP0_Config4;
1002 int32_t CP0_Config4_rw_bitmask;
1003 #define CP0C4_M 31
1004 #define CP0C4_IE 29 /* 30..29 */
1005 #define CP0C4_AE 28
1006 #define CP0C4_VTLBSizeExt 24 /* 27..24 */
1007 #define CP0C4_KScrExist 16
1008 #define CP0C4_MMUExtDef 14
1009 #define CP0C4_FTLBPageSize 8 /* 12..8 */
1010 /* bit layout if MMUExtDef=1 */
1011 #define CP0C4_MMUSizeExt 0 /* 7..0 */
1012 /* bit layout if MMUExtDef=2 */
1013 #define CP0C4_FTLBWays 4 /* 7..4 */
1014 #define CP0C4_FTLBSets 0 /* 3..0 */
1015 int32_t CP0_Config5;
1016 int32_t CP0_Config5_rw_bitmask;
1017 #define CP0C5_M 31
1018 #define CP0C5_K 30
1019 #define CP0C5_CV 29
1020 #define CP0C5_EVA 28
1021 #define CP0C5_MSAEn 27
1022 #define CP0C5_PMJ 23 /* 25..23 */
1023 #define CP0C5_WR2 22
1024 #define CP0C5_NMS 21
1025 #define CP0C5_ULS 20
1026 #define CP0C5_XPA 19
1027 #define CP0C5_CRCP 18
1028 #define CP0C5_MI 17
1029 #define CP0C5_GI 15 /* 16..15 */
1030 #define CP0C5_CA2 14
1031 #define CP0C5_XNP 13
1032 #define CP0C5_DEC 11
1033 #define CP0C5_L2C 10
1034 #define CP0C5_UFE 9
1035 #define CP0C5_FRE 8
1036 #define CP0C5_VP 7
1037 #define CP0C5_SBRI 6
1038 #define CP0C5_MVH 5
1039 #define CP0C5_LLB 4
1040 #define CP0C5_MRP 3
1041 #define CP0C5_UFR 2
1042 #define CP0C5_NFExists 0
1043 int32_t CP0_Config6;
1044 int32_t CP0_Config7;
1045 uint64_t CP0_LLAddr;
1046 uint64_t CP0_MAAR[MIPS_MAAR_MAX];
1047 int32_t CP0_MAARI;
1048 /* XXX: Maybe make LLAddr per-TC? */
1049 /*
1050 * CP0 Register 17
1051 */
1052 target_ulong lladdr; /* LL virtual address compared against SC */
1053 target_ulong llval;
1054 uint64_t llval_wp;
1055 uint32_t llnewval_wp;
1056 #ifdef TARGET_CHERI
1057 uint64_t linkedflag; // TODO: remove this!
1058 #endif
1059 uint64_t CP0_LLAddr_rw_bitmask;
1060 int CP0_LLAddr_shift;
1061 /*
1062 * CP0 Register 18
1063 */
1064 target_ulong CP0_WatchLo[8];
1065 /*
1066 * CP0 Register 19
1067 */
1068 uint64_t CP0_WatchHi[8];
1069 #define CP0WH_ASID 16
1070 /*
1071 * CP0 Register 20
1072 */
1073 target_ulong CP0_XContext;
1074 int32_t CP0_Framemask;
1075 /*
1076 * CP0 Register 23
1077 */
1078 int32_t CP0_Debug;
1079 #define CP0DB_DBD 31
1080 #define CP0DB_DM 30
1081 #define CP0DB_LSNM 28
1082 #define CP0DB_Doze 27
1083 #define CP0DB_Halt 26
1084 #define CP0DB_CNT 25
1085 #define CP0DB_IBEP 24
1086 #define CP0DB_DBEP 21
1087 #define CP0DB_IEXI 20
1088 #define CP0DB_VER 15
1089 #define CP0DB_DEC 10
1090 #define CP0DB_SSt 8
1091 #define CP0DB_DINT 5
1092 #define CP0DB_DIB 4
1093 #define CP0DB_DDBS 3
1094 #define CP0DB_DDBL 2
1095 #define CP0DB_DBp 1
1096 #define CP0DB_DSS 0
1097 /*
1098 * CP0 Register 24
1099 */
1100 target_ulong CP0_DEPC;
1101 /*
1102 * CP0 Register 25
1103 */
1104 int32_t CP0_Performance0;
1105 /*
1106 * CP0 Register 26
1107 */
1108 int32_t CP0_ErrCtl;
1109 #define CP0EC_WST 29
1110 #define CP0EC_SPR 28
1111 #define CP0EC_ITC 26
1112 /*
1113 * CP0 Register 28
1114 */
1115 uint64_t CP0_TagLo;
1116 int32_t CP0_DataLo;
1117 /*
1118 * CP0 Register 29
1119 */
1120 int32_t CP0_TagHi;
1121 int32_t CP0_DataHi;
1122 /*
1123 * CP0 Register 30
1124 */
1125 #if !defined(TARGET_CHERI)
1126 /* We use ErrorEPCC for TARGET_CHERI */
1127 target_ulong CP0_ErrorEPC;
1128 #endif
1129 /*
1130 * CP0 Register 31
1131 */
1132 int32_t CP0_DESAVE;
1133 target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
1134
1135 /* We waste some space so we can handle shadow registers like TCs. */
1136 TCState tcs[MIPS_SHADOW_SET_MAX];
1137 CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
1138 /* QEMU */
1139 int error_code;
1140 #define EXCP_TLB_NOMATCH 0x1
1141 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
1142 uint32_t hflags; /* CPU State */
1143 /* TMASK defines different execution modes */
1144 #ifdef TARGET_CHERI
1145 #define MIPS_HFLAG_TMASK 0x3F5807FF
1146 #else
1147 #define MIPS_HFLAG_TMASK 0x1F5807FF
1148 #endif /* TARGET_CHERI */
1149 #define MIPS_HFLAG_MODE 0x00007 /* execution modes */
1150 /*
1151 * The KSU flags must be the lowest bits in hflags. The flag order
1152 * must be the same as defined for CP0 Status. This allows to use
1153 * the bits as the value of mmu_idx.
1154 */
1155 #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */
1156 #define MIPS_HFLAG_UM 0x00002 /* user mode flag */
1157 #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */
1158 #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */
1159 #define MIPS_HFLAG_DM 0x00004 /* Debug mode */
1160 #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */
1161 #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */
1162 #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */
1163 #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */
1164 /*
1165 * True if the MIPS IV COP1X instructions can be used. This also
1166 * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
1167 * and RSQRT.D.
1168 */
1169 #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */
1170 #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */
1171 #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */
1172 #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */
1173 #define MIPS_HFLAG_M16_SHIFT 10
1174 /*
1175 * If translation is interrupted between the branch instruction and
1176 * the delay slot, record what type of branch it is so that we can
1177 * resume translation properly. It might be possible to reduce
1178 * this from three bits to two.
1179 */
1180 #define MIPS_HFLAG_BMASK_BASE 0x803800
1181 #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */
1182 #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */
1183 #define MIPS_HFLAG_BL 0x01800 /* Likely branch */
1184 #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */
1185 #ifdef TARGET_CHERI
1186 #define MIPS_HFLAG_BRC 0x02800 /* branch to register and load PCC */
1187 #define MIPS_HFLAG_BRCCALL 0x03000 /* ccall load PCC and IDC */
1188 #endif /* TARGET_CHERI */
1189 /* Extra flags about the current pending branch. */
1190 #define MIPS_HFLAG_BMASK_EXT 0x7C000
1191 #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */
1192 #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */
1193 #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */
1194 #define MIPS_HFLAG_BDS_STRICT 0x20000 /* Strict delay slot size */
1195 #define MIPS_HFLAG_BX 0x40000 /* branch exchanges execution mode */
1196 #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
1197 /* MIPS DSP resources access. */
1198 #define MIPS_HFLAG_DSP 0x080000 /* Enable access to DSP resources. */
1199 #define MIPS_HFLAG_DSP_R2 0x100000 /* Enable access to DSP R2 resources. */
1200 #define MIPS_HFLAG_DSP_R3 0x20000000 /* Enable access to DSP R3 resources. */
1201 /* Extra flag about HWREna register. */
1202 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
1203 #define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */
1204 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot */
1205 #define MIPS_HFLAG_MSA 0x1000000
1206 #define MIPS_HFLAG_FRE 0x2000000 /* FRE enabled */
1207 #define MIPS_HFLAG_ELPA 0x4000000
1208 #define MIPS_HFLAG_ITC_CACHE 0x8000000 /* CACHE instr. operates on ITC tag */
1209 #define MIPS_HFLAG_ERL 0x10000000 /* error level flag */
1210 #ifdef TARGET_CHERI
1211 #define MIPS_HFLAG_COP2X 0x20000000 /* CHERI/CP2 enabled */
1212 #endif /* TARGET_CHERI */
1213 target_ulong btarget; /* Jump / branch target */
1214 target_ulong bcond; /* Branch condition (if needed) */
1215
1216 int SYNCI_Step; /* Address step size for SYNCI */
1217 int CCRes; /* Cycle count resolution/divisor */
1218 uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
1219 uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
1220 uint64_t insn_flags; /* Supported instruction set */
1221 int saarp;
1222
1223
1224
1225 /* BERI Statcounters: */
1226 uint64_t statcounters_icount_user;
1227 uint64_t statcounters_icount_kernel;
1228 /* The other ones are CHERI only for now */
1229 #if defined(TARGET_CHERI)
1230 uint64_t statcounters_itlb_miss;
1231 uint64_t statcounters_dtlb_miss;
1232 uint64_t statcounters_cap_read;
1233 uint64_t statcounters_cap_read_tagged;
1234 uint64_t statcounters_cap_write;
1235 uint64_t statcounters_cap_write_tagged;
1236
1237 uint64_t statcounters_imprecise_setbounds;
1238 uint64_t statcounters_unrepresentable_caps;
1239 /* TODO: we could implement the TLB ones as well */
1240
1241 /*
1242 * See section 3.9.2 (Table 3.3) of the CHERI Architecture Reference v7.
1243 */
1244 uint16_t CP2_CapCause; /* Upper 8 bits exception code; lower reg# */
1245 /* See cheri-archspecific.h */
1246
1247 #define MASK_CCALL_SEL(op) ((op) & 0x7ff)
1248 #define CCALL_SELECTOR_0 (0x0)
1249 #define CCALL_SELECTOR_1 (0x01)
1250 #define CCALL_SELECTOR_CRETURN (0x7ff)
1251
1252 #endif /* TARGET_CHERI */
1253
1254 #ifdef CONFIG_MIPS_LOG_INSTR
1255 #define TRACE_MODE_USER "User mode"
1256 const char *last_mode;
1257 #define IN_USERSPACE(env) ((env->hflags & MIPS_HFLAG_UM) == MIPS_HFLAG_UM)
1258 #endif /* CONFIG_MIPS_LOG_INSTR */
1259
1260 /* Fields up to this point are cleared by a CPU reset */
1261 struct {} end_reset_fields;
1262
1263 /* Fields from here on are preserved across CPU reset. */
1264 CPUMIPSMVPContext *mvp;
1265 #if !defined(CONFIG_USER_ONLY)
1266 CPUMIPSTLBContext *tlb;
1267 #endif
1268
1269 const mips_def_t *cpu_model;
1270 void *irq[8];
1271 QEMUTimer *timer; /* Internal timer */
1272 struct MIPSITUState *itu;
1273 MemoryRegion *itc_tag; /* ITC Configuration Tags */
1274 #ifdef CONFIG_MIPS_LOG_INSTR
1275 /*
1276 * Processor state after the last instruction.
1277 * Used for instruction tracing.
1278 */
1279 target_ulong last_gpr[32];
1280 target_ulong last_cop0[32*8];
1281 #ifdef TARGET_CHERI
1282 cap_register_t last_C[32];
1283 cap_register_t last_CapBranchTarget;
1284 struct cheri_cap_hwregs last_CHWR;
1285 #endif // TARGET_CHERI
1286
1287 cvtrace_t cvtrace;
1288 #endif /* CONFIG_MIPS_LOG_INSTR */
1289 target_ulong exception_base; /* ExceptionBase input to the core */
1290 };
1291
1292 /**
1293 * MIPSCPU:
1294 * @env: #CPUMIPSState
1295 *
1296 * A MIPS CPU.
1297 */
1298 struct MIPSCPU {
1299 /*< private >*/
1300 CPUState parent_obj;
1301 /*< public >*/
1302
1303 CPUNegativeOffsetState neg;
1304 CPUMIPSState env;
1305 };
1306
1307
1308 void mips_cpu_list(void);
1309
1310 #define cpu_signal_handler cpu_mips_signal_handler
1311 #define cpu_list mips_cpu_list
1312
1313 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
1314 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
1315
1316 /*
1317 * MMU modes definitions. We carefully match the indices with our
1318 * hflags layout.
1319 */
1320 #define MMU_USER_IDX 2
1321
hflags_mmu_index(uint32_t hflags)1322 static inline int hflags_mmu_index(uint32_t hflags)
1323 {
1324 if (hflags & MIPS_HFLAG_ERL) {
1325 return 3; /* ERL */
1326 } else {
1327 return hflags & MIPS_HFLAG_KSU;
1328 }
1329 }
1330
cpu_mmu_index(CPUMIPSState * env,bool ifetch)1331 static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
1332 {
1333 return hflags_mmu_index(env->hflags);
1334 }
1335
1336 typedef CPUMIPSState CPUArchState;
1337 typedef MIPSCPU ArchCPU;
1338
1339 #include "exec/cpu-all.h"
1340 #include "cpu_cheri.h"
1341
1342 /*
1343 * Memory access type :
1344 * may be needed for precise access rights control and precise exceptions.
1345 */
1346 enum {
1347 /* 1 bit to define user level / supervisor access */
1348 ACCESS_USER = 0x00,
1349 ACCESS_SUPER = 0x01,
1350 /* 1 bit to indicate direction */
1351 ACCESS_STORE = 0x02,
1352 /* Type of instruction that generated the access */
1353 ACCESS_CODE = 0x10, /* Code fetch access */
1354 ACCESS_INT = 0x20, /* Integer load/store access */
1355 ACCESS_FLOAT = 0x30, /* floating point load/store access */
1356 };
1357
1358 /* Exceptions */
1359 typedef enum {
1360 EXCP_NONE = -1,
1361 EXCP_RESET = 0,
1362 EXCP_SRESET,
1363 EXCP_DSS,
1364 EXCP_DINT,
1365 EXCP_DDBL,
1366 EXCP_DDBS,
1367 EXCP_NMI,
1368 EXCP_MCHECK,
1369 EXCP_EXT_INTERRUPT, /* 8 */
1370 EXCP_DFWATCH,
1371 EXCP_DIB,
1372 EXCP_IWATCH,
1373 EXCP_AdEL,
1374 EXCP_AdES,
1375 EXCP_TLBF,
1376 EXCP_IBE,
1377 EXCP_DBp, /* 16 */
1378 EXCP_SYSCALL,
1379 EXCP_BREAK,
1380 EXCP_CpU,
1381 EXCP_RI,
1382 EXCP_OVERFLOW,
1383 EXCP_TRAP,
1384 EXCP_FPE,
1385 EXCP_DWATCH, /* 24 */
1386 EXCP_LTLBL,
1387 EXCP_TLBL,
1388 EXCP_TLBS,
1389 EXCP_DBE,
1390 EXCP_THREAD,
1391 EXCP_MDMX,
1392 EXCP_C2E,
1393 EXCP_CACHE, /* 32 */
1394 EXCP_DSPDIS,
1395 EXCP_MSADIS,
1396 EXCP_MSAFPE,
1397 EXCP_TLBXI,
1398 EXCP_TLBRI,
1399
1400 EXCP_LAST = EXCP_TLBRI,
1401 } MipsExcp;
1402
1403 /*
1404 * This is an internally generated WAKE request line.
1405 * It is driven by the CPU itself. Raised when the MT
1406 * block wants to wake a VPE from an inactive state and
1407 * cleared when VPE goes from active to inactive.
1408 */
1409 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
1410
1411 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
1412
1413 #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
1414 #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
1415 #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
1416
1417 bool cpu_supports_cps_smp(const char *cpu_type);
1418 bool cpu_supports_isa(const char *cpu_type, uint64_t isa);
1419 void cpu_set_exception_base(int vp_index, target_ulong address);
1420
1421 /* mips_int.c */
1422 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
1423
1424 /* mips_itu.c */
1425 void itc_reconfigure(struct MIPSITUState *tag);
1426
1427 /* helper.c */
1428 target_ulong exception_resume_pc(CPUMIPSState *env);
1429
1430 #ifdef CONFIG_MIPS_LOG_INSTR
1431 void dump_store(CPUMIPSState *env, int opc, target_ulong addr,
1432 target_ulong value);
1433 #ifdef TARGET_CHERI
1434 void dump_changed_capreg(CPUMIPSState *env, const cap_register_t *cr,
1435 cap_register_t *old_reg, const char* name);
1436 void dump_changed_cop2(CPUMIPSState *env, TCState *cur);
1437 #endif /* TARGET_CHERI */
1438 #endif /* CONFIG_MIPS_LOG_INSTR */
1439
cpu_get_tb_cpu_state(CPUMIPSState * env,target_ulong * pc,target_ulong * cs_base,uint32_t * flags)1440 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
1441 target_ulong *cs_base, uint32_t *flags)
1442 {
1443 *pc = PC_ADDR(env);
1444 #ifdef TARGET_CHERI
1445 *cs_base = cap_get_base(&env->active_tc.PCC);
1446 #else
1447 *cs_base = 0;
1448 #endif
1449 *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
1450 MIPS_HFLAG_HWRENA_ULR);
1451 }
1452
should_use_error_epc(CPUMIPSState * env)1453 static inline bool should_use_error_epc(CPUMIPSState *env)
1454 {
1455 // If ERL is set, eret and exceptions use ErrorEPC instead of EPC
1456 return env->CP0_Status & (1 << CP0St_ERL);
1457 }
1458
in_kernel_mode(CPUMIPSState * env)1459 static inline bool in_kernel_mode(CPUMIPSState *env) {
1460 // TODO: what about env->CP0_Debug & (1 << CP0DB_DM)
1461 // If ERL or EXL is set we have taken an exception and are in the kernel
1462 if ((env->CP0_Status & BIT(CP0St_ERL)) || (env->CP0_Status & BIT(CP0St_EXL))) {
1463 return true;
1464 }
1465 uint32_t ksu = extract32(env->CP0_Status, CP0St_KSU, 2);
1466 // KSU = 0 -> kernel, 1 -> supervisor, 2 -> user
1467 if (ksu == 0 || ksu == 1) {
1468 return true;
1469 }
1470 return false;
1471 }
1472
1473 #ifdef TARGET_CHERI
1474 #define is_beri_or_cheri(env) true
1475 #else
1476 #define is_beri_or_cheri(env) (strcmp(env->cpu_model->name, "BERI") == 0)
1477 #endif
1478
1479 // Note: the pc does not have to be up-to-date, tb start is fine.
1480 // We may miss a few dumps or print too many if -dfilter is on but
1481 // that shouldn't really matter.
cpu_get_recent_pc(CPUMIPSState * env)1482 static inline target_ulong cpu_get_recent_pc(CPUMIPSState *env)
1483 {
1484 #ifdef TARGET_CHERI
1485 return env->active_tc.PCC._cr_cursor;
1486 #else
1487 return env->active_tc.PC;
1488 #endif
1489 }
1490
pc_is_current(CPUArchState * env)1491 static inline bool pc_is_current(CPUArchState *env)
1492 {
1493 #ifdef CONFIG_DEBUG_TCG
1494 return env->active_tc._pc_is_current;
1495 #else
1496 return true;
1497 #endif
1498 }
mips_update_pc_impl(TCState * state,target_ulong pc_addr,bool can_be_unrepresenable)1499 static inline void mips_update_pc_impl(TCState *state, target_ulong pc_addr, bool can_be_unrepresenable)
1500 {
1501 #ifdef TARGET_CHERI
1502 cheri_update_pcc(&state->PCC, pc_addr, can_be_unrepresenable);
1503 #else
1504 state->PC = pc_addr;
1505 #endif
1506 #ifdef CONFIG_DEBUG_TCG
1507 state->_pc_is_current = true;
1508 #endif
1509 }
1510
mips_update_pc(CPUMIPSState * env,target_ulong pc_addr,bool can_be_unrepresenable)1511 static inline void mips_update_pc(CPUMIPSState *env, target_ulong pc_addr, bool can_be_unrepresenable)
1512 {
1513 mips_update_pc_impl(&env->active_tc, pc_addr, can_be_unrepresenable);
1514 }
1515
1516 #if defined(TARGET_CHERI)
1517 void cheri_cpu_dump_statistics(CPUState *cs, int flags);
1518 void cheri_cpu_dump_statistics_f(CPUState *cs, FILE* f, int flags);
1519 void qemu_log_capreg(const cap_register_t *cr, const char* prefix, const char* name);
1520 hwaddr cpu_mips_translate_address_c2(CPUMIPSState *env, target_ulong address,
1521 MMUAccessType rw, int reg, int *prot,
1522 uintptr_t retpc);
1523 #endif /* TARGET_CHERI */
1524
1525 #endif /* MIPS_CPU_H */
1526