1 /*-
2 * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef __MLX5_FPGA_CORE_H__
34 #define __MLX5_FPGA_CORE_H__
35
36 #ifdef CONFIG_MLX5_FPGA
37
38 #include <dev/mlx5/mlx5_fpga/cmd.h>
39 #include <dev/mlx5/mlx5_fpga/sdk.h>
40
41 /* Represents client-specific and Innova device-specific information */
42 struct mlx5_fpga_client_data {
43 struct list_head list;
44 struct mlx5_fpga_client *client;
45 void *data;
46 bool added;
47 };
48
49 enum mlx5_fdev_state {
50 MLX5_FDEV_STATE_SUCCESS = 0,
51 MLX5_FDEV_STATE_FAILURE = 1,
52 MLX5_FDEV_STATE_IN_PROGRESS = 2,
53 MLX5_FDEV_STATE_DISCONNECTED = 3,
54 MLX5_FDEV_STATE_NONE = 0xFFFF,
55 };
56
57 /* Represents an Innova device */
58 struct mlx5_fpga_device {
59 struct mlx5_core_dev *mdev;
60 struct completion load_event;
61 spinlock_t state_lock; /* Protects state transitions */
62 enum mlx5_fdev_state fdev_state;
63 enum mlx5_fpga_status image_status;
64 enum mlx5_fpga_image last_admin_image;
65 enum mlx5_fpga_image last_oper_image;
66
67 /* QP Connection resources */
68 struct {
69 u32 pdn;
70 struct mlx5_core_mkey mkey;
71 struct mlx5_uars_page *uar;
72 } conn_res;
73
74 struct mlx5_fpga_ipsec *ipsec;
75
76 struct list_head list;
77 struct list_head client_data_list;
78
79 /* Shell Transactions state */
80 struct mlx5_fpga_conn *shell_conn;
81 struct mlx5_fpga_trans_device_state *trans;
82 };
83
84 #define mlx5_fpga_dbg(__adev, format, ...) \
85 dev_dbg(&(__adev)->mdev->pdev->dev, "FPGA: %s:%d:(pid %d): " format, \
86 __func__, __LINE__, current->pid, ##__VA_ARGS__)
87
88 #define mlx5_fpga_err(__adev, format, ...) \
89 dev_err(&(__adev)->mdev->pdev->dev, "FPGA: %s:%d:(pid %d): " format, \
90 __func__, __LINE__, current->pid, ##__VA_ARGS__)
91
92 #define mlx5_fpga_warn(__adev, format, ...) \
93 dev_warn(&(__adev)->mdev->pdev->dev, "FPGA: %s:%d:(pid %d): " format, \
94 __func__, __LINE__, current->pid, ##__VA_ARGS__)
95
96 #define mlx5_fpga_warn_ratelimited(__adev, format, ...) \
97 dev_warn_ratelimited(&(__adev)->mdev->pdev->dev, "FPGA: %s:%d: " \
98 format, __func__, __LINE__, ##__VA_ARGS__)
99
100 #define mlx5_fpga_notice(__adev, format, ...) \
101 dev_notice(&(__adev)->mdev->pdev->dev, "FPGA: " format, ##__VA_ARGS__)
102
103 #define mlx5_fpga_info(__adev, format, ...) \
104 dev_info(&(__adev)->mdev->pdev->dev, "FPGA: " format, ##__VA_ARGS__)
105
106 int mlx5_fpga_init(struct mlx5_core_dev *mdev);
107 void mlx5_fpga_cleanup(struct mlx5_core_dev *mdev);
108 int mlx5_fpga_device_start(struct mlx5_core_dev *mdev);
109 void mlx5_fpga_device_stop(struct mlx5_core_dev *mdev);
110 void mlx5_fpga_event(struct mlx5_core_dev *mdev, u8 event, void *data);
111
112 #else
113
mlx5_fpga_init(struct mlx5_core_dev * mdev)114 static inline int mlx5_fpga_init(struct mlx5_core_dev *mdev)
115 {
116 return 0;
117 }
118
mlx5_fpga_cleanup(struct mlx5_core_dev * mdev)119 static inline void mlx5_fpga_cleanup(struct mlx5_core_dev *mdev)
120 {
121 }
122
mlx5_fpga_device_start(struct mlx5_core_dev * mdev)123 static inline int mlx5_fpga_device_start(struct mlx5_core_dev *mdev)
124 {
125 return 0;
126 }
127
mlx5_fpga_device_stop(struct mlx5_core_dev * mdev)128 static inline void mlx5_fpga_device_stop(struct mlx5_core_dev *mdev)
129 {
130 }
131
mlx5_fpga_event(struct mlx5_core_dev * mdev,u8 event,void * data)132 static inline void mlx5_fpga_event(struct mlx5_core_dev *mdev, u8 event,
133 void *data)
134 {
135 }
136
137 #endif
138
139 #endif /* __MLX5_FPGA_CORE_H__ */
140