1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_DMA1_QM_REGS_H_ 14 #define ASIC_REG_DMA1_QM_REGS_H_ 15 16 /* 17 ***************************************** 18 * DMA1_QM (Prototype: QMAN) 19 ***************************************** 20 */ 21 22 #define mmDMA1_QM_GLBL_CFG0 0x528000 23 24 #define mmDMA1_QM_GLBL_CFG1 0x528004 25 26 #define mmDMA1_QM_GLBL_PROT 0x528008 27 28 #define mmDMA1_QM_GLBL_ERR_CFG 0x52800C 29 30 #define mmDMA1_QM_GLBL_SECURE_PROPS_0 0x528010 31 32 #define mmDMA1_QM_GLBL_SECURE_PROPS_1 0x528014 33 34 #define mmDMA1_QM_GLBL_SECURE_PROPS_2 0x528018 35 36 #define mmDMA1_QM_GLBL_SECURE_PROPS_3 0x52801C 37 38 #define mmDMA1_QM_GLBL_SECURE_PROPS_4 0x528020 39 40 #define mmDMA1_QM_GLBL_NON_SECURE_PROPS_0 0x528024 41 42 #define mmDMA1_QM_GLBL_NON_SECURE_PROPS_1 0x528028 43 44 #define mmDMA1_QM_GLBL_NON_SECURE_PROPS_2 0x52802C 45 46 #define mmDMA1_QM_GLBL_NON_SECURE_PROPS_3 0x528030 47 48 #define mmDMA1_QM_GLBL_NON_SECURE_PROPS_4 0x528034 49 50 #define mmDMA1_QM_GLBL_STS0 0x528038 51 52 #define mmDMA1_QM_GLBL_STS1_0 0x528040 53 54 #define mmDMA1_QM_GLBL_STS1_1 0x528044 55 56 #define mmDMA1_QM_GLBL_STS1_2 0x528048 57 58 #define mmDMA1_QM_GLBL_STS1_3 0x52804C 59 60 #define mmDMA1_QM_GLBL_STS1_4 0x528050 61 62 #define mmDMA1_QM_GLBL_MSG_EN_0 0x528054 63 64 #define mmDMA1_QM_GLBL_MSG_EN_1 0x528058 65 66 #define mmDMA1_QM_GLBL_MSG_EN_2 0x52805C 67 68 #define mmDMA1_QM_GLBL_MSG_EN_3 0x528060 69 70 #define mmDMA1_QM_GLBL_MSG_EN_4 0x528068 71 72 #define mmDMA1_QM_PQ_BASE_LO_0 0x528070 73 74 #define mmDMA1_QM_PQ_BASE_LO_1 0x528074 75 76 #define mmDMA1_QM_PQ_BASE_LO_2 0x528078 77 78 #define mmDMA1_QM_PQ_BASE_LO_3 0x52807C 79 80 #define mmDMA1_QM_PQ_BASE_HI_0 0x528080 81 82 #define mmDMA1_QM_PQ_BASE_HI_1 0x528084 83 84 #define mmDMA1_QM_PQ_BASE_HI_2 0x528088 85 86 #define mmDMA1_QM_PQ_BASE_HI_3 0x52808C 87 88 #define mmDMA1_QM_PQ_SIZE_0 0x528090 89 90 #define mmDMA1_QM_PQ_SIZE_1 0x528094 91 92 #define mmDMA1_QM_PQ_SIZE_2 0x528098 93 94 #define mmDMA1_QM_PQ_SIZE_3 0x52809C 95 96 #define mmDMA1_QM_PQ_PI_0 0x5280A0 97 98 #define mmDMA1_QM_PQ_PI_1 0x5280A4 99 100 #define mmDMA1_QM_PQ_PI_2 0x5280A8 101 102 #define mmDMA1_QM_PQ_PI_3 0x5280AC 103 104 #define mmDMA1_QM_PQ_CI_0 0x5280B0 105 106 #define mmDMA1_QM_PQ_CI_1 0x5280B4 107 108 #define mmDMA1_QM_PQ_CI_2 0x5280B8 109 110 #define mmDMA1_QM_PQ_CI_3 0x5280BC 111 112 #define mmDMA1_QM_PQ_CFG0_0 0x5280C0 113 114 #define mmDMA1_QM_PQ_CFG0_1 0x5280C4 115 116 #define mmDMA1_QM_PQ_CFG0_2 0x5280C8 117 118 #define mmDMA1_QM_PQ_CFG0_3 0x5280CC 119 120 #define mmDMA1_QM_PQ_CFG1_0 0x5280D0 121 122 #define mmDMA1_QM_PQ_CFG1_1 0x5280D4 123 124 #define mmDMA1_QM_PQ_CFG1_2 0x5280D8 125 126 #define mmDMA1_QM_PQ_CFG1_3 0x5280DC 127 128 #define mmDMA1_QM_PQ_ARUSER_31_11_0 0x5280E0 129 130 #define mmDMA1_QM_PQ_ARUSER_31_11_1 0x5280E4 131 132 #define mmDMA1_QM_PQ_ARUSER_31_11_2 0x5280E8 133 134 #define mmDMA1_QM_PQ_ARUSER_31_11_3 0x5280EC 135 136 #define mmDMA1_QM_PQ_STS0_0 0x5280F0 137 138 #define mmDMA1_QM_PQ_STS0_1 0x5280F4 139 140 #define mmDMA1_QM_PQ_STS0_2 0x5280F8 141 142 #define mmDMA1_QM_PQ_STS0_3 0x5280FC 143 144 #define mmDMA1_QM_PQ_STS1_0 0x528100 145 146 #define mmDMA1_QM_PQ_STS1_1 0x528104 147 148 #define mmDMA1_QM_PQ_STS1_2 0x528108 149 150 #define mmDMA1_QM_PQ_STS1_3 0x52810C 151 152 #define mmDMA1_QM_CQ_CFG0_0 0x528110 153 154 #define mmDMA1_QM_CQ_CFG0_1 0x528114 155 156 #define mmDMA1_QM_CQ_CFG0_2 0x528118 157 158 #define mmDMA1_QM_CQ_CFG0_3 0x52811C 159 160 #define mmDMA1_QM_CQ_CFG0_4 0x528120 161 162 #define mmDMA1_QM_CQ_CFG1_0 0x528124 163 164 #define mmDMA1_QM_CQ_CFG1_1 0x528128 165 166 #define mmDMA1_QM_CQ_CFG1_2 0x52812C 167 168 #define mmDMA1_QM_CQ_CFG1_3 0x528130 169 170 #define mmDMA1_QM_CQ_CFG1_4 0x528134 171 172 #define mmDMA1_QM_CQ_ARUSER_31_11_0 0x528138 173 174 #define mmDMA1_QM_CQ_ARUSER_31_11_1 0x52813C 175 176 #define mmDMA1_QM_CQ_ARUSER_31_11_2 0x528140 177 178 #define mmDMA1_QM_CQ_ARUSER_31_11_3 0x528144 179 180 #define mmDMA1_QM_CQ_ARUSER_31_11_4 0x528148 181 182 #define mmDMA1_QM_CQ_STS0_0 0x52814C 183 184 #define mmDMA1_QM_CQ_STS0_1 0x528150 185 186 #define mmDMA1_QM_CQ_STS0_2 0x528154 187 188 #define mmDMA1_QM_CQ_STS0_3 0x528158 189 190 #define mmDMA1_QM_CQ_STS0_4 0x52815C 191 192 #define mmDMA1_QM_CQ_STS1_0 0x528160 193 194 #define mmDMA1_QM_CQ_STS1_1 0x528164 195 196 #define mmDMA1_QM_CQ_STS1_2 0x528168 197 198 #define mmDMA1_QM_CQ_STS1_3 0x52816C 199 200 #define mmDMA1_QM_CQ_STS1_4 0x528170 201 202 #define mmDMA1_QM_CQ_PTR_LO_0 0x528174 203 204 #define mmDMA1_QM_CQ_PTR_HI_0 0x528178 205 206 #define mmDMA1_QM_CQ_TSIZE_0 0x52817C 207 208 #define mmDMA1_QM_CQ_CTL_0 0x528180 209 210 #define mmDMA1_QM_CQ_PTR_LO_1 0x528184 211 212 #define mmDMA1_QM_CQ_PTR_HI_1 0x528188 213 214 #define mmDMA1_QM_CQ_TSIZE_1 0x52818C 215 216 #define mmDMA1_QM_CQ_CTL_1 0x528190 217 218 #define mmDMA1_QM_CQ_PTR_LO_2 0x528194 219 220 #define mmDMA1_QM_CQ_PTR_HI_2 0x528198 221 222 #define mmDMA1_QM_CQ_TSIZE_2 0x52819C 223 224 #define mmDMA1_QM_CQ_CTL_2 0x5281A0 225 226 #define mmDMA1_QM_CQ_PTR_LO_3 0x5281A4 227 228 #define mmDMA1_QM_CQ_PTR_HI_3 0x5281A8 229 230 #define mmDMA1_QM_CQ_TSIZE_3 0x5281AC 231 232 #define mmDMA1_QM_CQ_CTL_3 0x5281B0 233 234 #define mmDMA1_QM_CQ_PTR_LO_4 0x5281B4 235 236 #define mmDMA1_QM_CQ_PTR_HI_4 0x5281B8 237 238 #define mmDMA1_QM_CQ_TSIZE_4 0x5281BC 239 240 #define mmDMA1_QM_CQ_CTL_4 0x5281C0 241 242 #define mmDMA1_QM_CQ_PTR_LO_STS_0 0x5281C4 243 244 #define mmDMA1_QM_CQ_PTR_LO_STS_1 0x5281C8 245 246 #define mmDMA1_QM_CQ_PTR_LO_STS_2 0x5281CC 247 248 #define mmDMA1_QM_CQ_PTR_LO_STS_3 0x5281D0 249 250 #define mmDMA1_QM_CQ_PTR_LO_STS_4 0x5281D4 251 252 #define mmDMA1_QM_CQ_PTR_HI_STS_0 0x5281D8 253 254 #define mmDMA1_QM_CQ_PTR_HI_STS_1 0x5281DC 255 256 #define mmDMA1_QM_CQ_PTR_HI_STS_2 0x5281E0 257 258 #define mmDMA1_QM_CQ_PTR_HI_STS_3 0x5281E4 259 260 #define mmDMA1_QM_CQ_PTR_HI_STS_4 0x5281E8 261 262 #define mmDMA1_QM_CQ_TSIZE_STS_0 0x5281EC 263 264 #define mmDMA1_QM_CQ_TSIZE_STS_1 0x5281F0 265 266 #define mmDMA1_QM_CQ_TSIZE_STS_2 0x5281F4 267 268 #define mmDMA1_QM_CQ_TSIZE_STS_3 0x5281F8 269 270 #define mmDMA1_QM_CQ_TSIZE_STS_4 0x5281FC 271 272 #define mmDMA1_QM_CQ_CTL_STS_0 0x528200 273 274 #define mmDMA1_QM_CQ_CTL_STS_1 0x528204 275 276 #define mmDMA1_QM_CQ_CTL_STS_2 0x528208 277 278 #define mmDMA1_QM_CQ_CTL_STS_3 0x52820C 279 280 #define mmDMA1_QM_CQ_CTL_STS_4 0x528210 281 282 #define mmDMA1_QM_CQ_IFIFO_CNT_0 0x528214 283 284 #define mmDMA1_QM_CQ_IFIFO_CNT_1 0x528218 285 286 #define mmDMA1_QM_CQ_IFIFO_CNT_2 0x52821C 287 288 #define mmDMA1_QM_CQ_IFIFO_CNT_3 0x528220 289 290 #define mmDMA1_QM_CQ_IFIFO_CNT_4 0x528224 291 292 #define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_0 0x528228 293 294 #define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_1 0x52822C 295 296 #define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_2 0x528230 297 298 #define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_3 0x528234 299 300 #define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_4 0x528238 301 302 #define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_0 0x52823C 303 304 #define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_1 0x528240 305 306 #define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_2 0x528244 307 308 #define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_3 0x528248 309 310 #define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_4 0x52824C 311 312 #define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_0 0x528250 313 314 #define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_1 0x528254 315 316 #define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_2 0x528258 317 318 #define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_3 0x52825C 319 320 #define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_4 0x528260 321 322 #define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_0 0x528264 323 324 #define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_1 0x528268 325 326 #define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_2 0x52826C 327 328 #define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_3 0x528270 329 330 #define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_4 0x528274 331 332 #define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_0 0x528278 333 334 #define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_1 0x52827C 335 336 #define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_2 0x528280 337 338 #define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_3 0x528284 339 340 #define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_4 0x528288 341 342 #define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_0 0x52828C 343 344 #define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_1 0x528290 345 346 #define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_2 0x528294 347 348 #define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_3 0x528298 349 350 #define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_4 0x52829C 351 352 #define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_0 0x5282A0 353 354 #define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_1 0x5282A4 355 356 #define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_2 0x5282A8 357 358 #define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_3 0x5282AC 359 360 #define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_4 0x5282B0 361 362 #define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_0 0x5282B4 363 364 #define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_1 0x5282B8 365 366 #define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_2 0x5282BC 367 368 #define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_3 0x5282C0 369 370 #define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_4 0x5282C4 371 372 #define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_0 0x5282C8 373 374 #define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_1 0x5282CC 375 376 #define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_2 0x5282D0 377 378 #define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_3 0x5282D4 379 380 #define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_4 0x5282D8 381 382 #define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5282E0 383 384 #define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5282E4 385 386 #define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5282E8 387 388 #define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5282EC 389 390 #define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5282F0 391 392 #define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5282F4 393 394 #define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5282F8 395 396 #define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5282FC 397 398 #define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x528300 399 400 #define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x528304 401 402 #define mmDMA1_QM_CP_FENCE0_RDATA_0 0x528308 403 404 #define mmDMA1_QM_CP_FENCE0_RDATA_1 0x52830C 405 406 #define mmDMA1_QM_CP_FENCE0_RDATA_2 0x528310 407 408 #define mmDMA1_QM_CP_FENCE0_RDATA_3 0x528314 409 410 #define mmDMA1_QM_CP_FENCE0_RDATA_4 0x528318 411 412 #define mmDMA1_QM_CP_FENCE1_RDATA_0 0x52831C 413 414 #define mmDMA1_QM_CP_FENCE1_RDATA_1 0x528320 415 416 #define mmDMA1_QM_CP_FENCE1_RDATA_2 0x528324 417 418 #define mmDMA1_QM_CP_FENCE1_RDATA_3 0x528328 419 420 #define mmDMA1_QM_CP_FENCE1_RDATA_4 0x52832C 421 422 #define mmDMA1_QM_CP_FENCE2_RDATA_0 0x528330 423 424 #define mmDMA1_QM_CP_FENCE2_RDATA_1 0x528334 425 426 #define mmDMA1_QM_CP_FENCE2_RDATA_2 0x528338 427 428 #define mmDMA1_QM_CP_FENCE2_RDATA_3 0x52833C 429 430 #define mmDMA1_QM_CP_FENCE2_RDATA_4 0x528340 431 432 #define mmDMA1_QM_CP_FENCE3_RDATA_0 0x528344 433 434 #define mmDMA1_QM_CP_FENCE3_RDATA_1 0x528348 435 436 #define mmDMA1_QM_CP_FENCE3_RDATA_2 0x52834C 437 438 #define mmDMA1_QM_CP_FENCE3_RDATA_3 0x528350 439 440 #define mmDMA1_QM_CP_FENCE3_RDATA_4 0x528354 441 442 #define mmDMA1_QM_CP_FENCE0_CNT_0 0x528358 443 444 #define mmDMA1_QM_CP_FENCE0_CNT_1 0x52835C 445 446 #define mmDMA1_QM_CP_FENCE0_CNT_2 0x528360 447 448 #define mmDMA1_QM_CP_FENCE0_CNT_3 0x528364 449 450 #define mmDMA1_QM_CP_FENCE0_CNT_4 0x528368 451 452 #define mmDMA1_QM_CP_FENCE1_CNT_0 0x52836C 453 454 #define mmDMA1_QM_CP_FENCE1_CNT_1 0x528370 455 456 #define mmDMA1_QM_CP_FENCE1_CNT_2 0x528374 457 458 #define mmDMA1_QM_CP_FENCE1_CNT_3 0x528378 459 460 #define mmDMA1_QM_CP_FENCE1_CNT_4 0x52837C 461 462 #define mmDMA1_QM_CP_FENCE2_CNT_0 0x528380 463 464 #define mmDMA1_QM_CP_FENCE2_CNT_1 0x528384 465 466 #define mmDMA1_QM_CP_FENCE2_CNT_2 0x528388 467 468 #define mmDMA1_QM_CP_FENCE2_CNT_3 0x52838C 469 470 #define mmDMA1_QM_CP_FENCE2_CNT_4 0x528390 471 472 #define mmDMA1_QM_CP_FENCE3_CNT_0 0x528394 473 474 #define mmDMA1_QM_CP_FENCE3_CNT_1 0x528398 475 476 #define mmDMA1_QM_CP_FENCE3_CNT_2 0x52839C 477 478 #define mmDMA1_QM_CP_FENCE3_CNT_3 0x5283A0 479 480 #define mmDMA1_QM_CP_FENCE3_CNT_4 0x5283A4 481 482 #define mmDMA1_QM_CP_STS_0 0x5283A8 483 484 #define mmDMA1_QM_CP_STS_1 0x5283AC 485 486 #define mmDMA1_QM_CP_STS_2 0x5283B0 487 488 #define mmDMA1_QM_CP_STS_3 0x5283B4 489 490 #define mmDMA1_QM_CP_STS_4 0x5283B8 491 492 #define mmDMA1_QM_CP_CURRENT_INST_LO_0 0x5283BC 493 494 #define mmDMA1_QM_CP_CURRENT_INST_LO_1 0x5283C0 495 496 #define mmDMA1_QM_CP_CURRENT_INST_LO_2 0x5283C4 497 498 #define mmDMA1_QM_CP_CURRENT_INST_LO_3 0x5283C8 499 500 #define mmDMA1_QM_CP_CURRENT_INST_LO_4 0x5283CC 501 502 #define mmDMA1_QM_CP_CURRENT_INST_HI_0 0x5283D0 503 504 #define mmDMA1_QM_CP_CURRENT_INST_HI_1 0x5283D4 505 506 #define mmDMA1_QM_CP_CURRENT_INST_HI_2 0x5283D8 507 508 #define mmDMA1_QM_CP_CURRENT_INST_HI_3 0x5283DC 509 510 #define mmDMA1_QM_CP_CURRENT_INST_HI_4 0x5283E0 511 512 #define mmDMA1_QM_CP_BARRIER_CFG_0 0x5283F4 513 514 #define mmDMA1_QM_CP_BARRIER_CFG_1 0x5283F8 515 516 #define mmDMA1_QM_CP_BARRIER_CFG_2 0x5283FC 517 518 #define mmDMA1_QM_CP_BARRIER_CFG_3 0x528400 519 520 #define mmDMA1_QM_CP_BARRIER_CFG_4 0x528404 521 522 #define mmDMA1_QM_CP_DBG_0_0 0x528408 523 524 #define mmDMA1_QM_CP_DBG_0_1 0x52840C 525 526 #define mmDMA1_QM_CP_DBG_0_2 0x528410 527 528 #define mmDMA1_QM_CP_DBG_0_3 0x528414 529 530 #define mmDMA1_QM_CP_DBG_0_4 0x528418 531 532 #define mmDMA1_QM_CP_ARUSER_31_11_0 0x52841C 533 534 #define mmDMA1_QM_CP_ARUSER_31_11_1 0x528420 535 536 #define mmDMA1_QM_CP_ARUSER_31_11_2 0x528424 537 538 #define mmDMA1_QM_CP_ARUSER_31_11_3 0x528428 539 540 #define mmDMA1_QM_CP_ARUSER_31_11_4 0x52842C 541 542 #define mmDMA1_QM_CP_AWUSER_31_11_0 0x528430 543 544 #define mmDMA1_QM_CP_AWUSER_31_11_1 0x528434 545 546 #define mmDMA1_QM_CP_AWUSER_31_11_2 0x528438 547 548 #define mmDMA1_QM_CP_AWUSER_31_11_3 0x52843C 549 550 #define mmDMA1_QM_CP_AWUSER_31_11_4 0x528440 551 552 #define mmDMA1_QM_ARB_CFG_0 0x528A00 553 554 #define mmDMA1_QM_ARB_CHOISE_Q_PUSH 0x528A04 555 556 #define mmDMA1_QM_ARB_WRR_WEIGHT_0 0x528A08 557 558 #define mmDMA1_QM_ARB_WRR_WEIGHT_1 0x528A0C 559 560 #define mmDMA1_QM_ARB_WRR_WEIGHT_2 0x528A10 561 562 #define mmDMA1_QM_ARB_WRR_WEIGHT_3 0x528A14 563 564 #define mmDMA1_QM_ARB_CFG_1 0x528A18 565 566 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_0 0x528A20 567 568 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_1 0x528A24 569 570 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_2 0x528A28 571 572 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_3 0x528A2C 573 574 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_4 0x528A30 575 576 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_5 0x528A34 577 578 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_6 0x528A38 579 580 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_7 0x528A3C 581 582 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_8 0x528A40 583 584 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_9 0x528A44 585 586 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_10 0x528A48 587 588 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_11 0x528A4C 589 590 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_12 0x528A50 591 592 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_13 0x528A54 593 594 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_14 0x528A58 595 596 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_15 0x528A5C 597 598 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_16 0x528A60 599 600 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_17 0x528A64 601 602 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_18 0x528A68 603 604 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_19 0x528A6C 605 606 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_20 0x528A70 607 608 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_21 0x528A74 609 610 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_22 0x528A78 611 612 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_23 0x528A7C 613 614 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_24 0x528A80 615 616 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_25 0x528A84 617 618 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_26 0x528A88 619 620 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_27 0x528A8C 621 622 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_28 0x528A90 623 624 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_29 0x528A94 625 626 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_30 0x528A98 627 628 #define mmDMA1_QM_ARB_MST_AVAIL_CRED_31 0x528A9C 629 630 #define mmDMA1_QM_ARB_MST_CRED_INC 0x528AA0 631 632 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x528AA4 633 634 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x528AA8 635 636 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x528AAC 637 638 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x528AB0 639 640 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x528AB4 641 642 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x528AB8 643 644 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x528ABC 645 646 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x528AC0 647 648 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x528AC4 649 650 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x528AC8 651 652 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x528ACC 653 654 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x528AD0 655 656 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x528AD4 657 658 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x528AD8 659 660 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x528ADC 661 662 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x528AE0 663 664 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x528AE4 665 666 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x528AE8 667 668 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x528AEC 669 670 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x528AF0 671 672 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x528AF4 673 674 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x528AF8 675 676 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x528AFC 677 678 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x528B00 679 680 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x528B04 681 682 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x528B08 683 684 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x528B0C 685 686 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x528B10 687 688 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x528B14 689 690 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x528B18 691 692 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x528B1C 693 694 #define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x528B20 695 696 #define mmDMA1_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x528B28 697 698 #define mmDMA1_QM_ARB_MST_SLAVE_EN 0x528B2C 699 700 #define mmDMA1_QM_ARB_MST_QUIET_PER 0x528B34 701 702 #define mmDMA1_QM_ARB_SLV_CHOISE_WDT 0x528B38 703 704 #define mmDMA1_QM_ARB_SLV_ID 0x528B3C 705 706 #define mmDMA1_QM_ARB_MSG_MAX_INFLIGHT 0x528B44 707 708 #define mmDMA1_QM_ARB_MSG_AWUSER_31_11 0x528B48 709 710 #define mmDMA1_QM_ARB_MSG_AWUSER_SEC_PROP 0x528B4C 711 712 #define mmDMA1_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x528B50 713 714 #define mmDMA1_QM_ARB_BASE_LO 0x528B54 715 716 #define mmDMA1_QM_ARB_BASE_HI 0x528B58 717 718 #define mmDMA1_QM_ARB_STATE_STS 0x528B80 719 720 #define mmDMA1_QM_ARB_CHOISE_FULLNESS_STS 0x528B84 721 722 #define mmDMA1_QM_ARB_MSG_STS 0x528B88 723 724 #define mmDMA1_QM_ARB_SLV_CHOISE_Q_HEAD 0x528B8C 725 726 #define mmDMA1_QM_ARB_ERR_CAUSE 0x528B9C 727 728 #define mmDMA1_QM_ARB_ERR_MSG_EN 0x528BA0 729 730 #define mmDMA1_QM_ARB_ERR_STS_DRP 0x528BA8 731 732 #define mmDMA1_QM_ARB_MST_CRED_STS_0 0x528BB0 733 734 #define mmDMA1_QM_ARB_MST_CRED_STS_1 0x528BB4 735 736 #define mmDMA1_QM_ARB_MST_CRED_STS_2 0x528BB8 737 738 #define mmDMA1_QM_ARB_MST_CRED_STS_3 0x528BBC 739 740 #define mmDMA1_QM_ARB_MST_CRED_STS_4 0x528BC0 741 742 #define mmDMA1_QM_ARB_MST_CRED_STS_5 0x528BC4 743 744 #define mmDMA1_QM_ARB_MST_CRED_STS_6 0x528BC8 745 746 #define mmDMA1_QM_ARB_MST_CRED_STS_7 0x528BCC 747 748 #define mmDMA1_QM_ARB_MST_CRED_STS_8 0x528BD0 749 750 #define mmDMA1_QM_ARB_MST_CRED_STS_9 0x528BD4 751 752 #define mmDMA1_QM_ARB_MST_CRED_STS_10 0x528BD8 753 754 #define mmDMA1_QM_ARB_MST_CRED_STS_11 0x528BDC 755 756 #define mmDMA1_QM_ARB_MST_CRED_STS_12 0x528BE0 757 758 #define mmDMA1_QM_ARB_MST_CRED_STS_13 0x528BE4 759 760 #define mmDMA1_QM_ARB_MST_CRED_STS_14 0x528BE8 761 762 #define mmDMA1_QM_ARB_MST_CRED_STS_15 0x528BEC 763 764 #define mmDMA1_QM_ARB_MST_CRED_STS_16 0x528BF0 765 766 #define mmDMA1_QM_ARB_MST_CRED_STS_17 0x528BF4 767 768 #define mmDMA1_QM_ARB_MST_CRED_STS_18 0x528BF8 769 770 #define mmDMA1_QM_ARB_MST_CRED_STS_19 0x528BFC 771 772 #define mmDMA1_QM_ARB_MST_CRED_STS_20 0x528C00 773 774 #define mmDMA1_QM_ARB_MST_CRED_STS_21 0x528C04 775 776 #define mmDMA1_QM_ARB_MST_CRED_STS_22 0x528C08 777 778 #define mmDMA1_QM_ARB_MST_CRED_STS_23 0x528C0C 779 780 #define mmDMA1_QM_ARB_MST_CRED_STS_24 0x528C10 781 782 #define mmDMA1_QM_ARB_MST_CRED_STS_25 0x528C14 783 784 #define mmDMA1_QM_ARB_MST_CRED_STS_26 0x528C18 785 786 #define mmDMA1_QM_ARB_MST_CRED_STS_27 0x528C1C 787 788 #define mmDMA1_QM_ARB_MST_CRED_STS_28 0x528C20 789 790 #define mmDMA1_QM_ARB_MST_CRED_STS_29 0x528C24 791 792 #define mmDMA1_QM_ARB_MST_CRED_STS_30 0x528C28 793 794 #define mmDMA1_QM_ARB_MST_CRED_STS_31 0x528C2C 795 796 #define mmDMA1_QM_CGM_CFG 0x528C70 797 798 #define mmDMA1_QM_CGM_STS 0x528C74 799 800 #define mmDMA1_QM_CGM_CFG1 0x528C78 801 802 #define mmDMA1_QM_LOCAL_RANGE_BASE 0x528C80 803 804 #define mmDMA1_QM_LOCAL_RANGE_SIZE 0x528C84 805 806 #define mmDMA1_QM_CSMR_STRICT_PRIO_CFG 0x528C90 807 808 #define mmDMA1_QM_HBW_RD_RATE_LIM_CFG_1 0x528C94 809 810 #define mmDMA1_QM_LBW_WR_RATE_LIM_CFG_0 0x528C98 811 812 #define mmDMA1_QM_LBW_WR_RATE_LIM_CFG_1 0x528C9C 813 814 #define mmDMA1_QM_HBW_RD_RATE_LIM_CFG_0 0x528CA0 815 816 #define mmDMA1_QM_GLBL_AXCACHE 0x528CA4 817 818 #define mmDMA1_QM_IND_GW_APB_CFG 0x528CB0 819 820 #define mmDMA1_QM_IND_GW_APB_WDATA 0x528CB4 821 822 #define mmDMA1_QM_IND_GW_APB_RDATA 0x528CB8 823 824 #define mmDMA1_QM_IND_GW_APB_STATUS 0x528CBC 825 826 #define mmDMA1_QM_GLBL_ERR_ADDR_LO 0x528CD0 827 828 #define mmDMA1_QM_GLBL_ERR_ADDR_HI 0x528CD4 829 830 #define mmDMA1_QM_GLBL_ERR_WDATA 0x528CD8 831 832 #define mmDMA1_QM_GLBL_MEM_INIT_BUSY 0x528D00 833 834 #endif /* ASIC_REG_DMA1_QM_REGS_H_ */ 835