1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_DMA2_QM_REGS_H_ 14 #define ASIC_REG_DMA2_QM_REGS_H_ 15 16 /* 17 ***************************************** 18 * DMA2_QM (Prototype: QMAN) 19 ***************************************** 20 */ 21 22 #define mmDMA2_QM_GLBL_CFG0 0x548000 23 24 #define mmDMA2_QM_GLBL_CFG1 0x548004 25 26 #define mmDMA2_QM_GLBL_PROT 0x548008 27 28 #define mmDMA2_QM_GLBL_ERR_CFG 0x54800C 29 30 #define mmDMA2_QM_GLBL_SECURE_PROPS_0 0x548010 31 32 #define mmDMA2_QM_GLBL_SECURE_PROPS_1 0x548014 33 34 #define mmDMA2_QM_GLBL_SECURE_PROPS_2 0x548018 35 36 #define mmDMA2_QM_GLBL_SECURE_PROPS_3 0x54801C 37 38 #define mmDMA2_QM_GLBL_SECURE_PROPS_4 0x548020 39 40 #define mmDMA2_QM_GLBL_NON_SECURE_PROPS_0 0x548024 41 42 #define mmDMA2_QM_GLBL_NON_SECURE_PROPS_1 0x548028 43 44 #define mmDMA2_QM_GLBL_NON_SECURE_PROPS_2 0x54802C 45 46 #define mmDMA2_QM_GLBL_NON_SECURE_PROPS_3 0x548030 47 48 #define mmDMA2_QM_GLBL_NON_SECURE_PROPS_4 0x548034 49 50 #define mmDMA2_QM_GLBL_STS0 0x548038 51 52 #define mmDMA2_QM_GLBL_STS1_0 0x548040 53 54 #define mmDMA2_QM_GLBL_STS1_1 0x548044 55 56 #define mmDMA2_QM_GLBL_STS1_2 0x548048 57 58 #define mmDMA2_QM_GLBL_STS1_3 0x54804C 59 60 #define mmDMA2_QM_GLBL_STS1_4 0x548050 61 62 #define mmDMA2_QM_GLBL_MSG_EN_0 0x548054 63 64 #define mmDMA2_QM_GLBL_MSG_EN_1 0x548058 65 66 #define mmDMA2_QM_GLBL_MSG_EN_2 0x54805C 67 68 #define mmDMA2_QM_GLBL_MSG_EN_3 0x548060 69 70 #define mmDMA2_QM_GLBL_MSG_EN_4 0x548068 71 72 #define mmDMA2_QM_PQ_BASE_LO_0 0x548070 73 74 #define mmDMA2_QM_PQ_BASE_LO_1 0x548074 75 76 #define mmDMA2_QM_PQ_BASE_LO_2 0x548078 77 78 #define mmDMA2_QM_PQ_BASE_LO_3 0x54807C 79 80 #define mmDMA2_QM_PQ_BASE_HI_0 0x548080 81 82 #define mmDMA2_QM_PQ_BASE_HI_1 0x548084 83 84 #define mmDMA2_QM_PQ_BASE_HI_2 0x548088 85 86 #define mmDMA2_QM_PQ_BASE_HI_3 0x54808C 87 88 #define mmDMA2_QM_PQ_SIZE_0 0x548090 89 90 #define mmDMA2_QM_PQ_SIZE_1 0x548094 91 92 #define mmDMA2_QM_PQ_SIZE_2 0x548098 93 94 #define mmDMA2_QM_PQ_SIZE_3 0x54809C 95 96 #define mmDMA2_QM_PQ_PI_0 0x5480A0 97 98 #define mmDMA2_QM_PQ_PI_1 0x5480A4 99 100 #define mmDMA2_QM_PQ_PI_2 0x5480A8 101 102 #define mmDMA2_QM_PQ_PI_3 0x5480AC 103 104 #define mmDMA2_QM_PQ_CI_0 0x5480B0 105 106 #define mmDMA2_QM_PQ_CI_1 0x5480B4 107 108 #define mmDMA2_QM_PQ_CI_2 0x5480B8 109 110 #define mmDMA2_QM_PQ_CI_3 0x5480BC 111 112 #define mmDMA2_QM_PQ_CFG0_0 0x5480C0 113 114 #define mmDMA2_QM_PQ_CFG0_1 0x5480C4 115 116 #define mmDMA2_QM_PQ_CFG0_2 0x5480C8 117 118 #define mmDMA2_QM_PQ_CFG0_3 0x5480CC 119 120 #define mmDMA2_QM_PQ_CFG1_0 0x5480D0 121 122 #define mmDMA2_QM_PQ_CFG1_1 0x5480D4 123 124 #define mmDMA2_QM_PQ_CFG1_2 0x5480D8 125 126 #define mmDMA2_QM_PQ_CFG1_3 0x5480DC 127 128 #define mmDMA2_QM_PQ_ARUSER_31_11_0 0x5480E0 129 130 #define mmDMA2_QM_PQ_ARUSER_31_11_1 0x5480E4 131 132 #define mmDMA2_QM_PQ_ARUSER_31_11_2 0x5480E8 133 134 #define mmDMA2_QM_PQ_ARUSER_31_11_3 0x5480EC 135 136 #define mmDMA2_QM_PQ_STS0_0 0x5480F0 137 138 #define mmDMA2_QM_PQ_STS0_1 0x5480F4 139 140 #define mmDMA2_QM_PQ_STS0_2 0x5480F8 141 142 #define mmDMA2_QM_PQ_STS0_3 0x5480FC 143 144 #define mmDMA2_QM_PQ_STS1_0 0x548100 145 146 #define mmDMA2_QM_PQ_STS1_1 0x548104 147 148 #define mmDMA2_QM_PQ_STS1_2 0x548108 149 150 #define mmDMA2_QM_PQ_STS1_3 0x54810C 151 152 #define mmDMA2_QM_CQ_CFG0_0 0x548110 153 154 #define mmDMA2_QM_CQ_CFG0_1 0x548114 155 156 #define mmDMA2_QM_CQ_CFG0_2 0x548118 157 158 #define mmDMA2_QM_CQ_CFG0_3 0x54811C 159 160 #define mmDMA2_QM_CQ_CFG0_4 0x548120 161 162 #define mmDMA2_QM_CQ_CFG1_0 0x548124 163 164 #define mmDMA2_QM_CQ_CFG1_1 0x548128 165 166 #define mmDMA2_QM_CQ_CFG1_2 0x54812C 167 168 #define mmDMA2_QM_CQ_CFG1_3 0x548130 169 170 #define mmDMA2_QM_CQ_CFG1_4 0x548134 171 172 #define mmDMA2_QM_CQ_ARUSER_31_11_0 0x548138 173 174 #define mmDMA2_QM_CQ_ARUSER_31_11_1 0x54813C 175 176 #define mmDMA2_QM_CQ_ARUSER_31_11_2 0x548140 177 178 #define mmDMA2_QM_CQ_ARUSER_31_11_3 0x548144 179 180 #define mmDMA2_QM_CQ_ARUSER_31_11_4 0x548148 181 182 #define mmDMA2_QM_CQ_STS0_0 0x54814C 183 184 #define mmDMA2_QM_CQ_STS0_1 0x548150 185 186 #define mmDMA2_QM_CQ_STS0_2 0x548154 187 188 #define mmDMA2_QM_CQ_STS0_3 0x548158 189 190 #define mmDMA2_QM_CQ_STS0_4 0x54815C 191 192 #define mmDMA2_QM_CQ_STS1_0 0x548160 193 194 #define mmDMA2_QM_CQ_STS1_1 0x548164 195 196 #define mmDMA2_QM_CQ_STS1_2 0x548168 197 198 #define mmDMA2_QM_CQ_STS1_3 0x54816C 199 200 #define mmDMA2_QM_CQ_STS1_4 0x548170 201 202 #define mmDMA2_QM_CQ_PTR_LO_0 0x548174 203 204 #define mmDMA2_QM_CQ_PTR_HI_0 0x548178 205 206 #define mmDMA2_QM_CQ_TSIZE_0 0x54817C 207 208 #define mmDMA2_QM_CQ_CTL_0 0x548180 209 210 #define mmDMA2_QM_CQ_PTR_LO_1 0x548184 211 212 #define mmDMA2_QM_CQ_PTR_HI_1 0x548188 213 214 #define mmDMA2_QM_CQ_TSIZE_1 0x54818C 215 216 #define mmDMA2_QM_CQ_CTL_1 0x548190 217 218 #define mmDMA2_QM_CQ_PTR_LO_2 0x548194 219 220 #define mmDMA2_QM_CQ_PTR_HI_2 0x548198 221 222 #define mmDMA2_QM_CQ_TSIZE_2 0x54819C 223 224 #define mmDMA2_QM_CQ_CTL_2 0x5481A0 225 226 #define mmDMA2_QM_CQ_PTR_LO_3 0x5481A4 227 228 #define mmDMA2_QM_CQ_PTR_HI_3 0x5481A8 229 230 #define mmDMA2_QM_CQ_TSIZE_3 0x5481AC 231 232 #define mmDMA2_QM_CQ_CTL_3 0x5481B0 233 234 #define mmDMA2_QM_CQ_PTR_LO_4 0x5481B4 235 236 #define mmDMA2_QM_CQ_PTR_HI_4 0x5481B8 237 238 #define mmDMA2_QM_CQ_TSIZE_4 0x5481BC 239 240 #define mmDMA2_QM_CQ_CTL_4 0x5481C0 241 242 #define mmDMA2_QM_CQ_PTR_LO_STS_0 0x5481C4 243 244 #define mmDMA2_QM_CQ_PTR_LO_STS_1 0x5481C8 245 246 #define mmDMA2_QM_CQ_PTR_LO_STS_2 0x5481CC 247 248 #define mmDMA2_QM_CQ_PTR_LO_STS_3 0x5481D0 249 250 #define mmDMA2_QM_CQ_PTR_LO_STS_4 0x5481D4 251 252 #define mmDMA2_QM_CQ_PTR_HI_STS_0 0x5481D8 253 254 #define mmDMA2_QM_CQ_PTR_HI_STS_1 0x5481DC 255 256 #define mmDMA2_QM_CQ_PTR_HI_STS_2 0x5481E0 257 258 #define mmDMA2_QM_CQ_PTR_HI_STS_3 0x5481E4 259 260 #define mmDMA2_QM_CQ_PTR_HI_STS_4 0x5481E8 261 262 #define mmDMA2_QM_CQ_TSIZE_STS_0 0x5481EC 263 264 #define mmDMA2_QM_CQ_TSIZE_STS_1 0x5481F0 265 266 #define mmDMA2_QM_CQ_TSIZE_STS_2 0x5481F4 267 268 #define mmDMA2_QM_CQ_TSIZE_STS_3 0x5481F8 269 270 #define mmDMA2_QM_CQ_TSIZE_STS_4 0x5481FC 271 272 #define mmDMA2_QM_CQ_CTL_STS_0 0x548200 273 274 #define mmDMA2_QM_CQ_CTL_STS_1 0x548204 275 276 #define mmDMA2_QM_CQ_CTL_STS_2 0x548208 277 278 #define mmDMA2_QM_CQ_CTL_STS_3 0x54820C 279 280 #define mmDMA2_QM_CQ_CTL_STS_4 0x548210 281 282 #define mmDMA2_QM_CQ_IFIFO_CNT_0 0x548214 283 284 #define mmDMA2_QM_CQ_IFIFO_CNT_1 0x548218 285 286 #define mmDMA2_QM_CQ_IFIFO_CNT_2 0x54821C 287 288 #define mmDMA2_QM_CQ_IFIFO_CNT_3 0x548220 289 290 #define mmDMA2_QM_CQ_IFIFO_CNT_4 0x548224 291 292 #define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_0 0x548228 293 294 #define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_1 0x54822C 295 296 #define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_2 0x548230 297 298 #define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_3 0x548234 299 300 #define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_4 0x548238 301 302 #define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_0 0x54823C 303 304 #define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_1 0x548240 305 306 #define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_2 0x548244 307 308 #define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_3 0x548248 309 310 #define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_4 0x54824C 311 312 #define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_0 0x548250 313 314 #define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_1 0x548254 315 316 #define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_2 0x548258 317 318 #define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_3 0x54825C 319 320 #define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_4 0x548260 321 322 #define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_0 0x548264 323 324 #define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_1 0x548268 325 326 #define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_2 0x54826C 327 328 #define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_3 0x548270 329 330 #define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_4 0x548274 331 332 #define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_0 0x548278 333 334 #define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_1 0x54827C 335 336 #define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_2 0x548280 337 338 #define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_3 0x548284 339 340 #define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_4 0x548288 341 342 #define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_0 0x54828C 343 344 #define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_1 0x548290 345 346 #define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_2 0x548294 347 348 #define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_3 0x548298 349 350 #define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_4 0x54829C 351 352 #define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_0 0x5482A0 353 354 #define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_1 0x5482A4 355 356 #define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_2 0x5482A8 357 358 #define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_3 0x5482AC 359 360 #define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_4 0x5482B0 361 362 #define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_0 0x5482B4 363 364 #define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_1 0x5482B8 365 366 #define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_2 0x5482BC 367 368 #define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_3 0x5482C0 369 370 #define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_4 0x5482C4 371 372 #define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_0 0x5482C8 373 374 #define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_1 0x5482CC 375 376 #define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_2 0x5482D0 377 378 #define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_3 0x5482D4 379 380 #define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_4 0x5482D8 381 382 #define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5482E0 383 384 #define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5482E4 385 386 #define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5482E8 387 388 #define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5482EC 389 390 #define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5482F0 391 392 #define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5482F4 393 394 #define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5482F8 395 396 #define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5482FC 397 398 #define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x548300 399 400 #define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x548304 401 402 #define mmDMA2_QM_CP_FENCE0_RDATA_0 0x548308 403 404 #define mmDMA2_QM_CP_FENCE0_RDATA_1 0x54830C 405 406 #define mmDMA2_QM_CP_FENCE0_RDATA_2 0x548310 407 408 #define mmDMA2_QM_CP_FENCE0_RDATA_3 0x548314 409 410 #define mmDMA2_QM_CP_FENCE0_RDATA_4 0x548318 411 412 #define mmDMA2_QM_CP_FENCE1_RDATA_0 0x54831C 413 414 #define mmDMA2_QM_CP_FENCE1_RDATA_1 0x548320 415 416 #define mmDMA2_QM_CP_FENCE1_RDATA_2 0x548324 417 418 #define mmDMA2_QM_CP_FENCE1_RDATA_3 0x548328 419 420 #define mmDMA2_QM_CP_FENCE1_RDATA_4 0x54832C 421 422 #define mmDMA2_QM_CP_FENCE2_RDATA_0 0x548330 423 424 #define mmDMA2_QM_CP_FENCE2_RDATA_1 0x548334 425 426 #define mmDMA2_QM_CP_FENCE2_RDATA_2 0x548338 427 428 #define mmDMA2_QM_CP_FENCE2_RDATA_3 0x54833C 429 430 #define mmDMA2_QM_CP_FENCE2_RDATA_4 0x548340 431 432 #define mmDMA2_QM_CP_FENCE3_RDATA_0 0x548344 433 434 #define mmDMA2_QM_CP_FENCE3_RDATA_1 0x548348 435 436 #define mmDMA2_QM_CP_FENCE3_RDATA_2 0x54834C 437 438 #define mmDMA2_QM_CP_FENCE3_RDATA_3 0x548350 439 440 #define mmDMA2_QM_CP_FENCE3_RDATA_4 0x548354 441 442 #define mmDMA2_QM_CP_FENCE0_CNT_0 0x548358 443 444 #define mmDMA2_QM_CP_FENCE0_CNT_1 0x54835C 445 446 #define mmDMA2_QM_CP_FENCE0_CNT_2 0x548360 447 448 #define mmDMA2_QM_CP_FENCE0_CNT_3 0x548364 449 450 #define mmDMA2_QM_CP_FENCE0_CNT_4 0x548368 451 452 #define mmDMA2_QM_CP_FENCE1_CNT_0 0x54836C 453 454 #define mmDMA2_QM_CP_FENCE1_CNT_1 0x548370 455 456 #define mmDMA2_QM_CP_FENCE1_CNT_2 0x548374 457 458 #define mmDMA2_QM_CP_FENCE1_CNT_3 0x548378 459 460 #define mmDMA2_QM_CP_FENCE1_CNT_4 0x54837C 461 462 #define mmDMA2_QM_CP_FENCE2_CNT_0 0x548380 463 464 #define mmDMA2_QM_CP_FENCE2_CNT_1 0x548384 465 466 #define mmDMA2_QM_CP_FENCE2_CNT_2 0x548388 467 468 #define mmDMA2_QM_CP_FENCE2_CNT_3 0x54838C 469 470 #define mmDMA2_QM_CP_FENCE2_CNT_4 0x548390 471 472 #define mmDMA2_QM_CP_FENCE3_CNT_0 0x548394 473 474 #define mmDMA2_QM_CP_FENCE3_CNT_1 0x548398 475 476 #define mmDMA2_QM_CP_FENCE3_CNT_2 0x54839C 477 478 #define mmDMA2_QM_CP_FENCE3_CNT_3 0x5483A0 479 480 #define mmDMA2_QM_CP_FENCE3_CNT_4 0x5483A4 481 482 #define mmDMA2_QM_CP_STS_0 0x5483A8 483 484 #define mmDMA2_QM_CP_STS_1 0x5483AC 485 486 #define mmDMA2_QM_CP_STS_2 0x5483B0 487 488 #define mmDMA2_QM_CP_STS_3 0x5483B4 489 490 #define mmDMA2_QM_CP_STS_4 0x5483B8 491 492 #define mmDMA2_QM_CP_CURRENT_INST_LO_0 0x5483BC 493 494 #define mmDMA2_QM_CP_CURRENT_INST_LO_1 0x5483C0 495 496 #define mmDMA2_QM_CP_CURRENT_INST_LO_2 0x5483C4 497 498 #define mmDMA2_QM_CP_CURRENT_INST_LO_3 0x5483C8 499 500 #define mmDMA2_QM_CP_CURRENT_INST_LO_4 0x5483CC 501 502 #define mmDMA2_QM_CP_CURRENT_INST_HI_0 0x5483D0 503 504 #define mmDMA2_QM_CP_CURRENT_INST_HI_1 0x5483D4 505 506 #define mmDMA2_QM_CP_CURRENT_INST_HI_2 0x5483D8 507 508 #define mmDMA2_QM_CP_CURRENT_INST_HI_3 0x5483DC 509 510 #define mmDMA2_QM_CP_CURRENT_INST_HI_4 0x5483E0 511 512 #define mmDMA2_QM_CP_BARRIER_CFG_0 0x5483F4 513 514 #define mmDMA2_QM_CP_BARRIER_CFG_1 0x5483F8 515 516 #define mmDMA2_QM_CP_BARRIER_CFG_2 0x5483FC 517 518 #define mmDMA2_QM_CP_BARRIER_CFG_3 0x548400 519 520 #define mmDMA2_QM_CP_BARRIER_CFG_4 0x548404 521 522 #define mmDMA2_QM_CP_DBG_0_0 0x548408 523 524 #define mmDMA2_QM_CP_DBG_0_1 0x54840C 525 526 #define mmDMA2_QM_CP_DBG_0_2 0x548410 527 528 #define mmDMA2_QM_CP_DBG_0_3 0x548414 529 530 #define mmDMA2_QM_CP_DBG_0_4 0x548418 531 532 #define mmDMA2_QM_CP_ARUSER_31_11_0 0x54841C 533 534 #define mmDMA2_QM_CP_ARUSER_31_11_1 0x548420 535 536 #define mmDMA2_QM_CP_ARUSER_31_11_2 0x548424 537 538 #define mmDMA2_QM_CP_ARUSER_31_11_3 0x548428 539 540 #define mmDMA2_QM_CP_ARUSER_31_11_4 0x54842C 541 542 #define mmDMA2_QM_CP_AWUSER_31_11_0 0x548430 543 544 #define mmDMA2_QM_CP_AWUSER_31_11_1 0x548434 545 546 #define mmDMA2_QM_CP_AWUSER_31_11_2 0x548438 547 548 #define mmDMA2_QM_CP_AWUSER_31_11_3 0x54843C 549 550 #define mmDMA2_QM_CP_AWUSER_31_11_4 0x548440 551 552 #define mmDMA2_QM_ARB_CFG_0 0x548A00 553 554 #define mmDMA2_QM_ARB_CHOISE_Q_PUSH 0x548A04 555 556 #define mmDMA2_QM_ARB_WRR_WEIGHT_0 0x548A08 557 558 #define mmDMA2_QM_ARB_WRR_WEIGHT_1 0x548A0C 559 560 #define mmDMA2_QM_ARB_WRR_WEIGHT_2 0x548A10 561 562 #define mmDMA2_QM_ARB_WRR_WEIGHT_3 0x548A14 563 564 #define mmDMA2_QM_ARB_CFG_1 0x548A18 565 566 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_0 0x548A20 567 568 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_1 0x548A24 569 570 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_2 0x548A28 571 572 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_3 0x548A2C 573 574 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_4 0x548A30 575 576 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_5 0x548A34 577 578 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_6 0x548A38 579 580 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_7 0x548A3C 581 582 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_8 0x548A40 583 584 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_9 0x548A44 585 586 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_10 0x548A48 587 588 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_11 0x548A4C 589 590 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_12 0x548A50 591 592 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_13 0x548A54 593 594 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_14 0x548A58 595 596 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_15 0x548A5C 597 598 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_16 0x548A60 599 600 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_17 0x548A64 601 602 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_18 0x548A68 603 604 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_19 0x548A6C 605 606 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_20 0x548A70 607 608 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_21 0x548A74 609 610 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_22 0x548A78 611 612 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_23 0x548A7C 613 614 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_24 0x548A80 615 616 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_25 0x548A84 617 618 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_26 0x548A88 619 620 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_27 0x548A8C 621 622 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_28 0x548A90 623 624 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_29 0x548A94 625 626 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_30 0x548A98 627 628 #define mmDMA2_QM_ARB_MST_AVAIL_CRED_31 0x548A9C 629 630 #define mmDMA2_QM_ARB_MST_CRED_INC 0x548AA0 631 632 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x548AA4 633 634 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x548AA8 635 636 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x548AAC 637 638 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x548AB0 639 640 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x548AB4 641 642 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x548AB8 643 644 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x548ABC 645 646 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x548AC0 647 648 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x548AC4 649 650 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x548AC8 651 652 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x548ACC 653 654 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x548AD0 655 656 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x548AD4 657 658 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x548AD8 659 660 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x548ADC 661 662 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x548AE0 663 664 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x548AE4 665 666 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x548AE8 667 668 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x548AEC 669 670 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x548AF0 671 672 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x548AF4 673 674 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x548AF8 675 676 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x548AFC 677 678 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x548B00 679 680 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x548B04 681 682 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x548B08 683 684 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x548B0C 685 686 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x548B10 687 688 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x548B14 689 690 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x548B18 691 692 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x548B1C 693 694 #define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x548B20 695 696 #define mmDMA2_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x548B28 697 698 #define mmDMA2_QM_ARB_MST_SLAVE_EN 0x548B2C 699 700 #define mmDMA2_QM_ARB_MST_QUIET_PER 0x548B34 701 702 #define mmDMA2_QM_ARB_SLV_CHOISE_WDT 0x548B38 703 704 #define mmDMA2_QM_ARB_SLV_ID 0x548B3C 705 706 #define mmDMA2_QM_ARB_MSG_MAX_INFLIGHT 0x548B44 707 708 #define mmDMA2_QM_ARB_MSG_AWUSER_31_11 0x548B48 709 710 #define mmDMA2_QM_ARB_MSG_AWUSER_SEC_PROP 0x548B4C 711 712 #define mmDMA2_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x548B50 713 714 #define mmDMA2_QM_ARB_BASE_LO 0x548B54 715 716 #define mmDMA2_QM_ARB_BASE_HI 0x548B58 717 718 #define mmDMA2_QM_ARB_STATE_STS 0x548B80 719 720 #define mmDMA2_QM_ARB_CHOISE_FULLNESS_STS 0x548B84 721 722 #define mmDMA2_QM_ARB_MSG_STS 0x548B88 723 724 #define mmDMA2_QM_ARB_SLV_CHOISE_Q_HEAD 0x548B8C 725 726 #define mmDMA2_QM_ARB_ERR_CAUSE 0x548B9C 727 728 #define mmDMA2_QM_ARB_ERR_MSG_EN 0x548BA0 729 730 #define mmDMA2_QM_ARB_ERR_STS_DRP 0x548BA8 731 732 #define mmDMA2_QM_ARB_MST_CRED_STS_0 0x548BB0 733 734 #define mmDMA2_QM_ARB_MST_CRED_STS_1 0x548BB4 735 736 #define mmDMA2_QM_ARB_MST_CRED_STS_2 0x548BB8 737 738 #define mmDMA2_QM_ARB_MST_CRED_STS_3 0x548BBC 739 740 #define mmDMA2_QM_ARB_MST_CRED_STS_4 0x548BC0 741 742 #define mmDMA2_QM_ARB_MST_CRED_STS_5 0x548BC4 743 744 #define mmDMA2_QM_ARB_MST_CRED_STS_6 0x548BC8 745 746 #define mmDMA2_QM_ARB_MST_CRED_STS_7 0x548BCC 747 748 #define mmDMA2_QM_ARB_MST_CRED_STS_8 0x548BD0 749 750 #define mmDMA2_QM_ARB_MST_CRED_STS_9 0x548BD4 751 752 #define mmDMA2_QM_ARB_MST_CRED_STS_10 0x548BD8 753 754 #define mmDMA2_QM_ARB_MST_CRED_STS_11 0x548BDC 755 756 #define mmDMA2_QM_ARB_MST_CRED_STS_12 0x548BE0 757 758 #define mmDMA2_QM_ARB_MST_CRED_STS_13 0x548BE4 759 760 #define mmDMA2_QM_ARB_MST_CRED_STS_14 0x548BE8 761 762 #define mmDMA2_QM_ARB_MST_CRED_STS_15 0x548BEC 763 764 #define mmDMA2_QM_ARB_MST_CRED_STS_16 0x548BF0 765 766 #define mmDMA2_QM_ARB_MST_CRED_STS_17 0x548BF4 767 768 #define mmDMA2_QM_ARB_MST_CRED_STS_18 0x548BF8 769 770 #define mmDMA2_QM_ARB_MST_CRED_STS_19 0x548BFC 771 772 #define mmDMA2_QM_ARB_MST_CRED_STS_20 0x548C00 773 774 #define mmDMA2_QM_ARB_MST_CRED_STS_21 0x548C04 775 776 #define mmDMA2_QM_ARB_MST_CRED_STS_22 0x548C08 777 778 #define mmDMA2_QM_ARB_MST_CRED_STS_23 0x548C0C 779 780 #define mmDMA2_QM_ARB_MST_CRED_STS_24 0x548C10 781 782 #define mmDMA2_QM_ARB_MST_CRED_STS_25 0x548C14 783 784 #define mmDMA2_QM_ARB_MST_CRED_STS_26 0x548C18 785 786 #define mmDMA2_QM_ARB_MST_CRED_STS_27 0x548C1C 787 788 #define mmDMA2_QM_ARB_MST_CRED_STS_28 0x548C20 789 790 #define mmDMA2_QM_ARB_MST_CRED_STS_29 0x548C24 791 792 #define mmDMA2_QM_ARB_MST_CRED_STS_30 0x548C28 793 794 #define mmDMA2_QM_ARB_MST_CRED_STS_31 0x548C2C 795 796 #define mmDMA2_QM_CGM_CFG 0x548C70 797 798 #define mmDMA2_QM_CGM_STS 0x548C74 799 800 #define mmDMA2_QM_CGM_CFG1 0x548C78 801 802 #define mmDMA2_QM_LOCAL_RANGE_BASE 0x548C80 803 804 #define mmDMA2_QM_LOCAL_RANGE_SIZE 0x548C84 805 806 #define mmDMA2_QM_CSMR_STRICT_PRIO_CFG 0x548C90 807 808 #define mmDMA2_QM_HBW_RD_RATE_LIM_CFG_1 0x548C94 809 810 #define mmDMA2_QM_LBW_WR_RATE_LIM_CFG_0 0x548C98 811 812 #define mmDMA2_QM_LBW_WR_RATE_LIM_CFG_1 0x548C9C 813 814 #define mmDMA2_QM_HBW_RD_RATE_LIM_CFG_0 0x548CA0 815 816 #define mmDMA2_QM_GLBL_AXCACHE 0x548CA4 817 818 #define mmDMA2_QM_IND_GW_APB_CFG 0x548CB0 819 820 #define mmDMA2_QM_IND_GW_APB_WDATA 0x548CB4 821 822 #define mmDMA2_QM_IND_GW_APB_RDATA 0x548CB8 823 824 #define mmDMA2_QM_IND_GW_APB_STATUS 0x548CBC 825 826 #define mmDMA2_QM_GLBL_ERR_ADDR_LO 0x548CD0 827 828 #define mmDMA2_QM_GLBL_ERR_ADDR_HI 0x548CD4 829 830 #define mmDMA2_QM_GLBL_ERR_WDATA 0x548CD8 831 832 #define mmDMA2_QM_GLBL_MEM_INIT_BUSY 0x548D00 833 834 #endif /* ASIC_REG_DMA2_QM_REGS_H_ */ 835