1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "reg_helper.h"
27 #include "dcn30/dcn30_mpc.h"
28 #include "dcn30/dcn30_cm_common.h"
29 #include "dcn32_mpc.h"
30 #include "basics/conversion.h"
31 #include "dcn10/dcn10_cm_common.h"
32 #include "dc.h"
33 #include "dcn401/dcn401_mpc.h"
34
35 #define REG(reg)\
36 mpc30->mpc_regs->reg
37
38 #define CTX \
39 mpc30->base.ctx
40
41 #undef FN
42 #define FN(reg_name, field_name) \
43 mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name
44
45
mpc32_mpc_init(struct mpc * mpc)46 void mpc32_mpc_init(struct mpc *mpc)
47 {
48 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
49 int mpcc_id;
50
51 mpc3_mpc_init(mpc);
52
53 if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {
54 if (mpc30->mpc_mask->MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE && mpc30->mpc_mask->MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE) {
55 for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++) {
56 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE, 3);
57 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE, 3);
58 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE, 3);
59 }
60 }
61 if (mpc30->mpc_mask->MPCC_OGAM_MEM_LOW_PWR_MODE) {
62 for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++)
63 REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_LOW_PWR_MODE, 3);
64 }
65 }
66 }
67
mpc32_power_on_blnd_lut(struct mpc * mpc,uint32_t mpcc_id,bool power_on)68 void mpc32_power_on_blnd_lut(
69 struct mpc *mpc,
70 uint32_t mpcc_id,
71 bool power_on)
72 {
73 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
74
75 REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0, MPCC_MCM_1DLUT_MEM_PWR_DIS, power_on);
76
77 if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm) {
78 if (power_on) {
79 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_FORCE, 0);
80 REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_STATE, 0, 1, 5);
81 } else if (!mpc->ctx->dc->debug.disable_mem_low_power) {
82 /* TODO: change to mpc
83 * dpp_base->ctx->dc->optimized_required = true;
84 * dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true;
85 */
86 }
87 } else {
88 REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,
89 MPCC_MCM_1DLUT_MEM_PWR_FORCE, power_on == true ? 0 : 1);
90 }
91 }
92
mpc32_get_post1dlut_current(struct mpc * mpc,uint32_t mpcc_id)93 static enum dc_lut_mode mpc32_get_post1dlut_current(struct mpc *mpc, uint32_t mpcc_id)
94 {
95 enum dc_lut_mode mode;
96 uint32_t mode_current = 0;
97 uint32_t in_use = 0;
98
99 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
100
101 REG_GET(MPCC_MCM_1DLUT_CONTROL[mpcc_id],
102 MPCC_MCM_1DLUT_MODE_CURRENT, &mode_current);
103 REG_GET(MPCC_MCM_1DLUT_CONTROL[mpcc_id],
104 MPCC_MCM_1DLUT_SELECT_CURRENT, &in_use);
105
106 switch (mode_current) {
107 case 0:
108 case 1:
109 mode = LUT_BYPASS;
110 break;
111
112 case 2:
113 if (in_use == 0)
114 mode = LUT_RAM_A;
115 else
116 mode = LUT_RAM_B;
117 break;
118 default:
119 mode = LUT_BYPASS;
120 break;
121 }
122 return mode;
123 }
124
mpc32_configure_post1dlut(struct mpc * mpc,uint32_t mpcc_id,bool is_ram_a)125 void mpc32_configure_post1dlut(
126 struct mpc *mpc,
127 uint32_t mpcc_id,
128 bool is_ram_a)
129 {
130 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
131
132 //TODO: this
133 REG_UPDATE_2(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id],
134 MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 7,
135 MPCC_MCM_1DLUT_LUT_HOST_SEL, is_ram_a == true ? 0 : 1);
136
137 REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0);
138 }
139
mpc32_post1dlut_get_reg_field(struct dcn30_mpc * mpc,struct dcn3_xfer_func_reg * reg)140 static void mpc32_post1dlut_get_reg_field(
141 struct dcn30_mpc *mpc,
142 struct dcn3_xfer_func_reg *reg)
143 {
144 reg->shifts.exp_region0_lut_offset = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET;
145 reg->masks.exp_region0_lut_offset = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET;
146 reg->shifts.exp_region0_num_segments = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS;
147 reg->masks.exp_region0_num_segments = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS;
148 reg->shifts.exp_region1_lut_offset = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET;
149 reg->masks.exp_region1_lut_offset = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET;
150 reg->shifts.exp_region1_num_segments = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS;
151 reg->masks.exp_region1_num_segments = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS;
152
153 reg->shifts.field_region_end = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B;
154 reg->masks.field_region_end = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B;
155 reg->shifts.field_region_end_slope = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B;
156 reg->masks.field_region_end_slope = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B;
157 reg->shifts.field_region_end_base = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B;
158 reg->masks.field_region_end_base = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B;
159 reg->shifts.field_region_linear_slope = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B;
160 reg->masks.field_region_linear_slope = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B;
161 reg->shifts.exp_region_start = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B;
162 reg->masks.exp_region_start = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B;
163 reg->shifts.exp_resion_start_segment = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B;
164 reg->masks.exp_resion_start_segment = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B;
165 }
166
167 /*program blnd lut RAM A*/
mpc32_program_post1dluta_settings(struct mpc * mpc,uint32_t mpcc_id,const struct pwl_params * params)168 void mpc32_program_post1dluta_settings(
169 struct mpc *mpc,
170 uint32_t mpcc_id,
171 const struct pwl_params *params)
172 {
173 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
174 struct dcn3_xfer_func_reg gam_regs;
175
176 mpc32_post1dlut_get_reg_field(mpc30, &gam_regs);
177
178 gam_regs.start_cntl_b = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_B[mpcc_id]);
179 gam_regs.start_cntl_g = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_G[mpcc_id]);
180 gam_regs.start_cntl_r = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_R[mpcc_id]);
181 gam_regs.start_slope_cntl_b = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B[mpcc_id]);
182 gam_regs.start_slope_cntl_g = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G[mpcc_id]);
183 gam_regs.start_slope_cntl_r = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R[mpcc_id]);
184 gam_regs.start_end_cntl1_b = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_B[mpcc_id]);
185 gam_regs.start_end_cntl2_b = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL2_B[mpcc_id]);
186 gam_regs.start_end_cntl1_g = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_G[mpcc_id]);
187 gam_regs.start_end_cntl2_g = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL2_G[mpcc_id]);
188 gam_regs.start_end_cntl1_r = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_R[mpcc_id]);
189 gam_regs.start_end_cntl2_r = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL2_R[mpcc_id]);
190 gam_regs.region_start = REG(MPCC_MCM_1DLUT_RAMA_REGION_0_1[mpcc_id]);
191 gam_regs.region_end = REG(MPCC_MCM_1DLUT_RAMA_REGION_32_33[mpcc_id]);
192
193 cm_helper_program_gamcor_xfer_func(mpc->ctx, params, &gam_regs);
194 }
195
196 /*program blnd lut RAM B*/
mpc32_program_post1dlutb_settings(struct mpc * mpc,uint32_t mpcc_id,const struct pwl_params * params)197 void mpc32_program_post1dlutb_settings(
198 struct mpc *mpc,
199 uint32_t mpcc_id,
200 const struct pwl_params *params)
201 {
202 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
203 struct dcn3_xfer_func_reg gam_regs;
204
205 mpc32_post1dlut_get_reg_field(mpc30, &gam_regs);
206
207 gam_regs.start_cntl_b = REG(MPCC_MCM_1DLUT_RAMB_START_CNTL_B[mpcc_id]);
208 gam_regs.start_cntl_g = REG(MPCC_MCM_1DLUT_RAMB_START_CNTL_G[mpcc_id]);
209 gam_regs.start_cntl_r = REG(MPCC_MCM_1DLUT_RAMB_START_CNTL_R[mpcc_id]);
210 gam_regs.start_slope_cntl_b = REG(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B[mpcc_id]);
211 gam_regs.start_slope_cntl_g = REG(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G[mpcc_id]);
212 gam_regs.start_slope_cntl_r = REG(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R[mpcc_id]);
213 gam_regs.start_end_cntl1_b = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL1_B[mpcc_id]);
214 gam_regs.start_end_cntl2_b = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL2_B[mpcc_id]);
215 gam_regs.start_end_cntl1_g = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL1_G[mpcc_id]);
216 gam_regs.start_end_cntl2_g = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL2_G[mpcc_id]);
217 gam_regs.start_end_cntl1_r = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL1_R[mpcc_id]);
218 gam_regs.start_end_cntl2_r = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL2_R[mpcc_id]);
219 gam_regs.region_start = REG(MPCC_MCM_1DLUT_RAMB_REGION_0_1[mpcc_id]);
220 gam_regs.region_end = REG(MPCC_MCM_1DLUT_RAMB_REGION_32_33[mpcc_id]);
221
222 cm_helper_program_gamcor_xfer_func(mpc->ctx, params, &gam_regs);
223 }
224
mpc32_program_post1dlut_pwl(struct mpc * mpc,uint32_t mpcc_id,const struct pwl_result_data * rgb,uint32_t num)225 void mpc32_program_post1dlut_pwl(
226 struct mpc *mpc,
227 uint32_t mpcc_id,
228 const struct pwl_result_data *rgb,
229 uint32_t num)
230 {
231 uint32_t i;
232 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
233 uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;
234 uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;
235 uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;
236
237 if (is_rgb_equal(rgb, num)) {
238 for (i = 0 ; i < num; i++)
239 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].red_reg);
240 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_red);
241 } else {
242 REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0);
243 REG_UPDATE(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 4);
244 for (i = 0 ; i < num; i++)
245 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].red_reg);
246 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_red);
247
248 REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0);
249 REG_UPDATE(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 2);
250 for (i = 0 ; i < num; i++)
251 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].green_reg);
252 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_green);
253
254 REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0);
255 REG_UPDATE(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 1);
256 for (i = 0 ; i < num; i++)
257 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].blue_reg);
258 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_blue);
259 }
260 }
261
mpc32_program_post1dlut(struct mpc * mpc,const struct pwl_params * params,uint32_t mpcc_id)262 bool mpc32_program_post1dlut(
263 struct mpc *mpc,
264 const struct pwl_params *params,
265 uint32_t mpcc_id)
266 {
267 enum dc_lut_mode current_mode;
268 enum dc_lut_mode next_mode;
269 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
270
271 if (params == NULL) {
272 REG_SET(MPCC_MCM_1DLUT_CONTROL[mpcc_id], 0, MPCC_MCM_1DLUT_MODE, 0);
273 if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm)
274 mpc32_power_on_blnd_lut(mpc, mpcc_id, false);
275 return false;
276 }
277
278 current_mode = mpc32_get_post1dlut_current(mpc, mpcc_id);
279 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_B)
280 next_mode = LUT_RAM_A;
281 else
282 next_mode = LUT_RAM_B;
283
284 mpc32_power_on_blnd_lut(mpc, mpcc_id, true);
285 mpc32_configure_post1dlut(mpc, mpcc_id, next_mode == LUT_RAM_A);
286
287 if (next_mode == LUT_RAM_A)
288 mpc32_program_post1dluta_settings(mpc, mpcc_id, params);
289 else
290 mpc32_program_post1dlutb_settings(mpc, mpcc_id, params);
291
292 mpc32_program_post1dlut_pwl(
293 mpc, mpcc_id, params->rgb_resulted, params->hw_points_num);
294
295 REG_UPDATE_2(MPCC_MCM_1DLUT_CONTROL[mpcc_id],
296 MPCC_MCM_1DLUT_MODE, 2,
297 MPCC_MCM_1DLUT_SELECT, next_mode == LUT_RAM_A ? 0 : 1);
298
299 return true;
300 }
301
mpc32_get_shaper_current(struct mpc * mpc,uint32_t mpcc_id)302 static enum dc_lut_mode mpc32_get_shaper_current(struct mpc *mpc, uint32_t mpcc_id)
303 {
304 enum dc_lut_mode mode;
305 uint32_t state_mode;
306 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
307
308 REG_GET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_MODE_CURRENT, &state_mode);
309
310 switch (state_mode) {
311 case 0:
312 mode = LUT_BYPASS;
313 break;
314 case 1:
315 mode = LUT_RAM_A;
316 break;
317 case 2:
318 mode = LUT_RAM_B;
319 break;
320 default:
321 mode = LUT_BYPASS;
322 break;
323 }
324
325 return mode;
326 }
327
328
mpc32_configure_shaper_lut(struct mpc * mpc,bool is_ram_a,uint32_t mpcc_id)329 void mpc32_configure_shaper_lut(
330 struct mpc *mpc,
331 bool is_ram_a,
332 uint32_t mpcc_id)
333 {
334 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
335
336 REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id],
337 MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, 7);
338 REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id],
339 MPCC_MCM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1);
340 REG_SET(MPCC_MCM_SHAPER_LUT_INDEX[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_INDEX, 0);
341 }
342
343
mpc32_program_shaper_luta_settings(struct mpc * mpc,const struct pwl_params * params,uint32_t mpcc_id)344 void mpc32_program_shaper_luta_settings(
345 struct mpc *mpc,
346 const struct pwl_params *params,
347 uint32_t mpcc_id)
348 {
349 const struct gamma_curve *curve;
350 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
351
352 REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_B[mpcc_id], 0,
353 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
354 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
355 REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_G[mpcc_id], 0,
356 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x,
357 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
358 REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_R[mpcc_id], 0,
359 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x,
360 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
361
362 REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_B[mpcc_id], 0,
363 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
364 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
365 REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_G[mpcc_id], 0,
366 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x,
367 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y);
368 REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_R[mpcc_id], 0,
369 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x,
370 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y);
371
372 curve = params->arr_curve_points;
373 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_0_1[mpcc_id], 0,
374 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
375 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
376 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
377 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
378
379 curve += 2;
380 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_2_3[mpcc_id], 0,
381 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
382 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
383 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
384 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
385
386 curve += 2;
387 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_4_5[mpcc_id], 0,
388 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
389 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
390 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
391 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
392
393 curve += 2;
394 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_6_7[mpcc_id], 0,
395 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
396 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
397 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
398 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
399
400 curve += 2;
401 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_8_9[mpcc_id], 0,
402 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
403 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
404 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
405 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
406
407 curve += 2;
408 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_10_11[mpcc_id], 0,
409 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
410 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
411 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
412 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
413
414 curve += 2;
415 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_12_13[mpcc_id], 0,
416 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
417 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
418 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
419 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
420
421 curve += 2;
422 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_14_15[mpcc_id], 0,
423 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
424 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
425 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
426 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
427
428
429 curve += 2;
430 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_16_17[mpcc_id], 0,
431 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
432 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
433 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
434 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
435
436 curve += 2;
437 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_18_19[mpcc_id], 0,
438 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
439 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
440 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
441 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
442
443 curve += 2;
444 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_20_21[mpcc_id], 0,
445 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
446 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
447 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
448 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
449
450 curve += 2;
451 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_22_23[mpcc_id], 0,
452 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
453 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
454 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
455 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
456
457 curve += 2;
458 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_24_25[mpcc_id], 0,
459 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
460 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
461 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
462 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
463
464 curve += 2;
465 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_26_27[mpcc_id], 0,
466 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
467 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
468 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
469 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
470
471 curve += 2;
472 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_28_29[mpcc_id], 0,
473 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
474 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
475 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
476 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
477
478 curve += 2;
479 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_30_31[mpcc_id], 0,
480 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
481 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
482 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
483 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
484
485 curve += 2;
486 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_32_33[mpcc_id], 0,
487 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
488 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
489 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
490 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
491 }
492
493
mpc32_program_shaper_lutb_settings(struct mpc * mpc,const struct pwl_params * params,uint32_t mpcc_id)494 void mpc32_program_shaper_lutb_settings(
495 struct mpc *mpc,
496 const struct pwl_params *params,
497 uint32_t mpcc_id)
498 {
499 const struct gamma_curve *curve;
500 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
501
502 REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_B[mpcc_id], 0,
503 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
504 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
505 REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_G[mpcc_id], 0,
506 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x,
507 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
508 REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_R[mpcc_id], 0,
509 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x,
510 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
511
512 REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_B[mpcc_id], 0,
513 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
514 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
515 REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_G[mpcc_id], 0,
516 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x,
517 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y);
518 REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_R[mpcc_id], 0,
519 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x,
520 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y);
521
522 curve = params->arr_curve_points;
523 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_0_1[mpcc_id], 0,
524 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
525 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
526 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
527 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
528
529 curve += 2;
530 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_2_3[mpcc_id], 0,
531 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
532 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
533 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
534 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
535
536
537 curve += 2;
538 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_4_5[mpcc_id], 0,
539 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
540 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
541 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
542 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
543
544 curve += 2;
545 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_6_7[mpcc_id], 0,
546 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
547 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
548 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
549 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
550
551 curve += 2;
552 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_8_9[mpcc_id], 0,
553 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
554 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
555 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
556 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
557
558 curve += 2;
559 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_10_11[mpcc_id], 0,
560 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
561 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
562 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
563 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
564
565 curve += 2;
566 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_12_13[mpcc_id], 0,
567 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
568 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
569 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
570 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
571
572 curve += 2;
573 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_14_15[mpcc_id], 0,
574 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
575 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
576 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
577 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
578
579
580 curve += 2;
581 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_16_17[mpcc_id], 0,
582 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
583 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
584 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
585 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
586
587 curve += 2;
588 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_18_19[mpcc_id], 0,
589 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
590 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
591 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
592 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
593
594 curve += 2;
595 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_20_21[mpcc_id], 0,
596 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
597 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
598 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
599 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
600
601 curve += 2;
602 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_22_23[mpcc_id], 0,
603 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
604 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
605 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
606 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
607
608 curve += 2;
609 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_24_25[mpcc_id], 0,
610 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
611 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
612 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
613 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
614
615 curve += 2;
616 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_26_27[mpcc_id], 0,
617 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
618 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
619 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
620 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
621
622 curve += 2;
623 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_28_29[mpcc_id], 0,
624 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
625 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
626 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
627 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
628
629 curve += 2;
630 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_30_31[mpcc_id], 0,
631 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
632 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
633 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
634 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
635
636 curve += 2;
637 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_32_33[mpcc_id], 0,
638 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
639 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
640 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
641 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
642 }
643
644
mpc32_program_shaper_lut(struct mpc * mpc,const struct pwl_result_data * rgb,uint32_t num,uint32_t mpcc_id)645 void mpc32_program_shaper_lut(
646 struct mpc *mpc,
647 const struct pwl_result_data *rgb,
648 uint32_t num,
649 uint32_t mpcc_id)
650 {
651 uint32_t i, red, green, blue;
652 uint32_t red_delta, green_delta, blue_delta;
653 uint32_t red_value, green_value, blue_value;
654
655 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
656
657 for (i = 0 ; i < num; i++) {
658
659 red = rgb[i].red_reg;
660 green = rgb[i].green_reg;
661 blue = rgb[i].blue_reg;
662
663 red_delta = rgb[i].delta_red_reg;
664 green_delta = rgb[i].delta_green_reg;
665 blue_delta = rgb[i].delta_blue_reg;
666
667 red_value = ((red_delta & 0x3ff) << 14) | (red & 0x3fff);
668 green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff);
669 blue_value = ((blue_delta & 0x3ff) << 14) | (blue & 0x3fff);
670
671 REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, red_value);
672 REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, green_value);
673 REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, blue_value);
674 }
675
676 }
677
678
mpc32_power_on_shaper_3dlut(struct mpc * mpc,uint32_t mpcc_id,bool power_on)679 void mpc32_power_on_shaper_3dlut(
680 struct mpc *mpc,
681 uint32_t mpcc_id,
682 bool power_on)
683 {
684 uint32_t power_status_shaper = 2;
685 uint32_t power_status_3dlut = 2;
686 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
687 int max_retries = 10;
688
689 REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,
690 MPCC_MCM_3DLUT_MEM_PWR_DIS, power_on == true ? 1:0);
691 /* wait for memory to fully power up */
692 if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {
693 REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, 0, 1, max_retries);
694 REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, 0, 1, max_retries);
695 }
696
697 /*read status is not mandatory, it is just for debugging*/
698 REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, &power_status_shaper);
699 REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, &power_status_3dlut);
700
701 if (power_status_shaper != 0 && power_on == true)
702 BREAK_TO_DEBUGGER();
703
704 if (power_status_3dlut != 0 && power_on == true)
705 BREAK_TO_DEBUGGER();
706 }
707
708
mpc32_program_shaper(struct mpc * mpc,const struct pwl_params * params,uint32_t mpcc_id)709 bool mpc32_program_shaper(
710 struct mpc *mpc,
711 const struct pwl_params *params,
712 uint32_t mpcc_id)
713 {
714 enum dc_lut_mode current_mode;
715 enum dc_lut_mode next_mode;
716
717 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
718
719 if (params == NULL) {
720 REG_SET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_MODE, 0);
721 return false;
722 }
723
724 if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)
725 mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);
726
727 current_mode = mpc32_get_shaper_current(mpc, mpcc_id);
728
729 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
730 next_mode = LUT_RAM_B;
731 else
732 next_mode = LUT_RAM_A;
733
734 mpc32_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, mpcc_id);
735
736 if (next_mode == LUT_RAM_A)
737 mpc32_program_shaper_luta_settings(mpc, params, mpcc_id);
738 else
739 mpc32_program_shaper_lutb_settings(mpc, params, mpcc_id);
740
741 mpc32_program_shaper_lut(
742 mpc, params->rgb_resulted, params->hw_points_num, mpcc_id);
743
744 REG_SET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);
745 mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);
746
747 return true;
748 }
749
750
get3dlut_config(struct mpc * mpc,bool * is_17x17x17,bool * is_12bits_color_channel,int mpcc_id)751 static enum dc_lut_mode get3dlut_config(
752 struct mpc *mpc,
753 bool *is_17x17x17,
754 bool *is_12bits_color_channel,
755 int mpcc_id)
756 {
757 uint32_t i_mode, i_enable_10bits, lut_size;
758 enum dc_lut_mode mode;
759 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
760
761 REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id],
762 MPCC_MCM_3DLUT_MODE_CURRENT, &i_mode);
763
764 REG_GET(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id],
765 MPCC_MCM_3DLUT_30BIT_EN, &i_enable_10bits);
766
767 switch (i_mode) {
768 case 0:
769 mode = LUT_BYPASS;
770 break;
771 case 1:
772 mode = LUT_RAM_A;
773 break;
774 case 2:
775 mode = LUT_RAM_B;
776 break;
777 default:
778 mode = LUT_BYPASS;
779 break;
780 }
781 if (i_enable_10bits > 0)
782 *is_12bits_color_channel = false;
783 else
784 *is_12bits_color_channel = true;
785
786 REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, &lut_size);
787
788 if (lut_size == 0)
789 *is_17x17x17 = true;
790 else
791 *is_17x17x17 = false;
792
793 return mode;
794 }
795
796
mpc32_select_3dlut_ram(struct mpc * mpc,enum dc_lut_mode mode,bool is_color_channel_12bits,uint32_t mpcc_id)797 void mpc32_select_3dlut_ram(
798 struct mpc *mpc,
799 enum dc_lut_mode mode,
800 bool is_color_channel_12bits,
801 uint32_t mpcc_id)
802 {
803 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
804
805 REG_UPDATE_2(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id],
806 MPCC_MCM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,
807 MPCC_MCM_3DLUT_30BIT_EN, is_color_channel_12bits == true ? 0:1);
808 }
809
810
mpc32_select_3dlut_ram_mask(struct mpc * mpc,uint32_t ram_selection_mask,uint32_t mpcc_id)811 void mpc32_select_3dlut_ram_mask(
812 struct mpc *mpc,
813 uint32_t ram_selection_mask,
814 uint32_t mpcc_id)
815 {
816 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
817
818 REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_WRITE_EN_MASK,
819 ram_selection_mask);
820 REG_SET(MPCC_MCM_3DLUT_INDEX[mpcc_id], 0, MPCC_MCM_3DLUT_INDEX, 0);
821 }
822
823
mpc32_set3dlut_ram12(struct mpc * mpc,const struct dc_rgb * lut,uint32_t entries,uint32_t mpcc_id)824 void mpc32_set3dlut_ram12(
825 struct mpc *mpc,
826 const struct dc_rgb *lut,
827 uint32_t entries,
828 uint32_t mpcc_id)
829 {
830 uint32_t i, red, green, blue, red1, green1, blue1;
831 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
832
833 for (i = 0 ; i < entries; i += 2) {
834 red = lut[i].red<<4;
835 green = lut[i].green<<4;
836 blue = lut[i].blue<<4;
837 red1 = lut[i+1].red<<4;
838 green1 = lut[i+1].green<<4;
839 blue1 = lut[i+1].blue<<4;
840
841 REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0,
842 MPCC_MCM_3DLUT_DATA0, red,
843 MPCC_MCM_3DLUT_DATA1, red1);
844
845 REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0,
846 MPCC_MCM_3DLUT_DATA0, green,
847 MPCC_MCM_3DLUT_DATA1, green1);
848
849 REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0,
850 MPCC_MCM_3DLUT_DATA0, blue,
851 MPCC_MCM_3DLUT_DATA1, blue1);
852 }
853 }
854
855
mpc32_set3dlut_ram10(struct mpc * mpc,const struct dc_rgb * lut,uint32_t entries,uint32_t mpcc_id)856 void mpc32_set3dlut_ram10(
857 struct mpc *mpc,
858 const struct dc_rgb *lut,
859 uint32_t entries,
860 uint32_t mpcc_id)
861 {
862 uint32_t i, red, green, blue, value;
863 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
864
865 for (i = 0; i < entries; i++) {
866 red = lut[i].red;
867 green = lut[i].green;
868 blue = lut[i].blue;
869 //should we shift red 22bit and green 12?
870 value = (red<<20) | (green<<10) | blue;
871
872 REG_SET(MPCC_MCM_3DLUT_DATA_30BIT[mpcc_id], 0, MPCC_MCM_3DLUT_DATA_30BIT, value);
873 }
874
875 }
876
877
mpc32_set_3dlut_mode(struct mpc * mpc,enum dc_lut_mode mode,bool is_color_channel_12bits,bool is_lut_size17x17x17,uint32_t mpcc_id)878 static void mpc32_set_3dlut_mode(
879 struct mpc *mpc,
880 enum dc_lut_mode mode,
881 bool is_color_channel_12bits,
882 bool is_lut_size17x17x17,
883 uint32_t mpcc_id)
884 {
885 uint32_t lut_mode;
886 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
887
888 // set default 3DLUT to pre-blend
889 // TODO: implement movable CM location
890 REG_UPDATE(MPCC_MOVABLE_CM_LOCATION_CONTROL[mpcc_id], MPCC_MOVABLE_CM_LOCATION_CNTL, 0);
891
892 if (mode == LUT_BYPASS)
893 lut_mode = 0;
894 else if (mode == LUT_RAM_A)
895 lut_mode = 1;
896 else
897 lut_mode = 2;
898
899 REG_UPDATE_2(MPCC_MCM_3DLUT_MODE[mpcc_id],
900 MPCC_MCM_3DLUT_MODE, lut_mode,
901 MPCC_MCM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1);
902 }
903
904
mpc32_program_3dlut(struct mpc * mpc,const struct tetrahedral_params * params,int mpcc_id)905 bool mpc32_program_3dlut(
906 struct mpc *mpc,
907 const struct tetrahedral_params *params,
908 int mpcc_id)
909 {
910 enum dc_lut_mode mode;
911 bool is_17x17x17;
912 bool is_12bits_color_channel;
913 const struct dc_rgb *lut0;
914 const struct dc_rgb *lut1;
915 const struct dc_rgb *lut2;
916 const struct dc_rgb *lut3;
917 int lut_size0;
918 int lut_size;
919
920 if (params == NULL) {
921 mpc32_set_3dlut_mode(mpc, LUT_BYPASS, false, false, mpcc_id);
922 return false;
923 }
924 mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true);
925
926 mode = get3dlut_config(mpc, &is_17x17x17, &is_12bits_color_channel, mpcc_id);
927
928 if (mode == LUT_BYPASS || mode == LUT_RAM_B)
929 mode = LUT_RAM_A;
930 else
931 mode = LUT_RAM_B;
932
933 is_17x17x17 = !params->use_tetrahedral_9;
934 is_12bits_color_channel = params->use_12bits;
935 if (is_17x17x17) {
936 lut0 = params->tetrahedral_17.lut0;
937 lut1 = params->tetrahedral_17.lut1;
938 lut2 = params->tetrahedral_17.lut2;
939 lut3 = params->tetrahedral_17.lut3;
940 lut_size0 = sizeof(params->tetrahedral_17.lut0)/
941 sizeof(params->tetrahedral_17.lut0[0]);
942 lut_size = sizeof(params->tetrahedral_17.lut1)/
943 sizeof(params->tetrahedral_17.lut1[0]);
944 } else {
945 lut0 = params->tetrahedral_9.lut0;
946 lut1 = params->tetrahedral_9.lut1;
947 lut2 = params->tetrahedral_9.lut2;
948 lut3 = params->tetrahedral_9.lut3;
949 lut_size0 = sizeof(params->tetrahedral_9.lut0)/
950 sizeof(params->tetrahedral_9.lut0[0]);
951 lut_size = sizeof(params->tetrahedral_9.lut1)/
952 sizeof(params->tetrahedral_9.lut1[0]);
953 }
954
955 mpc32_select_3dlut_ram(mpc, mode,
956 is_12bits_color_channel, mpcc_id);
957 mpc32_select_3dlut_ram_mask(mpc, 0x1, mpcc_id);
958 if (is_12bits_color_channel)
959 mpc32_set3dlut_ram12(mpc, lut0, lut_size0, mpcc_id);
960 else
961 mpc32_set3dlut_ram10(mpc, lut0, lut_size0, mpcc_id);
962
963 mpc32_select_3dlut_ram_mask(mpc, 0x2, mpcc_id);
964 if (is_12bits_color_channel)
965 mpc32_set3dlut_ram12(mpc, lut1, lut_size, mpcc_id);
966 else
967 mpc32_set3dlut_ram10(mpc, lut1, lut_size, mpcc_id);
968
969 mpc32_select_3dlut_ram_mask(mpc, 0x4, mpcc_id);
970 if (is_12bits_color_channel)
971 mpc32_set3dlut_ram12(mpc, lut2, lut_size, mpcc_id);
972 else
973 mpc32_set3dlut_ram10(mpc, lut2, lut_size, mpcc_id);
974
975 mpc32_select_3dlut_ram_mask(mpc, 0x8, mpcc_id);
976 if (is_12bits_color_channel)
977 mpc32_set3dlut_ram12(mpc, lut3, lut_size, mpcc_id);
978 else
979 mpc32_set3dlut_ram10(mpc, lut3, lut_size, mpcc_id);
980
981 mpc32_set_3dlut_mode(mpc, mode, is_12bits_color_channel,
982 is_17x17x17, mpcc_id);
983
984 if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)
985 mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false);
986
987 return true;
988 }
989
990 static const struct mpc_funcs dcn32_mpc_funcs = {
991 .read_mpcc_state = mpc1_read_mpcc_state,
992 .insert_plane = mpc1_insert_plane,
993 .remove_mpcc = mpc1_remove_mpcc,
994 .mpc_init = mpc32_mpc_init,
995 .mpc_init_single_inst = mpc3_mpc_init_single_inst,
996 .update_blending = mpc2_update_blending,
997 .cursor_lock = mpc1_cursor_lock,
998 .get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp,
999 .wait_for_idle = mpc2_assert_idle_mpcc,
1000 .assert_mpcc_idle_before_connect = mpc2_assert_mpcc_idle_before_connect,
1001 .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,
1002 .set_denorm = mpc3_set_denorm,
1003 .set_denorm_clamp = mpc3_set_denorm_clamp,
1004 .set_output_csc = mpc3_set_output_csc,
1005 .set_ocsc_default = mpc3_set_ocsc_default,
1006 .set_output_gamma = mpc3_set_output_gamma,
1007 .insert_plane_to_secondary = NULL,
1008 .remove_mpcc_from_secondary = NULL,
1009 .set_dwb_mux = mpc3_set_dwb_mux,
1010 .disable_dwb_mux = mpc3_disable_dwb_mux,
1011 .is_dwb_idle = mpc3_is_dwb_idle,
1012 .set_gamut_remap = mpc3_set_gamut_remap,
1013 .program_shaper = mpc32_program_shaper,
1014 .program_3dlut = mpc32_program_3dlut,
1015 .program_1dlut = mpc32_program_post1dlut,
1016 .acquire_rmu = NULL,
1017 .release_rmu = NULL,
1018 .power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut,
1019 .get_mpc_out_mux = mpc1_get_mpc_out_mux,
1020 .set_bg_color = mpc1_set_bg_color,
1021 .set_movable_cm_location = mpc401_set_movable_cm_location,
1022 .populate_lut = mpc401_populate_lut,
1023 };
1024
1025
dcn32_mpc_construct(struct dcn30_mpc * mpc30,struct dc_context * ctx,const struct dcn30_mpc_registers * mpc_regs,const struct dcn30_mpc_shift * mpc_shift,const struct dcn30_mpc_mask * mpc_mask,int num_mpcc,int num_rmu)1026 void dcn32_mpc_construct(struct dcn30_mpc *mpc30,
1027 struct dc_context *ctx,
1028 const struct dcn30_mpc_registers *mpc_regs,
1029 const struct dcn30_mpc_shift *mpc_shift,
1030 const struct dcn30_mpc_mask *mpc_mask,
1031 int num_mpcc,
1032 int num_rmu)
1033 {
1034 int i;
1035
1036 mpc30->base.ctx = ctx;
1037
1038 mpc30->base.funcs = &dcn32_mpc_funcs;
1039
1040 mpc30->mpc_regs = mpc_regs;
1041 mpc30->mpc_shift = mpc_shift;
1042 mpc30->mpc_mask = mpc_mask;
1043
1044 mpc30->mpcc_in_use_mask = 0;
1045 mpc30->num_mpcc = num_mpcc;
1046 mpc30->num_rmu = num_rmu;
1047
1048 for (i = 0; i < MAX_MPCC; i++)
1049 mpc3_init_mpcc(&mpc30->base.mpcc_array[i], i);
1050 }
1051