1 /* $NetBSD: if_msk.c,v 1.119 2022/09/24 18:12:42 thorpej Exp $ */
2 /* $OpenBSD: if_msk.c,v 1.79 2009/10/15 17:54:56 deraadt Exp $ */
3
4 /*
5 * Copyright (c) 1997, 1998, 1999, 2000
6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $
36 */
37
38 /*
39 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
40 *
41 * Permission to use, copy, modify, and distribute this software for any
42 * purpose with or without fee is hereby granted, provided that the above
43 * copyright notice and this permission notice appear in all copies.
44 *
45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
52 */
53
54 #include <sys/cdefs.h>
55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.119 2022/09/24 18:12:42 thorpej Exp $");
56
57 #include <sys/param.h>
58 #include <sys/systm.h>
59 #include <sys/sockio.h>
60 #include <sys/mbuf.h>
61 #include <sys/mutex.h>
62 #include <sys/kernel.h>
63 #include <sys/socket.h>
64 #include <sys/device.h>
65 #include <sys/queue.h>
66 #include <sys/callout.h>
67 #include <sys/sysctl.h>
68 #include <sys/endian.h>
69 #ifdef __NetBSD__
70 #define letoh16 le16toh
71 #define letoh32 le32toh
72 #endif
73
74 #include <net/if.h>
75 #include <net/if_dl.h>
76 #include <net/if_types.h>
77
78 #include <net/if_media.h>
79
80 #include <net/bpf.h>
81 #include <sys/rndsource.h>
82
83 #include <dev/mii/mii.h>
84 #include <dev/mii/miivar.h>
85
86 #include <dev/pci/pcireg.h>
87 #include <dev/pci/pcivar.h>
88 #include <dev/pci/pcidevs.h>
89
90 #include <dev/pci/if_skreg.h>
91 #include <dev/pci/if_mskvar.h>
92
93 static int mskc_probe(device_t, cfdata_t, void *);
94 static void mskc_attach(device_t, device_t, void *);
95 static int mskc_detach(device_t, int);
96 static void mskc_reset(struct sk_softc *);
97 static bool mskc_suspend(device_t, const pmf_qual_t *);
98 static bool mskc_resume(device_t, const pmf_qual_t *);
99 static int msk_probe(device_t, cfdata_t, void *);
100 static void msk_attach(device_t, device_t, void *);
101 static int msk_detach(device_t, int);
102 static void msk_reset(struct sk_if_softc *);
103 static int mskcprint(void *, const char *);
104 static int msk_intr(void *);
105 static void msk_intr_yukon(struct sk_if_softc *);
106 static void msk_rxeof(struct sk_if_softc *, uint16_t, uint32_t);
107 static void msk_txeof(struct sk_if_softc *);
108 static int msk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *);
109 static void msk_start(struct ifnet *);
110 static int msk_ioctl(struct ifnet *, u_long, void *);
111 static int msk_init(struct ifnet *);
112 static void msk_init_yukon(struct sk_if_softc *);
113 static void msk_stop(struct ifnet *, int);
114 static void msk_watchdog(struct ifnet *);
115 static int msk_newbuf(struct sk_if_softc *);
116 static int msk_alloc_jumbo_mem(struct sk_if_softc *);
117 static void *msk_jalloc(struct sk_if_softc *);
118 static void msk_jfree(struct mbuf *, void *, size_t, void *);
119 static int msk_init_rx_ring(struct sk_if_softc *);
120 static int msk_init_tx_ring(struct sk_if_softc *);
121 static void msk_fill_rx_ring(struct sk_if_softc *);
122
123 static void msk_update_int_mod(struct sk_softc *, int);
124
125 static int msk_miibus_readreg(device_t, int, int, uint16_t *);
126 static int msk_miibus_writereg(device_t, int, int, uint16_t);
127 static void msk_miibus_statchg(struct ifnet *);
128
129 static void msk_setmulti(struct sk_if_softc *);
130 static void msk_setpromisc(struct sk_if_softc *);
131 static void msk_tick(void *);
132 static void msk_fill_rx_tick(void *);
133
134 /* #define MSK_DEBUG 1 */
135 #ifdef MSK_DEBUG
136 #define DPRINTF(x) if (mskdebug) printf x
137 #define DPRINTFN(n, x) if (mskdebug >= (n)) printf x
138 int mskdebug = MSK_DEBUG;
139
140 static void msk_dump_txdesc(struct msk_tx_desc *, int);
141 static void msk_dump_mbuf(struct mbuf *);
142 static void msk_dump_bytes(const char *, int);
143 #else
144 #define DPRINTF(x)
145 #define DPRINTFN(n, x)
146 #endif
147
148 static int msk_sysctl_handler(SYSCTLFN_PROTO);
149 static int msk_root_num;
150
151 #define MSK_ADDR_LO(x) ((uint64_t) (x) & 0xffffffffUL)
152 #define MSK_ADDR_HI(x) ((uint64_t) (x) >> 32)
153
154 /* supported device vendors */
155 static const struct device_compatible_entry compat_data[] = {
156 { .id = PCI_ID_CODE(PCI_VENDOR_DLINK,
157 PCI_PRODUCT_DLINK_DGE550SX) },
158 { .id = PCI_ID_CODE(PCI_VENDOR_DLINK,
159 PCI_PRODUCT_DLINK_DGE550T_B1) },
160 { .id = PCI_ID_CODE(PCI_VENDOR_DLINK,
161 PCI_PRODUCT_DLINK_DGE560SX) },
162 { .id = PCI_ID_CODE(PCI_VENDOR_DLINK,
163 PCI_PRODUCT_DLINK_DGE560T) },
164
165 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
166 PCI_PRODUCT_MARVELL_YUKONII_8021CU) },
167 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
168 PCI_PRODUCT_MARVELL_YUKONII_8021X) },
169 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
170 PCI_PRODUCT_MARVELL_YUKONII_8022CU) },
171 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
172 PCI_PRODUCT_MARVELL_YUKONII_8022X) },
173 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
174 PCI_PRODUCT_MARVELL_YUKON_8035) },
175 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
176 PCI_PRODUCT_MARVELL_YUKON_8036) },
177 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
178 PCI_PRODUCT_MARVELL_YUKON_8038) },
179 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
180 PCI_PRODUCT_MARVELL_YUKON_8039) },
181 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
182 PCI_PRODUCT_MARVELL_YUKON_8040) },
183 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
184 PCI_PRODUCT_MARVELL_YUKON_8040T) },
185 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
186 PCI_PRODUCT_MARVELL_YUKON_8042) },
187 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
188 PCI_PRODUCT_MARVELL_YUKON_8048) },
189 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
190 PCI_PRODUCT_MARVELL_YUKON_8050) },
191 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
192 PCI_PRODUCT_MARVELL_YUKON_8052) },
193 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
194 PCI_PRODUCT_MARVELL_YUKON_8053) },
195 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
196 PCI_PRODUCT_MARVELL_YUKON_8055) },
197 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
198 PCI_PRODUCT_MARVELL_YUKON_8055_2) },
199 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
200 PCI_PRODUCT_MARVELL_YUKON_8056) },
201 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
202 PCI_PRODUCT_MARVELL_YUKON_8057) },
203 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
204 PCI_PRODUCT_MARVELL_YUKON_8058) },
205 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
206 PCI_PRODUCT_MARVELL_YUKON_8059) },
207 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
208 PCI_PRODUCT_MARVELL_YUKONII_8061CU) },
209 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
210 PCI_PRODUCT_MARVELL_YUKONII_8061X) },
211 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
212 PCI_PRODUCT_MARVELL_YUKONII_8062CU) },
213 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
214 PCI_PRODUCT_MARVELL_YUKONII_8062X) },
215 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
216 PCI_PRODUCT_MARVELL_YUKON_8070) },
217 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
218 PCI_PRODUCT_MARVELL_YUKON_8071) },
219 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
220 PCI_PRODUCT_MARVELL_YUKON_8072) },
221 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
222 PCI_PRODUCT_MARVELL_YUKON_8075) },
223 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
224 PCI_PRODUCT_MARVELL_YUKON_8079) },
225 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
226 PCI_PRODUCT_MARVELL_YUKON_C032) },
227 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
228 PCI_PRODUCT_MARVELL_YUKON_C033) },
229 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
230 PCI_PRODUCT_MARVELL_YUKON_C034) },
231 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
232 PCI_PRODUCT_MARVELL_YUKON_C036) },
233 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
234 PCI_PRODUCT_MARVELL_YUKON_C042) },
235
236 { .id = PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH,
237 PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX) },
238 { .id = PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH,
239 PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21) },
240
241 PCI_COMPAT_EOL
242 };
243
244 static inline uint32_t
sk_win_read_4(struct sk_softc * sc,uint32_t reg)245 sk_win_read_4(struct sk_softc *sc, uint32_t reg)
246 {
247 return CSR_READ_4(sc, reg);
248 }
249
250 static inline uint16_t
sk_win_read_2(struct sk_softc * sc,uint32_t reg)251 sk_win_read_2(struct sk_softc *sc, uint32_t reg)
252 {
253 return CSR_READ_2(sc, reg);
254 }
255
256 static inline uint8_t
sk_win_read_1(struct sk_softc * sc,uint32_t reg)257 sk_win_read_1(struct sk_softc *sc, uint32_t reg)
258 {
259 return CSR_READ_1(sc, reg);
260 }
261
262 static inline void
sk_win_write_4(struct sk_softc * sc,uint32_t reg,uint32_t x)263 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x)
264 {
265 CSR_WRITE_4(sc, reg, x);
266 }
267
268 static inline void
sk_win_write_2(struct sk_softc * sc,uint32_t reg,uint16_t x)269 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x)
270 {
271 CSR_WRITE_2(sc, reg, x);
272 }
273
274 static inline void
sk_win_write_1(struct sk_softc * sc,uint32_t reg,uint8_t x)275 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x)
276 {
277 CSR_WRITE_1(sc, reg, x);
278 }
279
280 static int
msk_miibus_readreg(device_t dev,int phy,int reg,uint16_t * val)281 msk_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)
282 {
283 struct sk_if_softc *sc_if = device_private(dev);
284 uint16_t data;
285 int i;
286
287 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
288 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
289
290 for (i = 0; i < SK_TIMEOUT; i++) {
291 DELAY(1);
292 data = SK_YU_READ_2(sc_if, YUKON_SMICR);
293 if (data & YU_SMICR_READ_VALID)
294 break;
295 }
296
297 if (i == SK_TIMEOUT) {
298 device_printf(sc_if->sk_dev, "phy failed to come ready\n");
299 return ETIMEDOUT;
300 }
301
302 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, SK_TIMEOUT));
303
304 *val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
305
306 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#hx\n",
307 phy, reg, *val));
308
309 return 0;
310 }
311
312 static int
msk_miibus_writereg(device_t dev,int phy,int reg,uint16_t val)313 msk_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)
314 {
315 struct sk_if_softc *sc_if = device_private(dev);
316 int i;
317
318 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#hx\n",
319 phy, reg, val));
320
321 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
322 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
323 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
324
325 for (i = 0; i < SK_TIMEOUT; i++) {
326 DELAY(1);
327 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY))
328 break;
329 }
330
331 if (i == SK_TIMEOUT) {
332 device_printf(sc_if->sk_dev, "phy write timed out\n");
333 return ETIMEDOUT;
334 }
335
336 return 0;
337 }
338
339 static void
msk_miibus_statchg(struct ifnet * ifp)340 msk_miibus_statchg(struct ifnet *ifp)
341 {
342 struct sk_if_softc *sc_if = ifp->if_softc;
343 struct mii_data *mii = &sc_if->sk_mii;
344 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
345 int gpcr;
346
347 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR);
348 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN);
349
350 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO ||
351 sc_if->sk_softc->sk_type == SK_YUKON_FE_P) {
352 /* Set speed. */
353 gpcr |= YU_GPCR_SPEED_DIS;
354 switch (IFM_SUBTYPE(mii->mii_media_active)) {
355 case IFM_1000_SX:
356 case IFM_1000_LX:
357 case IFM_1000_CX:
358 case IFM_1000_T:
359 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED);
360 break;
361 case IFM_100_TX:
362 gpcr |= YU_GPCR_SPEED;
363 break;
364 }
365
366 /* Set duplex. */
367 gpcr |= YU_GPCR_DPLX_DIS;
368 if ((mii->mii_media_active & IFM_FDX) != 0)
369 gpcr |= YU_GPCR_DUPLEX;
370
371 /* Disable flow control. */
372 gpcr |= YU_GPCR_FCTL_DIS;
373 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS);
374 }
375
376 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr);
377
378 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n",
379 SK_YU_READ_2(sc_if, YUKON_GPCR)));
380 }
381
382 static void
msk_setmulti(struct sk_if_softc * sc_if)383 msk_setmulti(struct sk_if_softc *sc_if)
384 {
385 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if;
386 uint32_t hashes[2] = { 0, 0 };
387 int h;
388 struct ethercom *ec = &sc_if->sk_ethercom;
389 struct ether_multi *enm;
390 struct ether_multistep step;
391 uint16_t reg;
392
393 /* First, zot all the existing filters. */
394 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
395 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
396 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
397 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0);
398
399
400 /* Now program new ones. */
401 reg = SK_YU_READ_2(sc_if, YUKON_RCR);
402 reg |= YU_RCR_UFLEN;
403 allmulti:
404 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
405 if ((ifp->if_flags & IFF_PROMISC) != 0)
406 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN);
407 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
408 hashes[0] = 0xFFFFFFFF;
409 hashes[1] = 0xFFFFFFFF;
410 }
411 } else {
412 /* First find the tail of the list. */
413 ETHER_LOCK(ec);
414 ETHER_FIRST_MULTI(step, ec, enm);
415 while (enm != NULL) {
416 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
417 ETHER_ADDR_LEN)) {
418 ifp->if_flags |= IFF_ALLMULTI;
419 ETHER_UNLOCK(ec);
420 goto allmulti;
421 }
422 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) &
423 ((1 << SK_HASH_BITS) - 1);
424 if (h < 32)
425 hashes[0] |= (1 << h);
426 else
427 hashes[1] |= (1 << (h - 32));
428
429 ETHER_NEXT_MULTI(step, enm);
430 }
431 ETHER_UNLOCK(ec);
432 reg |= YU_RCR_MUFLEN;
433 }
434
435 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
436 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
437 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
438 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
439 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg);
440 }
441
442 static void
msk_setpromisc(struct sk_if_softc * sc_if)443 msk_setpromisc(struct sk_if_softc *sc_if)
444 {
445 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if;
446
447 if (ifp->if_flags & IFF_PROMISC)
448 SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
449 YU_RCR_UFLEN | YU_RCR_MUFLEN);
450 else
451 SK_YU_SETBIT_2(sc_if, YUKON_RCR,
452 YU_RCR_UFLEN | YU_RCR_MUFLEN);
453 }
454
455 static int
msk_init_rx_ring(struct sk_if_softc * sc_if)456 msk_init_rx_ring(struct sk_if_softc *sc_if)
457 {
458 struct msk_chain_data *cd = &sc_if->sk_cdata;
459 struct msk_ring_data *rd = sc_if->sk_rdata;
460 struct msk_rx_desc *r;
461
462 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT);
463
464 sc_if->sk_cdata.sk_rx_prod = 0;
465 sc_if->sk_cdata.sk_rx_cons = 0;
466 sc_if->sk_cdata.sk_rx_cnt = 0;
467 sc_if->sk_cdata.sk_rx_hiaddr = 0;
468
469 /* Mark the first ring element to initialize the high address. */
470 sc_if->sk_cdata.sk_rx_hiaddr = 0;
471 r = &rd->sk_rx_ring[cd->sk_rx_prod];
472 r->sk_addr = htole32(cd->sk_rx_hiaddr);
473 r->sk_len = 0;
474 r->sk_ctl = 0;
475 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_RXOPC_OWN;
476 MSK_CDRXSYNC(sc_if, cd->sk_rx_prod,
477 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
478 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT);
479 sc_if->sk_cdata.sk_rx_cnt++;
480
481 msk_fill_rx_ring(sc_if);
482 return 0;
483 }
484
485 static int
msk_init_tx_ring(struct sk_if_softc * sc_if)486 msk_init_tx_ring(struct sk_if_softc *sc_if)
487 {
488 struct msk_chain_data *cd = &sc_if->sk_cdata;
489 struct msk_ring_data *rd = sc_if->sk_rdata;
490 struct msk_tx_desc *t;
491
492 memset(rd->sk_tx_ring, 0, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT);
493
494 sc_if->sk_cdata.sk_tx_prod = 0;
495 sc_if->sk_cdata.sk_tx_cons = 0;
496 sc_if->sk_cdata.sk_tx_cnt = 0;
497 sc_if->sk_cdata.sk_tx_hiaddr = 0;
498
499 /* Mark the first ring element to initialize the high address. */
500 sc_if->sk_cdata.sk_tx_hiaddr = 0;
501 t = &rd->sk_tx_ring[cd->sk_tx_prod];
502 t->sk_addr = htole32(cd->sk_tx_hiaddr);
503 t->sk_len = 0;
504 t->sk_ctl = 0;
505 t->sk_opcode = SK_Y2_BMUOPC_ADDR64 | SK_Y2_TXOPC_OWN;
506 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT,
507 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
508 SK_INC(sc_if->sk_cdata.sk_tx_prod, MSK_TX_RING_CNT);
509 sc_if->sk_cdata.sk_tx_cnt++;
510
511 return 0;
512 }
513
514 static int
msk_newbuf(struct sk_if_softc * sc_if)515 msk_newbuf(struct sk_if_softc *sc_if)
516 {
517 struct sk_softc *sc = sc_if->sk_softc;
518 struct mbuf *m_new = NULL;
519 struct sk_chain *c;
520 struct msk_rx_desc *r;
521 void *buf = NULL;
522 bus_addr_t addr;
523 bus_dmamap_t rxmap;
524 size_t i;
525 uint32_t rxidx, frag, cur, hiaddr, total;
526 uint32_t entries = 0;
527 uint8_t own = 0;
528
529 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
530 if (m_new == NULL)
531 return ENOBUFS;
532
533 /* Allocate the jumbo buffer */
534 buf = msk_jalloc(sc_if);
535 if (buf == NULL) {
536 m_freem(m_new);
537 DPRINTFN(1, ("%s jumbo allocation failed -- packet "
538 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname));
539 return ENOBUFS;
540 }
541
542 /* Attach the buffer to the mbuf */
543 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN;
544 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if);
545
546 m_adj(m_new, ETHER_ALIGN);
547
548 rxidx = frag = cur = sc_if->sk_cdata.sk_rx_prod;
549 rxmap = sc_if->sk_cdata.sk_rx_chain[rxidx].sk_dmamap;
550
551 if (bus_dmamap_load_mbuf(sc->sc_dmatag, rxmap, m_new, BUS_DMA_NOWAIT)) {
552 DPRINTFN(2, ("msk_newbuf: dmamap_load failed\n"));
553 m_freem(m_new);
554 return ENOBUFS;
555 }
556
557 /* Count how many rx descriptors needed. */
558 hiaddr = sc_if->sk_cdata.sk_rx_hiaddr;
559 for (total = i = 0; i < rxmap->dm_nsegs; i++) {
560 if (hiaddr != MSK_ADDR_HI(rxmap->dm_segs[i].ds_addr)) {
561 hiaddr = MSK_ADDR_HI(rxmap->dm_segs[i].ds_addr);
562 total++;
563 }
564 total++;
565 }
566
567 if (total > MSK_RX_RING_CNT - sc_if->sk_cdata.sk_rx_cnt - 1) {
568 DPRINTFN(2, ("msk_newbuf: too few descriptors free\n"));
569 bus_dmamap_unload(sc->sc_dmatag, rxmap);
570 m_freem(m_new);
571 return ENOBUFS;
572 }
573
574 DPRINTFN(2, ("msk_newbuf: dm_nsegs=%d total desc=%u\n",
575 rxmap->dm_nsegs, total));
576
577 /* Sync the DMA map. */
578 bus_dmamap_sync(sc->sc_dmatag, rxmap, 0, rxmap->dm_mapsize,
579 BUS_DMASYNC_PREREAD);
580
581 for (i = 0; i < rxmap->dm_nsegs; i++) {
582 addr = rxmap->dm_segs[i].ds_addr;
583 DPRINTFN(2, ("msk_newbuf: addr %llx\n",
584 (unsigned long long)addr));
585 hiaddr = MSK_ADDR_HI(addr);
586
587 if (sc_if->sk_cdata.sk_rx_hiaddr != hiaddr) {
588 c = &sc_if->sk_cdata.sk_rx_chain[frag];
589 c->sk_mbuf = NULL;
590 r = &sc_if->sk_rdata->sk_rx_ring[frag];
591 r->sk_addr = htole32(hiaddr);
592 r->sk_len = 0;
593 r->sk_ctl = 0;
594 r->sk_opcode = SK_Y2_BMUOPC_ADDR64 | own;
595 own = SK_Y2_RXOPC_OWN;
596 sc_if->sk_cdata.sk_rx_hiaddr = hiaddr;
597 MSK_CDRXSYNC(sc_if, frag,
598 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
599 SK_INC(frag, MSK_RX_RING_CNT);
600 entries++;
601 DPRINTFN(10, ("%s: rx ADDR64: %#x\n",
602 sc_if->sk_ethercom.ec_if.if_xname, hiaddr));
603 }
604
605 c = &sc_if->sk_cdata.sk_rx_chain[frag];
606 r = &sc_if->sk_rdata->sk_rx_ring[frag];
607 r->sk_addr = htole32(MSK_ADDR_LO(addr));
608 r->sk_len = htole16(rxmap->dm_segs[i].ds_len);
609 r->sk_ctl = 0;
610 if (i == 0) {
611 r->sk_opcode = SK_Y2_RXOPC_PACKET | own;
612 } else
613 r->sk_opcode = SK_Y2_RXOPC_BUFFER | own;
614 own = SK_Y2_RXOPC_OWN;
615 MSK_CDRXSYNC(sc_if, frag,
616 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
617 cur = frag;
618 SK_INC(frag, MSK_RX_RING_CNT);
619 entries++;
620 }
621 KASSERTMSG(entries == total, "entries %u total %u", entries, total);
622
623 sc_if->sk_cdata.sk_rx_chain[rxidx].sk_dmamap =
624 sc_if->sk_cdata.sk_rx_chain[cur].sk_dmamap;
625 sc_if->sk_cdata.sk_rx_chain[cur].sk_mbuf = m_new;
626 sc_if->sk_cdata.sk_rx_chain[cur].sk_dmamap = rxmap;
627
628 sc_if->sk_rdata->sk_rx_ring[rxidx].sk_opcode |= SK_Y2_RXOPC_OWN;
629 MSK_CDRXSYNC(sc_if, rxidx,
630 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
631
632 sc_if->sk_cdata.sk_rx_cnt += entries;
633 sc_if->sk_cdata.sk_rx_prod = frag;
634
635 return 0;
636 }
637
638 /*
639 * Memory management for jumbo frames.
640 */
641
642 static int
msk_alloc_jumbo_mem(struct sk_if_softc * sc_if)643 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if)
644 {
645 struct sk_softc *sc = sc_if->sk_softc;
646 char *ptr, *kva;
647 int i, state, error;
648 struct sk_jpool_entry *entry;
649
650 state = error = 0;
651
652 /* Grab a big chunk o' storage. */
653 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0,
654 &sc_if->sk_cdata.sk_jumbo_seg, 1, &sc_if->sk_cdata.sk_jumbo_nseg,
655 BUS_DMA_NOWAIT)) {
656 aprint_error(": can't alloc rx buffers");
657 return ENOBUFS;
658 }
659
660 state = 1;
661 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg,
662 sc_if->sk_cdata.sk_jumbo_nseg, MSK_JMEM, (void **)&kva,
663 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) {
664 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM);
665 error = ENOBUFS;
666 goto out;
667 }
668
669 state = 2;
670 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0,
671 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) {
672 aprint_error(": can't create dma map");
673 error = ENOBUFS;
674 goto out;
675 }
676
677 state = 3;
678 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map,
679 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) {
680 aprint_error(": can't load dma map");
681 error = ENOBUFS;
682 goto out;
683 }
684
685 state = 4;
686 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva;
687 DPRINTFN(1,("msk_jumbo_buf = %p\n",
688 (void *)sc_if->sk_cdata.sk_jumbo_buf));
689
690 LIST_INIT(&sc_if->sk_jfree_listhead);
691 LIST_INIT(&sc_if->sk_jinuse_listhead);
692 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET);
693
694 /*
695 * Now divide it up into 9K pieces and save the addresses
696 * in an array.
697 */
698 ptr = sc_if->sk_cdata.sk_jumbo_buf;
699 for (i = 0; i < MSK_JSLOTS; i++) {
700 sc_if->sk_cdata.sk_jslots[i] = ptr;
701 ptr += SK_JLEN;
702 entry = malloc(sizeof(struct sk_jpool_entry),
703 M_DEVBUF, M_WAITOK);
704 entry->slot = i;
705 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
706 entry, jpool_entries);
707 }
708 out:
709 if (error != 0) {
710 switch (state) {
711 case 4:
712 bus_dmamap_unload(sc->sc_dmatag,
713 sc_if->sk_cdata.sk_rx_jumbo_map);
714 /* FALLTHROUGH */
715 case 3:
716 bus_dmamap_destroy(sc->sc_dmatag,
717 sc_if->sk_cdata.sk_rx_jumbo_map);
718 /* FALLTHROUGH */
719 case 2:
720 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM);
721 /* FALLTHROUGH */
722 case 1:
723 bus_dmamem_free(sc->sc_dmatag,
724 &sc_if->sk_cdata.sk_jumbo_seg,
725 sc_if->sk_cdata.sk_jumbo_nseg);
726 break;
727 default:
728 break;
729 }
730 }
731
732 return error;
733 }
734
735 static void
msk_free_jumbo_mem(struct sk_if_softc * sc_if)736 msk_free_jumbo_mem(struct sk_if_softc *sc_if)
737 {
738 struct sk_softc *sc = sc_if->sk_softc;
739
740 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map);
741 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map);
742 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_cdata.sk_jumbo_buf, MSK_JMEM);
743 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_cdata.sk_jumbo_seg,
744 sc_if->sk_cdata.sk_jumbo_nseg);
745 }
746
747 /*
748 * Allocate a jumbo buffer.
749 */
750 static void *
msk_jalloc(struct sk_if_softc * sc_if)751 msk_jalloc(struct sk_if_softc *sc_if)
752 {
753 struct sk_jpool_entry *entry;
754
755 mutex_enter(&sc_if->sk_jpool_mtx);
756 entry = LIST_FIRST(&sc_if->sk_jfree_listhead);
757
758 if (entry == NULL) {
759 mutex_exit(&sc_if->sk_jpool_mtx);
760 return NULL;
761 }
762
763 LIST_REMOVE(entry, jpool_entries);
764 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries);
765 mutex_exit(&sc_if->sk_jpool_mtx);
766 return sc_if->sk_cdata.sk_jslots[entry->slot];
767 }
768
769 /*
770 * Release a jumbo buffer.
771 */
772 static void
msk_jfree(struct mbuf * m,void * buf,size_t size,void * arg)773 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg)
774 {
775 struct sk_jpool_entry *entry;
776 struct sk_if_softc *sc;
777 int i;
778
779 /* Extract the softc struct pointer. */
780 sc = (struct sk_if_softc *)arg;
781
782 if (sc == NULL)
783 panic("msk_jfree: can't find softc pointer!");
784
785 /* calculate the slot this buffer belongs to */
786 i = ((vaddr_t)buf
787 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN;
788
789 if ((i < 0) || (i >= MSK_JSLOTS))
790 panic("msk_jfree: asked to free buffer that we don't manage!");
791
792 mutex_enter(&sc->sk_jpool_mtx);
793 entry = LIST_FIRST(&sc->sk_jinuse_listhead);
794 if (entry == NULL)
795 panic("msk_jfree: buffer not in use!");
796 entry->slot = i;
797 LIST_REMOVE(entry, jpool_entries);
798 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries);
799 mutex_exit(&sc->sk_jpool_mtx);
800
801 if (__predict_true(m != NULL))
802 pool_cache_put(mb_cache, m);
803
804 /* Now that we know we have a free RX buffer, refill if running out */
805 if ((sc->sk_ethercom.ec_if.if_flags & IFF_RUNNING) != 0
806 && sc->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3))
807 callout_schedule(&sc->sk_tick_rx, 0);
808 }
809
810 static int
msk_ioctl(struct ifnet * ifp,u_long cmd,void * data)811 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data)
812 {
813 struct sk_if_softc *sc = ifp->if_softc;
814 int s, error;
815
816 s = splnet();
817
818 DPRINTFN(2, ("msk_ioctl ETHER cmd %lx\n", cmd));
819 switch (cmd) {
820 case SIOCSIFFLAGS:
821 if ((error = ifioctl_common(ifp, cmd, data)) != 0)
822 break;
823
824 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
825 case IFF_RUNNING:
826 msk_stop(ifp, 1);
827 break;
828 case IFF_UP:
829 msk_init(ifp);
830 break;
831 case IFF_UP | IFF_RUNNING:
832 if ((ifp->if_flags ^ sc->sk_if_flags) == IFF_PROMISC) {
833 msk_setpromisc(sc);
834 msk_setmulti(sc);
835 } else
836 msk_init(ifp);
837 break;
838 }
839 sc->sk_if_flags = ifp->if_flags;
840 break;
841 default:
842 error = ether_ioctl(ifp, cmd, data);
843 if (error == ENETRESET) {
844 error = 0;
845 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI)
846 ;
847 else if (ifp->if_flags & IFF_RUNNING) {
848 /*
849 * Multicast list has changed; set the hardware
850 * filter accordingly.
851 */
852 msk_setmulti(sc);
853 }
854 }
855 break;
856 }
857
858 splx(s);
859 return error;
860 }
861
862 static void
msk_update_int_mod(struct sk_softc * sc,int verbose)863 msk_update_int_mod(struct sk_softc *sc, int verbose)
864 {
865 uint32_t imtimer_ticks;
866
867 /*
868 * Configure interrupt moderation. The moderation timer
869 * defers interrupts specified in the interrupt moderation
870 * timer mask based on the timeout specified in the interrupt
871 * moderation timer init register. Each bit in the timer
872 * register represents one tick, so to specify a timeout in
873 * microseconds, we have to multiply by the correct number of
874 * ticks-per-microsecond.
875 */
876 switch (sc->sk_type) {
877 case SK_YUKON_EC:
878 case SK_YUKON_EC_U:
879 case SK_YUKON_EX:
880 case SK_YUKON_SUPR:
881 case SK_YUKON_ULTRA2:
882 case SK_YUKON_OPTIMA:
883 case SK_YUKON_PRM:
884 case SK_YUKON_OPTIMA2:
885 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC;
886 break;
887 case SK_YUKON_FE:
888 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE;
889 break;
890 case SK_YUKON_FE_P:
891 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P;
892 break;
893 case SK_YUKON_XL:
894 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL;
895 break;
896 default:
897 imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
898 }
899 if (verbose)
900 aprint_verbose_dev(sc->sk_dev,
901 "interrupt moderation is %d us\n", sc->sk_int_mod);
902 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod));
903 sk_win_write_4(sc, SK_IMMR, 0); /* moderate no interrupts */
904 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
905 sc->sk_int_mod_pending = 0;
906 }
907
908 /*
909 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
910 * IDs against our list and return a device name if we find a match.
911 */
912 static int
mskc_probe(device_t parent,cfdata_t match,void * aux)913 mskc_probe(device_t parent, cfdata_t match, void *aux)
914 {
915 struct pci_attach_args *pa = (struct pci_attach_args *)aux;
916
917 return pci_compatible_match(pa, compat_data);
918 }
919
920 /*
921 * Force the GEnesis into reset, then bring it out of reset.
922 */
923 static void
mskc_reset(struct sk_softc * sc)924 mskc_reset(struct sk_softc *sc)
925 {
926 uint32_t imtimer_ticks, reg1;
927 uint16_t status;
928 int reg;
929
930 DPRINTFN(2, ("mskc_reset\n"));
931
932 /* Disable ASF */
933 if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_SUPR)) {
934 CSR_WRITE_4(sc, SK_Y2_CPU_WDOG, 0);
935 status = CSR_READ_2(sc, SK_Y2_ASF_HCU_CCSR);
936 /* Clear AHB bridge & microcontroller reset. */
937 status &= ~(SK_Y2_ASF_HCU_CSSR_ARB_RST |
938 SK_Y2_ASF_HCU_CSSR_CPU_RST_MODE);
939 /* Clear ASF microcontroller state. */
940 status &= ~SK_Y2_ASF_HCU_CSSR_UC_STATE_MSK;
941 status &= ~SK_Y2_ASF_HCU_CSSR_CPU_CLK_DIVIDE_MSK;
942 CSR_WRITE_2(sc, SK_Y2_ASF_HCU_CCSR, status);
943 CSR_WRITE_4(sc, SK_Y2_CPU_WDOG, 0);
944 } else
945 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET);
946 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF);
947
948 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET);
949 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET);
950
951 DELAY(1000);
952 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET);
953 DELAY(2);
954 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
955 sk_win_write_1(sc, SK_TESTCTL1, 2);
956
957 if (sc->sk_type == SK_YUKON_EC_U || sc->sk_type == SK_YUKON_EX ||
958 sc->sk_type >= SK_YUKON_FE_P) {
959 uint32_t our;
960
961 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON);
962
963 /* enable all clocks. */
964 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0);
965 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4));
966 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST |
967 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN |
968 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY |
969 SK_Y2_REG4_ASPM_CLKRUN_REQUEST);
970 /* Set all bits to 0 except bits 15..12 */
971 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our);
972 /* Set to default value */
973 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0);
974
975 /*
976 * Disable status race, workaround for Yukon EC Ultra &
977 * Yukon EX.
978 */
979 reg1 = sk_win_read_4(sc, SK_GPIO);
980 reg1 |= SK_Y2_GPIO_STAT_RACE_DIS;
981 sk_win_write_4(sc, SK_GPIO, reg1);
982 sk_win_read_4(sc, SK_GPIO);
983 }
984
985 /* release PHY from PowerDown/Coma mode. */
986 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1));
987 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1)
988 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA);
989 else
990 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA);
991 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1);
992
993 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1)
994 sk_win_write_1(sc, SK_Y2_CLKGATE,
995 SK_Y2_CLKGATE_LINK1_GATE_DIS |
996 SK_Y2_CLKGATE_LINK2_GATE_DIS |
997 SK_Y2_CLKGATE_LINK1_CORE_DIS |
998 SK_Y2_CLKGATE_LINK2_CORE_DIS |
999 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS);
1000 else
1001 sk_win_write_1(sc, SK_Y2_CLKGATE, 0);
1002
1003 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1004 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET);
1005 DELAY(1000);
1006 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1007 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR);
1008
1009 if (sc->sk_type == SK_YUKON_EX || sc->sk_type == SK_YUKON_SUPR) {
1010 CSR_WRITE_2(sc, SK_GMAC_CTRL, SK_GMAC_BYP_MACSECRX |
1011 SK_GMAC_BYP_MACSECTX | SK_GMAC_BYP_RETR_FIFO);
1012 }
1013
1014 sk_win_write_1(sc, SK_TESTCTL1, 1);
1015
1016 DPRINTFN(2, ("mskc_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR)));
1017 DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n",
1018 CSR_READ_2(sc, SK_LINK_CTRL)));
1019
1020 /* Clear I2C IRQ noise */
1021 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1);
1022
1023 /* Disable hardware timer */
1024 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP);
1025 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR);
1026
1027 /* Disable descriptor polling */
1028 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
1029
1030 /* Disable time stamps */
1031 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP);
1032 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR);
1033
1034 /* Enable RAM interface */
1035 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1036 for (reg = SK_TO0;reg <= SK_TO11; reg++)
1037 sk_win_write_1(sc, reg, 36);
1038 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET);
1039 for (reg = SK_TO0;reg <= SK_TO11; reg++)
1040 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36);
1041
1042 /*
1043 * Configure interrupt moderation. The moderation timer
1044 * defers interrupts specified in the interrupt moderation
1045 * timer mask based on the timeout specified in the interrupt
1046 * moderation timer init register. Each bit in the timer
1047 * register represents one tick, so to specify a timeout in
1048 * microseconds, we have to multiply by the correct number of
1049 * ticks-per-microsecond.
1050 */
1051 switch (sc->sk_type) {
1052 case SK_YUKON_EC:
1053 case SK_YUKON_EC_U:
1054 case SK_YUKON_EX:
1055 case SK_YUKON_SUPR:
1056 case SK_YUKON_ULTRA2:
1057 case SK_YUKON_OPTIMA:
1058 case SK_YUKON_PRM:
1059 case SK_YUKON_OPTIMA2:
1060 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC;
1061 break;
1062 case SK_YUKON_FE:
1063 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE;
1064 break;
1065 case SK_YUKON_FE_P:
1066 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P;
1067 break;
1068 case SK_YUKON_XL:
1069 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL;
1070 break;
1071 default:
1072 imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
1073 break;
1074 }
1075
1076 /* Reset status ring. */
1077 memset(sc->sk_status_ring, 0,
1078 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc));
1079 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0,
1080 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD);
1081 sc->sk_status_idx = 0;
1082
1083 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET);
1084 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET);
1085
1086 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1);
1087 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO,
1088 MSK_ADDR_LO(sc->sk_status_map->dm_segs[0].ds_addr));
1089 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI,
1090 MSK_ADDR_HI(sc->sk_status_map->dm_segs[0].ds_addr));
1091 if (sc->sk_type == SK_YUKON_EC &&
1092 sc->sk_rev == SK_YUKON_EC_REV_A1) {
1093 /* WA for dev. #4.3 */
1094 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH,
1095 SK_STAT_BMU_TXTHIDX_MSK);
1096 /* WA for dev. #4.18 */
1097 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21);
1098 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07);
1099 } else {
1100 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a);
1101 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10);
1102 if (sc->sk_type == SK_YUKON_XL)
1103 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x04);
1104 else
1105 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x10);
1106 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */
1107 }
1108
1109 #if 0
1110 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100));
1111 #endif
1112 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000));
1113
1114 /* Enable status unit. */
1115 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON);
1116
1117 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START);
1118 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START);
1119 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START);
1120
1121 msk_update_int_mod(sc, 0);
1122 }
1123
1124 static int
msk_probe(device_t parent,cfdata_t match,void * aux)1125 msk_probe(device_t parent, cfdata_t match, void *aux)
1126 {
1127 struct skc_attach_args *sa = aux;
1128
1129 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B)
1130 return 0;
1131
1132 switch (sa->skc_type) {
1133 case SK_YUKON_XL:
1134 case SK_YUKON_EC_U:
1135 case SK_YUKON_EX:
1136 case SK_YUKON_EC:
1137 case SK_YUKON_FE:
1138 case SK_YUKON_FE_P:
1139 case SK_YUKON_SUPR:
1140 case SK_YUKON_ULTRA2:
1141 case SK_YUKON_OPTIMA:
1142 case SK_YUKON_PRM:
1143 case SK_YUKON_OPTIMA2:
1144 return 1;
1145 }
1146
1147 return 0;
1148 }
1149
1150 static void
msk_reset(struct sk_if_softc * sc_if)1151 msk_reset(struct sk_if_softc *sc_if)
1152 {
1153 /* GMAC and GPHY Reset */
1154 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
1155 SK_IF_WRITE_1(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
1156 DELAY(1000);
1157 SK_IF_WRITE_1(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR);
1158 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
1159 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
1160 }
1161
1162 static bool
msk_resume(device_t dv,const pmf_qual_t * qual)1163 msk_resume(device_t dv, const pmf_qual_t *qual)
1164 {
1165 struct sk_if_softc *sc_if = device_private(dv);
1166
1167 msk_init_yukon(sc_if);
1168 return true;
1169 }
1170
1171 /*
1172 * Each XMAC chip is attached as a separate logical IP interface.
1173 * Single port cards will have only one logical interface of course.
1174 */
1175 static void
msk_attach(device_t parent,device_t self,void * aux)1176 msk_attach(device_t parent, device_t self, void *aux)
1177 {
1178 struct sk_if_softc *sc_if = device_private(self);
1179 struct sk_softc *sc = device_private(parent);
1180 struct skc_attach_args *sa = aux;
1181 bus_dmamap_t dmamap;
1182 struct ifnet *ifp;
1183 struct mii_data * const mii = &sc_if->sk_mii;
1184 void *kva;
1185 int i;
1186 uint32_t chunk;
1187 int mii_flags;
1188
1189 sc_if->sk_dev = self;
1190 sc_if->sk_port = sa->skc_port;
1191 sc_if->sk_softc = sc;
1192 sc->sk_if[sa->skc_port] = sc_if;
1193
1194 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port));
1195
1196 /*
1197 * Get station address for this interface. Note that
1198 * dual port cards actually come with three station
1199 * addresses: one for each port, plus an extra. The
1200 * extra one is used by the SysKonnect driver software
1201 * as a 'virtual' station address for when both ports
1202 * are operating in failover mode. Currently we don't
1203 * use this extra address.
1204 */
1205 for (i = 0; i < ETHER_ADDR_LEN; i++)
1206 sc_if->sk_enaddr[i] =
1207 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i);
1208
1209 aprint_normal(": Ethernet address %s\n",
1210 ether_sprintf(sc_if->sk_enaddr));
1211
1212 /*
1213 * Set up RAM buffer addresses. The Yukon2 has a small amount
1214 * of SRAM on it, somewhere between 4K and 48K. We need to
1215 * divide this up between the transmitter and receiver. We
1216 * give the receiver 2/3 of the memory (rounded down), and the
1217 * transmitter whatever remains.
1218 */
1219 if (sc->sk_ramsize) {
1220 chunk = (2 * (sc->sk_ramsize / sizeof(uint64_t)) / 3) & ~0xff;
1221 sc_if->sk_rx_ramstart = 0;
1222 sc_if->sk_rx_ramend = sc_if->sk_rx_ramstart + chunk - 1;
1223 chunk = (sc->sk_ramsize / sizeof(uint64_t)) - chunk;
1224 sc_if->sk_tx_ramstart = sc_if->sk_rx_ramend + 1;
1225 sc_if->sk_tx_ramend = sc_if->sk_tx_ramstart + chunk - 1;
1226
1227 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n"
1228 " tx_ramstart=%#x tx_ramend=%#x\n",
1229 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend,
1230 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend));
1231 }
1232
1233 /* Allocate the descriptor queues. */
1234 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data),
1235 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg,
1236 BUS_DMA_NOWAIT)) {
1237 aprint_error(": can't alloc rx buffers\n");
1238 goto fail;
1239 }
1240 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg,
1241 sc_if->sk_ring_nseg,
1242 sizeof(struct msk_ring_data), &kva,
1243 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) {
1244 aprint_error(": can't map dma buffers (%zu bytes)\n",
1245 sizeof(struct msk_ring_data));
1246 goto fail_1;
1247 }
1248 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1,
1249 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT,
1250 &sc_if->sk_ring_map)) {
1251 aprint_error(": can't create dma map\n");
1252 goto fail_2;
1253 }
1254 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva,
1255 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) {
1256 aprint_error(": can't load dma map\n");
1257 goto fail_3;
1258 }
1259
1260 for (i = 0; i < MSK_TX_RING_CNT; i++) {
1261 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL;
1262
1263 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG,
1264 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) {
1265 aprint_error_dev(sc_if->sk_dev,
1266 "Can't create TX dmamap\n");
1267 goto fail_3;
1268 }
1269
1270 sc_if->sk_cdata.sk_tx_chain[i].sk_dmamap = dmamap;
1271 }
1272
1273 for (i = 0; i < MSK_RX_RING_CNT; i++) {
1274 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL;
1275
1276 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN,
1277 howmany(SK_JLEN + 1, NBPG),
1278 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) {
1279 aprint_error_dev(sc_if->sk_dev,
1280 "Can't create RX dmamap\n");
1281 goto fail_3;
1282 }
1283
1284 sc_if->sk_cdata.sk_rx_chain[i].sk_dmamap = dmamap;
1285 }
1286
1287 sc_if->sk_rdata = (struct msk_ring_data *)kva;
1288 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data));
1289
1290 if (sc->sk_type != SK_YUKON_FE &&
1291 sc->sk_type != SK_YUKON_FE_P)
1292 sc_if->sk_pktlen = SK_JLEN;
1293 else
1294 sc_if->sk_pktlen = MCLBYTES;
1295
1296 /* Try to allocate memory for jumbo buffers. */
1297 if (msk_alloc_jumbo_mem(sc_if)) {
1298 aprint_error(": jumbo buffer allocation failed\n");
1299 goto fail_3;
1300 }
1301
1302 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU;
1303 if (sc->sk_type != SK_YUKON_FE &&
1304 sc->sk_type != SK_YUKON_FE_P)
1305 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
1306
1307 ifp = &sc_if->sk_ethercom.ec_if;
1308 ifp->if_softc = sc_if;
1309 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1310 ifp->if_ioctl = msk_ioctl;
1311 ifp->if_start = msk_start;
1312 ifp->if_stop = msk_stop;
1313 ifp->if_init = msk_init;
1314 ifp->if_watchdog = msk_watchdog;
1315 ifp->if_baudrate = 1000000000;
1316 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1);
1317 IFQ_SET_READY(&ifp->if_snd);
1318 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ);
1319
1320 msk_reset(sc_if);
1321
1322 /*
1323 * Do miibus setup.
1324 */
1325 DPRINTFN(2, ("msk_attach: 1\n"));
1326
1327 mii->mii_ifp = ifp;
1328 mii->mii_readreg = msk_miibus_readreg;
1329 mii->mii_writereg = msk_miibus_writereg;
1330 mii->mii_statchg = msk_miibus_statchg;
1331
1332 sc_if->sk_ethercom.ec_mii = mii;
1333 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus);
1334 mii_flags = MIIF_DOPAUSE;
1335 if (sc->sk_fibertype)
1336 mii_flags |= MIIF_HAVEFIBER;
1337 mii_attach(self, mii, 0xffffffff, 0, MII_OFFSET_ANY, mii_flags);
1338 if (LIST_FIRST(&mii->mii_phys) == NULL) {
1339 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n");
1340 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL,
1341 0, NULL);
1342 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL);
1343 } else
1344 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
1345
1346 callout_init(&sc_if->sk_tick_ch, 0);
1347 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if);
1348 callout_schedule(&sc_if->sk_tick_ch, hz);
1349
1350 callout_init(&sc_if->sk_tick_rx, 0);
1351 callout_setfunc(&sc_if->sk_tick_rx, msk_fill_rx_tick, sc_if);
1352
1353 /*
1354 * Call MI attach routines.
1355 */
1356 if_attach(ifp);
1357 if_deferred_start_init(ifp, NULL);
1358 ether_ifattach(ifp, sc_if->sk_enaddr);
1359
1360 if (pmf_device_register(self, NULL, msk_resume))
1361 pmf_class_network_register(self, ifp);
1362 else
1363 aprint_error_dev(self, "couldn't establish power handler\n");
1364
1365 if (sc->rnd_attached++ == 0) {
1366 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev),
1367 RND_TYPE_NET, RND_FLAG_DEFAULT);
1368 }
1369
1370 DPRINTFN(2, ("msk_attach: end\n"));
1371 return;
1372
1373 fail_3:
1374 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map);
1375 fail_2:
1376 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data));
1377 fail_1:
1378 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg);
1379 fail:
1380 sc->sk_if[sa->skc_port] = NULL;
1381 }
1382
1383 static int
msk_detach(device_t self,int flags)1384 msk_detach(device_t self, int flags)
1385 {
1386 struct sk_if_softc *sc_if = device_private(self);
1387 struct sk_softc *sc = sc_if->sk_softc;
1388 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if;
1389 int i;
1390
1391 if (sc->sk_if[sc_if->sk_port] == NULL)
1392 return 0;
1393
1394 msk_stop(ifp, 1);
1395
1396 for (i = 0; i < MSK_TX_RING_CNT; i++) {
1397 bus_dmamap_destroy(sc->sc_dmatag,
1398 sc_if->sk_cdata.sk_tx_chain[i].sk_dmamap);
1399 }
1400
1401 for (i = 0; i < MSK_RX_RING_CNT; i++) {
1402 bus_dmamap_destroy(sc->sc_dmatag,
1403 sc_if->sk_cdata.sk_rx_chain[i].sk_dmamap);
1404 }
1405
1406 if (--sc->rnd_attached == 0)
1407 rnd_detach_source(&sc->rnd_source);
1408
1409 callout_halt(&sc_if->sk_tick_ch, NULL);
1410 callout_destroy(&sc_if->sk_tick_ch);
1411
1412 callout_halt(&sc_if->sk_tick_rx, NULL);
1413 callout_destroy(&sc_if->sk_tick_rx);
1414
1415 /* Detach any PHYs we might have. */
1416 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL)
1417 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY);
1418
1419 pmf_device_deregister(self);
1420
1421 ether_ifdetach(ifp);
1422 if_detach(ifp);
1423
1424 /* Delete any remaining media. */
1425 ifmedia_fini(&sc_if->sk_mii.mii_media);
1426
1427 msk_free_jumbo_mem(sc_if);
1428
1429 bus_dmamem_unmap(sc->sc_dmatag, sc_if->sk_rdata,
1430 sizeof(struct msk_ring_data));
1431 bus_dmamem_free(sc->sc_dmatag,
1432 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg);
1433 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map);
1434 sc->sk_if[sc_if->sk_port] = NULL;
1435
1436 return 0;
1437 }
1438
1439 static int
mskcprint(void * aux,const char * pnp)1440 mskcprint(void *aux, const char *pnp)
1441 {
1442 struct skc_attach_args *sa = aux;
1443
1444 if (pnp)
1445 aprint_normal("msk port %c at %s",
1446 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp);
1447 else
1448 aprint_normal(" port %c",
1449 (sa->skc_port == SK_PORT_A) ? 'A' : 'B');
1450 return UNCONF;
1451 }
1452
1453 /*
1454 * Attach the interface. Allocate softc structures, do ifmedia
1455 * setup and ethernet/BPF attach.
1456 */
1457 static void
mskc_attach(device_t parent,device_t self,void * aux)1458 mskc_attach(device_t parent, device_t self, void *aux)
1459 {
1460 struct sk_softc *sc = device_private(self);
1461 struct pci_attach_args *pa = aux;
1462 struct skc_attach_args skca;
1463 pci_chipset_tag_t pc = pa->pa_pc;
1464 pcireg_t command, memtype;
1465 const char *intrstr = NULL;
1466 int rc, sk_nodenum;
1467 uint8_t hw, pmd;
1468 const char *revstr = NULL;
1469 const struct sysctlnode *node;
1470 void *kva;
1471 char intrbuf[PCI_INTRSTR_LEN];
1472
1473 DPRINTFN(2, ("begin mskc_attach\n"));
1474
1475 sc->sk_dev = self;
1476 /*
1477 * Handle power management nonsense.
1478 */
1479 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF;
1480
1481 if (command == 0x01) {
1482 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL);
1483 if (command & SK_PSTATE_MASK) {
1484 uint32_t iobase, membase, irq;
1485
1486 /* Save important PCI config data. */
1487 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO);
1488 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM);
1489 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE);
1490
1491 /* Reset the power state. */
1492 aprint_normal_dev(sc->sk_dev, "chip is in D%d power "
1493 "mode -- setting to D0\n",
1494 command & SK_PSTATE_MASK);
1495 command &= 0xFFFFFFFC;
1496 pci_conf_write(pc, pa->pa_tag,
1497 SK_PCI_PWRMGMTCTRL, command);
1498
1499 /* Restore PCI config data. */
1500 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase);
1501 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase);
1502 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq);
1503 }
1504 }
1505
1506 /*
1507 * Map control/status registers.
1508 */
1509 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM);
1510 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag,
1511 &sc->sk_bhandle, NULL, &sc->sk_bsize)) {
1512 aprint_error(": can't map mem space\n");
1513 return;
1514 }
1515
1516 if (pci_dma64_available(pa))
1517 sc->sc_dmatag = pa->pa_dmat64;
1518 else
1519 sc->sc_dmatag = pa->pa_dmat;
1520
1521 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
1522 command |= PCI_COMMAND_MASTER_ENABLE;
1523 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command);
1524
1525 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1526 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4);
1527
1528 /* bail out here if chip is not recognized */
1529 if (!(SK_IS_YUKON2(sc))) {
1530 aprint_error(": unknown chip type: %d\n", sc->sk_type);
1531 goto fail_1;
1532 }
1533 DPRINTFN(2, ("mskc_attach: allocate interrupt\n"));
1534
1535 /* Allocate interrupt */
1536 if (pci_intr_alloc(pa, &sc->sk_pihp, NULL, 0)) {
1537 aprint_error(": couldn't map interrupt\n");
1538 goto fail_1;
1539 }
1540
1541 intrstr = pci_intr_string(pc, sc->sk_pihp[0], intrbuf, sizeof(intrbuf));
1542 sc->sk_intrhand = pci_intr_establish_xname(pc, sc->sk_pihp[0], IPL_NET,
1543 msk_intr, sc, device_xname(sc->sk_dev));
1544 if (sc->sk_intrhand == NULL) {
1545 aprint_error(": couldn't establish interrupt");
1546 if (intrstr != NULL)
1547 aprint_error(" at %s", intrstr);
1548 aprint_error("\n");
1549 goto fail_1;
1550 }
1551 sc->sk_pc = pc;
1552
1553 if (bus_dmamem_alloc(sc->sc_dmatag,
1554 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc),
1555 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc),
1556 0, &sc->sk_status_seg, 1, &sc->sk_status_nseg, BUS_DMA_NOWAIT)) {
1557 aprint_error(": can't alloc status buffers\n");
1558 goto fail_2;
1559 }
1560
1561 if (bus_dmamem_map(sc->sc_dmatag,
1562 &sc->sk_status_seg, sc->sk_status_nseg,
1563 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc),
1564 &kva, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) {
1565 aprint_error(": can't map dma buffers (%zu bytes)\n",
1566 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc));
1567 goto fail_3;
1568 }
1569 if (bus_dmamap_create(sc->sc_dmatag,
1570 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1,
1571 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0,
1572 BUS_DMA_NOWAIT, &sc->sk_status_map)) {
1573 aprint_error(": can't create dma map\n");
1574 goto fail_4;
1575 }
1576 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva,
1577 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc),
1578 NULL, BUS_DMA_NOWAIT)) {
1579 aprint_error(": can't load dma map\n");
1580 goto fail_5;
1581 }
1582 sc->sk_status_ring = (struct msk_status_desc *)kva;
1583
1584 sc->sk_int_mod = SK_IM_DEFAULT;
1585 sc->sk_int_mod_pending = 0;
1586
1587 /* Reset the adapter. */
1588 mskc_reset(sc);
1589
1590 sc->sk_ramsize = sk_win_read_1(sc, SK_EPROM0) * 4096;
1591 DPRINTFN(2, ("mskc_attach: ramsize=%dK\n", sc->sk_ramsize / 1024));
1592
1593 pmd = sk_win_read_1(sc, SK_PMDTYPE);
1594 if (pmd == 'L' || pmd == 'S' || pmd == 'P')
1595 sc->sk_fibertype = 1;
1596
1597 switch (sc->sk_type) {
1598 case SK_YUKON_XL:
1599 sc->sk_name = "Yukon-2 XL";
1600 break;
1601 case SK_YUKON_EC_U:
1602 sc->sk_name = "Yukon-2 EC Ultra";
1603 break;
1604 case SK_YUKON_EX:
1605 sc->sk_name = "Yukon-2 Extreme";
1606 break;
1607 case SK_YUKON_EC:
1608 sc->sk_name = "Yukon-2 EC";
1609 break;
1610 case SK_YUKON_FE:
1611 sc->sk_name = "Yukon-2 FE";
1612 break;
1613 case SK_YUKON_FE_P:
1614 sc->sk_name = "Yukon-2 FE+";
1615 break;
1616 case SK_YUKON_SUPR:
1617 sc->sk_name = "Yukon-2 Supreme";
1618 break;
1619 case SK_YUKON_ULTRA2:
1620 sc->sk_name = "Yukon-2 Ultra 2";
1621 break;
1622 case SK_YUKON_OPTIMA:
1623 sc->sk_name = "Yukon-2 Optima";
1624 break;
1625 case SK_YUKON_PRM:
1626 sc->sk_name = "Yukon-2 Optima Prime";
1627 break;
1628 case SK_YUKON_OPTIMA2:
1629 sc->sk_name = "Yukon-2 Optima 2";
1630 break;
1631 default:
1632 sc->sk_name = "Yukon (Unknown)";
1633 }
1634
1635 if (sc->sk_type == SK_YUKON_XL) {
1636 switch (sc->sk_rev) {
1637 case SK_YUKON_XL_REV_A0:
1638 revstr = "A0";
1639 break;
1640 case SK_YUKON_XL_REV_A1:
1641 revstr = "A1";
1642 break;
1643 case SK_YUKON_XL_REV_A2:
1644 revstr = "A2";
1645 break;
1646 case SK_YUKON_XL_REV_A3:
1647 revstr = "A3";
1648 break;
1649 default:
1650 break;
1651 }
1652 }
1653
1654 if (sc->sk_type == SK_YUKON_EC) {
1655 switch (sc->sk_rev) {
1656 case SK_YUKON_EC_REV_A1:
1657 revstr = "A1";
1658 break;
1659 case SK_YUKON_EC_REV_A2:
1660 revstr = "A2";
1661 break;
1662 case SK_YUKON_EC_REV_A3:
1663 revstr = "A3";
1664 break;
1665 default:
1666 break;
1667 }
1668 }
1669
1670 if (sc->sk_type == SK_YUKON_FE) {
1671 switch (sc->sk_rev) {
1672 case SK_YUKON_FE_REV_A1:
1673 revstr = "A1";
1674 break;
1675 case SK_YUKON_FE_REV_A2:
1676 revstr = "A2";
1677 break;
1678 default:
1679 break;
1680 }
1681 }
1682
1683 if (sc->sk_type == SK_YUKON_EC_U) {
1684 switch (sc->sk_rev) {
1685 case SK_YUKON_EC_U_REV_A0:
1686 revstr = "A0";
1687 break;
1688 case SK_YUKON_EC_U_REV_A1:
1689 revstr = "A1";
1690 break;
1691 case SK_YUKON_EC_U_REV_B0:
1692 revstr = "B0";
1693 break;
1694 case SK_YUKON_EC_U_REV_B1:
1695 revstr = "B1";
1696 break;
1697 default:
1698 break;
1699 }
1700 }
1701
1702 if (sc->sk_type == SK_YUKON_FE) {
1703 switch (sc->sk_rev) {
1704 case SK_YUKON_FE_REV_A1:
1705 revstr = "A1";
1706 break;
1707 case SK_YUKON_FE_REV_A2:
1708 revstr = "A2";
1709 break;
1710 default:
1711 ;
1712 }
1713 }
1714
1715 if (sc->sk_type == SK_YUKON_FE_P && sc->sk_rev == SK_YUKON_FE_P_REV_A0)
1716 revstr = "A0";
1717
1718 if (sc->sk_type == SK_YUKON_EX) {
1719 switch (sc->sk_rev) {
1720 case SK_YUKON_EX_REV_A0:
1721 revstr = "A0";
1722 break;
1723 case SK_YUKON_EX_REV_B0:
1724 revstr = "B0";
1725 break;
1726 default:
1727 ;
1728 }
1729 }
1730
1731 if (sc->sk_type == SK_YUKON_SUPR) {
1732 switch (sc->sk_rev) {
1733 case SK_YUKON_SUPR_REV_A0:
1734 revstr = "A0";
1735 break;
1736 case SK_YUKON_SUPR_REV_B0:
1737 revstr = "B0";
1738 break;
1739 case SK_YUKON_SUPR_REV_B1:
1740 revstr = "B1";
1741 break;
1742 default:
1743 ;
1744 }
1745 }
1746
1747 if (sc->sk_type == SK_YUKON_PRM) {
1748 switch (sc->sk_rev) {
1749 case SK_YUKON_PRM_REV_Z1:
1750 revstr = "Z1";
1751 break;
1752 case SK_YUKON_PRM_REV_A0:
1753 revstr = "A0";
1754 break;
1755 default:
1756 ;
1757 }
1758 }
1759
1760 /* Announce the product name. */
1761 aprint_normal(", %s", sc->sk_name);
1762 if (revstr != NULL)
1763 aprint_normal(" rev. %s", revstr);
1764 aprint_normal(" (0x%x)\n", sc->sk_rev);
1765
1766 aprint_normal_dev(sc->sk_dev, "interrupting at %s\n", intrstr);
1767
1768 sc->sk_macs = 1;
1769
1770 hw = sk_win_read_1(sc, SK_Y2_HWRES);
1771 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) {
1772 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) &
1773 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0)
1774 sc->sk_macs++;
1775 }
1776
1777 skca.skc_port = SK_PORT_A;
1778 skca.skc_type = sc->sk_type;
1779 skca.skc_rev = sc->sk_rev;
1780 (void)config_found(sc->sk_dev, &skca, mskcprint, CFARGS_NONE);
1781
1782 if (sc->sk_macs > 1) {
1783 skca.skc_port = SK_PORT_B;
1784 skca.skc_type = sc->sk_type;
1785 skca.skc_rev = sc->sk_rev;
1786 (void)config_found(sc->sk_dev, &skca, mskcprint, CFARGS_NONE);
1787 }
1788
1789 /* Turn on the 'driver is loaded' LED. */
1790 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1791
1792 /* skc sysctl setup */
1793
1794 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node,
1795 0, CTLTYPE_NODE, device_xname(sc->sk_dev),
1796 SYSCTL_DESCR("mskc per-controller controls"),
1797 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE,
1798 CTL_EOL)) != 0) {
1799 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n");
1800 goto fail_6;
1801 }
1802
1803 sk_nodenum = node->sysctl_num;
1804
1805 /* interrupt moderation time in usecs */
1806 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node,
1807 CTLFLAG_READWRITE,
1808 CTLTYPE_INT, "int_mod",
1809 SYSCTL_DESCR("msk interrupt moderation timer"),
1810 msk_sysctl_handler, 0, (void *)sc,
1811 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE,
1812 CTL_EOL)) != 0) {
1813 aprint_normal_dev(sc->sk_dev,
1814 "couldn't create int_mod sysctl node\n");
1815 goto fail_6;
1816 }
1817
1818 if (!pmf_device_register(self, mskc_suspend, mskc_resume))
1819 aprint_error_dev(self, "couldn't establish power handler\n");
1820
1821 return;
1822
1823 fail_6:
1824 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map);
1825 fail_4:
1826 bus_dmamem_unmap(sc->sc_dmatag, kva,
1827 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc));
1828 fail_3:
1829 bus_dmamem_free(sc->sc_dmatag,
1830 &sc->sk_status_seg, sc->sk_status_nseg);
1831 sc->sk_status_nseg = 0;
1832 fail_5:
1833 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map);
1834 fail_2:
1835 pci_intr_disestablish(pc, sc->sk_intrhand);
1836 sc->sk_intrhand = NULL;
1837 fail_1:
1838 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize);
1839 sc->sk_bsize = 0;
1840 }
1841
1842 static int
mskc_detach(device_t self,int flags)1843 mskc_detach(device_t self, int flags)
1844 {
1845 struct sk_softc *sc = device_private(self);
1846 int rv;
1847
1848 if (sc->sk_intrhand) {
1849 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand);
1850 sc->sk_intrhand = NULL;
1851 }
1852
1853 if (sc->sk_pihp != NULL) {
1854 pci_intr_release(sc->sk_pc, sc->sk_pihp, 1);
1855 sc->sk_pihp = NULL;
1856 }
1857
1858 rv = config_detach_children(self, flags);
1859 if (rv != 0)
1860 return rv;
1861
1862 sysctl_teardown(&sc->sk_clog);
1863
1864 if (sc->sk_status_nseg > 0) {
1865 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map);
1866 bus_dmamem_unmap(sc->sc_dmatag, sc->sk_status_ring,
1867 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc));
1868 bus_dmamem_free(sc->sc_dmatag,
1869 &sc->sk_status_seg, sc->sk_status_nseg);
1870 }
1871
1872 if (sc->sk_bsize > 0)
1873 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize);
1874
1875 return 0;
1876 }
1877
1878 static int
msk_encap(struct sk_if_softc * sc_if,struct mbuf * m_head,uint32_t * txidx)1879 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx)
1880 {
1881 struct sk_softc *sc = sc_if->sk_softc;
1882 struct msk_tx_desc *f = NULL;
1883 uint32_t frag, cur, hiaddr, total;
1884 uint32_t entries = 0;
1885 uint8_t own = 0;
1886 size_t i;
1887 bus_dmamap_t txmap;
1888 bus_addr_t addr;
1889
1890 DPRINTFN(2, ("msk_encap\n"));
1891
1892 txmap = sc_if->sk_cdata.sk_tx_chain[*txidx].sk_dmamap;
1893
1894 cur = frag = *txidx;
1895
1896 #ifdef MSK_DEBUG
1897 if (mskdebug >= 2)
1898 msk_dump_mbuf(m_head);
1899 #endif
1900
1901 /*
1902 * Start packing the mbufs in this chain into
1903 * the fragment pointers. Stop when we run out
1904 * of fragments or hit the end of the mbuf chain.
1905 */
1906 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head,
1907 BUS_DMA_NOWAIT)) {
1908 DPRINTFN(2, ("msk_encap: dmamap failed\n"));
1909 return ENOBUFS;
1910 }
1911
1912 /* Count how many tx descriptors needed. */
1913 hiaddr = sc_if->sk_cdata.sk_tx_hiaddr;
1914 for (total = i = 0; i < txmap->dm_nsegs; i++) {
1915 if (hiaddr != MSK_ADDR_HI(txmap->dm_segs[i].ds_addr)) {
1916 hiaddr = MSK_ADDR_HI(txmap->dm_segs[i].ds_addr);
1917 total++;
1918 }
1919 total++;
1920 }
1921
1922 if (total > MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2) {
1923 DPRINTFN(2, ("msk_encap: too few descriptors free\n"));
1924 bus_dmamap_unload(sc->sc_dmatag, txmap);
1925 return ENOBUFS;
1926 }
1927
1928 DPRINTFN(2, ("msk_encap: dm_nsegs=%d total desc=%u\n",
1929 txmap->dm_nsegs, total));
1930
1931 /* Sync the DMA map. */
1932 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize,
1933 BUS_DMASYNC_PREWRITE);
1934
1935 for (i = 0; i < txmap->dm_nsegs; i++) {
1936 addr = txmap->dm_segs[i].ds_addr;
1937 DPRINTFN(2, ("msk_encap: addr %llx\n",
1938 (unsigned long long)addr));
1939 hiaddr = MSK_ADDR_HI(addr);
1940
1941 if (sc_if->sk_cdata.sk_tx_hiaddr != hiaddr) {
1942 f = &sc_if->sk_rdata->sk_tx_ring[frag];
1943 f->sk_addr = htole32(hiaddr);
1944 f->sk_len = 0;
1945 f->sk_ctl = 0;
1946 f->sk_opcode = SK_Y2_BMUOPC_ADDR64 | own;
1947 own = SK_Y2_TXOPC_OWN;
1948 sc_if->sk_cdata.sk_tx_hiaddr = hiaddr;
1949 SK_INC(frag, MSK_TX_RING_CNT);
1950 entries++;
1951 DPRINTFN(10, ("%s: tx ADDR64: %#x\n",
1952 sc_if->sk_ethercom.ec_if.if_xname, hiaddr));
1953 }
1954
1955 f = &sc_if->sk_rdata->sk_tx_ring[frag];
1956 f->sk_addr = htole32(MSK_ADDR_LO(addr));
1957 f->sk_len = htole16(txmap->dm_segs[i].ds_len);
1958 f->sk_ctl = 0;
1959 if (i == 0) {
1960 f->sk_opcode = SK_Y2_TXOPC_PACKET | own;
1961 } else
1962 f->sk_opcode = SK_Y2_TXOPC_BUFFER | own;
1963 own = SK_Y2_TXOPC_OWN;
1964 cur = frag;
1965 SK_INC(frag, MSK_TX_RING_CNT);
1966 entries++;
1967 }
1968 KASSERTMSG(entries == total, "entries %u total %u", entries, total);
1969
1970 sc_if->sk_cdata.sk_tx_chain[*txidx].sk_dmamap =
1971 sc_if->sk_cdata.sk_tx_chain[cur].sk_dmamap;
1972 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head;
1973 sc_if->sk_cdata.sk_tx_chain[cur].sk_dmamap = txmap;
1974
1975 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG;
1976
1977 /* Sync descriptors before handing to chip */
1978 MSK_CDTXSYNC(sc_if, *txidx, entries,
1979 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1980
1981 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN;
1982
1983 /* Sync first descriptor to hand it off */
1984 MSK_CDTXSYNC(sc_if, *txidx, 1,
1985 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1986
1987 sc_if->sk_cdata.sk_tx_cnt += entries;
1988
1989 #ifdef MSK_DEBUG
1990 if (mskdebug >= 2) {
1991 struct msk_tx_desc *le;
1992 uint32_t idx;
1993 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) {
1994 le = &sc_if->sk_rdata->sk_tx_ring[idx];
1995 msk_dump_txdesc(le, idx);
1996 }
1997 }
1998 #endif
1999
2000 *txidx = frag;
2001
2002 DPRINTFN(2, ("msk_encap: successful: %u entries\n", entries));
2003
2004 return 0;
2005 }
2006
2007 static void
msk_start(struct ifnet * ifp)2008 msk_start(struct ifnet *ifp)
2009 {
2010 struct sk_if_softc *sc_if = ifp->if_softc;
2011 struct mbuf *m_head = NULL;
2012 uint32_t idx = sc_if->sk_cdata.sk_tx_prod;
2013 int pkts = 0;
2014
2015 DPRINTFN(2, ("msk_start\n"));
2016
2017 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) {
2018 IFQ_POLL(&ifp->if_snd, m_head);
2019 if (m_head == NULL)
2020 break;
2021
2022 /*
2023 * Pack the data into the transmit ring. If we
2024 * don't have room, set the OACTIVE flag and wait
2025 * for the NIC to drain the ring.
2026 */
2027 if (msk_encap(sc_if, m_head, &idx)) {
2028 ifp->if_flags |= IFF_OACTIVE;
2029 break;
2030 }
2031
2032 /* now we are committed to transmit the packet */
2033 IFQ_DEQUEUE(&ifp->if_snd, m_head);
2034 pkts++;
2035
2036 /*
2037 * If there's a BPF listener, bounce a copy of this frame
2038 * to him.
2039 */
2040 bpf_mtap(ifp, m_head, BPF_D_OUT);
2041 }
2042 if (pkts == 0)
2043 return;
2044
2045 /* Transmit */
2046 if (idx != sc_if->sk_cdata.sk_tx_prod) {
2047 sc_if->sk_cdata.sk_tx_prod = idx;
2048 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx);
2049
2050 /* Set a timeout in case the chip goes out to lunch. */
2051 ifp->if_timer = 5;
2052 }
2053 }
2054
2055 static void
msk_watchdog(struct ifnet * ifp)2056 msk_watchdog(struct ifnet *ifp)
2057 {
2058 struct sk_if_softc *sc_if = ifp->if_softc;
2059
2060 /*
2061 * Reclaim first as there is a possibility of losing Tx completion
2062 * interrupts.
2063 */
2064 msk_txeof(sc_if);
2065 if (sc_if->sk_cdata.sk_tx_cnt != 0) {
2066 device_printf(sc_if->sk_dev, "watchdog timeout\n");
2067
2068 if_statinc(ifp, if_oerrors);
2069
2070 /* XXX Resets both ports; we shouldn't do that. */
2071 mskc_reset(sc_if->sk_softc);
2072 msk_reset(sc_if);
2073 msk_init(ifp);
2074 }
2075 }
2076
2077 static bool
mskc_suspend(device_t dv,const pmf_qual_t * qual)2078 mskc_suspend(device_t dv, const pmf_qual_t *qual)
2079 {
2080 struct sk_softc *sc = device_private(dv);
2081
2082 DPRINTFN(2, ("mskc_suspend\n"));
2083
2084 /* Turn off the 'driver is loaded' LED. */
2085 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
2086
2087 return true;
2088 }
2089
2090 static bool
mskc_resume(device_t dv,const pmf_qual_t * qual)2091 mskc_resume(device_t dv, const pmf_qual_t *qual)
2092 {
2093 struct sk_softc *sc = device_private(dv);
2094
2095 DPRINTFN(2, ("mskc_resume\n"));
2096
2097 mskc_reset(sc);
2098 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
2099
2100 return true;
2101 }
2102
2103 static __inline int
msk_rxvalid(struct sk_softc * sc,uint32_t stat,uint32_t len)2104 msk_rxvalid(struct sk_softc *sc, uint32_t stat, uint32_t len)
2105 {
2106 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
2107 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
2108 YU_RXSTAT_JABBER)) != 0 ||
2109 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
2110 YU_RXSTAT_BYTES(stat) != len)
2111 return 0;
2112
2113 return 1;
2114 }
2115
2116 static void
msk_rxeof(struct sk_if_softc * sc_if,uint16_t len,uint32_t rxstat)2117 msk_rxeof(struct sk_if_softc *sc_if, uint16_t len, uint32_t rxstat)
2118 {
2119 struct sk_softc *sc = sc_if->sk_softc;
2120 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if;
2121 struct mbuf *m;
2122 unsigned cur, prod, tail, total_len = len;
2123 bus_dmamap_t dmamap;
2124
2125 cur = sc_if->sk_cdata.sk_rx_cons;
2126 prod = sc_if->sk_cdata.sk_rx_prod;
2127
2128 DPRINTFN(2, ("msk_rxeof: cur %u prod %u rx_cnt %u\n", cur, prod,
2129 sc_if->sk_cdata.sk_rx_cnt));
2130
2131 while (prod != cur) {
2132 MSK_CDRXSYNC(sc_if, cur,
2133 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2134
2135 tail = cur;
2136 SK_INC(cur, MSK_RX_RING_CNT);
2137
2138 sc_if->sk_cdata.sk_rx_cnt--;
2139 m = sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf;
2140 sc_if->sk_cdata.sk_rx_chain[tail].sk_mbuf = NULL;
2141 if (m != NULL)
2142 break; /* found it */
2143 }
2144 sc_if->sk_cdata.sk_rx_cons = cur;
2145 DPRINTFN(2, ("msk_rxeof: cur %u rx_cnt %u m %p\n", cur,
2146 sc_if->sk_cdata.sk_rx_cnt, m));
2147
2148 if (m == NULL)
2149 return;
2150
2151 dmamap = sc_if->sk_cdata.sk_rx_chain[tail].sk_dmamap;
2152
2153 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0,
2154 uimin(dmamap->dm_mapsize, total_len), BUS_DMASYNC_POSTREAD);
2155 bus_dmamap_unload(sc->sc_dmatag, dmamap);
2156
2157 if (total_len < SK_MIN_FRAMELEN ||
2158 total_len > ETHER_MAX_LEN_JUMBO ||
2159 msk_rxvalid(sc, rxstat, total_len) == 0) {
2160 if_statinc(ifp, if_ierrors);
2161 m_freem(m);
2162 return;
2163 }
2164
2165 m_set_rcvif(m, ifp);
2166 m->m_pkthdr.len = m->m_len = total_len;
2167
2168 /* pass it on. */
2169 if_percpuq_enqueue(ifp->if_percpuq, m);
2170 }
2171
2172 static void
msk_txeof(struct sk_if_softc * sc_if)2173 msk_txeof(struct sk_if_softc *sc_if)
2174 {
2175 struct sk_softc *sc = sc_if->sk_softc;
2176 struct msk_tx_desc *cur_tx;
2177 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if;
2178 uint32_t idx, reg, sk_ctl;
2179 bus_dmamap_t dmamap;
2180
2181 DPRINTFN(2, ("msk_txeof\n"));
2182
2183 if (sc_if->sk_port == SK_PORT_A)
2184 reg = SK_STAT_BMU_TXA1_RIDX;
2185 else
2186 reg = SK_STAT_BMU_TXA2_RIDX;
2187
2188 /*
2189 * Go through our tx ring and free mbufs for those
2190 * frames that have been sent.
2191 */
2192 idx = sc_if->sk_cdata.sk_tx_cons;
2193 while (idx != sk_win_read_2(sc, reg)) {
2194 MSK_CDTXSYNC(sc_if, idx, 1,
2195 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2196
2197 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx];
2198 sk_ctl = cur_tx->sk_ctl;
2199 #ifdef MSK_DEBUG
2200 if (mskdebug >= 2)
2201 msk_dump_txdesc(cur_tx, idx);
2202 #endif
2203 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG)
2204 if_statinc(ifp, if_opackets);
2205 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) {
2206 dmamap = sc_if->sk_cdata.sk_tx_chain[idx].sk_dmamap;
2207
2208 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0,
2209 dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
2210
2211 bus_dmamap_unload(sc->sc_dmatag, dmamap);
2212 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf);
2213 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL;
2214 }
2215 sc_if->sk_cdata.sk_tx_cnt--;
2216 SK_INC(idx, MSK_TX_RING_CNT);
2217 }
2218 if (idx == sc_if->sk_cdata.sk_tx_cons)
2219 return;
2220
2221 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0;
2222
2223 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2)
2224 ifp->if_flags &= ~IFF_OACTIVE;
2225
2226 sc_if->sk_cdata.sk_tx_cons = idx;
2227 }
2228
2229 static void
msk_fill_rx_ring(struct sk_if_softc * sc_if)2230 msk_fill_rx_ring(struct sk_if_softc *sc_if)
2231 {
2232 /* Make sure to not completely wrap around */
2233 while (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT - 1)) {
2234 if (msk_newbuf(sc_if) == ENOBUFS) {
2235 goto schedretry;
2236 }
2237 }
2238
2239 return;
2240
2241 schedretry:
2242 /* Try later */
2243 callout_schedule(&sc_if->sk_tick_rx, hz/2);
2244 }
2245
2246 static void
msk_fill_rx_tick(void * xsc_if)2247 msk_fill_rx_tick(void *xsc_if)
2248 {
2249 struct sk_if_softc *sc_if = xsc_if;
2250 int s, rx_prod;
2251
2252 KASSERT(KERNEL_LOCKED_P()); /* XXXSMP */
2253
2254 s = splnet();
2255 rx_prod = sc_if->sk_cdata.sk_rx_prod;
2256 msk_fill_rx_ring(sc_if);
2257 if (rx_prod != sc_if->sk_cdata.sk_rx_prod) {
2258 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX,
2259 sc_if->sk_cdata.sk_rx_prod);
2260 }
2261 splx(s);
2262 }
2263
2264 static void
msk_tick(void * xsc_if)2265 msk_tick(void *xsc_if)
2266 {
2267 struct sk_if_softc *sc_if = xsc_if;
2268 struct mii_data *mii = &sc_if->sk_mii;
2269 int s;
2270
2271 s = splnet();
2272 mii_tick(mii);
2273 splx(s);
2274
2275 callout_schedule(&sc_if->sk_tick_ch, hz);
2276 }
2277
2278 static void
msk_intr_yukon(struct sk_if_softc * sc_if)2279 msk_intr_yukon(struct sk_if_softc *sc_if)
2280 {
2281 uint8_t status;
2282
2283 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
2284 /* RX overrun */
2285 if ((status & SK_GMAC_INT_RX_OVER) != 0) {
2286 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
2287 SK_RFCTL_RX_FIFO_OVER);
2288 }
2289 /* TX underrun */
2290 if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
2291 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST,
2292 SK_TFCTL_TX_FIFO_UNDER);
2293 }
2294
2295 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status));
2296 }
2297
2298 static int
msk_intr(void * xsc)2299 msk_intr(void *xsc)
2300 {
2301 struct sk_softc *sc = xsc;
2302 struct sk_if_softc *sc_if;
2303 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A];
2304 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B];
2305 struct ifnet *ifp0 = NULL, *ifp1 = NULL;
2306 uint32_t status;
2307 struct msk_status_desc *cur_st;
2308 bool retried = false;
2309
2310 status = CSR_READ_4(sc, SK_Y2_ISSR2);
2311 if (status == 0xffffffff)
2312 return 0;
2313 if (status == 0) {
2314 CSR_WRITE_4(sc, SK_Y2_ICR, 2);
2315 return 0;
2316 }
2317
2318 status = CSR_READ_4(sc, SK_ISR);
2319
2320 if (sc_if0 != NULL)
2321 ifp0 = &sc_if0->sk_ethercom.ec_if;
2322 if (sc_if1 != NULL)
2323 ifp1 = &sc_if1->sk_ethercom.ec_if;
2324
2325 if (sc_if0 && (status & SK_Y2_IMR_MAC1) &&
2326 (ifp0->if_flags & IFF_RUNNING)) {
2327 msk_intr_yukon(sc_if0);
2328 }
2329
2330 if (sc_if1 && (status & SK_Y2_IMR_MAC2) &&
2331 (ifp1->if_flags & IFF_RUNNING)) {
2332 msk_intr_yukon(sc_if1);
2333 }
2334
2335 again:
2336 MSK_CDSTSYNC(sc, sc->sk_status_idx,
2337 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2338 cur_st = &sc->sk_status_ring[sc->sk_status_idx];
2339
2340 while (cur_st->sk_opcode & SK_Y2_STOPC_OWN) {
2341 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN;
2342 switch (cur_st->sk_opcode) {
2343 case SK_Y2_STOPC_RXSTAT:
2344 sc_if = sc->sk_if[cur_st->sk_link & 0x01];
2345 if (sc_if) {
2346 msk_rxeof(sc_if, letoh16(cur_st->sk_len),
2347 letoh32(cur_st->sk_status));
2348 if (sc_if->sk_cdata.sk_rx_cnt < (MSK_RX_RING_CNT/3))
2349 msk_fill_rx_tick(sc_if);
2350 }
2351 break;
2352 case SK_Y2_STOPC_TXSTAT:
2353 if (sc_if0)
2354 msk_txeof(sc_if0);
2355 if (sc_if1)
2356 msk_txeof(sc_if1);
2357 break;
2358 default:
2359 aprint_error("opcode=0x%x\n", cur_st->sk_opcode);
2360 break;
2361 }
2362 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT);
2363
2364 MSK_CDSTSYNC(sc, sc->sk_status_idx,
2365 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2366 cur_st = &sc->sk_status_ring[sc->sk_status_idx];
2367 }
2368
2369 if (CSR_READ_2(sc, SK_STAT_BMU_PUTIDX) == sc->sk_status_idx) {
2370 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR);
2371 } else if (!retried) {
2372 retried = true;
2373 goto again;
2374 }
2375
2376 CSR_WRITE_4(sc, SK_Y2_ICR, 2);
2377
2378 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd))
2379 if_schedule_deferred_start(ifp0);
2380 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd))
2381 if_schedule_deferred_start(ifp1);
2382
2383 KASSERT(sc->rnd_attached > 0);
2384 rnd_add_uint32(&sc->rnd_source, status);
2385
2386 if (sc->sk_int_mod_pending)
2387 msk_update_int_mod(sc, 1);
2388
2389 return (status & sc->sk_intrmask) != 0;
2390 }
2391
2392 static void
msk_init_yukon(struct sk_if_softc * sc_if)2393 msk_init_yukon(struct sk_if_softc *sc_if)
2394 {
2395 uint32_t v;
2396 uint16_t reg;
2397 struct sk_softc *sc;
2398 int i;
2399
2400 sc = sc_if->sk_softc;
2401
2402 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n",
2403 CSR_READ_4(sc_if->sk_softc, SK_CSR)));
2404
2405 DPRINTFN(6, ("msk_init_yukon: 1\n"));
2406
2407 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n",
2408 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL)));
2409
2410 DPRINTFN(6, ("msk_init_yukon: 3\n"));
2411
2412 /* unused read of the interrupt source register */
2413 DPRINTFN(6, ("msk_init_yukon: 4\n"));
2414 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2415
2416 DPRINTFN(6, ("msk_init_yukon: 4a\n"));
2417 reg = SK_YU_READ_2(sc_if, YUKON_PAR);
2418 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg));
2419
2420 /* MIB Counter Clear Mode set */
2421 reg |= YU_PAR_MIB_CLR;
2422 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg));
2423 DPRINTFN(6, ("msk_init_yukon: 4b\n"));
2424 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2425
2426 /* MIB Counter Clear Mode clear */
2427 DPRINTFN(6, ("msk_init_yukon: 5\n"));
2428 reg &= ~YU_PAR_MIB_CLR;
2429 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2430
2431 /* receive control reg */
2432 DPRINTFN(6, ("msk_init_yukon: 7\n"));
2433 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
2434
2435 /* transmit control register */
2436 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10));
2437
2438 /* transmit flow control register */
2439 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff);
2440
2441 /* transmit parameter register */
2442 DPRINTFN(6, ("msk_init_yukon: 8\n"));
2443 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
2444 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04);
2445
2446 /* serial mode register */
2447 DPRINTFN(6, ("msk_init_yukon: 9\n"));
2448 reg = YU_SMR_DATA_BLIND(0x1c) |
2449 YU_SMR_MFL_VLAN |
2450 YU_SMR_IPG_DATA(0x1e);
2451
2452 if (sc->sk_type != SK_YUKON_FE &&
2453 sc->sk_type != SK_YUKON_FE_P)
2454 reg |= YU_SMR_MFL_JUMBO;
2455
2456 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
2457
2458 DPRINTFN(6, ("msk_init_yukon: 10\n"));
2459 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if;
2460 /* msk_attach calls me before ether_ifattach so check null */
2461 if (ifp != NULL && ifp->if_sadl != NULL)
2462 memcpy(sc_if->sk_enaddr, CLLADDR(ifp->if_sadl),
2463 sizeof(sc_if->sk_enaddr));
2464 /* Setup Yukon's address */
2465 for (i = 0; i < 3; i++) {
2466 /* Write Source Address 1 (unicast filter) */
2467 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
2468 sc_if->sk_enaddr[i * 2] |
2469 sc_if->sk_enaddr[i * 2 + 1] << 8);
2470 }
2471
2472 for (i = 0; i < 3; i++) {
2473 reg = sk_win_read_2(sc_if->sk_softc,
2474 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
2475 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
2476 }
2477
2478 /* Set promiscuous mode */
2479 msk_setpromisc(sc_if);
2480
2481 /* Set multicast filter */
2482 DPRINTFN(6, ("msk_init_yukon: 11\n"));
2483 msk_setmulti(sc_if);
2484
2485 /* enable interrupt mask for counter overflows */
2486 DPRINTFN(6, ("msk_init_yukon: 12\n"));
2487 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
2488 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
2489 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
2490
2491 /* Configure RX MAC FIFO Flush Mask */
2492 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
2493 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
2494 YU_RXSTAT_JABBER;
2495 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
2496
2497 /* Configure RX MAC FIFO */
2498 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
2499 v = SK_RFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
2500 if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_FE_P))
2501 v |= SK_RFCTL_RX_OVER_ON;
2502 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
2503
2504 if ((sc->sk_type == SK_YUKON_FE_P) &&
2505 (sc->sk_rev == SK_YUKON_FE_P_REV_A0))
2506 v = 0x178; /* Magic value */
2507 else {
2508 /* Increase flush threshold to 64 bytes */
2509 v = SK_RFCTL_FIFO_THRESHOLD + 1;
2510 }
2511 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, v);
2512
2513 /* Configure TX MAC FIFO */
2514 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
2515 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
2516
2517 if ((sc->sk_type == SK_YUKON_FE_P) &&
2518 (sc->sk_rev == SK_YUKON_FE_P_REV_A0)) {
2519 v = SK_IF_READ_2(sc_if, 0, SK_TXMF1_END);
2520 v &= ~SK_TXEND_WM_ON;
2521 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_END, v);
2522 }
2523
2524 #if 1
2525 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN);
2526 #endif
2527 DPRINTFN(6, ("msk_init_yukon: end\n"));
2528 }
2529
2530 /*
2531 * Note that to properly initialize any part of the GEnesis chip,
2532 * you first have to take it out of reset mode.
2533 */
2534 static int
msk_init(struct ifnet * ifp)2535 msk_init(struct ifnet *ifp)
2536 {
2537 struct sk_if_softc *sc_if = ifp->if_softc;
2538 struct sk_softc *sc = sc_if->sk_softc;
2539 int rc = 0, s;
2540 uint32_t imr, imtimer_ticks;
2541
2542
2543 DPRINTFN(2, ("msk_init\n"));
2544
2545 s = splnet();
2546
2547 /* Cancel pending I/O and free all RX/TX buffers. */
2548 msk_stop(ifp, 1);
2549
2550 /* Configure I2C registers */
2551
2552 /* Configure XMAC(s) */
2553 msk_init_yukon(sc_if);
2554 if ((rc = ether_mediachange(ifp)) != 0)
2555 goto out;
2556
2557 /* Configure transmit arbiter(s) */
2558 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON);
2559 #if 0
2560 /* SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); */
2561 #endif
2562
2563 if (sc->sk_ramsize) {
2564 /* Configure RAMbuffers */
2565 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
2566 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
2567 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
2568 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
2569 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
2570 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
2571
2572 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET);
2573 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON);
2574 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart);
2575 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart);
2576 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart);
2577 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend);
2578 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON);
2579 }
2580
2581 /* Configure BMUs */
2582 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016);
2583 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28);
2584 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080);
2585 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */
2586
2587 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016);
2588 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28);
2589 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080);
2590 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */
2591
2592 /* Make sure the sync transmit queue is disabled. */
2593 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET);
2594
2595 /* Init descriptors */
2596 if (msk_init_rx_ring(sc_if) == ENOBUFS) {
2597 aprint_error_dev(sc_if->sk_dev, "initialization failed: no "
2598 "memory for rx buffers\n");
2599 msk_stop(ifp, 1);
2600 splx(s);
2601 return ENOBUFS;
2602 }
2603
2604 if (msk_init_tx_ring(sc_if) == ENOBUFS) {
2605 aprint_error_dev(sc_if->sk_dev, "initialization failed: no "
2606 "memory for tx buffers\n");
2607 msk_stop(ifp, 1);
2608 splx(s);
2609 return ENOBUFS;
2610 }
2611
2612 /* Set interrupt moderation if changed via sysctl. */
2613 switch (sc->sk_type) {
2614 case SK_YUKON_EC:
2615 case SK_YUKON_EC_U:
2616 case SK_YUKON_EX:
2617 case SK_YUKON_SUPR:
2618 case SK_YUKON_ULTRA2:
2619 case SK_YUKON_OPTIMA:
2620 case SK_YUKON_PRM:
2621 case SK_YUKON_OPTIMA2:
2622 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC;
2623 break;
2624 case SK_YUKON_FE:
2625 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE;
2626 break;
2627 case SK_YUKON_FE_P:
2628 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE_P;
2629 break;
2630 case SK_YUKON_XL:
2631 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL;
2632 break;
2633 default:
2634 imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
2635 }
2636 imr = sk_win_read_4(sc, SK_IMTIMERINIT);
2637 if (imr != SK_IM_USECS(sc->sk_int_mod)) {
2638 sk_win_write_4(sc, SK_IMTIMERINIT,
2639 SK_IM_USECS(sc->sk_int_mod));
2640 aprint_verbose_dev(sc->sk_dev,
2641 "interrupt moderation is %d us\n", sc->sk_int_mod);
2642 }
2643
2644 /* Initialize prefetch engine. */
2645 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001);
2646 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002);
2647 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1);
2648 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO,
2649 MSK_RX_RING_ADDR(sc_if, 0));
2650 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI,
2651 (uint64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32);
2652 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008);
2653 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR);
2654
2655 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001);
2656 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002);
2657 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1);
2658 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO,
2659 MSK_TX_RING_ADDR(sc_if, 0));
2660 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI,
2661 (uint64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32);
2662 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008);
2663 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR);
2664
2665 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX,
2666 sc_if->sk_cdata.sk_rx_prod);
2667
2668
2669 if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_SUPR)) {
2670 /* Disable flushing of non-ASF packets. */
2671 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST,
2672 SK_RFCTL_RX_MACSEC_FLUSH_OFF);
2673 }
2674
2675 /* Configure interrupt handling */
2676 if (sc_if->sk_port == SK_PORT_A)
2677 sc->sk_intrmask |= SK_Y2_INTRS1;
2678 else
2679 sc->sk_intrmask |= SK_Y2_INTRS2;
2680 sc->sk_intrmask |= SK_Y2_IMR_BMU;
2681 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2682
2683 ifp->if_flags |= IFF_RUNNING;
2684 ifp->if_flags &= ~IFF_OACTIVE;
2685
2686 callout_schedule(&sc_if->sk_tick_ch, hz);
2687
2688 out:
2689 splx(s);
2690 return rc;
2691 }
2692
2693 /*
2694 * Note: the logic of second parameter is inverted compared to OpenBSD
2695 * code, since this code uses the function as if_stop hook too.
2696 */
2697 static void
msk_stop(struct ifnet * ifp,int disable)2698 msk_stop(struct ifnet *ifp, int disable)
2699 {
2700 struct sk_if_softc *sc_if = ifp->if_softc;
2701 struct sk_softc *sc = sc_if->sk_softc;
2702 bus_dmamap_t dmamap;
2703 int i;
2704
2705 DPRINTFN(2, ("msk_stop\n"));
2706
2707 callout_stop(&sc_if->sk_tick_ch);
2708 callout_stop(&sc_if->sk_tick_rx);
2709
2710 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2711
2712 /* Stop transfer of Tx descriptors */
2713
2714 /* Stop transfer of Rx descriptors */
2715
2716 if (disable) {
2717 /* Turn off various components of this interface. */
2718 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
2719 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
2720 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
2721 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF);
2722 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE);
2723 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF);
2724 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
2725 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2726 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP);
2727 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
2728 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
2729
2730 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001);
2731 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001);
2732
2733 /* Disable interrupts */
2734 if (sc_if->sk_port == SK_PORT_A)
2735 sc->sk_intrmask &= ~SK_Y2_INTRS1;
2736 else
2737 sc->sk_intrmask &= ~SK_Y2_INTRS2;
2738 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2739 }
2740
2741 /* Free RX and TX mbufs still in the queues. */
2742 for (i = 0; i < MSK_RX_RING_CNT; i++) {
2743 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) {
2744 dmamap = sc_if->sk_cdata.sk_rx_chain[i].sk_dmamap;
2745
2746 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0,
2747 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
2748
2749 bus_dmamap_unload(sc->sc_dmatag, dmamap);
2750
2751 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf);
2752 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL;
2753 }
2754 }
2755
2756 sc_if->sk_cdata.sk_rx_prod = 0;
2757 sc_if->sk_cdata.sk_rx_cons = 0;
2758 sc_if->sk_cdata.sk_rx_cnt = 0;
2759
2760 for (i = 0; i < MSK_TX_RING_CNT; i++) {
2761 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) {
2762 dmamap = sc_if->sk_cdata.sk_tx_chain[i].sk_dmamap;
2763
2764 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0,
2765 dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
2766
2767 bus_dmamap_unload(sc->sc_dmatag, dmamap);
2768
2769 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf);
2770 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL;
2771 }
2772 }
2773 }
2774
2775 CFATTACH_DECL3_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach,
2776 mskc_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN);
2777
2778 CFATTACH_DECL3_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach,
2779 msk_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN);
2780
2781 #ifdef MSK_DEBUG
2782 static void
msk_dump_txdesc(struct msk_tx_desc * le,int idx)2783 msk_dump_txdesc(struct msk_tx_desc *le, int idx)
2784 {
2785 #define DESC_PRINT(X) \
2786 if (X) \
2787 printf("txdesc[%d]." #X "=%#x\n", \
2788 idx, X);
2789
2790 DESC_PRINT(letoh32(le->sk_addr));
2791 DESC_PRINT(letoh16(le->sk_len));
2792 DESC_PRINT(le->sk_ctl);
2793 DESC_PRINT(le->sk_opcode);
2794 #undef DESC_PRINT
2795 }
2796
2797 static void
msk_dump_bytes(const char * data,int len)2798 msk_dump_bytes(const char *data, int len)
2799 {
2800 int c, i, j;
2801
2802 for (i = 0; i < len; i += 16) {
2803 printf("%08x ", i);
2804 c = len - i;
2805 if (c > 16) c = 16;
2806
2807 for (j = 0; j < c; j++) {
2808 printf("%02x ", data[i + j] & 0xff);
2809 if ((j & 0xf) == 7 && j > 0)
2810 printf(" ");
2811 }
2812
2813 for (; j < 16; j++)
2814 printf(" ");
2815 printf(" ");
2816
2817 for (j = 0; j < c; j++) {
2818 int ch = data[i + j] & 0xff;
2819 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' ');
2820 }
2821
2822 printf("\n");
2823
2824 if (c < 16)
2825 break;
2826 }
2827 }
2828
2829 static void
msk_dump_mbuf(struct mbuf * m)2830 msk_dump_mbuf(struct mbuf *m)
2831 {
2832 int count = m->m_pkthdr.len;
2833
2834 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len);
2835
2836 while (count > 0 && m) {
2837 printf("m=%p, m->m_data=%p, m->m_len=%d\n",
2838 m, m->m_data, m->m_len);
2839 if (mskdebug >= 4)
2840 msk_dump_bytes(mtod(m, char *), m->m_len);
2841
2842 count -= m->m_len;
2843 m = m->m_next;
2844 }
2845 }
2846 #endif
2847
2848 static int
msk_sysctl_handler(SYSCTLFN_ARGS)2849 msk_sysctl_handler(SYSCTLFN_ARGS)
2850 {
2851 int error, t;
2852 struct sysctlnode node;
2853 struct sk_softc *sc;
2854
2855 node = *rnode;
2856 sc = node.sysctl_data;
2857 t = sc->sk_int_mod;
2858 node.sysctl_data = &t;
2859 error = sysctl_lookup(SYSCTLFN_CALL(&node));
2860 if (error || newp == NULL)
2861 return error;
2862
2863 if (t < SK_IM_MIN || t > SK_IM_MAX)
2864 return EINVAL;
2865
2866 /* update the softc with sysctl-changed value, and mark
2867 for hardware update */
2868 sc->sk_int_mod = t;
2869 sc->sk_int_mod_pending = 1;
2870 return 0;
2871 }
2872
2873 /*
2874 * Set up sysctl(3) MIB, hw.msk.* - Individual controllers will be
2875 * set up in mskc_attach()
2876 */
2877 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup")
2878 {
2879 int rc;
2880 const struct sysctlnode *node;
2881
2882 if ((rc = sysctl_createv(clog, 0, NULL, &node,
2883 0, CTLTYPE_NODE, "msk",
2884 SYSCTL_DESCR("msk interface controls"),
2885 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) {
2886 goto err;
2887 }
2888
2889 msk_root_num = node->sysctl_num;
2890 return;
2891
2892 err:
2893 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc);
2894 }
2895