1//
2// Copyright 2016 Ettus Research
3// Copyright 2018 Ettus Research, a National Instruments Company
4//
5// SPDX-License-Identifier: LGPL-3.0-or-later
6//
7
8module regport_resp_mux #(
9  parameter WIDTH      = 32,
10  parameter NUM_SLAVES = 2
11)(
12  input                            clk,
13  input                            reset,
14
15  input [NUM_SLAVES-1:0]           sla_rd_resp,
16  input [(NUM_SLAVES*WIDTH)-1:0]   sla_rd_data,
17
18  output reg                       mst_rd_resp,
19  output reg [WIDTH-1:0]           mst_rd_data
20);
21  // Treat sla_rd_resp as a one-hot bus.
22  // If multiple resp lines are asserted at the same time, then
23  // it is a violation of the register port protocol
24
25  wire [NUM_SLAVES-1:0] bit_options[0:WIDTH-1];
26  wire [WIDTH-1:0]      data_out;
27
28  genvar i, b;
29  generate
30     for (b = 0; b < WIDTH; b = b + 1) begin
31        for (i = 0; i < NUM_SLAVES; i = i + 1) begin
32           assign bit_options[b][i] = sla_rd_data[(i*WIDTH)+b];
33        end
34        assign data_out[b] = |(bit_options[b] & sla_rd_resp);
35     end
36  endgenerate
37
38  always @(posedge clk) begin
39     mst_rd_data <= data_out;
40     if (reset)
41        mst_rd_resp <= 1'b0;
42     else
43        mst_rd_resp <= |(sla_rd_resp);
44  end
45
46endmodule
47