1 /*! 2 * \file t_mykonos.h 3 * \brief Contains type definitions for Mykonos API 4 * 5 * Mykonos API version: 1.5.1.3565 6 */ 7 8 /** 9 * \page Disclaimer Legal Disclaimer 10 * Copyright 2015-2017 Analog Devices Inc. 11 * Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file. 12 * 13 */ 14 15 #ifndef _T_MYKONOS_LIB_H_ 16 #define _T_MYKONOS_LIB_H_ 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 #include "common.h" 23 24 25 /** 26 * \brief Enum of unique error codes from the Mykonos API functions. 27 * Each error condition in the library should get its own enum value to allow 28 * easy debug of errors. 29 */ 30 typedef enum 31 { 32 MYKONOS_ERR_OK=0, 33 MYKONOS_ERR_HAL_LAYER, 34 MYKONOS_ERR_INV_PARM, 35 MYKONOS_ERR_FAILED, 36 MYKONOS_ERR_WAITFOREVENT_INV_PARM, 37 MYKONOS_ERR_WAITFOREVENT_TIMEDOUT, 38 MYKONOS_ERR_SETENSM_INVALID_NEWSTATE_WAIT, 39 MYKONOS_ERR_SETENSM_INVALID_NEWSTATE_ALERT, 40 MYKONOS_ERR_SETENSM_INVALID_NEWSTATE_TXRX, 41 MYKONOS_ERR_SETENSM_INVALIDSTATE, 42 MYKONOS_ERR_PU_RXPATH_INV_PARAM, 43 MYKONOS_ERR_PU_TXPATH_INV_PARAM, 44 MYKONOS_ERR_PU_OBSRXPATH_INV_PARAM, 45 MYKONOS_ERR_INIT_INV_ORXCHAN, 46 MYKONOS_ERR_INIT_INV_RXSYNCB_ORXSYNCB_MODE, 47 MYKONOS_ERR_INIT_INV_TXFIR_INTERPOLATION, 48 MYKONOS_ERR_INIT_INV_TXHB2_INTERPOLATION, 49 MYKONOS_ERR_INIT_INV_TXHB1_INTERPOLATION, 50 MYKONOS_ERR_INIT_INV_RXFIR_DECIMATION, 51 MYKONOS_ERR_INIT_INV_RXDEC5_DECIMATION, 52 MYKONOS_ERR_INIT_INV_RXHB1_DECIMATION, 53 MYKONOS_ERR_INIT_INV_SNIFFER_RHB1, 54 MYKONOS_ERR_INIT_INV_SNIFFER_RFIR_DEC, 55 MYKONOS_ERR_INIT_INV_ORX_RHB1, 56 MYKONOS_ERR_INIT_INV_ORX_RFIR_DEC, 57 MYKONOS_ERR_INIT_INV_ADCDIV, 58 MYKONOS_ERR_INIT_INV_DACDIV, 59 MYKONOS_ERR_INIT_INV_OBSRX_ADCDIV, 60 MYKONOS_ERR_CLKPLL_INV_HSDIV, 61 MYKONOS_ERR_CLKPLL_INV_VCODIV, 62 MYKONOS_ERR_CLKPLL_INV_RXTXPROFILES, 63 MYKONOS_ERR_SETCLKPLL_INV_VCOINDEX, 64 MYKONOS_ERR_SETCLKPLL_INV_FRACWORD, 65 MYKONOS_ERR_SETRFPLL_INV_PLLNAME, 66 MYKONOS_ERR_SETRFPLL_INV_LO_PARM, 67 MYKONOS_ERR_INV_SCALEDDEVCLK_PARAM, 68 MYKONOS_ERR_NULL_DEVICE_PARAM, 69 MYKONOS_ERR_CALCDEVCLK_NULLPARAM, 70 MYKONOS_ERR_SETRFPLL_INV_VCOINDEX, 71 MYKONOS_ERR_SETRFPLL_INV_REFCLK, 72 MYKONOS_ERR_SETORXGAIN_INV_CHANNEL, 73 MYKONOS_ERR_SETORXGAIN_INV_GAIN, 74 MYKONOS_ERR_GETORX1GAIN_INV_POINTER, 75 MYKONOS_ERR_GETORX2GAIN_INV_POINTER, 76 MYKONOS_ERR_GETSNIFFGAIN_INV_POINTER, 77 MYKONOS_ERR_GETOBSRXGAIN_CH_DISABLED, 78 MYKONOS_ERR_SETTX1ATTEN_INV_PARM, 79 MYKONOS_ERR_SETTX1ATTEN_INV_STEPSIZE_PARM, 80 MYKONOS_ERR_SETTX2ATTEN_INV_PARM, 81 MYKONOS_ERR_SETTX2ATTEN_INV_STEPSIZE_PARM, 82 MYKONOS_ERR_PROGRAMFIR_INV_NUMTAPS_PARM, 83 MYKONOS_ERR_PROGRAMFIR_INV_FIRNAME_PARM, 84 MYKONOS_ERR_RXFIR_INV_GAIN_PARM, 85 MYKONOS_ERR_OBSRXFIR_INV_GAIN_PARM, 86 MYKONOS_ERR_SRXFIR_INV_GAIN_PARM, 87 MYKONOS_ERR_TXFIR_INV_GAIN_PARM, 88 MYKONOS_ERR_READFIR_NULL_PARM, 89 MYKONOS_ERR_READFIR_COEFS_NULL, 90 MYKONOS_ERR_READFIR_INV_FIRNAME_PARM, 91 MYKONOS_ERR_READFIR_INV_NUMTAPS_PARM, 92 MYKONOS_ERR_SETRX1GAIN_INV_GAIN_PARM, 93 MYKONOS_ERR_SETRX2GAIN_INV_GAIN_PARM, 94 MYKONOS_ERR_INITSER_INV_VCODIV_PARM, 95 MYKONOS_ERR_INITSER_INV_VCODIV1_HSCLK_PARM, 96 MYKONOS_ERR_INITSER_INV_VCODIV1P5_HSCLK_PARM, 97 MYKONOS_ERR_INITDES_INV_VCODIV_PARM, 98 MYKONOS_ERR_SER_INV_M_PARM, 99 MYKONOS_ERR_SER_INV_L_PARM, 100 MYKONOS_ERR_SER_INV_LANERATE_PARM, 101 MYKONOS_ERR_SER_INV_LANEEN_PARM, 102 MYKONOS_ERR_SER_INV_AMP_PARM, 103 MYKONOS_ERR_SER_INV_PREEMP_PARM, 104 MYKONOS_ERR_SER_INV_LANEPN_PARM, 105 MYKONOS_ERR_SER_LANE_CONFLICT_PARM, 106 MYKONOS_ERR_SER_INV_TXSER_DIV_PARM, 107 MYKONOS_ERR_SER_LANE_RATE_CONFLICT_PARM, 108 MYKONOS_ERR_SER_INV_REAL_IF_DATA_PARM, 109 MYKONOS_ERR_HS_AND_LANE_RATE_NOT_INTEGER_MULT, 110 MYKONOS_ERR_DES_HS_AND_LANE_RATE_NOT_INTEGER_MULT, 111 MYKONOS_ERR_DESER_INV_M_PARM, 112 MYKONOS_ERR_DESER_INV_L_PARM, 113 MYKONOS_ERR_DESER_INV_HSCLK_PARM, 114 MYKONOS_ERR_DESER_INV_LANERATE_PARM, 115 MYKONOS_ERR_DESER_INV_LANEEN_PARM, 116 MYKONOS_ERR_DESER_INV_EQ_PARM, 117 MYKONOS_ERR_DESER_INV_LANEPN_PARM, 118 MYKONOS_ERR_FRAMER_INV_M_PARM, 119 MYKONOS_ERR_FRAMER_INV_BANKID_PARM, 120 MYKONOS_ERR_FRAMER_INV_LANEID_PARM, 121 MYKONOS_ERR_FRAMER_INV_K_OFFSET_PARAM, 122 MYKONOS_ERR_FRAMER_INV_REAL_IF_DATA_PARM, 123 MYKONOS_ERR_OBSRX_FRAMER_INV_M_PARM, 124 MYKONOS_ERR_OBSRX_FRAMER_INV_BANKID_PARM, 125 MYKONOS_ERR_OBSRX_FRAMER_INV_LANEID_PARM, 126 MYKONOS_ERR_OBSRX_FRAMER_INV_K_OFFSET_PARAM, 127 MYKONOS_ERR_OBSRX_FRAMER_INV_REAL_IF_DATA_PARM, 128 MYKONOS_ERR_DEFRAMER_INV_M_PARM, 129 MYKONOS_ERR_DEFRAMER_INV_BANKID_PARM, 130 MYKONOS_ERR_ERR_DEFRAMER_INV_LANEID_PARM, 131 MYKONOS_ERR_DEFRAMER_INV_K_OFFSET_PARAM, 132 MYKONOS_ERR_DEFRAMER_INV_K_PARAM, 133 MYKONOS_ERR_DEFRAMER_INV_FK_PARAM, 134 MYKONOS_ERR_RX_FRAMER_INV_PRBS_POLYORDER_PARAM, 135 MYKONOS_ERR_OBSRX_FRAMER_INV_PRBS_POLYORDER_PARAM, 136 MYKONOS_ERR_DEFRAMER_INV_PRBS_ENABLE_PARAM, 137 MYKONOS_ERR_DEFRAMER_INV_PRBS_POLYORDER_PARAM, 138 MYKONOS_ERR_DEFRAMER_INV_PRBS_CNTR_SEL_PARAM, 139 MYKONOS_ERR_INITARM_INV_DATARATE_PARM, 140 MYKONOS_ERR_INITARM_INV_REGCLK, 141 MYKONOS_ERR_INITARM_INV_ARMCLK_PARAM, 142 MYKONOS_ERR_LOADHEX_INV_CHARCOUNT, 143 MYKONOS_ERR_LOADHEX_INVALID_FIRSTCHAR, 144 MYKONOS_ERR_LOADHEX_INVALID_CHKSUM, 145 MYKONOS_ERR_LOADBIN_INVALID_BYTECOUNT, 146 MYKONOS_ERR_ARM_INVALID_BUILDCHKSUM, 147 MYKONOS_ERR_READARMMEM_INV_ADDR_PARM, 148 MYKONOS_ERR_WRITEARMMEM_INV_ADDR_PARM, 149 MYKONOS_ERR_ARMCMD_INV_OPCODE_PARM, 150 MYKONOS_ERR_ARMCMD_INV_NUMBYTES_PARM, 151 MYKONOS_ERR_ARMCMDSTATUS_INV_OPCODE_PARM, 152 MYKONOS_ERR_CHECKDEVSTRUCT_SPI, 153 MYKONOS_ERR_CHECKDEVSTRUCT_RX, 154 MYKONOS_ERR_CHECKDEVSTRUCT_RXSUB, 155 MYKONOS_ERR_CHECKDEVSTRUCT_RXFIR, 156 MYKONOS_ERR_CHECKDEVSTRUCT_TX, 157 MYKONOS_ERR_CHECKDEVSTRUCT_TXSUB, 158 MYKONOS_ERR_CHECKDEVSTRUCT_TXFIR, 159 MYKONOS_ERR_CHECKDEVSTRUCT_OBSRX, 160 MYKONOS_ERR_CHECKDEVSTRUCT_OBSRXSUB, 161 MYKONOS_ERR_CHECKDEVSTRUCT_SNIFFERFIR, 162 MYKONOS_ERR_CHECKDEVSTRUCT_ORXFIR, 163 MYKONOS_ERR_CHECKDEVSTRUCT_ORXGAINCTRL, 164 MYKONOS_ERR_CHECKDEVSTRUCT_SNIFFERGAINCTRL, 165 MYKONOS_ERR_CHECKDEVSTRUCT_OBSRXFRAMER, 166 MYKONOS_ERR_INITSER_INV_PROFILE, 167 MYKONOS_ERR_INITDES_INV_TXPROFILE, 168 MYKONOS_ERR_JESD204B_ILAS_MISMATCH, 169 MYKONOS_ERR_RXGAINTABLE_INV_CHANNEL, 170 MYKONOS_ERR_RXGAINTABLE_INV_GAIN_INDEX_RANGE, 171 MYKONOS_ERR_WRITE_CFG_MEMORY_FAILED, 172 MYKONOS_ERR_INV_RXFRAMER_PCLKDIV_PARM, 173 MYKONOS_ERR_RXFRAMER_INV_FK_PARAM, 174 MYKONOS_ERR_OBSRXFRAMER_INV_FK_PARAM, 175 MYKONOS_ERR_INV_OBSRXFRAMER_PCLKDIV_PARM, 176 MYKONOS_ERR_PU_OBSRXPATH_INV_LOSOURCE_PARAM, 177 MYKONOS_ERR_ARM_RADIOON_FAILED, 178 MYKONOS_ERR_INV_RX_GAIN_MODE_PARM, 179 MYKONOS_ERR_INV_ORX_GAIN_MODE_PARM, 180 MYKONOS_ERR_INV_AGC_RX_STRUCT_INIT, 181 MYKONOS_ERR_INV_AGC_RX_APD_THRESH_DIFF_VS_ATTACK_GAIN_STEP, 182 MYKONOS_ERR_INV_AGC_RX_PEAK_WAIT_TIME_PARM, 183 MYKONOS_ERR_INV_AGC_RX_GAIN_UPDATE_TIME_PARM, 184 MYKONOS_ERR_INV_AGC_RX_APD_HIGH_THRESH_PARM, 185 MYKONOS_ERR_INV_AGC_RX_APD_LOW_THRESH_PARM, 186 MYKONOS_ERR_INV_AGC_RX_BLOCK_DET_DECAY_PARM, 187 MYKONOS_ERR_INV_AGC_RX_APD_GAIN_STEP_PARM, 188 MYKONOS_ERR_INV_AGC_RX_HB2_GAIN_STEP_PARM, 189 MYKONOS_ERR_INV_AGC_RX_RECOVERY_GAIN_STEP_PARM, 190 MYKONOS_ERR_INV_AGC_PMD_MEAS_CONFIG, 191 MYKONOS_ERR_INV_AGC_PMD_MEAS_DURATION, 192 MYKONOS_ERR_INV_AGC_RX_ENABLE_SYNC_PULSE_GAIN_COUNTER, 193 MYKONOS_ERR_INV_AGC_RX_LOW_THS_PREV_GAIN_INC, 194 MYKONOS_ERR_INV_AGC_RX_PEAK_STRUCT_INIT, 195 MYKONOS_ERR_INV_AGC_RX_PEAK_THRESH_MODE, 196 MYKONOS_ERR_INV_AGC_RX_PWR_STRUCT_INIT, 197 MYKONOS_ERR_INV_AGC_RX_RESET_ON_RX_ENABLE, 198 MYKONOS_ERR_INV_AGC_RX_SLOW_LOOP_SETTLING_DELAY, 199 MYKONOS_ERR_INV_AGC_RX1_MAX_GAIN_INDEX, 200 MYKONOS_ERR_INV_AGC_RX1_MIN_GAIN_INDEX, 201 MYKONOS_ERR_INV_AGC_RX2_MAX_GAIN_INDEX, 202 MYKONOS_ERR_INV_AGC_RX2_MIN_GAIN_INDEX, 203 MYKONOS_ERR_INV_AGC_RX_PMD_LOWER_HIGH_THRESH, 204 MYKONOS_ERR_INV_AGC_RX_PMD_LOWER_LOW_THRESH, 205 MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_HIGH_THRESH, 206 MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_LOW_THRESH, 207 MYKONOS_ERR_INV_AGC_RX_PMD_LOWER_LOW_GAIN_STEP, 208 MYKONOS_ERR_INV_AGC_RX_PMD_LOWER_HIGH_GAIN_STEP, 209 MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_LOW_GAIN_STEP, 210 MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_HIGH_GAIN_STEP, 211 MYKONOS_ERR_INV_AGC_RX_APD_HIGH_GAIN_STEP_PARM, 212 MYKONOS_ERR_INV_AGC_RX_APD_LOW_GAIN_STEP_PARM, 213 MYKONOS_ERR_INV_AGC_RX_HB2_HIGH_GAIN_STEP_PARM, 214 MYKONOS_ERR_INV_AGC_RX_HB2_HIGH_THRESH_PARM, 215 MYKONOS_ERR_INV_AGC_RX_HB2_LOW_GAIN_STEP_PARM, 216 MYKONOS_ERR_INV_AGC_RX_HB2_LOW_THRESH_PARM, 217 MYKONOS_ERR_INV_AGC_RX_HB2_VERY_LOW_GAIN_STEP_PARM, 218 MYKONOS_ERR_INV_AGC_RX_HB2_VERY_LOW_THRESH_PARM, 219 MYKONOS_ERR_INV_AGC_RX_PKDET_FAST_ATTACK_VALUE, 220 MYKONOS_ERR_INV_AGC_RX_HB2_OVLD_ENABLE, 221 MYKONOS_ERR_INV_AGC_RX_HB2_OVLD_DUR_CNT, 222 MYKONOS_ERR_INV_AGC_RX_HB2_OVLD_THRESH_CNT, 223 MYKONOS_ERR_INV_AGC_OBSRX_STRUCT_INIT, 224 MYKONOS_ERR_INV_AGC_OBSRX_APD_THRESH_DIFF_VS_ATTACK_GAIN_STEP, 225 MYKONOS_ERR_INV_AGC_OBSRX_PEAK_WAIT_TIME_PARM, 226 MYKONOS_ERR_INV_AGC_OBSRX_GAIN_UPDATE_TIME_PARM, 227 MYKONOS_ERR_INV_AGC_OBSRX_APD_HIGH_THRESH_PARM, 228 MYKONOS_ERR_INV_AGC_OBSRX_APD_LOW_THRESH_PARM, 229 MYKONOS_ERR_INV_AGC_OBSRX_BLOCK_DET_DECAY_PARM, 230 MYKONOS_ERR_INV_AGC_OBSRX_APD_GAIN_STEP_PARM, 231 MYKONOS_ERR_INV_AGC_OBSRX_HB2_GAIN_STEP_PARM, 232 MYKONOS_ERR_INV_AGC_OBSRX_RECOVERY_GAIN_STEP_PARM, 233 MYKONOS_ERR_INV_AGC_OBSRX_MAX_GAIN_INDEX, 234 MYKONOS_ERR_INV_AGC_OBSRX_MIN_GAIN_INDEX, 235 MYKONOS_ERR_INV_AGC_OBSRX_SELECT, 236 MYKONOS_ERR_INV_AGC_OBSRX_PMD_MEAS_CONFIG, 237 MYKONOS_ERR_INV_AGC_OBSRX_PMD_MEAS_DURATION, 238 MYKONOS_ERR_INV_AGC_OBSRX_ENABLE_SYNC_PULSE_GAIN_COUNTER, 239 MYKONOS_ERR_INV_AGC_OBSRX_LOW_THS_PREV_GAIN_INC, 240 MYKONOS_ERR_INV_AGC_OBSRX_PEAK_STRUCT_INIT, 241 MYKONOS_ERR_INV_AGC_OBSRX_PEAK_THRESH_MODE, 242 MYKONOS_ERR_INV_AGC_OBSRX_PWR_STRUCT_INIT, 243 MYKONOS_ERR_INV_AGC_OBSRX_RESET_ON_RX_ENABLE, 244 MYKONOS_ERR_INV_AGC_OBSRX_SLOW_LOOP_SETTLING_DELAY, 245 MYKONOS_ERR_INV_AGC_OBSRX1_MAX_GAIN_INDEX, 246 MYKONOS_ERR_INV_AGC_OBSRX1_MIN_GAIN_INDEX, 247 MYKONOS_ERR_INV_AGC_OBSRX2_MAX_GAIN_INDEX, 248 MYKONOS_ERR_INV_AGC_OBSRX2_MIN_GAIN_INDEX, 249 MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_HIGH_THRESH, 250 MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_LOW_THRESH, 251 MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_HIGH_THRESH, 252 MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_LOW_THRESH, 253 MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_LOW_GAIN_STEP, 254 MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_HIGH_GAIN_STEP, 255 MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_LOW_GAIN_STEP, 256 MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_HIGH_GAIN_STEP, 257 MYKONOS_ERR_INV_AGC_OBSRX_APD_HIGH_GAIN_STEP_PARM, 258 MYKONOS_ERR_INV_AGC_OBSRX_APD_LOW_GAIN_STEP_PARM, 259 MYKONOS_ERR_INV_AGC_OBSRX_HB2_HIGH_GAIN_STEP_PARM, 260 MYKONOS_ERR_INV_AGC_OBSRX_HB2_HIGH_THRESH_PARM, 261 MYKONOS_ERR_INV_AGC_OBSRX_HB2_LOW_GAIN_STEP_PARM, 262 MYKONOS_ERR_INV_AGC_OBSRX_HB2_LOW_THRESH_PARM, 263 MYKONOS_ERR_INV_AGC_OBSRX_HB2_VERY_LOW_GAIN_STEP_PARM, 264 MYKONOS_ERR_INV_AGC_OBSRX_HB2_VERY_LOW_THRESH_PARM, 265 MYKONOS_ERR_INV_AGC_OBSRX_PKDET_FAST_ATTACK_VALUE, 266 MYKONOS_ERR_INV_AGC_OBSRX_HB2_OVLD_ENABLE, 267 MYKONOS_ERR_INV_AGC_OBSRX_HB2_OVLD_DUR_CNT, 268 MYKONOS_ERR_INV_AGC_OBSRX_HB2_OVLD_THRESH_CNT, 269 MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_CALPLL_LOCK, 270 MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_CLKPLLCP, 271 MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_CLKPLL_LOCK, 272 MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RXPLLCP, 273 MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RXPLL_LOCK, 274 MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_TXPLLCP, 275 MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_TXPLL_LOCK, 276 MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_SNIFFPLLCP, 277 MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_SNIFFPLL_LOCK, 278 MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RXBBFCALDONE, 279 MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_TXBBFCALDONE, 280 MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RFDCCALDONE, 281 MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_ADCTUNECALDONE, 282 MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RX1ADCPROFILE, 283 MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RX2ADCPROFILE, 284 MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_ORXADCPROFILE, 285 MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RCALDONE, 286 MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_ARMBUSY, 287 MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_INITARMDONE, 288 MYKONOS_ERR_TIMEDOUT_ARMMAILBOXBUSY, 289 MYKONOS_ERR_PU_OBSRXPATH_ARMERROR, 290 MYKONOS_ERR_EN_TRACKING_CALS_ARMSTATE_ERROR, 291 MYKONOS_ERR_SET_RADIOCTRL_PINS_ARMERROR, 292 MYKONOS_ERR_EN_TRACKING_CALS_ARMERROR, 293 MYKONOS_ERR_SETRFPLL_ARMERROR, 294 MYKONOS_ERR_INIT_INV_TXINPUTHB_PARM, 295 MYKONOS_ERR_LOAD_ADCPROFILE_INV_VCODIV, 296 MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_RXREQUIRED, 297 MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_ORXREQUIRED, 298 MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_SNRXREQUIRED, 299 MYKONOS_ERR_SETUP_PA_PROT_INV_AVG_DURATION, 300 MYKONOS_ERR_SETUP_PA_PROT_INV_STICKY_ENABLE, 301 MYKONOS_ERR_SETUP_PA_PROT_INV_ATTEN_STEP, 302 MYKONOS_ERR_SETUP_PA_PROT_INV_ATTEN_ENABLE, 303 MYKONOS_ERR_SETUP_PA_PROT_INV_POWER_THRESH, 304 MYKONOS_ERR_SETUP_PA_PROT_INV_TX_CHANNEL, 305 MYKONOS_ERR_GET_DAC_PWR_INV_POINTER, 306 MYKONOS_ERR_GET_PA_FLAG_STATUS_INV_POINTER, 307 MYKONOS_ERR_GET_OBSRX_OVERLOADS_NULL_PARM, 308 MYKONOS_ERR_GET_RX1_OVERLOADS_NULL_PARM, 309 MYKONOS_ERR_GET_RX2_OVERLOADS_NULL_PARM, 310 MYKONOS_ERR_GETRADIOSTATE_NULL_PARAM, 311 MYKONOS_ERR_ABORT_INITCALS_NULL_PARAM, 312 MYKONOS_ERR_ARM_RADIOOFF_FAILED, 313 MYKONOS_ERR_WAIT_INITCALS_NULL_PARAM, 314 MYKONOS_ERR_WAIT_INITCALS_CALFAILED, 315 MYKONOS_ERR_WAIT_INITCALS_ARMERROR, 316 MYKONOS_ERR_CHECK_PLL_LOCK_NULL_PARM, 317 MYKONOS_ERR_GET_TXFILTEROVRG_NULL_PARM, 318 MYKONOS_ERR_PROGRAM_RXGAIN_TABLE_NULL_PARM, 319 MYKONOS_ERR_PROGRAMFIR_NULL_PARM, 320 MYKONOS_ERR_PROGRAMFIR_COEFS_NULL, 321 MYKONOS_ERR_READ_DEFRAMERSTATUS_NULL_PARAM, 322 MYKONOS_ERR_READ_DEFRAMERPRBS_NULL_PARAM, 323 MYKONOS_ERR_READ_ORXFRAMERSTATUS_NULL_PARAM, 324 MYKONOS_ERR_READ_RXFRAMERSTATUS_NULL_PARAM, 325 MYKONOS_ERR_ARMCMDSTATUS_NULL_PARM, 326 MYKONOS_ERR_READARMCMDSTATUS_INV_OPCODE_PARM, 327 MYKONOS_ERR_READARMCMDSTATUS_NULL_PARM, 328 MYKONOS_ERR_READARMCMDSTATUSBYTE_NULL_PARM, 329 MYKONOS_ERR_ARMCMD_NULL_PARM, 330 MYKONOS_ERR_WRITEARMMEM_NULL_PARM, 331 MYKONOS_ERR_LOADBIN_NULL_PARAM, 332 MYKONOS_ERR_ARM_INV_ADDR_PARM, 333 MYKONOS_ERR_LOADARMCON_INVALID_BYTECOUNT, 334 MYKONOS_ERR_LOADARMCON_NULL_PARAM, 335 MYKONOS_ERR_GETTX1ATTEN_NULL_PARM, 336 MYKONOS_ERR_GETTX2ATTEN_NULL_PARM, 337 MYKONOS_ERR_ENFRAMERLINK_INV_LANESEN_PARM, 338 MYKONOS_ERR_ENOBSFRAMERLINK_INV_LANESEN_PARM, 339 MYKONOS_ERR_ENTXNCO_TXPROFILE_INVALID, 340 MYKONOS_ERR_ENTXNCO_TX1_FREQ_INVALID, 341 MYKONOS_ERR_ENTXNCO_TX2_FREQ_INVALID, 342 MYKONOS_ERR_JESD204B_ILAS_MISMATCH_NULLPARAM, 343 MYKONOS_ERR_LOAD_LBADCPROFILE_ARMMEM_FAILED, 344 MYKONOS_ERR_LOAD_SNRXADCPROFILE_ARMMEM_FAILED, 345 MYKONOS_ERR_LOAD_ADCPROFILE_SNRX_ADCDIV_ZERO, 346 MYKONOS_ERR_LOAD_ORXADCPROFILE_ARMMEM_FAILED, 347 MYKONOS_ERR_LOAD_ADCPROFILE_ORXADCDIV_ZERO, 348 MYKONOS_ERR_LOAD_RXADCPROFILE_ARMMEM_FAILED, 349 MYKONOS_ERR_LOAD_ADCPROFILE_RXADCDIV_ZERO, 350 MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_LBREQUIRED, 351 MYKONOS_ERR_LOAD_ADCPROFILE_MISSING_ORX_PROFILE, 352 MYKONOS_ERR_GETRFPLL_INV_PLLNAME, 353 MYKONOS_ERR_GETRFPLL_ARMERROR, 354 MYKONOS_ERR_GETRFPLL_NULLPARAM, 355 MYKONOS_ERR_INITARM_INV_VCODIV, 356 MYKONOS_ERR_GET_PLLFREQ_INV_HSDIV, 357 MYKONOS_ERR_GET_PLLFREQ_INV_VCODIV, 358 MYKONOS_ERR_GET_PLLFREQ_INV_REFCLKDIV, 359 MYKONOS_ERR_SETORXGAIN_INV_ORX1GAIN, 360 MYKONOS_ERR_SETORXGAIN_INV_ORX2GAIN, 361 MYKONOS_ERR_SETORXGAIN_INV_SNRXGAIN, 362 MYKONOS_ERR_GET_RX1_DEC_POWER_NUM_SAMPLES, 363 MYKONOS_ERR_GET_RX1_DEC_POWER_NULL_PARM, 364 MYKONOS_ERR_GET_RX2_DEC_POWER_NUM_SAMPLES, 365 MYKONOS_ERR_GET_RX2_DEC_POWER_NULL_PARM, 366 MYKONOS_ERR_GET_OBSRX_DEC_POWER_NUM_SAMPLES, 367 MYKONOS_ERR_GET_OBSRX_DEC_POWER_NULL_PARM, 368 MYKONOS_ERR_GETARMVER_NULL_PARM, 369 MYKONOS_ERR_EN_CLGCTRACKING_ARMSTATE_ERROR, 370 MYKONOS_ERR_EN_DPDTRACKING_ARMSTATE_ERROR, 371 MYKONOS_ERR_RESTDPDMOD_WRONGBUFFERSIZE, 372 MYKONOS_ERR_RESTDPDMOD_ARMSTATE, 373 MYKONOS_ERR_RESTDPDMOD_INVALID_TXCHANNEL, 374 MYKONOS_ERR_RESTDPDMOD_ARMERRFLAG, 375 MYKONOS_ERR_SAVDPDMOD_WRONGBUFFERSIZE, 376 MYKONOS_ERR_SAVDPDMOD_ARMSTATE, 377 MYKONOS_ERR_SAVDPDMOD_INVALID_TXCHANNEL, 378 MYKONOS_ERR_SAVDPDMOD_ARMERRFLAG, 379 MYKONOS_ERR_WRITEARMCFG_ARMERRFLAG, 380 MYKONOS_ERR_CFGDPD_TXORX_PROFILE_INV, 381 MYKONOS_ERR_CFGDPD_NULL_DPDCFGSTRUCT, 382 MYKONOS_ERR_CFGDPD_INV_DPDDAMPING, 383 MYKONOS_ERR_CFGDPD_INV_DPDSAMPLES, 384 MYKONOS_ERR_CFGDPD_INV_DPDOUTLIERTHRESH, 385 MYKONOS_ERR_CFGDPD_INV_DPDPRIORWEIGHT, 386 MYKONOS_ERR_CFGCLGC_INV_DESIREDGAIN, 387 MYKONOS_ERR_CFGCLGC_INV_TXATTENLIMIT, 388 MYKONOS_ERR_CFGCLGC_INV_CLGC_CTRLRATIO, 389 MYKONOS_ERR_SETCLGCGAIN_INV_DESIREDGAIN, 390 MYKONOS_ERR_SETCLGCGAIN_INV_TXCHANNEL, 391 MYKONOS_ERR_SETCLGCGAIN_TRACK_ARMERRFLAG, 392 MYKONOS_ERR_CFGDPD_INV_DPD_ADDDELAY, 393 MYKONOS_ERR_CFGDPD_INV_PNSEQLEVEL, 394 MYKONOS_ERR_READARMCFG_ARMERRFLAG, 395 MYKONOS_ERR_GETPENDTRKCALS_NULL_PARAM, 396 MYKONOS_ERR_ARMCMDSTATUS_ARMERROR, 397 MYKONOS_ERR_WAITARMCMDSTATUS_TIMEOUT, 398 MYKONOS_ERR_PU_GETOBSRXPATH_ARMERROR, 399 MYKONOS_ERR_GETDPDCFG_NULL_DPDCFGSTRUCT, 400 MYKONOS_ERR_GETDPDCFG_TXORX_PROFILE_INV, 401 MYKONOS_ERR_GETDPDSTATUS_ARMERRFLAG, 402 MYKONOS_ERR_GETDPDSTATUS_NULLPARAM, 403 MYKONOS_ERR_SETDEFOBSRXPATH_NULL_OBSRX_STRUCT, 404 MYKONOS_ERR_SETDEFOBSRXPATH_NULL_DEF_OBSRX_STRUCT, 405 MYKONOS_ERR_GETCLGCSTATUS_NULLPARAM, 406 MYKONOS_ERR_GETCLGCSTATUS_ARMERRFLAG, 407 MYKONOS_ERR_CHECKDEVSTRUCT_NULLDEVPOINTER, 408 MYKONOS_ERR_READ_DEFFIFODEPTH_NULL_PARAM, 409 MYKONOS_ERR_READ_DEFFIFODEPTH_LMFCCOUNT_NULL_PARAM, 410 MYKONOS_ERR_GETDPDSTATUS_INV_CH, 411 MYKONOS_ERR_GETCLGCSTATUS_INV_CH, 412 MYKONOS_ERR_INIT_INV_TXINPUTHB_INV_RATE, 413 MYKONOS_ERR_INIT_INV_TXINPUTHB0_INV_RATE, 414 MYKONOS_ERR_TXFIR_TAPSEXCEEDED, 415 MYKONOS_ERR_TXFIR_INV_NUMROWS, 416 MYKONOS_ERR_TXFIR_INV_NUMTAPS_PARM, 417 MYKONOS_ERR_RXFIR_TAPSEXCEEDED, 418 MYKONOS_ERR_ORXFIR_TAPSEXCEEDED, 419 MYKONOS_ERR_SNRXFIR_TAPSEXCEEDED, 420 MYKONOS_ERR_GETINITCALSTATUS_NULL_PARAM, 421 MYKONOS_ERR_GETINITCALSTATUS_ARMERROR, 422 MYKONOS_ERR_CFGDPD_INV_NUMWEIGHTS, 423 MYKONOS_ERR_CFGDPD_INV_MODELVERSION, 424 MYKONOS_ERR_SETDPDACT_INV_TXCHANNEL, 425 MYKONOS_ERR_SETDPDACT_INV_STATE, 426 MYKONOS_ERR_SETDPDACT_ARMERRFLAG, 427 MYKONOS_ERR_CFGCLGC_TXORX_PROFILE_INV, 428 MYKONOS_ERR_CFGCLGC_NULL_CLGCCFGSTRUCT, 429 MYKONOS_ERR_GETCLGCCFG_TXORX_PROFILE_INV, 430 MYKONOS_ERR_GETCLGCCFG_NULL_CFGSTRUCT, 431 MYKONOS_ERR_CALCDIGCLK_NULLDEV_PARAM, 432 MYKONOS_ERR_CALCDIGCLK_NULL_CLKSTRUCT, 433 MYKONOS_ERR_CFGCLGC_INV_CLGC_ADDDELAY, 434 MYKONOS_ERR_CFGCLGC_INV_PNSEQLEVEL, 435 MYKONOS_ERR_CFGVSWR_TXORX_PROFILE_INV, 436 MYKONOS_ERR_CFGVSWR_ARMSTATE_ERROR, 437 MYKONOS_ERR_CFGVSWR_INV_3P3GPIOPIN, 438 MYKONOS_ERR_CFGVSWR_INV_PNSEQLEVEL, 439 MYKONOS_ERR_CFGVSWR_INV_VSWR_ADDDELAY, 440 MYKONOS_ERR_CFGVSWR_NULL_VSWRCFGSTRUCT, 441 MYKONOS_ERR_GETVSWRCFG_NULL_CFGSTRUCT, 442 MYKONOS_ERR_GETVSWRCFG_TXORX_PROFILE_INV, 443 MYKONOS_ERR_GETVSWRSTATUS_ARMERRFLAG, 444 MYKONOS_ERR_GETVSWRSTATUS_INV_CH, 445 MYKONOS_ERR_GETVSWRSTATUS_NULLPARAM, 446 MYKONOS_ERR_SET_RX_MAX_GAIN_INDEX, 447 MYKONOS_ERR_SET_RX_MIN_GAIN_INDEX, 448 MYKONOS_ERR_AGC_MIN_MAX_RX_CHANNEL, 449 MYKONOS_ERR_SET_ORX_MAX_GAIN_INDEX_CHANNEL, 450 MYKONOS_ERR_SET_ORX_MAX_GAIN_INDEX, 451 MYKONOS_ERR_SET_ORX_MIN_GAIN_INDEX, 452 MYKONOS_ERR_AGC_MIN_MAX_ORX_CHANNEL, 453 MYKONOS_ERR_RX1_TEMP_GAIN_COMP_RANGE, 454 MYKONOS_ERR_RX2_TEMP_GAIN_COMP_RANGE, 455 MYKONOS_ERR_OBS_RX_TEMP_GAIN_COMP_RANGE, 456 MYKONOS_ERR_RX1_TEMP_GAIN_COMP_STEP, 457 MYKONOS_ERR_RX2_TEMP_GAIN_COMP_STEP, 458 MYKONOS_ERR_OBS_RX_TEMP_GAIN_COMP_STEP, 459 MYKONOS_ERR_RX1_TEMP_GAIN_COMP_NULL, 460 MYKONOS_ERR_RX2_TEMP_GAIN_COMP_NULL, 461 MYKONOS_ERR_OBS_RX_TEMP_GAIN_COMP_NULL, 462 MYKONOS_ERR_GETTXLOLSTATUS_NULLPARAM, 463 MYKONOS_ERR_GETTXLOLSTATUS_INV_CH, 464 MYKONOS_ERR_GETTXLOLSTATUS_ARMERRFLAG, 465 MYKONOS_ERR_GETTXQECSTATUS_NULLPARAM, 466 MYKONOS_ERR_GETTXQECSTATUS_INV_CH, 467 MYKONOS_ERR_GETTXQECSTATUS_ARMERRFLAG, 468 MYKONOS_ERR_GETRXQECSTATUS_NULLPARAM, 469 MYKONOS_ERR_GETRXQECSTATUS_INV_CH, 470 MYKONOS_ERR_GETRXQECSTATUS_ARMERRFLAG, 471 MYKONOS_ERR_GETORXQECSTATUS_NULLPARAM, 472 MYKONOS_ERR_GETORXQECSTATUS_INV_CH, 473 MYKONOS_ERR_GETORXQECSTATUS_ARMERRFLAG, 474 MYKONOS_ERR_RESCHEDULE_TRACK_CAL_INV, 475 MYKONOS_ERR_RESCHEDULE_TRACK_ARMERRFLAG, 476 477 MYKONOS_ERR_SETSTATEALL_TRACK_CAL_INV, 478 MYKONOS_ERR_SETSTATEALL_TRACK_ARMERRFLAG, 479 480 MYKONOS_ERR_GETSTATEALL_TRACK_NULL_PARAM, 481 MYKONOS_ERR_GETSTATEALL_TRACK_ARMERRFLAG, 482 MYKONOS_ERR_GETSTATEALL_TRACK_ARMERROR, 483 484 MYKONOS_ERR_SETSTATE_TRACK_CAL_INV, 485 MYKONOS_ERR_SETSTATE_TRACK_ARMERRFLAG, 486 487 MYKONOS_ERR_GETSTATE_TRACK_NULL_PARAM, 488 MYKONOS_ERR_GETSTATE_TRACK_ARMERRFLAG, 489 MYKONOS_ERR_GETSTATE_TRACK_ARMERROR, 490 491 MYKONOS_ERR_ARMSTATE_PROFILE_ERROR, 492 MYKONOS_ERR_ARMSTATE_CAL_ERROR, 493 MYKONOS_ERR_ARMSTATE_EXCEPTION, 494 MYKONOS_ERR_WAITARMCSTATE_TIMEOUT, 495 496 MYKONOS_ERR_GETPRODUCTID_NULL_PARAM, 497 MYKONOS_ERR_GET_API_VERSION_NULL_PARAM, 498 499 MYKONOS_ERR_PROFILES_HSDIGCLK, 500 MYKONOS_ERR_RXPROFILE_RXCHANNEL, 501 MYKONOS_ERR_RXPROFILE_IQRATE, 502 MYKONOS_ERR_RXPROFILE_RFBW, 503 MYKONOS_ERR_RXPROFILE_FILTER_DECIMATION, 504 MYKONOS_ERR_RXPROFILE_FIR_COEFS, 505 MYKONOS_ERR_RXPROFILE_ADCDIV, 506 MYKONOS_ERR_TXPROFILE_IQRATE, 507 MYKONOS_ERR_TXPROFILE_RFBW, 508 MYKONOS_ERR_TXPROFILE_FILTER_INTERPOLATION, 509 MYKONOS_ERR_TXPROFILE_FIR_COEFS, 510 MYKONOS_ERR_TXPROFILE_DACDIV, 511 MYKONOS_ERR_RESET_TXLOL_INV_PARAM, 512 MYKONOS_ERR_RESET_TXLOL_ARMERROR, 513 MYKONOS_ERR_SETRFPLL_LF_INV_STABILITY, 514 MYKONOS_ERR_SETRFPLL_LF_PLLNAME, 515 MYKONOS_ERR_SETRFPLL_LF_INV_TXRX_LOOPBANDWIDTH, 516 MYKONOS_ERR_SETRFPLL_LF_INV_SNF_LOOPBANDWIDTH, 517 MYKONOS_ERR_SETRFPLL_LF_ARMERROR, 518 MYKONOS_ERR_GETRFPLL_LF_ARMERROR, 519 MYKONOS_ERR_GETRFPLL_LF_NULLPARAM, 520 MYKONOS_ERR_GETRFPLL_LF_INV_PLLNAME, 521 MYKONOS_ERR_DC_OFFSET_INV_CHAN, 522 MYKONOS_ERR_SET_RF_DC_OFFSET_INV_MEASURECNT, 523 MYKONOS_ERR_SET_RF_DC_OFFSET_MEASURECNT_MIN_LIMIT, 524 MYKONOS_ERR_GET_RF_DC_OFFSET_NULL_MEASURECNT, 525 MYKONOS_ERR_RF_DC_OFFSET_INV_ENABLE_MASK, 526 MYKONOS_ERR_RF_DC_OFFSET_NULL_ENABLE_MASK, 527 MYKONOS_ERR_SET_DIG_DC_OFFSET_INV_MSHIFT, 528 MYKONOS_ERR_GET_DIG_DC_OFFSET_NULL_MSHIFT, 529 MYKONOS_ERR_DIG_DC_OFFSET_INV_ENABLE_MASK, 530 MYKONOS_ERR_DIG_DC_OFFSET_NULL_ENABLE_MASK, 531 MYKONOS_ERR_CFGCLGC_INV_THRESHOLD, 532 MYKONOS_ERR_RESETDPD_INV_TXCHANNEL, 533 MYKONOS_ERR_RESETDPD_ARMERRFLAG, 534 MYKONOS_ERR_RESETDPD_WRONG_PARAM, 535 MYKONOS_WRN_RADIO_ON_NOT_MODIFIABLE, 536 MYKONOS_ERR_SET_PATH_DELAY_NULL_PARAM, 537 MYKONOS_ERR_SET_PATH_DELAY_PARAM_OUT_OF_RANGE, 538 MYKONOS_ERR_GET_PATH_DELAY_NULL_PARAM, 539 MYKONOS_ERR_GET_PATH_DELAY_INVALID_SELECTION, 540 MYKONOS_ERR_GET_PATH_DELAY_ARMERRFLAG, 541 542 543 MYKONOS_ERR_GETDPD_ERROR_CNT_NULLPARAM, 544 MYKONOS_ERR_GETDPD_ERROR_CNT_INV_CH, 545 MYKONOS_ERR_GETDPD_ERROR_CNT_ARMERRFLAG, 546 547 MYKONOS_ERR_SETDPDACT_NULL_ACTSTRUCT, 548 MYKONOS_ERR_SETDPDACT_INV_ACTMODE, 549 MYKONOS_ERR_SETDPDACT_INV_LEVEL, 550 MYKONOS_ERR_GETDPDACT_NULL_ACTSTRUCT, 551 552 MYKONOS_ERR_SETDPDACTCHECK_NULL_ACTSTRUCT, 553 MYKONOS_ERR_SETDPDACTCHECK_INV_ACTMODE, 554 MYKONOS_ERR_SETDPDACTCHECK_INV_LEVEL, 555 MYKONOS_ERR_GETDPDACTCHECK_NULL_ACTSTRUCT, 556 557 MYKONOS_ERR_CLGCATTENTUNCFG_NULL_ATTRANGECFGSTRUCT, 558 MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_MODE, 559 MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_PRESET, 560 MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_RANGE, 561 MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_TX1_SETTINGS, 562 MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_TX2_SETTINGS, 563 564 MYKONOS_ERR_CLGCATTENTUNCFGGET_NULL_ATTRANGECFGSTRUCT, 565 566 MYKONOS_ERR_END 567 } mykonosErr_t; 568 569 /** 570 * \brief Enum for Mykonos low voltage GPIO available pins 571 */ 572 typedef enum 573 { 574 MYKGPIONAN = 0x00, 575 MYKGPIO0 = 0x1, 576 MYKGPIO1 = 0x2, 577 MYKGPIO2 = 0x4, 578 MYKGPIO3 = 0x8, 579 MYKGPIO4 = 0x10, 580 MYKGPIO5 = 0x20, 581 MYKGPIO6 = 0x40, 582 MYKGPIO7 = 0x80, 583 MYKGPIO8 = 0x100, 584 MYKGPIO9 = 0x200, 585 MYKGPIO10 = 0x400, 586 MYKGPIO11 = 0x800, 587 MYKGPIO12 = 0x1000, 588 MYKGPIO13 = 0x2000, 589 MYKGPIO14 = 0x4000, 590 MYKGPIO15 = 0x8000, 591 MYKGPIO16 = 0x10000, 592 MYKGPIO17 = 0x20000, 593 MYKGPIO18 = 0x40000 594 } mykonosGpioSelect_t; 595 596 597 /** 598 * \brief Enum of valid Mykonos Enable State Machine (ENSM) states 599 */ 600 typedef enum 601 { 602 WAIT = 0, /*!< Mykonos ENSM state upon which a power up in the WAIT/SLEEP state occurs */ 603 INIT = 1, /*!< Mykonos ENSM state upon which a power up delay state ocurrs to allow clocks to stabilize */ 604 WAITCALS = 2, /*!< Mykonos ENSM state upon which calibrations are initializing */ 605 ALERTCALS = 3, /*!< Mykonos ENSM state upon which calibrations are occurring */ 606 ALERTLDS = 4, /*!< Mykonos ENSM state upon which a delay state is occurring when moving from WAIT to ALERT to allow internal circuits to power up */ 607 ALERT = 5, /*!< Mykonos ENSM state upon which the internal RF synth is powered up, and TX and RX data paths are still powered down */ 608 TX_RX = 6, /*!< Mykonos ENSM state upon which the ability to power up data paths depending on the TxEnable/RxEnable pins or SPI bits */ 609 FLUSH = 7 /*!< Mykonos ENSM state upon which the data paths are cleared when exiting the TX_RX state */ 610 } mykonosEnsmState_t; 611 612 613 /** 614 * \brief Enum of possible Tx channels 615 */ 616 typedef enum 617 { 618 TXOFF = 0, 619 TX1 = 1, 620 TX2 = 2, 621 TX1_TX2 = 3 622 } mykonosTxChannels_t; 623 624 /** 625 * \brief Enum of possible Rx channels 626 */ 627 typedef enum 628 { 629 RXOFF = 0, 630 RX1 = 1, 631 RX2 = 2, 632 RX1_RX2 = 3 633 } mykonosRxChannels_t; 634 635 /** 636 * \brief Enum of possible Observation Rx channels 637 */ 638 typedef enum 639 { 640 OBS_RXOFF = 0, 641 OBS_RX1_TXLO = 1, 642 OBS_RX2_TXLO = 2, 643 OBS_INTERNALCALS = 3, 644 OBS_SNIFFER = 4, 645 OBS_RX1_SNIFFERLO = 5, 646 OBS_RX2_SNIFFERLO = 6, 647 OBS_SNIFFER_A = 0x14, 648 OBS_SNIFFER_B = 0x24, 649 OBS_SNIFFER_C = 0x34 650 } mykonosObsRxChannels_t; 651 652 /** 653 * \brief Enum of possible Sniffer Rx channels 654 */ 655 typedef enum 656 { 657 SNIFFER_A = 1, 658 SNIFFER_B = 2, 659 SNIFFER_C = 3 660 } mykonosSnifferChannel_t; 661 662 /** 663 * \brief Enum of possible Observation Rx channels to enable and run calibrations for during init. 664 * Choose ENUM value that enables all channels that will be used in the system. During system use, 665 * only one channel can be used at a time. This is also used to alert the ARM processor 666 * which observation channels are valid for the current desired system setup. 667 */ 668 typedef enum 669 { 670 MYK_OBS_RXOFF = 0x00, 671 MYK_ORX1 = 0x01, 672 MYK_ORX2 = 0x02, 673 MYK_ORX1_ORX2 = 0x03, 674 MYK_SNRXA = 0x04, 675 MYK_SNRXB = 0x08, 676 MYK_SNRXC = 0x10, 677 MYK_SNRXA_B_C = 0x1C 678 } mykonosObsRxChannelsEn_t; 679 680 /** 681 * \brief Enum of possible DAC divider settings (2x, 2.5x, 4x) 682 */ 683 typedef enum 684 { 685 DACDIV_2, 686 DACDIV_2p5, 687 DACDIV_4 688 } mykonosDacDiv_t; 689 690 /** 691 * \brief Enum of possible VCO divider settings (1x, 1.5x, 2x, 3x) 692 */ 693 typedef enum 694 { 695 VCODIV_1 = 0, 696 VCODIV_1p5 = 1, 697 VCODIV_2 = 2, 698 VCODIV_3 = 3 699 } mykonosVcoDiv_t; 700 701 /** 702 * \brief Enum of possible PRBS pattern settings 703 */ 704 typedef enum 705 { 706 MYK_PRBS7 = 0, 707 MYK_PRBS15 = 1, 708 MYK_PRBS31 = 2 709 } mykonosPrbsOrder_t; 710 711 /** 712 * \brief Enum of RF PLL names 713 */ 714 typedef enum 715 { 716 CLK_PLL, 717 RX_PLL, 718 TX_PLL, 719 SNIFFER_PLL 720 } mykonosRfPllName_t; 721 722 /** 723 * \brief Enum of Rx profile types 724 */ 725 typedef enum 726 { 727 MYK_RX_PROFILE, 728 MYK_OBS_PROFILE, 729 MYK_SNIFFER_PROFILE 730 } mykonosRxProfType_t; 731 732 /** 733 * \brief Enum of ORx PLL names 734 */ 735 typedef enum 736 { 737 OBSLO_TX_PLL, 738 OBSLO_SNIFFER_PLL 739 } mykonosObsRxLoSource_t; 740 741 /** 742 * \brief Enum of possible wait events to use with MYKONOS_waitForEvent() 743 */ 744 typedef enum 745 { 746 CALPLL_LOCK, 747 CLKPLLCP, 748 CLKPLL_LOCK, 749 RF_RXPLLCP, 750 RF_RXPLL_LOCK, 751 RF_TXPLLCP, 752 RF_TXPLL_LOCK, 753 RF_SNIFFERPLLCP, 754 RF_SNIFFERPLL_LOCK, 755 RXBBF_CALDONE, 756 TXBBF_CALDONE, 757 RX_RFDC_CALDONE, 758 RX_ADCTUNER_CALDONE, 759 RX1_ADCPROFILE, 760 RX2_ADCPROFILE, 761 ORX_ADCPROFILE, 762 RCAL_CALDONE, 763 ARMBUSY, 764 INITARM_DONE 765 } waitEvent_t; 766 767 /** 768 * \brief Enum to set the desired FIR filter type for related functions 769 */ 770 typedef enum 771 { 772 TX1_FIR = 1, 773 TX2_FIR = 2, 774 TX1TX2_FIR = 3, 775 RX1_FIR = 4, 776 RX2_FIR = 8, 777 RX1RX2_FIR = 12, 778 OBSRX_A_FIR = 16, 779 OBSRX_B_FIR = 32 780 } mykonosfirName_t; 781 782 /** 783 * \brief Enum to set the desired Rx gain table channel 784 */ 785 typedef enum 786 { 787 RX1_GT = 1, 788 RX2_GT, 789 RX1_RX2_GT, 790 ORX_GT, 791 SNRX_GT, 792 LOOPBACK_GT 793 }mykonosGainTable_t; 794 795 /** 796 * \brief Enum to set the Rx Gain control mode 797 */ 798 typedef enum 799 { 800 MGC = 0, /*!< Manual Gain Control */ 801 AGC = 2, /*!< Automatic Gain Control (AGC) */ 802 HYBRID = 3 /*!< Hybrid AGC Gain Control */ 803 804 } mykonosGainMode_t; 805 806 /** 807 * \brief Enum to set the Tx Atenuation step size 808 */ 809 typedef enum 810 { 811 TXATTEN_0P05_DB = 0, /*!< Tx attenuation 0.05dB step size */ 812 TXATTEN_0P1_DB = 1, /*!< Tx attenuation 0.1dB step size */ 813 TXATTEN_0P2_DB = 2, /*!< Tx attenuation 0.2dB step size */ 814 TXATTEN_0P4_DB = 3 /*!< Tx attenuation 0.4dB step size */ 815 } mykonosTxAttenStepSize_t; 816 817 /** 818 * \brief Enum to help set the init calibration mask 819 */ 820 typedef enum 821 { 822 TX_BB_FILTER = 0x0001, 823 ADC_TUNER = 0x0002, 824 TIA_3DB_CORNER = 0x0004, 825 DC_OFFSET = 0x0008, 826 TX_ATTENUATION_DELAY = 0x0010, 827 RX_GAIN_DELAY = 0x0020, 828 FLASH_CAL = 0x0040, 829 PATH_DELAY = 0x0080, 830 TX_LO_LEAKAGE_INTERNAL = 0x0100, 831 TX_LO_LEAKAGE_EXTERNAL = 0x0200, 832 TX_QEC_INIT = 0x0400, 833 LOOPBACK_RX_LO_DELAY = 0x0800, 834 LOOPBACK_RX_RX_QEC_INIT = 0x1000, 835 RX_LO_DELAY = 0x2000, 836 RX_QEC_INIT = 0x4000, 837 DPD_INIT = 0x8000, 838 CLGC_INIT = 0x10000, 839 VSWR_INIT = 0x20000 840 } mykonosInitCalibrations_t; 841 842 /** 843 * \brief Enum to help set the tracking calibration mask 844 */ 845 typedef enum 846 { 847 TRACK_RX1_QEC = 0x00001, 848 TRACK_RX2_QEC = 0x00002, 849 TRACK_ORX1_QEC = 0x00004, 850 TRACK_ORX2_QEC = 0x00008, 851 TRACK_TX1_LOL = 0x00010, 852 TRACK_TX2_LOL = 0x00020, 853 TRACK_TX1_QEC = 0x00040, 854 TRACK_TX2_QEC = 0x00080, 855 TRACK_TX1_DPD = 0x00100, 856 TRACK_TX2_DPD = 0x00200, 857 TRACK_TX1_CLGC = 0x00400, 858 TRACK_TX2_CLGC = 0x00800, 859 TRACK_TX1_VSWR = 0x01000, 860 TRACK_TX2_VSWR = 0x02000, 861 TRACK_ORX1_QEC_SNLO = 0x10000, 862 TRACK_ORX2_QEC_SNLO = 0x20000, 863 TRACK_SRX_QEC = 0x40000 864 } mykonosTrackingCalibrations_t; 865 866 867 /** 868 * \brief Enum to select the desired status calibration path delay read back 869 */ 870 typedef enum 871 { 872 MYK_DPD_PATH_DELAY = 0, 873 MYK_CLGC_PATH_DELAY = 1, 874 MYK_VSWR_PATH_DELAY = 2 875 } mykonosPathDelaySel_t; 876 877 /** 878 * \brief Enum to set the GPIO3v3 mode 879 */ 880 typedef enum 881 { 882 GPIO3V3_LEVELTRANSLATE_MODE = 1, /*!< Level translate mode, signal level on low voltage GPIO output on GPIO3v3 pins */ 883 GPIO3V3_INVLEVELTRANSLATE_MODE = 2, /*!< Inverted Level translate mode, inverse of signal level on low voltage GPIO output on GPIO3v3 pins */ 884 GPIO3V3_BITBANG_MODE = 3, /*!< Manual mode, API function sets output pin levels and reads input pin levels */ 885 GPIO3V3_EXTATTEN_LUT_MODE = 4 /*!< GPIO3v3 output level follows Rx1/Rx2 gain table external control 6bit field. */ 886 } mykonosGpio3v3Mode_t; 887 888 /** 889 * \brief Enum to set the low voltage GPIO mode 890 */ 891 typedef enum 892 { 893 GPIO_MONITOR_MODE = 0, /*!< Allows a choice of debug signals to output from Mykonos to monitor the state of the device */ 894 GPIO_BITBANG_MODE = 3, /*!< Manual mode, API function sets output pin levels and reads input pin levels */ 895 GPIO_ARM_OUT_MODE = 9, /*!< Allows internal ARM processor to output on GPIO pins */ 896 GPIO_SLICER_OUT_MODE = 10 /*!< Allows Slicer active configuration to the GPIO output pins */ 897 } mykonosGpioMode_t; 898 899 /** 900 * \brief Enum for ARM states 901 */ 902 typedef enum 903 { 904 MYK_ARM_POWERUP = 0x00, /*!< ARM is powered up and ready to be programmed */ 905 MYK_ARM_READY = 0x01, /*!< ARM enter this state once the boot up sequence is completed */ 906 MYK_ARM_IDLE = 0x02, /*!< ARM enter this state after initial calibrations are completed */ 907 MYK_ARM_RADIO_ON = 0x04, /*!< ARM has moved from MYKONOS_ARM_IDLE state into MYKONOS_ARM_RADIO_ON after the proper command, an abort command will move back to MYKONOS_ARM_IDLE state */ 908 MYK_ARM_PROFILE_ERROR = 0x08, /*!< ARM has detected an illegal profile */ 909 MYK_ARM_CAL_ERROR = 0x40, /*!< ARM has detected an error in the tracking calibrations */ 910 MYK_ARM_EXCEPTION = 0x80 /*!< ARM system problem has been detected */ 911 } mykonosArmState_t; 912 913 /** 914 * \brief Enum for channel selection for DC offset settings. 915 */ 916 typedef enum 917 { 918 MYK_DC_OFFSET_RX_CHN = 0x01, /*!< Select Rx channel */ 919 MYK_DC_OFFSET_ORX_CHN = 0x02, /*!< Select ORx channel */ 920 MYK_DC_OFFSET_SNF_CHN = 0x04 /*!< Select Sniffer channel */ 921 }mykonosDcOffsetChannels_t; 922 923 /** 924 * \brief Enum of Rx channels for configuring (Enable /disable) DC offsets. 925 */ 926 typedef enum 927 { 928 MYK_DC_OFFSET_ALL_OFF = 0x00, /*!< Disable all the channels */ 929 MYK_DC_OFFSET_RX1 = 0x01, /*!< Enables Rx1 */ 930 MYK_DC_OFFSET_RX2 = 0x02, /*!< Enables Rx2 */ 931 MYK_DC_OFFSET_SNF = 0x04, /*!< Enables Sniffer */ 932 MYK_DC_OFFSET_ORX = 0x08, /*!< Enables ORx */ 933 MYK_DC_OFFSET_AVAILABLE = 0x0F /*!< Enables all the channels */ 934 }mykonosRxDcOffsettEn_t; 935 936 /** 937 * \brief Enum of build type 938 */ 939 typedef enum 940 { 941 MYK_BUILD_RELEASE = 0X00, 942 MYK_BUILD_DEBUG = 0x01, 943 MYK_BUILD_TEST_OBJECT = 0x04 944 }mykonosBuild_t; 945 946 /** 947 * \brief Enum for DPD error codes 948 */ 949 typedef enum 950 { 951 MYK_NO_ERROR = 0, /*!< No Error */ 952 MYK_ORX_DISABLED = 1, /*!< ORX_DISABLED */ 953 MYK_TX_DISABLED = 2, /*!< TX_DISABLED */ 954 MYK_PATHDELAY_NOT_SETUP = 3, /*!< PATHDELAY_NOT_SETUP */ 955 MYK_DPD_INIT_NOT_RUN = 4, /*!< DPD_INIT_NOT_RUN */ 956 MYK_ORX_SIG_TOO_LOW = 5, /*!< ORX_SIG_TOO_LOW */ 957 MYK_ORX_SIG_SATURATED = 6, /*!< ORX_SIG_SATURATED */ 958 MYK_TX_SIG_TOO_LOW = 7, /*!< TX_SIG_TOO_LOW */ 959 MYK_TX_SIG_SATURATED = 8, /*!< TX_SIG_SATURATED */ 960 MYK_MODEL_ERROR_HIGH = 9, /*!< MODEL_ERROR_HIGH */ 961 MYK_AM_AM_OUTLIERS = 10, /*!< AM_AM_OUTLIERS */ 962 MYK_INVALID_TX_PROFILE = 11, /*!< INVALID_TX_PROFILE */ 963 MYK_ORX_TRACKING_DISABLED = 12, /*!< ORX_TRACKING_DISABLED ORx tracking must be enabled */ 964 MYK_ERR_RESERVED_13 = 13, /*!< Reserved DPD error */ 965 MYK_ERR_BAD_ACTUATOR_MODEL = 14, /*!< DPD actuator model is in bad state */ 966 MYK_ERR_LOW_POWER_ACTUATOR_BYPASS = 15, /*!< DPD actuator bypassed due to low input power */ 967 968 MYK_DPD_ERROR_END 969 } mykonosDpdErrors_t; 970 971 /** 972 * \brief Enum for DPD reset modes 973 */ 974 typedef enum 975 { 976 MYK_DPD_NO_ACTION = 0, /*!< DPD no Action error */ 977 MYK_DPD_RESET_FULL = 1, /*!< Full DPD reset */ 978 MYK_DPD_RESET_PRIOR = 4, /*!< Reset only prior model */ 979 MYK_DPD_RESET_CORRELATOR = 8, /*!< Reset correlator only */ 980 981 MYK_DPD_RESET_END 982 } mykonosDpdResetMode_t; 983 984 985 /** 986 * \brief Enum for CLGC Tx attenuation tuning range modes 987 */ 988 typedef enum 989 { 990 MYK_CLGC_ATTEN_TUNING_PRESET = 0, /*!< Set attenuation to the tx[]AttenTuningPreset */ 991 MYK_CLGC_ATTEN_DISCARD = 1, /*!< Ignore calculated attenuation level and keep the existing one */ 992 MYK_CLGC_ATTEN_UPDATE = 2, /*!< Set attenuation to tx[]AttenTuningPreset + tx[]AttenTuningRange if calculated attenuation is above this level 993 Set attenuation to tx[]AttenTuningPreset - tx[]AttenTuningRange if calculated attenuation is below this level*/ 994 995 MYK_CLGC_ATTEN_END 996 } mykonosClgcAttenTuningMode_t; 997 998 /** 999 * \brief Data structure to hold 3.3 VDC GPIO settings 1000 */ 1001 typedef struct 1002 { 1003 uint16_t gpio3v3Oe; /*!< Pin direction: bit per 3.3v GPIO, 0=Input, 1=Output from Mykonos device */ 1004 mykonosGpio3v3Mode_t gpio3v3SrcCtrl3_0; /*!< Mode for GPIO3v3[3:0] pins */ 1005 mykonosGpio3v3Mode_t gpio3v3SrcCtrl7_4; /*!< Mode for GPIO3v3[7:4] pins */ 1006 mykonosGpio3v3Mode_t gpio3v3SrcCtrl11_8; /*!< Mode for GPIO3v3[11:8] pins */ 1007 } mykonosGpio3v3_t; 1008 1009 /** 1010 * \brief Data structure to hold low voltage GPIO settings 1011 */ 1012 typedef struct 1013 { 1014 uint32_t gpioOe; /*!< Output Enable per low voltage GPIO pin (1=output, 0=input) */ 1015 mykonosGpioMode_t gpioSrcCtrl3_0; /*!< Mode for low voltage GPIO[3:0] pins */ 1016 mykonosGpioMode_t gpioSrcCtrl7_4; /*!< Mode for low voltage GPIO[7:4] pins */ 1017 mykonosGpioMode_t gpioSrcCtrl11_8; /*!< Mode for low voltage GPIO[11:8] pins */ 1018 mykonosGpioMode_t gpioSrcCtrl15_12; /*!< Mode for low voltage GPIO[15:12] pins */ 1019 mykonosGpioMode_t gpioSrcCtrl18_16; /*!< Mode for low voltage GPIO[18:16] pins */ 1020 } mykonosGpioLowVoltage_t; 1021 1022 /** 1023 * \brief Structure used within the DPD config structure to hold a int8_t complex number 1024 */ 1025 typedef struct{ 1026 int8_t real; /*!< real part of the complex number */ 1027 int8_t imag; /*!< imaginary part of the complex number */ 1028 } int8_cpx; 1029 1030 /** 1031 * \brief Structure to configure DPD (Only valid for a DPD-enabled transceiver) 1032 * \deprecated robustModeling member of this structure is no longer in use. 1033 * This information is loaded into the ARM memory using the 1034 * MYKONOS_configDpd() function before running the DPD init or tracking 1035 * calibrations. These values can only be changed when the ARM is in the 1036 * radioOff state. 1037 */ 1038 typedef struct 1039 { 1040 uint8_t damping; /*!< 1/2^(damping + 8) fraction of previous model 'forgotten' per adaptation (default: 5 = '1/8192' , valid 0 to 15), 0 = infinite damping */ 1041 uint8_t numWeights; /*!< number of weights to use for int8_cpx weights weights member of this structure (default = 1) */ 1042 uint8_t modelVersion; /*!< DPD model version: one of four different generalized polynomial models: 0 = same as R0 silicon, 1-3 are new and the best one depends on the PA (default: 2) */ 1043 uint8_t highPowerModelUpdate; /*!< 1 = Update saved model whenever peak Tx digital RMS is within 1dB of historical peak Tx RMS */ 1044 uint8_t modelPriorWeight; /*!< Determines how much weight the loaded prior model has on DPD modeling (Valid 0 - 32, default 20) */ 1045 uint8_t robustModeling; /*!< This is deprecated and no longer in use */ 1046 uint16_t samples; /*!< number of samples to capture (default: 512, valid 64 - 32768) */ 1047 uint16_t outlierThreshold; /*!< threshold for sample in AM-AM plot outside of 1:1 line to be thrown out. (default: 50% = 8192/2, valid 8192 to 1) */ 1048 int16_t additionalDelayOffset; /*!< 16th of an ORx sample (16=1sample), (default 0, valid -64 to 64) */ 1049 uint16_t pathDelayPnSeqLevel; /*!< Default 255 (-30dBFs=(20Log10(value/8192)), (valid range 1 to 8191) */ 1050 int8_cpx weights[3]; /*!< DPD model error weighting (real/imag valid from -128 to 127) */ 1051 } mykonosDpdConfig_t; 1052 1053 /** 1054 * \brief Structure to configure the feature to bypass DPD actuator when signal power below a threshold 1055 * 1056 */ 1057 typedef struct 1058 { 1059 uint8_t bypassActuatorEn; /*!< Enable/Disable feature to bypass actuator when input power below a certain threshold */ 1060 mykonosDpdResetMode_t bypassActuatorMode; /*!< Follows reset DPD enum */ 1061 uint16_t bypassActuatorLevel; /*!< Tx RMS level below which actuator is bypassed. P_dBFS = 20*log10(bypassActuatorLevel/8192) */ 1062 } mykonosDpdBypassConfig_t; 1063 1064 1065 1066 /** 1067 * \brief Structure to configure the DPD actuator gain check 1068 * 1069 */ 1070 typedef struct 1071 { 1072 uint8_t actuatorGainCheckEn; /*!< Enable Gain check for DPD actuator */ 1073 mykonosDpdResetMode_t actuatorGainCheckMode; /*!< Follows reset DPD enum */ 1074 uint16_t actuatorGainCheckLevel; /*!< If the gain difference before and after the actuator exceeds this value an error will be issued 1075 and the actuator will reset depending on the actuatorGainCheckMode, in 0.01dB, where a value of 200 => 2dB*/ 1076 } mykonosDpdActuatorCheck_t; 1077 1078 /** 1079 * \brief Structure to configure CLGC (Closed Loop Gain Control) (Only valid for a DPD-enabled transceiver) 1080 * 1081 * This information is loaded into the ARM memory using the 1082 * MYKONOS_configClgc() function before running the CLGC init or tracking 1083 * calibrations. 1084 * These values can be changed when the ARM is in the radioOff or radioOn states. 1085 */ 1086 typedef struct 1087 { 1088 int16_t tx1DesiredGain; /*!< (value = 100 * dB (valid range -32768 to 32767) - total gain and attenuation from Mykonos Tx1 output to ORx1 input in (dB * 100) */ 1089 int16_t tx2DesiredGain; /*!< (value = 100 * dB (valid range -32768 to 32767) - total gain and attenuation from Mykonos Tx2 output to ORx2 input in (dB * 100) */ 1090 uint16_t tx1AttenLimit; /*!< (valid range 0 - 40dB), no default, depends on PA, Protects PA by making sure Tx1Atten is not reduced below the limit */ 1091 uint16_t tx2AttenLimit; /*!< (valid range 0 - 40dB), no default, depends on PA, Protects PA by making sure Tx2Atten is not reduced below the limit */ 1092 uint16_t tx1ControlRatio; /*!< valid range 1-100, default 45 */ 1093 uint16_t tx2ControlRatio; /*!< valid range 1-100, default 45 */ 1094 uint8_t allowTx1AttenUpdates; /*!< 0= allow CLGC to run, but Tx1Atten will not be updated. User can still read back power measurements. 1=CLGC runs, and Tx1Atten automatically updated */ 1095 uint8_t allowTx2AttenUpdates; /*!< 0= allow CLGC to run, but Tx2Atten will not be updated. User can still read back power measurements. 1=CLGC runs, and Tx2Atten automatically updated */ 1096 1097 int16_t additionalDelayOffset; /*!< 16th of an ORx sample (16=1sample), (default 0, valid -64 to 64) */ 1098 uint16_t pathDelayPnSeqLevel; /*!< Default 255 (-30dBFs=(20Log10(value/8192)), (valid range 1 to 8191) */ 1099 1100 uint16_t tx1RelThreshold; /*!< Threshold for Tx1 in order to stop tracking, value = 100 * dB, default 6db then value = 600 */ 1101 uint16_t tx2RelThreshold; /*!< Threshold for Tx2 in order to stop tracking, value = 100 * dB, default 6db then value = 600 */ 1102 uint8_t tx1RelThresholdEn; /*!< Threshold feature enable for Tx1, 0 = disable, 1 = enable, default = 0 */ 1103 uint8_t tx2RelThresholdEn; /*!< Threshold feature enable for Tx2, 0 = disable, 1 = enable, default = 0 */ 1104 } mykonosClgcConfig_t; 1105 1106 /** 1107 * \brief Structure to configure the CLGC attenuation tuning range 1108 */ 1109 typedef struct 1110 { 1111 mykonosClgcAttenTuningMode_t tx1AttenTuningLimitMode; /*!< Tx1 CLGC Attenuation tuning mode */ 1112 mykonosClgcAttenTuningMode_t tx2AttenTuningLimitMode; /*!< Tx2 CLGC Attenuation tuning mode */ 1113 uint16_t tx1AttenTuningPreset; /*!< Tx1 CLGC nominal attenuation, valid range is 0 to 839 with a 0.05dB*/ 1114 uint16_t tx2AttenTuningPreset; /*!< Tx2 CLGC nominal attenuation, valid range is 0 to 839 with a 0.05dB*/ 1115 uint16_t tx1AttenTuningRange; /*!< Tx1 CLGC relative attenuation range around nominal attenuation, valid range is 0 to 420 with a 0.05dB*/ 1116 uint16_t tx2AttenTuningRange; /*!< Tx2 CLGC relative attenuation range around nominal attenuation, valid range is 0 to 420 with a 0.05dB*/ 1117 } mykonosClgcAttenTuningConfig_t; 1118 1119 /** 1120 * \brief Structure to configure VSWR (Only valid for a DPD-enabled transceiver) 1121 * 1122 * This information is loaded into the ARM memory using the 1123 * MYKONOS_configVswr() function before running the VSWR init or tracking 1124 * calibrations. 1125 * These values can be changed when the ARM is in the radioOff states. 1126 */ 1127 typedef struct 1128 { 1129 /* VSWR init cal parameters */ 1130 int16_t additionalDelayOffset; /*!< 16th of an ORx sample (16=1sample), (default 0, valid -64 to 64) */ 1131 uint16_t pathDelayPnSeqLevel; /*!< Default 255 (-30dBFs=(20Log10(value/8192)), (valid range 1 to 8191) */ 1132 1133 /* VSWR tracking cal parameters */ 1134 uint8_t tx1VswrSwitchGpio3p3Pin; /*!< 3p3V GPIO pin to use to control VSWR switch for Tx1 (valid 0-11) (output from Mykonos) */ 1135 uint8_t tx2VswrSwitchGpio3p3Pin; /*!< 3p3V GPIO pin to use to control VSWR switch for Tx2 (valid 0-11) (output from Mykonos) */ 1136 uint8_t tx1VswrSwitchPolarity; /*!< 3p3v GPIO pin polarity for forward path of Tx1, opposite used for reflection path (1 = high level, 0 = low level) */ 1137 uint8_t tx2VswrSwitchPolarity; /*!< 3p3v GPIO pin polarity for forward path of Tx2, opposite used for reflection path (1 = high level, 0 = low level) */ 1138 uint8_t tx1VswrSwitchDelay_us; /*!< Delay for Tx1 after flipping the VSWR switch until measurement is made. In us resolution with a range from 0 to 255us */ 1139 uint8_t tx2VswrSwitchDelay_us; /*!< Delay for Tx2 after flipping the VSWR switch until measurement is made. In us resolution with a range from 0 to 255us */ 1140 } mykonosVswrConfig_t; 1141 1142 typedef struct 1143 { 1144 /** 1145 * errorStatus(decimal) | Description 1146 * ---------------------|----------------------- 1147 * 0 | NO ERROR (Tracking success) 1148 * 1 | Tx data path not enabled 1149 * 2 | ORX data path is not enabled 1150 * 3 | Loopback switch closed 1151 * 4 | VSWR init cal was not run 1152 * 5 | Path delay not setup 1153 * 6 | Data measurement was aborted 1154 * 7 | VSWR disabled 1155 * 8 | If set, entered cal but not finished 1156 * 9 | No GPIO configured in single ORx configuration 1157 * 10 | Tx is not observable with any of the ORx Channels 1158 * 11 | ORX_TRACKING_DISABLED ORx tracking must be enabled 1159 * 1160 */ 1161 uint32_t errorStatus; 1162 uint32_t trackCount; /*!< Number of times VSWR tracking has run since last reset */ 1163 int32_t forwardGainRms_dB; /*!< Forward RMS gain measured from Tx to ORx path (1 = 0.01 dB Gain) */ 1164 int32_t forwardGainReal; /*!< Real part of the forward path complex gain (1 = 0.01 linear Gain) */ 1165 int32_t forwardGainImag; /*!< Imaginary part of the forward path complex gain (1 = 0.01 linear Gain) */ 1166 int32_t reflectedGainRms_dB; /*!< Measured reflection path gain in RMS (1 = 0.01 dB Gain) */ 1167 int32_t reflectedGainReal; /*!< Real part of the reflection path complex gain (1 = 0.01 linear Gain) */ 1168 int32_t reflectedGainImag; /*!< Imaginary part of the reflection path complex gain (1 = 0.01 linear Gain) */ 1169 int32_t vswr_forward_tx_rms; /*!< Forward RMS measured from Tx path (1 = 0.01 dBFS) */ 1170 int32_t vswr_forward_orx_rms; /*!< Forward RMS measured from ORx path (1 = 0.01 dBFS) */ 1171 int32_t vswr_reflection_tx_rms; /*!< Reflected RMS measured from Tx path (1 = 0.01 dBFS) */ 1172 int32_t vswr_reflection_orx_rms; /*!< Reflected RMS measured from ORx path (1 = 0.01 dBFS) */ 1173 } mykonosVswrStatus_t; 1174 1175 /** 1176 * \brief Data structure to hold Mykonos FIR filter settings 1177 */ 1178 typedef struct 1179 { 1180 int8_t gain_dB; /*!< Filter gain in dB*/ 1181 uint8_t numFirCoefs; /*!< Number of coefficients in the FIR filter */ 1182 int16_t *coefs; /*!< A pointer to an array of filter coefficients */ 1183 } mykonosFir_t; 1184 1185 /** 1186 * \brief Data structure to hold Mykonos JESD204b Framer configuration settings 1187 */ 1188 typedef struct 1189 { 1190 uint8_t bankId; /*!< JESD204B Configuration Bank ID extension to Device ID. Range is 0..15 */ 1191 uint8_t deviceId; /*!< JESD204B Configuration Device ID link identification number. Range is 0..255 */ 1192 uint8_t lane0Id; /*!< JESD204B Configuration starting Lane ID. If more than one lane is used, each lane will increment from the Lane0 ID. Range is 0..31 */ 1193 uint8_t M; /*!< Number of ADCs (0, 2, or 4) where 2 ADCs are required per receive chain (I and Q) */ 1194 uint8_t K; /*!< Number of frames in a multiframe. Default = 32, F*K must be modulo 4. Where, F=2*M/numberOfLanes */ 1195 uint8_t scramble; /*!< Scrambling off if framerScramble = 0, if framerScramble > 0 scrambling is enabled */ 1196 uint8_t externalSysref; /*!< External SYSREF select. 0 = use internal SYSREF, 1 = use external SYSREF */ 1197 uint8_t serializerLanesEnabled; /*!< Serializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */ 1198 uint8_t serializerLaneCrossbar; /*!< Lane crossbar to map framer lane outputs to physical lanes */ 1199 uint8_t serializerAmplitude; /*!< Serializer amplitude setting. Default = 22. Range is 0..31 */ 1200 uint8_t preEmphasis; /*!< Serializer pre-emphasis setting. Default = 4 Range is 0..7 */ 1201 uint8_t invertLanePolarity; /*!< Lane inversion select. Default = 0. Where, bit[0] = 0 will invert lane [0], bit[1] = 0 will invert lane 1, etc. */ 1202 uint8_t lmfcOffset; /*!< LMFC offset value for deterministic latency setting. Range is 0..31 */ 1203 uint8_t newSysrefOnRelink; /*!< Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, 0 = not set */ 1204 uint8_t enableAutoChanXbar; /*!< Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set */ 1205 uint8_t obsRxSyncbSelect; /*!< Selects SYNCb input source. Where, 0 = use RXSYNCB for this framer, 1 = use OBSRX_SYNCB for this framer */ 1206 uint8_t rxSyncbMode; /*!< Flag for determining if CMOS mode for RX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS */ 1207 uint8_t overSample; /*!< Selects framer bit repeat or oversampling mode for lane rate matching. Where, 0 = bitRepeat mode (changes effective lanerate), 1 = overSample (maintains same lane rate between ObsRx framer and Rx framer and oversamples the ADC samples) */ 1208 uint8_t enableManualLaneXbar; /*!< Flag for determining if API will calculate the appropriate settings for framer lane outputs to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in serializerLaneCrossbar will be used */ 1209 } mykonosJesd204bFramerConfig_t; 1210 1211 /* NO Doxygen content required for this data structure as this is used internally */ 1212 /// @cond 1213 typedef struct 1214 { 1215 uint8_t DID; /*!< JESD204B Configuration Device ID for ILAS check */ 1216 uint8_t BID; /*!< JESD204B Configuration Bank ID for ILAS check */ 1217 uint8_t LID0; /*!< JESD204B Configuration starting Lane ID for ILAS check */ 1218 uint8_t L; /*!< JESD204B Configuration L = lanes per data converter for ILAS check */ 1219 uint8_t SCR; /*!< JESD204B Configuration scramble setting for ILAS check */ 1220 uint8_t F; /*!< JESD204B Configuration F = octets per frame for ILAS check */ 1221 uint8_t K; /*!< JESD204B Configuration K = frames per multiframe for ILAS check */ 1222 uint8_t M; /*!< JESD204B Configuration M = number of data converters for ILAS check */ 1223 uint8_t N; /*!< JESD204B Configuration N = data converter sample resolution for ILAS check */ 1224 uint8_t CS; /*!< JESD204B Configuration CS = number of control bits transferred per sample per frame for ILAS check */ 1225 uint8_t NP; /*!< JESD204B Configuration NP = JESD204B word size based on the highest resolution of the data converter for ILAS check */ 1226 uint8_t S; /*!< JESD204B Configuration S = number of samples/data converter/frame for ILAS check */ 1227 uint8_t CF; /*!< JESD204B Configuration CF = '0' = control bits appended to each sample, '1' = appended to end of frame for ILAS check */ 1228 uint8_t HD; /*!< JESD204B Configuration HD = high density bit - samples are contained within lane (0) or divided over more than one lane (1) for ILAS check */ 1229 uint8_t FCHK0; /*!< JESD204B Configuration checksum for ILAS check */ 1230 } mykonosJesd204bLane0Config_t; 1231 /// @endcond 1232 1233 /** 1234 * \brief Data structure to hold the settings for the deserializer and deframer configuration 1235 * 1236 * EQ Settings | 3GHz Loss (dB) |6GHz Loss (dB) | max FR408HR Length (in) | max FR4 Length (in) 1237 *-------------|----------------|---------------|-------------------------|--------------------- 1238 * 0 | 6.5 | 14 | 20 | 12 1239 * 1 | 11.5 | 21 | 30 | 20 1240 * 2 | 18 | 31 | 46 | 32 1241 * 3 | 21.5 | 38 | 56 | 40 1242 * 4 | 22 | 39 | 60 | 43 1243 */ 1244 typedef struct 1245 { 1246 uint8_t bankId; /*!< Extension to Device ID. Range is 0..15 */ 1247 uint8_t deviceId; /*!< Link identification number. Range is 0..255 */ 1248 uint8_t lane0Id; /*!< Lane0 ID. Range is 0..31 */ 1249 uint8_t M; /*!< Number of DACs (0, 2, or 4) - 2 DACs per transmit chain (I and Q) */ 1250 uint8_t K; /*!< Number of frames in a multiframe. Default = 32, F*K = modulo 4. Where, F=2*M/numberOfLanes */ 1251 uint8_t scramble; /*!< Scrambling off if scramble = 0, if framerScramble > 0 scrambling is enabled */ 1252 uint8_t externalSysref; /*!< External SYSREF select. 0 = use internal SYSREF, 1 = external SYSREF */ 1253 uint8_t deserializerLanesEnabled; /*!< Deserializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */ 1254 uint8_t deserializerLaneCrossbar; /*!< Lane crossbar to map physical lanes to deframer lane inputs [1:0] = Deframer Input 0 Lane section, [3:2] = Deframer Input 1 lane select, etc */ 1255 uint8_t EQSetting; /*!< Equalizer setting. Applied to all deserializer lanes. Range is 0..4 */ 1256 uint8_t invertLanePolarity; /*!< PN inversion per each lane. bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert PN of Lane 1, etc */ 1257 uint8_t lmfcOffset; /*!< LMFC offset value to adjust deterministic latency. Range is 0..31 */ 1258 uint8_t newSysrefOnRelink; /*!< Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, '0' = not set */ 1259 uint8_t enableAutoChanXbar; /*!< Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set */ 1260 uint8_t txSyncbMode; /*!< Flag for determining if CMOS mode for TX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS */ 1261 uint8_t enableManualLaneXbar; /*!< Flag for determining if API will calculate the appropriate settings for deframer lane in to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in deserializerLaneCrossbar will be used */ 1262 } mykonosJesd204bDeframerConfig_t; 1263 1264 /** 1265 * \brief Data structure to hold settings for the current Rx specific use case profile 1266 */ 1267 typedef struct 1268 { 1269 uint8_t adcDiv; /*!< The divider used to generate the ADC clock (Valid: 1,2) */ 1270 mykonosFir_t *rxFir; /*!< Pointer to Rx FIR filter structure */ 1271 uint8_t rxFirDecimation; /*!< Rx FIR decimation (1,2,4) */ 1272 uint8_t rxDec5Decimation; /*!< Decimation of Dec5 or Dec4 filter (5,4) */ 1273 uint8_t enHighRejDec5; /*!< If set, and DEC5 filter used, will use a higher rejection DEC5 FIR filter. Where, 1 = enabled, 0 = disabled */ 1274 uint8_t rhb1Decimation; /*!< RX Halfband1 (HB1) decimation. Can be either 1 or 2 */ 1275 uint32_t iqRate_kHz; /*!< Rx IQ data rate in kHz */ 1276 uint32_t rfBandwidth_Hz; /*!< Rx RF passband bandwidth for the profile */ 1277 uint32_t rxBbf3dBCorner_kHz; /*!< Rx BBF (TIA) 3dB corner in kHz */ 1278 uint16_t *customAdcProfile; /*!< Custom ADC profile to set the bandwidth of the ADC response */ 1279 } mykonosRxProfile_t; 1280 1281 /** 1282 * \brief Data structure to hold settings for the current Tx specific use case profile 1283 */ 1284 typedef struct 1285 { 1286 mykonosDacDiv_t dacDiv; /*!< The divider used to generate the DAC clock (ENUM Values)*/ 1287 mykonosFir_t *txFir; /*!< Pointer to Tx FIR filter structure */ 1288 uint8_t txFirInterpolation; /*!< The TX digital FIR filter interpolation (1,2,4) */ 1289 uint8_t thb1Interpolation; /*!< Tx Halfband1 (HB1) filter interpolation (1,2) */ 1290 uint8_t thb2Interpolation; /*!< Tx Halfband2 (HB2) filter interpolation (1,2) */ 1291 uint8_t txInputHbInterpolation; /*!< Interpolation of half band filter before the programmable FIR (valid 1,2,4) */ 1292 uint32_t iqRate_kHz; /*!< Tx IQ data rate in kHz */ 1293 uint32_t primarySigBandwidth_Hz; /*!< Tx primary signal BW */ 1294 uint32_t rfBandwidth_Hz; /*!< Tx RF passband bandwidth for the profile */ 1295 uint32_t txDac3dBCorner_kHz; /*!< DAC filter 3dB corner in kHz */ 1296 uint32_t txBbf3dBCorner_kHz; /*!< Tx BBF 3dB corner in kHz */ 1297 uint8_t enableDpdDataPath; /*!< Enable Tx Dynamic pre distortion - only valid for a DPD-enabled transceiver */ 1298 } mykonosTxProfile_t; 1299 1300 /** 1301 * \brief Data structure to hold SnRx gain control settings for initialization and during use 1302 */ 1303 typedef struct 1304 { 1305 mykonosGainMode_t gainMode; /*!< Current Sniffer gain control mode setting */ 1306 uint8_t gainIndex; /*!< Current Sniffer gain index. Can be used differently for Manual Gain control/AGC */ 1307 uint8_t maxGainIndex; /*!< Max gain index for the currently loaded Sniffer Gain table */ 1308 uint8_t minGainIndex; /*!< Min gain index for the currently loaded Sniffer Gain table */ 1309 } mykonosSnifferGainControl_t; 1310 1311 /** 1312 * \brief Data structure to hold ORx gain control settings for initialization and during use 1313 */ 1314 typedef struct 1315 { 1316 mykonosGainMode_t gainMode; /*!< Current ORx gain control mode setting */ 1317 uint8_t orx1GainIndex; /*!< ORx1 Gain Index, can be used in different ways for manual and AGC gain control */ 1318 uint8_t orx2GainIndex; /*!< ORx2 Gain Index, can be used in different ways for manual and AGC gain control */ 1319 uint8_t maxGainIndex; /*!< Max gain index for the currently loaded ORx Gain table */ 1320 uint8_t minGainIndex; /*!< Min gain index for the currently loaded ORx Gain table */ 1321 } mykonosORxGainControl_t; 1322 1323 /** 1324 * \brief Data structure to hold Rx gain control settings for initialization and during use 1325 */ 1326 typedef struct 1327 { 1328 mykonosGainMode_t gainMode; /*!< Current Rx gain control mode setting */ 1329 uint8_t rx1GainIndex; /*!< Rx1 Gain Index, can be used in different ways for manual and AGC gain control */ 1330 uint8_t rx2GainIndex; /*!< Rx2 Gain Index, can be used in different ways for manual and AGC gain control */ 1331 uint8_t rx1MaxGainIndex; /*!< Max gain index for the currently loaded Rx1 Gain table */ 1332 uint8_t rx1MinGainIndex; /*!< Min gain index for the currently loaded Rx1 Gain table */ 1333 uint8_t rx2MaxGainIndex; /*!< Max gain index for the currently loaded Rx2 Gain table */ 1334 uint8_t rx2MinGainIndex; /*!< Min gain index for the currently loaded Rx2 Gain table */ 1335 uint8_t rx1Rssi; /*!< Stores Rx1 RSSI value read back from the Mykonos */ 1336 uint8_t rx2Rssi; /*!< Stores Rx2 RSSI value read back from the Mykonos */ 1337 } mykonosRxGainControl_t; 1338 1339 /** 1340 * \brief Data structure to hold peak detector settings for the AGC 1341 */ 1342 typedef struct 1343 { 1344 /* Threshold Settings */ 1345 uint8_t apdHighThresh; /*!< APD high threshold. Must be greater than apdLowThresh. Min = apdLowThresh, Max = 0x3F. 6-bit field. */ 1346 uint8_t apdLowThresh; /*!< APD low threshold. Must be less than apdHighThresh. Min = 0, Max = apdHighThresh. 6-bit field. */ 1347 uint8_t hb2HighThresh; /*!< HB2 high threshold. Must be greater than hb2LowThresh. Min = hb2LowThresh, Max = 0xFF. 8-bit field. */ 1348 uint8_t hb2LowThresh; /*!< HB2 low threshold. Must be less than hb2HighThresh. Min = 0, Max = hb2HighThresh. 8-bit field. */ 1349 uint8_t hb2VeryLowThresh; /*!< HB2 very low threshold. Must be less than hb2LowThresh. Min = 0, Max = hb2LowThresh. 8-bit field. */ 1350 1351 /* Threshold Counter Settings */ 1352 uint8_t apdHighThreshExceededCnt; /*!< APD high threshold exceeded counter. Sets number of peaks to detect above apdHighThresh to cause gain decrement according to apdHighGainStepAttack. 8-bit field. */ 1353 uint8_t apdLowThreshExceededCnt; /*!< APD low threshold exceeded counter. Sets number of peaks to detect below apdLowThresh to cause gain increment according to apdLowGainStepRecovery. 8-bit field. */ 1354 uint8_t hb2HighThreshExceededCnt; /*!< HB2 high threshold exceeded counter. Sets number of overloads to detect above hb2HighThresh to cause gain decrement according to hb2HighGainStepAttack. 8-bit field. */ 1355 uint8_t hb2LowThreshExceededCnt; /*!< HB2 low threshold exceeded counter. Sets number of peaks to detect below hb2LowThresh to cause gain increment according to hb2LowGainStepRecovery. 8-bit field. */ 1356 uint8_t hb2VeryLowThreshExceededCnt; /*!< HB2 very low threshold exceeded counter. Sets number of peaks to detect below hb2VeryLowThresh to cause gain increment according to hb2VeryLowGainStepRecovery. 8-bit field. */ 1357 1358 /* Gain Step Settings */ 1359 uint8_t apdHighGainStepAttack; /*!< Number of gain indices to decrement gain when apdHighThreshExceededCnt is exceeded. 5-bit field. */ 1360 uint8_t apdLowGainStepRecovery; /*!< Number of gain indices to increment gain when apdLowThreshExceededCnt is exceeded. 5-bit field */ 1361 uint8_t hb2HighGainStepAttack; /*!< Number of gain indices to decrement gain when hb2HighThreshExceededCnt is exceeded. 5-bit field */ 1362 uint8_t hb2LowGainStepRecovery; /*!< Number of gain indices to increment gain when hb2LowThreshExceededCnt is exceeded. 5-bit field*/ 1363 uint8_t hb2VeryLowGainStepRecovery; /*!< Number of gain indices to increment gain when hb2VeryLowThreshExceededCnt is exceeded. 5-bit field */ 1364 1365 /* Fast Attack Settings */ 1366 uint8_t apdFastAttack; /*!< [1] Enables APD fast attack mode - gain decrements immediately when apdHighThreshExceededCnt is exceeded. [0] disables APD fast attack mode - gain decrements at the expiry of agcGainUpdateCounter. 1-bit field. */ 1367 uint8_t hb2FastAttack; /*!< [1] Enables HB2 fast attack mode - gain decrements immediately when hb2HighThreshExceededCnt is exceeded. [0] disables HB2 fast attack mode - gain decrements at the expiry of agcGainUpdateCounter. 1-bit field. */ 1368 1369 /* HB2 Configuration Settings */ 1370 uint8_t hb2OverloadDetectEnable; /*!< [1] Enables the HB2 overload detector. [0] Disables the HB2 overload detector. 1-bit field. */ 1371 uint8_t hb2OverloadDurationCnt; /*!< Sets the samples size window of the HB2 overload detector. If hb2OverloadThreshCnt number of overloads are detected, the hb2xxxThreshExceededCnt increments. 3-bit field. [001]=1, [001]=4, [010]=8, [011]=12, [100]=16, [101]=24, [110]=32, [111]=INVALID */ 1372 uint8_t hb2OverloadThreshCnt; /*!< Sets the number of individual overloads necessary within hb2OverloadDurationCnt samples to increment the hb2xxxThreshExceededCnt */ 1373 } mykonosPeakDetAgcCfg_t; 1374 1375 /** 1376 * \brief Data structure to hold power measurement settings for the AGC 1377 */ 1378 typedef struct 1379 { 1380 /* Threshold Settings */ 1381 uint8_t pmdUpperHighThresh; /*!< Power measurement upper band, high threshold . This value is a positive offset to the pmdUpperLowThresh threshold. 4-bit field */ 1382 uint8_t pmdUpperLowThresh; /*!< Power measurement upper band, low threshold. This value sets the threshold in (negative) -dBFS. Byte value must be less than pmdLowerHighThresh. 7-bit field */ 1383 uint8_t pmdLowerHighThresh; /*!< Power measurement lower band, high threshold. This value sets the threshold in (negative) -dBFS. Byte value must be greater than pmdUpperLowThresh. 7-bit field */ 1384 uint8_t pmdLowerLowThresh; /*!< Power measurement lower band, low threshold. This value is a negative offset to the pmdLowerHighThresh threshold. 4-bit field */ 1385 1386 /* Gain Step Settings */ 1387 uint8_t pmdUpperHighGainStepAttack; /*!< Number of gain indices to decrement gain if pmdUpperHighThresh is exceeded by the end of the agcGainUpdateCounter. 5-bit field */ 1388 uint8_t pmdUpperLowGainStepAttack; /*!< Number of gain indices to decrement gain if pmdUpperLowThresh is exceeded by the end of the agcGainUpdateCounter. 5-bit field */ 1389 uint8_t pmdLowerHighGainStepRecovery; /*!< Number of gain indices to increment gain if pmdLowerHighThresh is not exceeded by the end of the agcGainUpdateCounter. 5-bit field */ 1390 uint8_t pmdLowerLowGainStepRecovery; /*!< Number of gain indices to increment gain if pmdLowerLowThresh is not exceeded by the end of the agcGainUpdateCounter. 5-bit field */ 1391 1392 /* PMD Configuration Settings */ 1393 uint8_t pmdMeasDuration; /*!< Number of samples to measure power on. The number of samples corresponding to the 4-bit word is 8*2^(pmdMeasDuration[3:0]). This value must be less than agcGainUpdateCounter */ 1394 uint8_t pmdMeasConfig; /*!< Power measurement configuration. 2-bit field. [00]=PMD disabled, [01]=PMD Enabled at HB2 output, [10]=Enabled at RFIR output (recommended), [11]=PMD Enabled at BBDC2 */ 1395 } mykonosPowerMeasAgcCfg_t; 1396 1397 /** 1398 * \brief Data structure to hold general AGC settings for initialization and during use 1399 */ 1400 typedef struct 1401 { 1402 /* Gain Table Settings */ 1403 uint8_t agcRx1MaxGainIndex; /*!< Maximum Rx1 gain index allowed in AGC mode. Must be greater than agcRx1MinGainIndex and valid gain index. 8-bit field */ 1404 uint8_t agcRx1MinGainIndex; /*!< Minimum Rx1 gain index allowed in AGC mode. Must be less than agcRx1MinGainIndex and valid gain index. 8-bit field */ 1405 uint8_t agcRx2MaxGainIndex; /*!< Maximum Rx2 gain index allowed in AGC mode. Must be greater than agcRx2MinGainIndex and valid gain index. 8-bit field */ 1406 uint8_t agcRx2MinGainIndex; /*!< Minimum Rx2 gain index allowed in AGC mode. Must be less than agcRx2MinGainIndex and valid gain index. 8-bit field */ 1407 uint8_t agcObsRxMaxGainIndex; /*!< Maximum ObsRx gain index allowed in AGC mode. Must be greater than agcObsRxMinGainIndex and valid gain index. 8-bit field */ 1408 uint8_t agcObsRxMinGainIndex; /*!< Minimum ObsRx gain index allowed in AGC mode. Must be less than agcObsRxMaxGainIndex and valid gain index. 8-bit field */ 1409 uint8_t agcObsRxSelect; /*!< Sniffer or ObsRx AGC channel select. [1] = SnRx */ 1410 1411 /* AGC Mode Selection */ 1412 uint8_t agcPeakThresholdMode; /*!< [1] = Peak Threshold Mode, power based gain changes are disabled. [0] = Peak and overload detectors are ignored for gain changes */ 1413 uint8_t agcLowThsPreventGainIncrease; /*!< [1] PMD based gain increments are ignored if apd/hb2LowThreshExceedCnt is high [0] apdLowThreshExceededCnt and hb2LowThreshExceededCnt are "Don't cares" to the AGC gain recovery */ 1414 1415 /* AGC General Settings */ 1416 uint32_t agcGainUpdateCounter; /*!< Number of samples for the AGC gain update counter. Counter operates on the IQ data rate. 22-bit field. Min = 0x000001, Max = 0x3FFFFF */ 1417 uint8_t agcSlowLoopSettlingDelay; /*!< Number of IQ data rate clock cycles to wait after a gain change before peak/power measurements resume. 7-bit field */ 1418 uint8_t agcPeakWaitTime; /*!< Number of IQ data rate clock cycles to wait to enable peak/overload detectors after AGC is enabled. 5-bit field. Min = 0x02. Max = 0x1F */ 1419 uint8_t agcResetOnRxEnable; /*!< [1] = Performs a reset of the AGC slow loop state machine when Rx is disabled. [0] = AGC slow loop state machine maintains its state when Rx is disabled. */ 1420 uint8_t agcEnableSyncPulseForGainCounter; /*!< [1] = Allows sync of agcGainUpdateCounter to the time-slot boundary. GPIO setup required. [0] = agcGainUpdateCounter functions as normal */ 1421 1422 mykonosPeakDetAgcCfg_t *peakAgc; /*!< pointer to structure for Peak AGC */ 1423 mykonosPowerMeasAgcCfg_t *powerAgc; /*!< pointer to structure for Power AGC */ 1424 } mykonosAgcCfg_t; 1425 1426 /** 1427 * \brief Data structure to hold Tx data path settings 1428 */ 1429 typedef struct 1430 { 1431 mykonosTxProfile_t *txProfile; /*!< Tx datapath profile, 3dB corner frequencies, and digital filter enables */ 1432 mykonosJesd204bDeframerConfig_t *deframer; /*!< Mykonos JESD204b deframer config for the Tx data path */ 1433 mykonosTxChannels_t txChannels; /*!< The desired Tx channels to enable during initialization */ 1434 uint8_t txPllUseExternalLo; /*!< Internal LO=0, external LO*2 if =1 */ 1435 uint64_t txPllLoFrequency_Hz; /*!< Tx PLL LO frequency (internal or external LO) */ 1436 mykonosTxAttenStepSize_t txAttenStepSize; /*!< Tx Attenuation step size */ 1437 uint16_t tx1Atten_mdB; /*!< Initial and current Tx1 Attenuation */ 1438 uint16_t tx2Atten_mdB; /*!< Initial and current Tx2 Attenuation */ 1439 mykonosDpdConfig_t *dpdConfig; /*!< DPD settings. Only valid for a DPD-enabled transceiver, set pointer to NULL otherwise */ 1440 mykonosClgcConfig_t *clgcConfig; /*!< CLGC settings. Only valid for a DPD-enabled transceiver, set pointer to NULL otherwise */ 1441 mykonosVswrConfig_t *vswrConfig; /*!< VSWR settings. Only valid for a DPD-enabled transceiver, set pointer to NULL otherwise */ 1442 } mykonosTxSettings_t; 1443 1444 /** 1445 * \brief Data structure to hold Rx data path settings 1446 */ 1447 typedef struct 1448 { 1449 mykonosRxProfile_t *rxProfile; /*!< Rx datapath profile, 3dB corner frequencies, and digital filter enables */ 1450 mykonosJesd204bFramerConfig_t *framer; /*!< Rx JESD204b framer configuration structure */ 1451 mykonosRxGainControl_t *rxGainCtrl; /*!< Rx Gain control settings structure */ 1452 mykonosAgcCfg_t *rxAgcCtrl; /*!< Rx AGC control settings structure */ 1453 mykonosRxChannels_t rxChannels; /*!< The desired Rx Channels to enable during initialization */ 1454 uint8_t rxPllUseExternalLo; /*!< Internal LO = 0, external LO*2 = 1 */ 1455 uint64_t rxPllLoFrequency_Hz; /*!< Rx PLL LO Frequency (internal or external LO) */ 1456 uint8_t realIfData; /*!< Flag to choose if complex baseband or real IF data are selected for Rx and ObsRx paths. Where, if > 0 = real IF data, '0' = zero IF (IQ) data*/ 1457 } mykonosRxSettings_t; 1458 1459 /** 1460 * \brief Data structure to hold ORx data path settings 1461 */ 1462 typedef struct 1463 { 1464 mykonosRxProfile_t *orxProfile; /*!< ORx datapath profile, 3dB corner frequencies, and digital filter enables. */ 1465 mykonosORxGainControl_t *orxGainCtrl; /*!< ObsRx gain control settings structure */ 1466 mykonosAgcCfg_t *orxAgcCtrl; /*!< ORx AGC control settings structure */ 1467 mykonosRxProfile_t *snifferProfile; /*!< Sniffer datapath profile, 3dB corner frequencies, and digital filter enables. */ 1468 mykonosSnifferGainControl_t *snifferGainCtrl; /*!< SnRx gain control settings structure */ 1469 mykonosJesd204bFramerConfig_t *framer; /*!< ObsRx JESD204b framer configuration structure */ 1470 mykonosObsRxChannelsEn_t obsRxChannelsEnable; /*!< The desired ObsRx channels to configure/calibrate during initialization */ 1471 mykonosObsRxLoSource_t obsRxLoSource; /*!< The sniffer/ORx mixers can use the TX_PLL or SNIFFER_PLL */ 1472 uint64_t snifferPllLoFrequency_Hz; /*!< SnRx PLL LO frequency in Hz */ 1473 uint8_t realIfData; /*!< Flag to choose if complex baseband or real IF data are selected for Rx and ObsRx paths. Where if > 0 = real IF data, '0' = complex data */ 1474 uint16_t *customLoopbackAdcProfile; /*!< Custom Loopback ADC profile to set the bandwidth of the ADC response */ 1475 mykonosObsRxChannels_t defaultObsRxChannel; /*!< Default ObsRx channel to enter when radioOn called */ 1476 } mykonosObsRxSettings_t; 1477 1478 1479 /** 1480 * \brief Data structure to hold ARM GPIO pin assignments for each ARM input/output pin. 1481 */ 1482 typedef struct 1483 { 1484 uint8_t useRx2EnablePin; /*!< 0= RX1_ENABLE controls RX1 and RX2, 1 = separate RX1_ENABLE/RX2_ENABLE pins */ 1485 uint8_t useTx2EnablePin; /*!< 0= TX1_ENABLE controls TX1 and TX2, 1 = separate TX1_ENABLE/TX2_ENABLE pins */ 1486 uint8_t txRxPinMode; /*!< 0= ARM command mode, 1 = Pin mode to power up Tx/Rx chains */ 1487 uint8_t orxPinMode; /*!< 0= ARM command mode, 1 = Pin mode to power up ObsRx receiver*/ 1488 1489 /* Mykonos ARM input GPIO pins -- Only valid if orxPinMode = 1 */ 1490 uint8_t orxTriggerPin; /*!< Select desired GPIO pin (valid 4-15) */ 1491 uint8_t orxMode2Pin; /*!< Select desired GPIO pin (valid 0-18) */ 1492 uint8_t orxMode1Pin; /*!< Select desired GPIO pin (valid 0-18) */ 1493 uint8_t orxMode0Pin; /*!< Select desired GPIO pin (valid 0-18) */ 1494 1495 /* Mykonos ARM output GPIO pins -- always available, even when pin mode not enabled*/ 1496 uint8_t rx1EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */ 1497 uint8_t rx2EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */ 1498 uint8_t tx1EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */ 1499 uint8_t tx2EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */ 1500 uint8_t orx1EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */ 1501 uint8_t orx2EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */ 1502 uint8_t srxEnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */ 1503 uint8_t txObsSelect; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */ 1504 /* When 2Tx are used with only 1 ORx input, this GPIO tells the BBIC which Tx channel is */ 1505 /* active for calibrations, so BBIC can route correct RF Tx path into the single ORx input */ 1506 } mykonosArmGpioConfig_t; 1507 1508 /** 1509 * \brief Data structure to hold auxiliary IO settings (AuxDAC, ARM GPIO, GPIO3.3v, low voltage GPIO, HSCP, etc) 1510 */ 1511 typedef struct 1512 { 1513 uint16_t auxDacEnable; /*!< Aux DAC enable. One bit per Aux DAC. Where bit[0] = Aux DAC 0, bit[1] = Aux DAC 1, etc */ 1514 uint16_t auxDacValue[10]; /*!< Aux DAC value */ 1515 uint8_t auxDacSlope[10]; /*!< Aux DAC slope */ 1516 uint8_t auxDacVref[10]; /*!< Aux DAC voltage reference value */ 1517 1518 mykonosGpio3v3_t *gpio3v3; /*!< GPIO 3.3 VDC settings data structure pointer */ 1519 mykonosGpioLowVoltage_t *gpio; /*!< Low voltage GPIO settings data structure pointer */ 1520 mykonosArmGpioConfig_t *armGpio; /*!< Mykonos ARM GPIO settings*/ 1521 } mykonosAuxIo_t; 1522 1523 /** 1524 * \brief Data structure to hold digital clock settings 1525 */ 1526 typedef struct 1527 { 1528 uint32_t deviceClock_kHz; /*!< CLKPLL and device reference clock frequency in kHz */ 1529 uint32_t clkPllVcoFreq_kHz; /*!< CLKPLL VCO frequency in kHz */ 1530 mykonosVcoDiv_t clkPllVcoDiv; /*!< CLKPLL VCO divider */ 1531 uint8_t clkPllHsDiv; /*!< CLKPLL high speed clock divider */ 1532 } mykonosDigClocks_t; 1533 1534 1535 /** 1536 * \brief Data structure used to read back the Init Calibration Status 1537 */ 1538 typedef struct 1539 { 1540 uint32_t calsDoneLastRun; /*!< Init cals that completed in the last call to MYKONOS_runInitCals() */ 1541 uint32_t calsDoneLifetime; /*!< Init cals that have completed successfully since loading of the ARM processor */ 1542 uint32_t calsMinimum; /*!< Minimum set of init cals that must complete before device can move to radioOn state */ 1543 uint8_t initErrCal; /*!< If an init cal had an error, this represents the opcode of the init cal that reported an error */ 1544 uint8_t initErrCode; /*!< If an init cal had an error, this represents the ARM error code describing the failure */ 1545 } mykonosInitCalStatus_t; 1546 1547 /** 1548 * \brief Data structure used to read back DPD calibration status 1549 */ 1550 typedef struct 1551 { 1552 /** 1553 * dpdErrorStatus (decimal) | Description 1554 * --------------------------|----------------------- 1555 * 0 | No Error 1556 * 1 | ORX_DISABLED 1557 * 2 | TX_DISABLED 1558 * 3 | PATHDELAY_NOT_SETUP 1559 * 4 | DPD_INIT_NOT_RUN 1560 * 5 | ORX_SIG_TOO_LOW 1561 * 6 | ORX_SIG_SATURATED 1562 * 7 | TX_SIG_TOO_LOW 1563 * 8 | TX_SIG_SATURATED 1564 * 9 | MODEL_ERROR_HIGH 1565 * 10 | AM_AM_OUTLIERS 1566 * 11 | INVALID_TX_PROFILE 1567 * 12 | ORX_TRACKING_DISABLED ORx tracking must be enabled 1568 * 13 | Cal suspended 1569 * 14 | Reserved 1570 * 15 | Reserved 1571 * 16 | Reserved 1572 * 17 | Reserved 1573 * 18 | Reserved 1574 */ 1575 uint32_t dpdErrorStatus; 1576 uint32_t dpdTrackCount; /*!< Number of times DPD tracking has run since last reset */ 1577 uint32_t dpdModelErrorPercent; /*!< Percent Error of PA model * 10 to include 1 decimal place */ 1578 uint32_t dpdExtPathDelay; /*!< External path delay from Tx output to ORx input, at 1/16 sample resolution of ORx sample rate */ 1579 uint16_t dpdMaxAdaptationCurrent; /*!< max amplitude of current adaptation */ 1580 uint16_t dpdMaxAdaptation; /*!< max amplitude of adaptation since DPD started*/ 1581 uint32_t dpdIterCount; /*!< number of times DPD tracking has run since last reset*/ 1582 } mykonosDpdStatus_t; 1583 1584 /** 1585 * \brief Data structure used to read back CLGC calibration status 1586 */ 1587 typedef struct 1588 { 1589 /** 1590 * clgcErrorStatus(decimal) | Description 1591 * -------------------------|----------------------- 1592 * 0 | NO ERROR 1593 * 1 | TX Disabled 1594 * 2 | ORx is disabled 1595 * 3 | Loopback switch is clo 1596 * 4 | Data measurement aborted during capture 1597 * 5 | No initial calibration was done 1598 * 6 | Path delay not setup 1599 * 7 | No apply control is possible 1600 * 8 | Control value is out of range 1601 * 9 | CLGC feature is disabled 1602 * 10 | TX attenuation is capped 1603 * 11 | Gain measurement 1604 * 12 | No GPIO configured in single ORx configuration 1605 * 13 | Tx is not observable with any of the ORx Channels 1606 * 14 | ORX_TRACKING_DISABLED ORx tracking must be enabled 1607 * 15 | PA Protection Activated 1608 * 16 | Relative Threshold Violated 1609 * 17 | RESERVED 1610 * 18 | RESERVED 1611 * 19 | RESERVED 1612 */ 1613 uint32_t errorStatus; 1614 uint32_t trackCount; /*!< Number of times CLGC tracking has run since last reset */ 1615 int32_t desiredGain; /*!< Desired gain/attenuation from Tx output to ORx input of Mykonos device. 0.01 dB resolution */ 1616 int32_t currentGain; /*!< Current measured gain in 0.01 dB resolution. */ 1617 uint32_t txGain; /*!< Current TxAttenuation setting, same as MYKONOS_getTx1/2Attenuation(), in 0.05dB resolution */ 1618 int32_t txRms; /*!< Tx digital sample power measured at DPD block input (0.01 dB resolution) */ 1619 int32_t orxRms; /*!< ORx digital sample power measured at ORx port (0.01 dB resolution) */ 1620 } mykonosClgcStatus_t; 1621 1622 /** 1623 * \brief Data structure to hold Tx LOL Status 1624 */ 1625 typedef struct 1626 { 1627 uint32_t errorCode; /*!< error code from Tx LOL */ 1628 uint32_t percentComplete; /*!< percent of required data collected for the current cal. Range 0 to 100 */ 1629 uint32_t performanceMetric; /*!< Variance of the corrections, and gives an indication in dB on how much LO leakage is corrected on an average tracking pass. */ 1630 uint32_t iterCount; /*!< running counter that increments each time the cal runs to completion */ 1631 uint32_t updateCount; /*!< running counter that increments each time the cal updates the correction/actuator hardware */ 1632 } mykonosTxLolStatus_t; 1633 1634 /** 1635 * \brief This structure contains the internal path delay 1636 * 1637 */ 1638 typedef struct 1639 { 1640 uint32_t forwardPathDelayCh1; /*!< Forward path delay for Channel 1 valid range is from 0 to 4095 at 1/16 sample resolution of ORx sample rate */ 1641 uint32_t reversePathDelayCh1; /*!< Reverse path delay for Channel 1 valid range is from 0 to 4095 at 1/16 sample resolution of ORx sample rate */ 1642 uint32_t forwardPathDelayCh2; /*!< Forward path delay for Channel 2 valid range is from 0 to 4095 at 1/16 sample resolution of ORx sample rate */ 1643 uint32_t reversePathDelayCh2; /*!< Reverse path delay for Channel 2 valid range is from 0 to 4095 at 1/16 sample resolution of ORx sample rate */ 1644 } mykonosPathdelay_t; 1645 1646 /** 1647 * \brief This structure contains the DPD error status counters for the different errors 1648 * 1649 */ 1650 typedef struct 1651 { 1652 uint32_t dpdErrorCount; /*!< DPD total error count */ 1653 uint32_t errorCounter[MYK_DPD_ERROR_END]; /*!< array for individual error counters corresponding to ::mykonosDpdErrors_t */ 1654 } mykonosDpdErrorCounters_t; 1655 1656 /** 1657 * \brief Data structure to hold Tx QEC Status 1658 */ 1659 typedef struct 1660 { 1661 uint32_t errorCode; /*!< error code from Tx QEC */ 1662 uint32_t percentComplete; /*!< percent of required data collected for the current cal. Range 0 to 100 */ 1663 uint32_t performanceMetric; /*!< Number of codes adjusted which is the number of codes of correction made last time which can be converted to an IRR power metric as with Rx QEC, if desired. */ 1664 uint32_t iterCount; /*!< running counter that increments each time the cal runs to completion */ 1665 uint32_t updateCount; /*!< running counter that increments each time the cal updates the correction/actuator hardware */ 1666 } mykonosTxQecStatus_t; 1667 1668 /** 1669 * \brief Data structure to hold Rx QEC Status 1670 */ 1671 typedef struct 1672 { 1673 uint32_t errorCode; /*!< error code from Rx QEC */ 1674 uint32_t percentComplete; /*!< percent of required data collected for the current cal. Range 0 to 100 */ 1675 uint32_t selfcheckIrrDb; /*!< selfCheckIrrdDb - Power-weighted average Image Rejection Ratio (IRR) in dBc. */ 1676 uint32_t iterCount; /*!< running counter that increments each time the cal runs to completion */ 1677 uint32_t updateCount; /*!< running counter that increments each time the cal updates the correction/actuator hardware */ 1678 } mykonosRxQecStatus_t; 1679 1680 /** 1681 * \brief Data structure to hold Orx QEC Status 1682 */ 1683 typedef struct 1684 { 1685 uint32_t errorCode; /*!< error code from Orx QEC */ 1686 uint32_t percentComplete; /*!< percent of required data collected for the current cal. Range 0 to 100 */ 1687 uint32_t selfcheckIrrDb; /*!< selfCheckIrrdDb - Power-weighted average Image Rejection Ratio (IRR) in dBc. */ 1688 uint32_t iterCount; /*!< running counter that increments each time the cal runs to completion */ 1689 uint32_t updateCount; /*!< running counter that increments each time the cal updates the correction/actuator hardware */ 1690 } mykonosOrxQecStatus_t; 1691 1692 /** 1693 * \brief Data structure to hold Mykonos device settings 1694 */ 1695 typedef struct 1696 { 1697 spiSettings_t *spiSettings; /*!< SPI settings data structure pointer */ 1698 mykonosRxSettings_t *rx; /*!< Rx settings data structure pointer */ 1699 mykonosTxSettings_t *tx; /*!< Tx settings data structure pointer */ 1700 mykonosObsRxSettings_t *obsRx; /*!< ObsRx settings data structure pointer */ 1701 mykonosAuxIo_t *auxIo; /*!< Auxiliary IO settings data structure pointer */ 1702 mykonosDigClocks_t *clocks; /*!< Holds settings for CLKPLL and reference clock */ 1703 uint8_t profilesValid; /*!< Mykonos initialize function uses this as an output to remember which profile data structure pointers are valid */ 1704 } mykonosDevice_t; 1705 1706 #ifdef __cplusplus 1707 } 1708 #endif 1709 1710 #endif 1711