1 /* Target-dependent code for the IA-64 for GDB, the GNU debugger.
2
3 Copyright 1999, 2000, 2001, 2002, 2003, 2004 Free Software
4 Foundation, Inc.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
22
23 #include "defs.h"
24 #include "inferior.h"
25 #include "gdbcore.h"
26 #include "arch-utils.h"
27 #include "floatformat.h"
28 #include "regcache.h"
29 #include "reggroups.h"
30 #include "frame.h"
31 #include "frame-base.h"
32 #include "frame-unwind.h"
33 #include "doublest.h"
34 #include "value.h"
35 #include "gdb_assert.h"
36 #include "objfiles.h"
37 #include "elf/common.h" /* for DT_PLTGOT value */
38 #include "elf-bfd.h"
39 #include "dis-asm.h"
40 #include "infcall.h"
41 #include "ia64-tdep.h"
42
43 #ifdef HAVE_LIBUNWIND_IA64_H
44 #include "elf/ia64.h" /* for PT_IA_64_UNWIND value */
45 #include "libunwind-frame.h"
46 #include "libunwind-ia64.h"
47 #endif
48
49 /* Hook for determining the global pointer when calling functions in
50 the inferior under AIX. The initialization code in ia64-aix-nat.c
51 sets this hook to the address of a function which will find the
52 global pointer for a given address.
53
54 The generic code which uses the dynamic section in the inferior for
55 finding the global pointer is not of much use on AIX since the
56 values obtained from the inferior have not been relocated. */
57
58 CORE_ADDR (*native_find_global_pointer) (CORE_ADDR) = 0;
59
60 /* An enumeration of the different IA-64 instruction types. */
61
62 typedef enum instruction_type
63 {
64 A, /* Integer ALU ; I-unit or M-unit */
65 I, /* Non-ALU integer; I-unit */
66 M, /* Memory ; M-unit */
67 F, /* Floating-point ; F-unit */
68 B, /* Branch ; B-unit */
69 L, /* Extended (L+X) ; I-unit */
70 X, /* Extended (L+X) ; I-unit */
71 undefined /* undefined or reserved */
72 } instruction_type;
73
74 /* We represent IA-64 PC addresses as the value of the instruction
75 pointer or'd with some bit combination in the low nibble which
76 represents the slot number in the bundle addressed by the
77 instruction pointer. The problem is that the Linux kernel
78 multiplies its slot numbers (for exceptions) by one while the
79 disassembler multiplies its slot numbers by 6. In addition, I've
80 heard it said that the simulator uses 1 as the multiplier.
81
82 I've fixed the disassembler so that the bytes_per_line field will
83 be the slot multiplier. If bytes_per_line comes in as zero, it
84 is set to six (which is how it was set up initially). -- objdump
85 displays pretty disassembly dumps with this value. For our purposes,
86 we'll set bytes_per_line to SLOT_MULTIPLIER. This is okay since we
87 never want to also display the raw bytes the way objdump does. */
88
89 #define SLOT_MULTIPLIER 1
90
91 /* Length in bytes of an instruction bundle */
92
93 #define BUNDLE_LEN 16
94
95 static gdbarch_init_ftype ia64_gdbarch_init;
96
97 static gdbarch_register_name_ftype ia64_register_name;
98 static gdbarch_register_type_ftype ia64_register_type;
99 static gdbarch_breakpoint_from_pc_ftype ia64_breakpoint_from_pc;
100 static gdbarch_skip_prologue_ftype ia64_skip_prologue;
101 static gdbarch_extract_return_value_ftype ia64_extract_return_value;
102 static struct type *is_float_or_hfa_type (struct type *t);
103
104 static struct type *builtin_type_ia64_ext;
105
106 #define NUM_IA64_RAW_REGS 462
107
108 static int sp_regnum = IA64_GR12_REGNUM;
109 static int fp_regnum = IA64_VFP_REGNUM;
110 static int lr_regnum = IA64_VRAP_REGNUM;
111
112 /* NOTE: we treat the register stack registers r32-r127 as pseudo-registers because
113 they may not be accessible via the ptrace register get/set interfaces. */
114 enum pseudo_regs { FIRST_PSEUDO_REGNUM = NUM_IA64_RAW_REGS, VBOF_REGNUM = IA64_NAT127_REGNUM + 1, V32_REGNUM,
115 V127_REGNUM = V32_REGNUM + 95,
116 VP0_REGNUM, VP16_REGNUM = VP0_REGNUM + 16, VP63_REGNUM = VP0_REGNUM + 63, LAST_PSEUDO_REGNUM };
117
118 /* Array of register names; There should be ia64_num_regs strings in
119 the initializer. */
120
121 static char *ia64_register_names[] =
122 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
123 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
124 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
125 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
126 "", "", "", "", "", "", "", "",
127 "", "", "", "", "", "", "", "",
128 "", "", "", "", "", "", "", "",
129 "", "", "", "", "", "", "", "",
130 "", "", "", "", "", "", "", "",
131 "", "", "", "", "", "", "", "",
132 "", "", "", "", "", "", "", "",
133 "", "", "", "", "", "", "", "",
134 "", "", "", "", "", "", "", "",
135 "", "", "", "", "", "", "", "",
136 "", "", "", "", "", "", "", "",
137 "", "", "", "", "", "", "", "",
138
139 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
140 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
141 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
142 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
143 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
144 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
145 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
146 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
147 "f64", "f65", "f66", "f67", "f68", "f69", "f70", "f71",
148 "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
149 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87",
150 "f88", "f89", "f90", "f91", "f92", "f93", "f94", "f95",
151 "f96", "f97", "f98", "f99", "f100", "f101", "f102", "f103",
152 "f104", "f105", "f106", "f107", "f108", "f109", "f110", "f111",
153 "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
154 "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127",
155
156 "", "", "", "", "", "", "", "",
157 "", "", "", "", "", "", "", "",
158 "", "", "", "", "", "", "", "",
159 "", "", "", "", "", "", "", "",
160 "", "", "", "", "", "", "", "",
161 "", "", "", "", "", "", "", "",
162 "", "", "", "", "", "", "", "",
163 "", "", "", "", "", "", "", "",
164
165 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
166
167 "vfp", "vrap",
168
169 "pr", "ip", "psr", "cfm",
170
171 "kr0", "kr1", "kr2", "kr3", "kr4", "kr5", "kr6", "kr7",
172 "", "", "", "", "", "", "", "",
173 "rsc", "bsp", "bspstore", "rnat",
174 "", "fcr", "", "",
175 "eflag", "csd", "ssd", "cflg", "fsr", "fir", "fdr", "",
176 "ccv", "", "", "", "unat", "", "", "",
177 "fpsr", "", "", "", "itc",
178 "", "", "", "", "", "", "", "", "", "",
179 "", "", "", "", "", "", "", "", "",
180 "pfs", "lc", "ec",
181 "", "", "", "", "", "", "", "", "", "",
182 "", "", "", "", "", "", "", "", "", "",
183 "", "", "", "", "", "", "", "", "", "",
184 "", "", "", "", "", "", "", "", "", "",
185 "", "", "", "", "", "", "", "", "", "",
186 "", "", "", "", "", "", "", "", "", "",
187 "",
188 "nat0", "nat1", "nat2", "nat3", "nat4", "nat5", "nat6", "nat7",
189 "nat8", "nat9", "nat10", "nat11", "nat12", "nat13", "nat14", "nat15",
190 "nat16", "nat17", "nat18", "nat19", "nat20", "nat21", "nat22", "nat23",
191 "nat24", "nat25", "nat26", "nat27", "nat28", "nat29", "nat30", "nat31",
192 "nat32", "nat33", "nat34", "nat35", "nat36", "nat37", "nat38", "nat39",
193 "nat40", "nat41", "nat42", "nat43", "nat44", "nat45", "nat46", "nat47",
194 "nat48", "nat49", "nat50", "nat51", "nat52", "nat53", "nat54", "nat55",
195 "nat56", "nat57", "nat58", "nat59", "nat60", "nat61", "nat62", "nat63",
196 "nat64", "nat65", "nat66", "nat67", "nat68", "nat69", "nat70", "nat71",
197 "nat72", "nat73", "nat74", "nat75", "nat76", "nat77", "nat78", "nat79",
198 "nat80", "nat81", "nat82", "nat83", "nat84", "nat85", "nat86", "nat87",
199 "nat88", "nat89", "nat90", "nat91", "nat92", "nat93", "nat94", "nat95",
200 "nat96", "nat97", "nat98", "nat99", "nat100","nat101","nat102","nat103",
201 "nat104","nat105","nat106","nat107","nat108","nat109","nat110","nat111",
202 "nat112","nat113","nat114","nat115","nat116","nat117","nat118","nat119",
203 "nat120","nat121","nat122","nat123","nat124","nat125","nat126","nat127",
204
205 "bof",
206
207 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
208 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
209 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
210 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
211 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
212 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
213 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
214 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
215 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
216 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
217 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
218 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
219
220 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7",
221 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15",
222 "p16", "p17", "p18", "p19", "p20", "p21", "p22", "p23",
223 "p24", "p25", "p26", "p27", "p28", "p29", "p30", "p31",
224 "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39",
225 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47",
226 "p48", "p49", "p50", "p51", "p52", "p53", "p54", "p55",
227 "p56", "p57", "p58", "p59", "p60", "p61", "p62", "p63",
228 };
229
230 struct ia64_frame_cache
231 {
232 CORE_ADDR base; /* frame pointer base for frame */
233 CORE_ADDR pc; /* function start pc for frame */
234 CORE_ADDR saved_sp; /* stack pointer for frame */
235 CORE_ADDR bsp; /* points at r32 for the current frame */
236 CORE_ADDR cfm; /* cfm value for current frame */
237 CORE_ADDR prev_cfm; /* cfm value for previous frame */
238 int frameless;
239 int sof; /* Size of frame (decoded from cfm value) */
240 int sol; /* Size of locals (decoded from cfm value) */
241 int sor; /* Number of rotating registers. (decoded from cfm value) */
242 CORE_ADDR after_prologue;
243 /* Address of first instruction after the last
244 prologue instruction; Note that there may
245 be instructions from the function's body
246 intermingled with the prologue. */
247 int mem_stack_frame_size;
248 /* Size of the memory stack frame (may be zero),
249 or -1 if it has not been determined yet. */
250 int fp_reg; /* Register number (if any) used a frame pointer
251 for this frame. 0 if no register is being used
252 as the frame pointer. */
253
254 /* Saved registers. */
255 CORE_ADDR saved_regs[NUM_IA64_RAW_REGS];
256
257 };
258
259 struct gdbarch_tdep
260 {
261 CORE_ADDR (*sigcontext_register_address) (CORE_ADDR, int);
262 /* OS specific function which, given a frame address
263 and register number, returns the offset to the
264 given register from the start of the frame. */
265 CORE_ADDR (*find_global_pointer) (CORE_ADDR);
266 };
267
268 #define SIGCONTEXT_REGISTER_ADDRESS \
269 (gdbarch_tdep (current_gdbarch)->sigcontext_register_address)
270 #define FIND_GLOBAL_POINTER \
271 (gdbarch_tdep (current_gdbarch)->find_global_pointer)
272
273 int
ia64_register_reggroup_p(struct gdbarch * gdbarch,int regnum,struct reggroup * group)274 ia64_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
275 struct reggroup *group)
276 {
277 int vector_p;
278 int float_p;
279 int raw_p;
280 if (group == all_reggroup)
281 return 1;
282 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
283 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
284 raw_p = regnum < NUM_IA64_RAW_REGS;
285 if (group == float_reggroup)
286 return float_p;
287 if (group == vector_reggroup)
288 return vector_p;
289 if (group == general_reggroup)
290 return (!vector_p && !float_p);
291 if (group == save_reggroup || group == restore_reggroup)
292 return raw_p;
293 return 0;
294 }
295
296 static const char *
ia64_register_name(int reg)297 ia64_register_name (int reg)
298 {
299 return ia64_register_names[reg];
300 }
301
302 struct type *
ia64_register_type(struct gdbarch * arch,int reg)303 ia64_register_type (struct gdbarch *arch, int reg)
304 {
305 if (reg >= IA64_FR0_REGNUM && reg <= IA64_FR127_REGNUM)
306 return builtin_type_ia64_ext;
307 else
308 return builtin_type_long;
309 }
310
311 static int
ia64_dwarf_reg_to_regnum(int reg)312 ia64_dwarf_reg_to_regnum (int reg)
313 {
314 if (reg >= IA64_GR32_REGNUM && reg <= IA64_GR127_REGNUM)
315 return V32_REGNUM + (reg - IA64_GR32_REGNUM);
316 return reg;
317 }
318
319 static int
floatformat_valid(const struct floatformat * fmt,const char * from)320 floatformat_valid (const struct floatformat *fmt, const char *from)
321 {
322 return 1;
323 }
324
325 const struct floatformat floatformat_ia64_ext =
326 {
327 floatformat_little, 82, 0, 1, 17, 65535, 0x1ffff, 18, 64,
328 floatformat_intbit_yes, "floatformat_ia64_ext", floatformat_valid
329 };
330
331
332 /* Extract ``len'' bits from an instruction bundle starting at
333 bit ``from''. */
334
335 static long long
extract_bit_field(char * bundle,int from,int len)336 extract_bit_field (char *bundle, int from, int len)
337 {
338 long long result = 0LL;
339 int to = from + len;
340 int from_byte = from / 8;
341 int to_byte = to / 8;
342 unsigned char *b = (unsigned char *) bundle;
343 unsigned char c;
344 int lshift;
345 int i;
346
347 c = b[from_byte];
348 if (from_byte == to_byte)
349 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
350 result = c >> (from % 8);
351 lshift = 8 - (from % 8);
352
353 for (i = from_byte+1; i < to_byte; i++)
354 {
355 result |= ((long long) b[i]) << lshift;
356 lshift += 8;
357 }
358
359 if (from_byte < to_byte && (to % 8 != 0))
360 {
361 c = b[to_byte];
362 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
363 result |= ((long long) c) << lshift;
364 }
365
366 return result;
367 }
368
369 /* Replace the specified bits in an instruction bundle */
370
371 static void
replace_bit_field(char * bundle,long long val,int from,int len)372 replace_bit_field (char *bundle, long long val, int from, int len)
373 {
374 int to = from + len;
375 int from_byte = from / 8;
376 int to_byte = to / 8;
377 unsigned char *b = (unsigned char *) bundle;
378 unsigned char c;
379
380 if (from_byte == to_byte)
381 {
382 unsigned char left, right;
383 c = b[from_byte];
384 left = (c >> (to % 8)) << (to % 8);
385 right = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
386 c = (unsigned char) (val & 0xff);
387 c = (unsigned char) (c << (from % 8 + 8 - to % 8)) >> (8 - to % 8);
388 c |= right | left;
389 b[from_byte] = c;
390 }
391 else
392 {
393 int i;
394 c = b[from_byte];
395 c = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
396 c = c | (val << (from % 8));
397 b[from_byte] = c;
398 val >>= 8 - from % 8;
399
400 for (i = from_byte+1; i < to_byte; i++)
401 {
402 c = val & 0xff;
403 val >>= 8;
404 b[i] = c;
405 }
406
407 if (to % 8 != 0)
408 {
409 unsigned char cv = (unsigned char) val;
410 c = b[to_byte];
411 c = c >> (to % 8) << (to % 8);
412 c |= ((unsigned char) (cv << (8 - to % 8))) >> (8 - to % 8);
413 b[to_byte] = c;
414 }
415 }
416 }
417
418 /* Return the contents of slot N (for N = 0, 1, or 2) in
419 and instruction bundle */
420
421 static long long
slotN_contents(char * bundle,int slotnum)422 slotN_contents (char *bundle, int slotnum)
423 {
424 return extract_bit_field (bundle, 5+41*slotnum, 41);
425 }
426
427 /* Store an instruction in an instruction bundle */
428
429 static void
replace_slotN_contents(char * bundle,long long instr,int slotnum)430 replace_slotN_contents (char *bundle, long long instr, int slotnum)
431 {
432 replace_bit_field (bundle, instr, 5+41*slotnum, 41);
433 }
434
435 static enum instruction_type template_encoding_table[32][3] =
436 {
437 { M, I, I }, /* 00 */
438 { M, I, I }, /* 01 */
439 { M, I, I }, /* 02 */
440 { M, I, I }, /* 03 */
441 { M, L, X }, /* 04 */
442 { M, L, X }, /* 05 */
443 { undefined, undefined, undefined }, /* 06 */
444 { undefined, undefined, undefined }, /* 07 */
445 { M, M, I }, /* 08 */
446 { M, M, I }, /* 09 */
447 { M, M, I }, /* 0A */
448 { M, M, I }, /* 0B */
449 { M, F, I }, /* 0C */
450 { M, F, I }, /* 0D */
451 { M, M, F }, /* 0E */
452 { M, M, F }, /* 0F */
453 { M, I, B }, /* 10 */
454 { M, I, B }, /* 11 */
455 { M, B, B }, /* 12 */
456 { M, B, B }, /* 13 */
457 { undefined, undefined, undefined }, /* 14 */
458 { undefined, undefined, undefined }, /* 15 */
459 { B, B, B }, /* 16 */
460 { B, B, B }, /* 17 */
461 { M, M, B }, /* 18 */
462 { M, M, B }, /* 19 */
463 { undefined, undefined, undefined }, /* 1A */
464 { undefined, undefined, undefined }, /* 1B */
465 { M, F, B }, /* 1C */
466 { M, F, B }, /* 1D */
467 { undefined, undefined, undefined }, /* 1E */
468 { undefined, undefined, undefined }, /* 1F */
469 };
470
471 /* Fetch and (partially) decode an instruction at ADDR and return the
472 address of the next instruction to fetch. */
473
474 static CORE_ADDR
fetch_instruction(CORE_ADDR addr,instruction_type * it,long long * instr)475 fetch_instruction (CORE_ADDR addr, instruction_type *it, long long *instr)
476 {
477 char bundle[BUNDLE_LEN];
478 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
479 long long template;
480 int val;
481
482 /* Warn about slot numbers greater than 2. We used to generate
483 an error here on the assumption that the user entered an invalid
484 address. But, sometimes GDB itself requests an invalid address.
485 This can (easily) happen when execution stops in a function for
486 which there are no symbols. The prologue scanner will attempt to
487 find the beginning of the function - if the nearest symbol
488 happens to not be aligned on a bundle boundary (16 bytes), the
489 resulting starting address will cause GDB to think that the slot
490 number is too large.
491
492 So we warn about it and set the slot number to zero. It is
493 not necessarily a fatal condition, particularly if debugging
494 at the assembly language level. */
495 if (slotnum > 2)
496 {
497 warning ("Can't fetch instructions for slot numbers greater than 2.\n"
498 "Using slot 0 instead");
499 slotnum = 0;
500 }
501
502 addr &= ~0x0f;
503
504 val = target_read_memory (addr, bundle, BUNDLE_LEN);
505
506 if (val != 0)
507 return 0;
508
509 *instr = slotN_contents (bundle, slotnum);
510 template = extract_bit_field (bundle, 0, 5);
511 *it = template_encoding_table[(int)template][slotnum];
512
513 if (slotnum == 2 || (slotnum == 1 && *it == L))
514 addr += 16;
515 else
516 addr += (slotnum + 1) * SLOT_MULTIPLIER;
517
518 return addr;
519 }
520
521 /* There are 5 different break instructions (break.i, break.b,
522 break.m, break.f, and break.x), but they all have the same
523 encoding. (The five bit template in the low five bits of the
524 instruction bundle distinguishes one from another.)
525
526 The runtime architecture manual specifies that break instructions
527 used for debugging purposes must have the upper two bits of the 21
528 bit immediate set to a 0 and a 1 respectively. A breakpoint
529 instruction encodes the most significant bit of its 21 bit
530 immediate at bit 36 of the 41 bit instruction. The penultimate msb
531 is at bit 25 which leads to the pattern below.
532
533 Originally, I had this set up to do, e.g, a "break.i 0x80000" But
534 it turns out that 0x80000 was used as the syscall break in the early
535 simulators. So I changed the pattern slightly to do "break.i 0x080001"
536 instead. But that didn't work either (I later found out that this
537 pattern was used by the simulator that I was using.) So I ended up
538 using the pattern seen below. */
539
540 #if 0
541 #define IA64_BREAKPOINT 0x00002000040LL
542 #endif
543 #define IA64_BREAKPOINT 0x00003333300LL
544
545 static int
ia64_memory_insert_breakpoint(CORE_ADDR addr,char * contents_cache)546 ia64_memory_insert_breakpoint (CORE_ADDR addr, char *contents_cache)
547 {
548 char bundle[BUNDLE_LEN];
549 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
550 long long instr;
551 int val;
552 int template;
553
554 if (slotnum > 2)
555 error("Can't insert breakpoint for slot numbers greater than 2.");
556
557 addr &= ~0x0f;
558
559 val = target_read_memory (addr, bundle, BUNDLE_LEN);
560
561 /* Check for L type instruction in 2nd slot, if present then
562 bump up the slot number to the 3rd slot */
563 template = extract_bit_field (bundle, 0, 5);
564 if (slotnum == 1 && template_encoding_table[template][1] == L)
565 {
566 slotnum = 2;
567 }
568
569 instr = slotN_contents (bundle, slotnum);
570 memcpy(contents_cache, &instr, sizeof(instr));
571 replace_slotN_contents (bundle, IA64_BREAKPOINT, slotnum);
572 if (val == 0)
573 target_write_memory (addr, bundle, BUNDLE_LEN);
574
575 return val;
576 }
577
578 static int
ia64_memory_remove_breakpoint(CORE_ADDR addr,char * contents_cache)579 ia64_memory_remove_breakpoint (CORE_ADDR addr, char *contents_cache)
580 {
581 char bundle[BUNDLE_LEN];
582 int slotnum = (addr & 0x0f) / SLOT_MULTIPLIER;
583 long long instr;
584 int val;
585 int template;
586
587 addr &= ~0x0f;
588
589 val = target_read_memory (addr, bundle, BUNDLE_LEN);
590
591 /* Check for L type instruction in 2nd slot, if present then
592 bump up the slot number to the 3rd slot */
593 template = extract_bit_field (bundle, 0, 5);
594 if (slotnum == 1 && template_encoding_table[template][1] == L)
595 {
596 slotnum = 2;
597 }
598
599 memcpy (&instr, contents_cache, sizeof instr);
600 replace_slotN_contents (bundle, instr, slotnum);
601 if (val == 0)
602 target_write_memory (addr, bundle, BUNDLE_LEN);
603
604 return val;
605 }
606
607 /* We don't really want to use this, but remote.c needs to call it in order
608 to figure out if Z-packets are supported or not. Oh, well. */
609 const unsigned char *
ia64_breakpoint_from_pc(CORE_ADDR * pcptr,int * lenptr)610 ia64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
611 {
612 static unsigned char breakpoint[] =
613 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
614 *lenptr = sizeof (breakpoint);
615 #if 0
616 *pcptr &= ~0x0f;
617 #endif
618 return breakpoint;
619 }
620
621 static CORE_ADDR
ia64_read_pc(ptid_t ptid)622 ia64_read_pc (ptid_t ptid)
623 {
624 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
625 CORE_ADDR pc_value = read_register_pid (IA64_IP_REGNUM, ptid);
626 int slot_num = (psr_value >> 41) & 3;
627
628 return pc_value | (slot_num * SLOT_MULTIPLIER);
629 }
630
631 void
ia64_write_pc(CORE_ADDR new_pc,ptid_t ptid)632 ia64_write_pc (CORE_ADDR new_pc, ptid_t ptid)
633 {
634 int slot_num = (int) (new_pc & 0xf) / SLOT_MULTIPLIER;
635 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
636 psr_value &= ~(3LL << 41);
637 psr_value |= (CORE_ADDR)(slot_num & 0x3) << 41;
638
639 new_pc &= ~0xfLL;
640
641 write_register_pid (IA64_PSR_REGNUM, psr_value, ptid);
642 write_register_pid (IA64_IP_REGNUM, new_pc, ptid);
643 }
644
645 #define IS_NaT_COLLECTION_ADDR(addr) ((((addr) >> 3) & 0x3f) == 0x3f)
646
647 /* Returns the address of the slot that's NSLOTS slots away from
648 the address ADDR. NSLOTS may be positive or negative. */
649 static CORE_ADDR
rse_address_add(CORE_ADDR addr,int nslots)650 rse_address_add(CORE_ADDR addr, int nslots)
651 {
652 CORE_ADDR new_addr;
653 int mandatory_nat_slots = nslots / 63;
654 int direction = nslots < 0 ? -1 : 1;
655
656 new_addr = addr + 8 * (nslots + mandatory_nat_slots);
657
658 if ((new_addr >> 9) != ((addr + 8 * 64 * mandatory_nat_slots) >> 9))
659 new_addr += 8 * direction;
660
661 if (IS_NaT_COLLECTION_ADDR(new_addr))
662 new_addr += 8 * direction;
663
664 return new_addr;
665 }
666
667 static void
ia64_pseudo_register_read(struct gdbarch * gdbarch,struct regcache * regcache,int regnum,void * buf)668 ia64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
669 int regnum, void *buf)
670 {
671 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
672 {
673 ULONGEST bsp;
674 ULONGEST cfm;
675 CORE_ADDR reg;
676 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
677 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
678
679 /* The bsp points at the end of the register frame so we
680 subtract the size of frame from it to get start of register frame. */
681 bsp = rse_address_add (bsp, -(cfm & 0x7f));
682
683 if ((cfm & 0x7f) > regnum - V32_REGNUM)
684 {
685 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
686 reg = read_memory_integer ((CORE_ADDR)reg_addr, 8);
687 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), reg);
688 }
689 else
690 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), 0);
691 }
692 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
693 {
694 ULONGEST unatN_val;
695 ULONGEST unat;
696 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
697 unatN_val = (unat & (1LL << (regnum - IA64_NAT0_REGNUM))) != 0;
698 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), unatN_val);
699 }
700 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
701 {
702 ULONGEST natN_val = 0;
703 ULONGEST bsp;
704 ULONGEST cfm;
705 CORE_ADDR gr_addr = 0;
706 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
707 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
708
709 /* The bsp points at the end of the register frame so we
710 subtract the size of frame from it to get start of register frame. */
711 bsp = rse_address_add (bsp, -(cfm & 0x7f));
712
713 if ((cfm & 0x7f) > regnum - V32_REGNUM)
714 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
715
716 if (gr_addr != 0)
717 {
718 /* Compute address of nat collection bits. */
719 CORE_ADDR nat_addr = gr_addr | 0x1f8;
720 CORE_ADDR nat_collection;
721 int nat_bit;
722 /* If our nat collection address is bigger than bsp, we have to get
723 the nat collection from rnat. Otherwise, we fetch the nat
724 collection from the computed address. */
725 if (nat_addr >= bsp)
726 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
727 else
728 nat_collection = read_memory_integer (nat_addr, 8);
729 nat_bit = (gr_addr >> 3) & 0x3f;
730 natN_val = (nat_collection >> nat_bit) & 1;
731 }
732
733 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), natN_val);
734 }
735 else if (regnum == VBOF_REGNUM)
736 {
737 /* A virtual register frame start is provided for user convenience.
738 It can be calculated as the bsp - sof (sizeof frame). */
739 ULONGEST bsp, vbsp;
740 ULONGEST cfm;
741 CORE_ADDR reg;
742 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
743 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
744
745 /* The bsp points at the end of the register frame so we
746 subtract the size of frame from it to get beginning of frame. */
747 vbsp = rse_address_add (bsp, -(cfm & 0x7f));
748 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), vbsp);
749 }
750 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
751 {
752 ULONGEST pr;
753 ULONGEST cfm;
754 ULONGEST prN_val;
755 CORE_ADDR reg;
756 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
757 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
758
759 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
760 {
761 /* Fetch predicate register rename base from current frame
762 marker for this frame. */
763 int rrb_pr = (cfm >> 32) & 0x3f;
764
765 /* Adjust the register number to account for register rotation. */
766 regnum = VP16_REGNUM
767 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
768 }
769 prN_val = (pr & (1LL << (regnum - VP0_REGNUM))) != 0;
770 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), prN_val);
771 }
772 else
773 memset (buf, 0, register_size (current_gdbarch, regnum));
774 }
775
776 static void
ia64_pseudo_register_write(struct gdbarch * gdbarch,struct regcache * regcache,int regnum,const void * buf)777 ia64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
778 int regnum, const void *buf)
779 {
780 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
781 {
782 ULONGEST bsp;
783 ULONGEST cfm;
784 CORE_ADDR reg;
785 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
786 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
787
788 bsp = rse_address_add (bsp, -(cfm & 0x7f));
789
790 if ((cfm & 0x7f) > regnum - V32_REGNUM)
791 {
792 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
793 write_memory (reg_addr, (void *)buf, 8);
794 }
795 }
796 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
797 {
798 ULONGEST unatN_val, unat, unatN_mask;
799 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
800 unatN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
801 unatN_mask = (1LL << (regnum - IA64_NAT0_REGNUM));
802 if (unatN_val == 0)
803 unat &= ~unatN_mask;
804 else if (unatN_val == 1)
805 unat |= unatN_mask;
806 regcache_cooked_write_unsigned (regcache, IA64_UNAT_REGNUM, unat);
807 }
808 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
809 {
810 ULONGEST natN_val;
811 ULONGEST bsp;
812 ULONGEST cfm;
813 CORE_ADDR gr_addr = 0;
814 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
815 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
816
817 /* The bsp points at the end of the register frame so we
818 subtract the size of frame from it to get start of register frame. */
819 bsp = rse_address_add (bsp, -(cfm & 0x7f));
820
821 if ((cfm & 0x7f) > regnum - V32_REGNUM)
822 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
823
824 natN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
825
826 if (gr_addr != 0 && (natN_val == 0 || natN_val == 1))
827 {
828 /* Compute address of nat collection bits. */
829 CORE_ADDR nat_addr = gr_addr | 0x1f8;
830 CORE_ADDR nat_collection;
831 int natN_bit = (gr_addr >> 3) & 0x3f;
832 ULONGEST natN_mask = (1LL << natN_bit);
833 /* If our nat collection address is bigger than bsp, we have to get
834 the nat collection from rnat. Otherwise, we fetch the nat
835 collection from the computed address. */
836 if (nat_addr >= bsp)
837 {
838 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
839 if (natN_val)
840 nat_collection |= natN_mask;
841 else
842 nat_collection &= ~natN_mask;
843 regcache_cooked_write_unsigned (regcache, IA64_RNAT_REGNUM, nat_collection);
844 }
845 else
846 {
847 char nat_buf[8];
848 nat_collection = read_memory_integer (nat_addr, 8);
849 if (natN_val)
850 nat_collection |= natN_mask;
851 else
852 nat_collection &= ~natN_mask;
853 store_unsigned_integer (nat_buf, register_size (current_gdbarch, regnum), nat_collection);
854 write_memory (nat_addr, nat_buf, 8);
855 }
856 }
857 }
858 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
859 {
860 ULONGEST pr;
861 ULONGEST cfm;
862 ULONGEST prN_val;
863 ULONGEST prN_mask;
864
865 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
866 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
867
868 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
869 {
870 /* Fetch predicate register rename base from current frame
871 marker for this frame. */
872 int rrb_pr = (cfm >> 32) & 0x3f;
873
874 /* Adjust the register number to account for register rotation. */
875 regnum = VP16_REGNUM
876 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
877 }
878 prN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
879 prN_mask = (1LL << (regnum - VP0_REGNUM));
880 if (prN_val == 0)
881 pr &= ~prN_mask;
882 else if (prN_val == 1)
883 pr |= prN_mask;
884 regcache_cooked_write_unsigned (regcache, IA64_PR_REGNUM, pr);
885 }
886 }
887
888 /* The ia64 needs to convert between various ieee floating-point formats
889 and the special ia64 floating point register format. */
890
891 static int
ia64_convert_register_p(int regno,struct type * type)892 ia64_convert_register_p (int regno, struct type *type)
893 {
894 return (regno >= IA64_FR0_REGNUM && regno <= IA64_FR127_REGNUM);
895 }
896
897 static void
ia64_register_to_value(struct frame_info * frame,int regnum,struct type * valtype,void * out)898 ia64_register_to_value (struct frame_info *frame, int regnum,
899 struct type *valtype, void *out)
900 {
901 char in[MAX_REGISTER_SIZE];
902 frame_register_read (frame, regnum, in);
903 convert_typed_floating (in, builtin_type_ia64_ext, out, valtype);
904 }
905
906 static void
ia64_value_to_register(struct frame_info * frame,int regnum,struct type * valtype,const void * in)907 ia64_value_to_register (struct frame_info *frame, int regnum,
908 struct type *valtype, const void *in)
909 {
910 char out[MAX_REGISTER_SIZE];
911 convert_typed_floating (in, valtype, out, builtin_type_ia64_ext);
912 put_frame_register (frame, regnum, out);
913 }
914
915
916 /* Limit the number of skipped non-prologue instructions since examining
917 of the prologue is expensive. */
918 static int max_skip_non_prologue_insns = 40;
919
920 /* Given PC representing the starting address of a function, and
921 LIM_PC which is the (sloppy) limit to which to scan when looking
922 for a prologue, attempt to further refine this limit by using
923 the line data in the symbol table. If successful, a better guess
924 on where the prologue ends is returned, otherwise the previous
925 value of lim_pc is returned. TRUST_LIMIT is a pointer to a flag
926 which will be set to indicate whether the returned limit may be
927 used with no further scanning in the event that the function is
928 frameless. */
929
930 /* FIXME: cagney/2004-02-14: This function and logic have largely been
931 superseded by skip_prologue_using_sal. */
932
933 static CORE_ADDR
refine_prologue_limit(CORE_ADDR pc,CORE_ADDR lim_pc,int * trust_limit)934 refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc, int *trust_limit)
935 {
936 struct symtab_and_line prologue_sal;
937 CORE_ADDR start_pc = pc;
938
939 /* Start off not trusting the limit. */
940 *trust_limit = 0;
941
942 prologue_sal = find_pc_line (pc, 0);
943 if (prologue_sal.line != 0)
944 {
945 int i;
946 CORE_ADDR addr = prologue_sal.end;
947
948 /* Handle the case in which compiler's optimizer/scheduler
949 has moved instructions into the prologue. We scan ahead
950 in the function looking for address ranges whose corresponding
951 line number is less than or equal to the first one that we
952 found for the function. (It can be less than when the
953 scheduler puts a body instruction before the first prologue
954 instruction.) */
955 for (i = 2 * max_skip_non_prologue_insns;
956 i > 0 && (lim_pc == 0 || addr < lim_pc);
957 i--)
958 {
959 struct symtab_and_line sal;
960
961 sal = find_pc_line (addr, 0);
962 if (sal.line == 0)
963 break;
964 if (sal.line <= prologue_sal.line
965 && sal.symtab == prologue_sal.symtab)
966 {
967 prologue_sal = sal;
968 }
969 addr = sal.end;
970 }
971
972 if (lim_pc == 0 || prologue_sal.end < lim_pc)
973 {
974 lim_pc = prologue_sal.end;
975 if (start_pc == get_pc_function_start (lim_pc))
976 *trust_limit = 1;
977 }
978 }
979 return lim_pc;
980 }
981
982 #define isScratch(_regnum_) ((_regnum_) == 2 || (_regnum_) == 3 \
983 || (8 <= (_regnum_) && (_regnum_) <= 11) \
984 || (14 <= (_regnum_) && (_regnum_) <= 31))
985 #define imm9(_instr_) \
986 ( ((((_instr_) & 0x01000000000LL) ? -1 : 0) << 8) \
987 | (((_instr_) & 0x00008000000LL) >> 20) \
988 | (((_instr_) & 0x00000001fc0LL) >> 6))
989
990 /* Allocate and initialize a frame cache. */
991
992 static struct ia64_frame_cache *
ia64_alloc_frame_cache(void)993 ia64_alloc_frame_cache (void)
994 {
995 struct ia64_frame_cache *cache;
996 int i;
997
998 cache = FRAME_OBSTACK_ZALLOC (struct ia64_frame_cache);
999
1000 /* Base address. */
1001 cache->base = 0;
1002 cache->pc = 0;
1003 cache->cfm = 0;
1004 cache->prev_cfm = 0;
1005 cache->sof = 0;
1006 cache->sol = 0;
1007 cache->sor = 0;
1008 cache->bsp = 0;
1009 cache->fp_reg = 0;
1010 cache->frameless = 1;
1011
1012 for (i = 0; i < NUM_IA64_RAW_REGS; i++)
1013 cache->saved_regs[i] = 0;
1014
1015 return cache;
1016 }
1017
1018 static CORE_ADDR
examine_prologue(CORE_ADDR pc,CORE_ADDR lim_pc,struct frame_info * next_frame,struct ia64_frame_cache * cache)1019 examine_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct frame_info *next_frame, struct ia64_frame_cache *cache)
1020 {
1021 CORE_ADDR next_pc;
1022 CORE_ADDR last_prologue_pc = pc;
1023 instruction_type it;
1024 long long instr;
1025 int cfm_reg = 0;
1026 int ret_reg = 0;
1027 int fp_reg = 0;
1028 int unat_save_reg = 0;
1029 int pr_save_reg = 0;
1030 int mem_stack_frame_size = 0;
1031 int spill_reg = 0;
1032 CORE_ADDR spill_addr = 0;
1033 char instores[8];
1034 char infpstores[8];
1035 char reg_contents[256];
1036 int trust_limit;
1037 int frameless = 1;
1038 int i;
1039 CORE_ADDR addr;
1040 char buf[8];
1041 CORE_ADDR bof, sor, sol, sof, cfm, rrb_gr;
1042
1043 memset (instores, 0, sizeof instores);
1044 memset (infpstores, 0, sizeof infpstores);
1045 memset (reg_contents, 0, sizeof reg_contents);
1046
1047 if (cache->after_prologue != 0
1048 && cache->after_prologue <= lim_pc)
1049 return cache->after_prologue;
1050
1051 lim_pc = refine_prologue_limit (pc, lim_pc, &trust_limit);
1052 next_pc = fetch_instruction (pc, &it, &instr);
1053
1054 /* We want to check if we have a recognizable function start before we
1055 look ahead for a prologue. */
1056 if (pc < lim_pc && next_pc
1057 && it == M && ((instr & 0x1ee0000003fLL) == 0x02c00000000LL))
1058 {
1059 /* alloc - start of a regular function. */
1060 int sor = (int) ((instr & 0x00078000000LL) >> 27);
1061 int sol = (int) ((instr & 0x00007f00000LL) >> 20);
1062 int sof = (int) ((instr & 0x000000fe000LL) >> 13);
1063 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1064
1065 /* Verify that the current cfm matches what we think is the
1066 function start. If we have somehow jumped within a function,
1067 we do not want to interpret the prologue and calculate the
1068 addresses of various registers such as the return address.
1069 We will instead treat the frame as frameless. */
1070 if (!next_frame ||
1071 (sof == (cache->cfm & 0x7f) &&
1072 sol == ((cache->cfm >> 7) & 0x7f)))
1073 frameless = 0;
1074
1075 cfm_reg = rN;
1076 last_prologue_pc = next_pc;
1077 pc = next_pc;
1078 }
1079 else
1080 {
1081 /* Look for a leaf routine. */
1082 if (pc < lim_pc && next_pc
1083 && (it == I || it == M)
1084 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1085 {
1086 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1087 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1088 | ((instr & 0x001f8000000LL) >> 20)
1089 | ((instr & 0x000000fe000LL) >> 13));
1090 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1091 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1092 int qp = (int) (instr & 0x0000000003fLL);
1093 if (qp == 0 && rN == 2 && imm == 0 && rM == 12 && fp_reg == 0)
1094 {
1095 /* mov r2, r12 - beginning of leaf routine */
1096 fp_reg = rN;
1097 last_prologue_pc = next_pc;
1098 }
1099 }
1100
1101 /* If we don't recognize a regular function or leaf routine, we are
1102 done. */
1103 if (!fp_reg)
1104 {
1105 pc = lim_pc;
1106 if (trust_limit)
1107 last_prologue_pc = lim_pc;
1108 }
1109 }
1110
1111 /* Loop, looking for prologue instructions, keeping track of
1112 where preserved registers were spilled. */
1113 while (pc < lim_pc)
1114 {
1115 next_pc = fetch_instruction (pc, &it, &instr);
1116 if (next_pc == 0)
1117 break;
1118
1119 if (it == B && ((instr & 0x1e1f800003fLL) != 0x04000000000LL))
1120 {
1121 /* Exit loop upon hitting a non-nop branch instruction. */
1122 if (trust_limit)
1123 lim_pc = pc;
1124 break;
1125 }
1126 else if (((instr & 0x3fLL) != 0LL) &&
1127 (frameless || ret_reg != 0))
1128 {
1129 /* Exit loop upon hitting a predicated instruction if
1130 we already have the return register or if we are frameless. */
1131 if (trust_limit)
1132 lim_pc = pc;
1133 break;
1134 }
1135 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00188000000LL))
1136 {
1137 /* Move from BR */
1138 int b2 = (int) ((instr & 0x0000000e000LL) >> 13);
1139 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1140 int qp = (int) (instr & 0x0000000003f);
1141
1142 if (qp == 0 && b2 == 0 && rN >= 32 && ret_reg == 0)
1143 {
1144 ret_reg = rN;
1145 last_prologue_pc = next_pc;
1146 }
1147 }
1148 else if ((it == I || it == M)
1149 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1150 {
1151 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1152 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1153 | ((instr & 0x001f8000000LL) >> 20)
1154 | ((instr & 0x000000fe000LL) >> 13));
1155 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1156 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1157 int qp = (int) (instr & 0x0000000003fLL);
1158
1159 if (qp == 0 && rN >= 32 && imm == 0 && rM == 12 && fp_reg == 0)
1160 {
1161 /* mov rN, r12 */
1162 fp_reg = rN;
1163 last_prologue_pc = next_pc;
1164 }
1165 else if (qp == 0 && rN == 12 && rM == 12)
1166 {
1167 /* adds r12, -mem_stack_frame_size, r12 */
1168 mem_stack_frame_size -= imm;
1169 last_prologue_pc = next_pc;
1170 }
1171 else if (qp == 0 && rN == 2
1172 && ((rM == fp_reg && fp_reg != 0) || rM == 12))
1173 {
1174 char buf[MAX_REGISTER_SIZE];
1175 CORE_ADDR saved_sp = 0;
1176 /* adds r2, spilloffset, rFramePointer
1177 or
1178 adds r2, spilloffset, r12
1179
1180 Get ready for stf.spill or st8.spill instructions.
1181 The address to start spilling at is loaded into r2.
1182 FIXME: Why r2? That's what gcc currently uses; it
1183 could well be different for other compilers. */
1184
1185 /* Hmm... whether or not this will work will depend on
1186 where the pc is. If it's still early in the prologue
1187 this'll be wrong. FIXME */
1188 if (next_frame)
1189 {
1190 frame_unwind_register (next_frame, sp_regnum, buf);
1191 saved_sp = extract_unsigned_integer (buf, 8);
1192 }
1193 spill_addr = saved_sp
1194 + (rM == 12 ? 0 : mem_stack_frame_size)
1195 + imm;
1196 spill_reg = rN;
1197 last_prologue_pc = next_pc;
1198 }
1199 else if (qp == 0 && rM >= 32 && rM < 40 && !instores[rM] &&
1200 rN < 256 && imm == 0)
1201 {
1202 /* mov rN, rM where rM is an input register */
1203 reg_contents[rN] = rM;
1204 last_prologue_pc = next_pc;
1205 }
1206 else if (frameless && qp == 0 && rN == fp_reg && imm == 0 &&
1207 rM == 2)
1208 {
1209 /* mov r12, r2 */
1210 last_prologue_pc = next_pc;
1211 break;
1212 }
1213 }
1214 else if (it == M
1215 && ( ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
1216 || ((instr & 0x1ffc8000000LL) == 0x0cec0000000LL) ))
1217 {
1218 /* stf.spill [rN] = fM, imm9
1219 or
1220 stf.spill [rN] = fM */
1221
1222 int imm = imm9(instr);
1223 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1224 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1225 int qp = (int) (instr & 0x0000000003fLL);
1226 if (qp == 0 && rN == spill_reg && spill_addr != 0
1227 && ((2 <= fM && fM <= 5) || (16 <= fM && fM <= 31)))
1228 {
1229 cache->saved_regs[IA64_FR0_REGNUM + fM] = spill_addr;
1230
1231 if ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
1232 spill_addr += imm;
1233 else
1234 spill_addr = 0; /* last one; must be done */
1235 last_prologue_pc = next_pc;
1236 }
1237 }
1238 else if ((it == M && ((instr & 0x1eff8000000LL) == 0x02110000000LL))
1239 || (it == I && ((instr & 0x1eff8000000LL) == 0x00050000000LL)) )
1240 {
1241 /* mov.m rN = arM
1242 or
1243 mov.i rN = arM */
1244
1245 int arM = (int) ((instr & 0x00007f00000LL) >> 20);
1246 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1247 int qp = (int) (instr & 0x0000000003fLL);
1248 if (qp == 0 && isScratch (rN) && arM == 36 /* ar.unat */)
1249 {
1250 /* We have something like "mov.m r3 = ar.unat". Remember the
1251 r3 (or whatever) and watch for a store of this register... */
1252 unat_save_reg = rN;
1253 last_prologue_pc = next_pc;
1254 }
1255 }
1256 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00198000000LL))
1257 {
1258 /* mov rN = pr */
1259 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1260 int qp = (int) (instr & 0x0000000003fLL);
1261 if (qp == 0 && isScratch (rN))
1262 {
1263 pr_save_reg = rN;
1264 last_prologue_pc = next_pc;
1265 }
1266 }
1267 else if (it == M
1268 && ( ((instr & 0x1ffc8000000LL) == 0x08cc0000000LL)
1269 || ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)))
1270 {
1271 /* st8 [rN] = rM
1272 or
1273 st8 [rN] = rM, imm9 */
1274 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1275 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1276 int qp = (int) (instr & 0x0000000003fLL);
1277 int indirect = rM < 256 ? reg_contents[rM] : 0;
1278 if (qp == 0 && rN == spill_reg && spill_addr != 0
1279 && (rM == unat_save_reg || rM == pr_save_reg))
1280 {
1281 /* We've found a spill of either the UNAT register or the PR
1282 register. (Well, not exactly; what we've actually found is
1283 a spill of the register that UNAT or PR was moved to).
1284 Record that fact and move on... */
1285 if (rM == unat_save_reg)
1286 {
1287 /* Track UNAT register */
1288 cache->saved_regs[IA64_UNAT_REGNUM] = spill_addr;
1289 unat_save_reg = 0;
1290 }
1291 else
1292 {
1293 /* Track PR register */
1294 cache->saved_regs[IA64_PR_REGNUM] = spill_addr;
1295 pr_save_reg = 0;
1296 }
1297 if ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)
1298 /* st8 [rN] = rM, imm9 */
1299 spill_addr += imm9(instr);
1300 else
1301 spill_addr = 0; /* must be done spilling */
1302 last_prologue_pc = next_pc;
1303 }
1304 else if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1305 {
1306 /* Allow up to one store of each input register. */
1307 instores[rM-32] = 1;
1308 last_prologue_pc = next_pc;
1309 }
1310 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1311 !instores[indirect-32])
1312 {
1313 /* Allow an indirect store of an input register. */
1314 instores[indirect-32] = 1;
1315 last_prologue_pc = next_pc;
1316 }
1317 }
1318 else if (it == M && ((instr & 0x1ff08000000LL) == 0x08c00000000LL))
1319 {
1320 /* One of
1321 st1 [rN] = rM
1322 st2 [rN] = rM
1323 st4 [rN] = rM
1324 st8 [rN] = rM
1325 Note that the st8 case is handled in the clause above.
1326
1327 Advance over stores of input registers. One store per input
1328 register is permitted. */
1329 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1330 int qp = (int) (instr & 0x0000000003fLL);
1331 int indirect = rM < 256 ? reg_contents[rM] : 0;
1332 if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1333 {
1334 instores[rM-32] = 1;
1335 last_prologue_pc = next_pc;
1336 }
1337 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1338 !instores[indirect-32])
1339 {
1340 /* Allow an indirect store of an input register. */
1341 instores[indirect-32] = 1;
1342 last_prologue_pc = next_pc;
1343 }
1344 }
1345 else if (it == M && ((instr & 0x1ff88000000LL) == 0x0cc80000000LL))
1346 {
1347 /* Either
1348 stfs [rN] = fM
1349 or
1350 stfd [rN] = fM
1351
1352 Advance over stores of floating point input registers. Again
1353 one store per register is permitted */
1354 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1355 int qp = (int) (instr & 0x0000000003fLL);
1356 if (qp == 0 && 8 <= fM && fM < 16 && !infpstores[fM - 8])
1357 {
1358 infpstores[fM-8] = 1;
1359 last_prologue_pc = next_pc;
1360 }
1361 }
1362 else if (it == M
1363 && ( ((instr & 0x1ffc8000000LL) == 0x08ec0000000LL)
1364 || ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)))
1365 {
1366 /* st8.spill [rN] = rM
1367 or
1368 st8.spill [rN] = rM, imm9 */
1369 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1370 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1371 int qp = (int) (instr & 0x0000000003fLL);
1372 if (qp == 0 && rN == spill_reg && 4 <= rM && rM <= 7)
1373 {
1374 /* We've found a spill of one of the preserved general purpose
1375 regs. Record the spill address and advance the spill
1376 register if appropriate. */
1377 cache->saved_regs[IA64_GR0_REGNUM + rM] = spill_addr;
1378 if ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)
1379 /* st8.spill [rN] = rM, imm9 */
1380 spill_addr += imm9(instr);
1381 else
1382 spill_addr = 0; /* Done spilling */
1383 last_prologue_pc = next_pc;
1384 }
1385 }
1386
1387 pc = next_pc;
1388 }
1389
1390 /* If not frameless and we aren't called by skip_prologue, then we need to calculate
1391 registers for the previous frame which will be needed later. */
1392
1393 if (!frameless && next_frame)
1394 {
1395 /* Extract the size of the rotating portion of the stack
1396 frame and the register rename base from the current
1397 frame marker. */
1398 cfm = cache->cfm;
1399 sor = cache->sor;
1400 sof = cache->sof;
1401 sol = cache->sol;
1402 rrb_gr = (cfm >> 18) & 0x7f;
1403
1404 /* Find the bof (beginning of frame). */
1405 bof = rse_address_add (cache->bsp, -sof);
1406
1407 for (i = 0, addr = bof;
1408 i < sof;
1409 i++, addr += 8)
1410 {
1411 if (IS_NaT_COLLECTION_ADDR (addr))
1412 {
1413 addr += 8;
1414 }
1415 if (i+32 == cfm_reg)
1416 cache->saved_regs[IA64_CFM_REGNUM] = addr;
1417 if (i+32 == ret_reg)
1418 cache->saved_regs[IA64_VRAP_REGNUM] = addr;
1419 if (i+32 == fp_reg)
1420 cache->saved_regs[IA64_VFP_REGNUM] = addr;
1421 }
1422
1423 /* For the previous argument registers we require the previous bof.
1424 If we can't find the previous cfm, then we can do nothing. */
1425 cfm = 0;
1426 if (cache->saved_regs[IA64_CFM_REGNUM] != 0)
1427 {
1428 cfm = read_memory_integer (cache->saved_regs[IA64_CFM_REGNUM], 8);
1429 }
1430 else if (cfm_reg != 0)
1431 {
1432 frame_unwind_register (next_frame, cfm_reg, buf);
1433 cfm = extract_unsigned_integer (buf, 8);
1434 }
1435 cache->prev_cfm = cfm;
1436
1437 if (cfm != 0)
1438 {
1439 sor = ((cfm >> 14) & 0xf) * 8;
1440 sof = (cfm & 0x7f);
1441 sol = (cfm >> 7) & 0x7f;
1442 rrb_gr = (cfm >> 18) & 0x7f;
1443
1444 /* The previous bof only requires subtraction of the sol (size of locals)
1445 due to the overlap between output and input of subsequent frames. */
1446 bof = rse_address_add (bof, -sol);
1447
1448 for (i = 0, addr = bof;
1449 i < sof;
1450 i++, addr += 8)
1451 {
1452 if (IS_NaT_COLLECTION_ADDR (addr))
1453 {
1454 addr += 8;
1455 }
1456 if (i < sor)
1457 cache->saved_regs[IA64_GR32_REGNUM + ((i + (sor - rrb_gr)) % sor)]
1458 = addr;
1459 else
1460 cache->saved_regs[IA64_GR32_REGNUM + i] = addr;
1461 }
1462
1463 }
1464 }
1465
1466 /* Try and trust the lim_pc value whenever possible. */
1467 if (trust_limit && lim_pc >= last_prologue_pc)
1468 last_prologue_pc = lim_pc;
1469
1470 cache->frameless = frameless;
1471 cache->after_prologue = last_prologue_pc;
1472 cache->mem_stack_frame_size = mem_stack_frame_size;
1473 cache->fp_reg = fp_reg;
1474
1475 return last_prologue_pc;
1476 }
1477
1478 CORE_ADDR
ia64_skip_prologue(CORE_ADDR pc)1479 ia64_skip_prologue (CORE_ADDR pc)
1480 {
1481 struct ia64_frame_cache cache;
1482 cache.base = 0;
1483 cache.after_prologue = 0;
1484 cache.cfm = 0;
1485 cache.bsp = 0;
1486
1487 /* Call examine_prologue with - as third argument since we don't have a next frame pointer to send. */
1488 return examine_prologue (pc, pc+1024, 0, &cache);
1489 }
1490
1491
1492 /* Normal frames. */
1493
1494 static struct ia64_frame_cache *
ia64_frame_cache(struct frame_info * next_frame,void ** this_cache)1495 ia64_frame_cache (struct frame_info *next_frame, void **this_cache)
1496 {
1497 struct ia64_frame_cache *cache;
1498 char buf[8];
1499 CORE_ADDR cfm, sof, sol, bsp, psr;
1500 int i;
1501
1502 if (*this_cache)
1503 return *this_cache;
1504
1505 cache = ia64_alloc_frame_cache ();
1506 *this_cache = cache;
1507
1508 frame_unwind_register (next_frame, sp_regnum, buf);
1509 cache->saved_sp = extract_unsigned_integer (buf, 8);
1510
1511 /* We always want the bsp to point to the end of frame.
1512 This way, we can always get the beginning of frame (bof)
1513 by subtracting frame size. */
1514 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1515 cache->bsp = extract_unsigned_integer (buf, 8);
1516
1517 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1518 psr = extract_unsigned_integer (buf, 8);
1519
1520 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1521 cfm = extract_unsigned_integer (buf, 8);
1522
1523 cache->sof = (cfm & 0x7f);
1524 cache->sol = (cfm >> 7) & 0x7f;
1525 cache->sor = ((cfm >> 14) & 0xf) * 8;
1526
1527 cache->cfm = cfm;
1528
1529 cache->pc = frame_func_unwind (next_frame);
1530
1531 if (cache->pc != 0)
1532 examine_prologue (cache->pc, frame_pc_unwind (next_frame), next_frame, cache);
1533
1534 cache->base = cache->saved_sp + cache->mem_stack_frame_size;
1535
1536 return cache;
1537 }
1538
1539 static void
ia64_frame_this_id(struct frame_info * next_frame,void ** this_cache,struct frame_id * this_id)1540 ia64_frame_this_id (struct frame_info *next_frame, void **this_cache,
1541 struct frame_id *this_id)
1542 {
1543 struct ia64_frame_cache *cache =
1544 ia64_frame_cache (next_frame, this_cache);
1545
1546 /* This marks the outermost frame. */
1547 if (cache->base == 0)
1548 return;
1549
1550 (*this_id) = frame_id_build_special (cache->base, cache->pc, cache->bsp);
1551 if (gdbarch_debug >= 1)
1552 fprintf_unfiltered (gdb_stdlog,
1553 "regular frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
1554 paddr_nz (this_id->code_addr),
1555 paddr_nz (this_id->stack_addr),
1556 paddr_nz (cache->bsp), next_frame);
1557 }
1558
1559 static void
ia64_frame_prev_register(struct frame_info * next_frame,void ** this_cache,int regnum,int * optimizedp,enum lval_type * lvalp,CORE_ADDR * addrp,int * realnump,void * valuep)1560 ia64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1561 int regnum, int *optimizedp,
1562 enum lval_type *lvalp, CORE_ADDR *addrp,
1563 int *realnump, void *valuep)
1564 {
1565 struct ia64_frame_cache *cache =
1566 ia64_frame_cache (next_frame, this_cache);
1567 char dummy_valp[MAX_REGISTER_SIZE];
1568 char buf[8];
1569
1570 gdb_assert (regnum >= 0);
1571
1572 if (!target_has_registers)
1573 error ("No registers.");
1574
1575 *optimizedp = 0;
1576 *addrp = 0;
1577 *lvalp = not_lval;
1578 *realnump = -1;
1579
1580 /* Rather than check each time if valuep is non-null, supply a dummy buffer
1581 when valuep is not supplied. */
1582 if (!valuep)
1583 valuep = dummy_valp;
1584
1585 memset (valuep, 0, register_size (current_gdbarch, regnum));
1586
1587 if (regnum == SP_REGNUM)
1588 {
1589 /* Handle SP values for all frames but the topmost. */
1590 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
1591 cache->base);
1592 }
1593 else if (regnum == IA64_BSP_REGNUM)
1594 {
1595 char cfm_valuep[MAX_REGISTER_SIZE];
1596 int cfm_optim;
1597 int cfm_realnum;
1598 enum lval_type cfm_lval;
1599 CORE_ADDR cfm_addr;
1600 CORE_ADDR bsp, prev_cfm, prev_bsp;
1601
1602 /* We want to calculate the previous bsp as the end of the previous register stack frame.
1603 This corresponds to what the hardware bsp register will be if we pop the frame
1604 back which is why we might have been called. We know the beginning of the current
1605 frame is cache->bsp - cache->sof. This value in the previous frame points to
1606 the start of the output registers. We can calculate the end of that frame by adding
1607 the size of output (sof (size of frame) - sol (size of locals)). */
1608 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1609 &cfm_optim, &cfm_lval, &cfm_addr, &cfm_realnum, cfm_valuep);
1610 prev_cfm = extract_unsigned_integer (cfm_valuep, 8);
1611
1612 bsp = rse_address_add (cache->bsp, -(cache->sof));
1613 prev_bsp = rse_address_add (bsp, (prev_cfm & 0x7f) - ((prev_cfm >> 7) & 0x7f));
1614
1615 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
1616 prev_bsp);
1617 }
1618 else if (regnum == IA64_CFM_REGNUM)
1619 {
1620 CORE_ADDR addr = cache->saved_regs[IA64_CFM_REGNUM];
1621
1622 if (addr != 0)
1623 {
1624 *lvalp = lval_memory;
1625 *addrp = addr;
1626 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
1627 }
1628 else if (cache->prev_cfm)
1629 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), cache->prev_cfm);
1630 else if (cache->frameless)
1631 {
1632 CORE_ADDR cfm = 0;
1633 frame_unwind_register (next_frame, IA64_PFS_REGNUM, valuep);
1634 }
1635 }
1636 else if (regnum == IA64_VFP_REGNUM)
1637 {
1638 /* If the function in question uses an automatic register (r32-r127)
1639 for the frame pointer, it'll be found by ia64_find_saved_register()
1640 above. If the function lacks one of these frame pointers, we can
1641 still provide a value since we know the size of the frame. */
1642 CORE_ADDR vfp = cache->base;
1643 store_unsigned_integer (valuep, register_size (current_gdbarch, IA64_VFP_REGNUM), vfp);
1644 }
1645 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
1646 {
1647 char pr_valuep[MAX_REGISTER_SIZE];
1648 int pr_optim;
1649 int pr_realnum;
1650 enum lval_type pr_lval;
1651 CORE_ADDR pr_addr;
1652 ULONGEST prN_val;
1653 ia64_frame_prev_register (next_frame, this_cache, IA64_PR_REGNUM,
1654 &pr_optim, &pr_lval, &pr_addr, &pr_realnum, pr_valuep);
1655 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
1656 {
1657 /* Fetch predicate register rename base from current frame
1658 marker for this frame. */
1659 int rrb_pr = (cache->cfm >> 32) & 0x3f;
1660
1661 /* Adjust the register number to account for register rotation. */
1662 regnum = VP16_REGNUM
1663 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
1664 }
1665 prN_val = extract_bit_field ((unsigned char *) pr_valuep,
1666 regnum - VP0_REGNUM, 1);
1667 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), prN_val);
1668 }
1669 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
1670 {
1671 char unat_valuep[MAX_REGISTER_SIZE];
1672 int unat_optim;
1673 int unat_realnum;
1674 enum lval_type unat_lval;
1675 CORE_ADDR unat_addr;
1676 ULONGEST unatN_val;
1677 ia64_frame_prev_register (next_frame, this_cache, IA64_UNAT_REGNUM,
1678 &unat_optim, &unat_lval, &unat_addr, &unat_realnum, unat_valuep);
1679 unatN_val = extract_bit_field ((unsigned char *) unat_valuep,
1680 regnum - IA64_NAT0_REGNUM, 1);
1681 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
1682 unatN_val);
1683 }
1684 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
1685 {
1686 int natval = 0;
1687 /* Find address of general register corresponding to nat bit we're
1688 interested in. */
1689 CORE_ADDR gr_addr;
1690
1691 gr_addr = cache->saved_regs[regnum - IA64_NAT0_REGNUM
1692 + IA64_GR0_REGNUM];
1693 if (gr_addr != 0)
1694 {
1695 /* Compute address of nat collection bits. */
1696 CORE_ADDR nat_addr = gr_addr | 0x1f8;
1697 CORE_ADDR bsp;
1698 CORE_ADDR nat_collection;
1699 int nat_bit;
1700 /* If our nat collection address is bigger than bsp, we have to get
1701 the nat collection from rnat. Otherwise, we fetch the nat
1702 collection from the computed address. */
1703 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1704 bsp = extract_unsigned_integer (buf, 8);
1705 if (nat_addr >= bsp)
1706 {
1707 frame_unwind_register (next_frame, IA64_RNAT_REGNUM, buf);
1708 nat_collection = extract_unsigned_integer (buf, 8);
1709 }
1710 else
1711 nat_collection = read_memory_integer (nat_addr, 8);
1712 nat_bit = (gr_addr >> 3) & 0x3f;
1713 natval = (nat_collection >> nat_bit) & 1;
1714 }
1715
1716 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), natval);
1717 }
1718 else if (regnum == IA64_IP_REGNUM)
1719 {
1720 CORE_ADDR pc = 0;
1721 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
1722
1723 if (addr != 0)
1724 {
1725 *lvalp = lval_memory;
1726 *addrp = addr;
1727 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
1728 pc = extract_unsigned_integer (buf, 8);
1729 }
1730 else if (cache->frameless)
1731 {
1732 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1733 pc = extract_unsigned_integer (buf, 8);
1734 }
1735 pc &= ~0xf;
1736 store_unsigned_integer (valuep, 8, pc);
1737 }
1738 else if (regnum == IA64_PSR_REGNUM)
1739 {
1740 /* We don't know how to get the complete previous PSR, but we need it for
1741 the slot information when we unwind the pc (pc is formed of IP register
1742 plus slot information from PSR). To get the previous slot information,
1743 we mask it off the return address. */
1744 ULONGEST slot_num = 0;
1745 CORE_ADDR pc= 0;
1746 CORE_ADDR psr = 0;
1747 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
1748
1749 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1750 psr = extract_unsigned_integer (buf, 8);
1751
1752 if (addr != 0)
1753 {
1754 *lvalp = lval_memory;
1755 *addrp = addr;
1756 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
1757 pc = extract_unsigned_integer (buf, 8);
1758 }
1759 else if (cache->frameless)
1760 {
1761 CORE_ADDR pc;
1762 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1763 pc = extract_unsigned_integer (buf, 8);
1764 }
1765 psr &= ~(3LL << 41);
1766 slot_num = pc & 0x3LL;
1767 psr |= (CORE_ADDR)slot_num << 41;
1768 store_unsigned_integer (valuep, 8, psr);
1769 }
1770 else if (regnum == IA64_BR0_REGNUM)
1771 {
1772 CORE_ADDR br0 = 0;
1773 CORE_ADDR addr = cache->saved_regs[IA64_BR0_REGNUM];
1774 if (addr != 0)
1775 {
1776 *lvalp = lval_memory;
1777 *addrp = addr;
1778 read_memory (addr, buf, register_size (current_gdbarch, IA64_BR0_REGNUM));
1779 br0 = extract_unsigned_integer (buf, 8);
1780 }
1781 store_unsigned_integer (valuep, 8, br0);
1782 }
1783 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
1784 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
1785 {
1786 CORE_ADDR addr = 0;
1787 if (regnum >= V32_REGNUM)
1788 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1789 addr = cache->saved_regs[regnum];
1790 if (addr != 0)
1791 {
1792 *lvalp = lval_memory;
1793 *addrp = addr;
1794 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
1795 }
1796 else if (cache->frameless)
1797 {
1798 char r_valuep[MAX_REGISTER_SIZE];
1799 int r_optim;
1800 int r_realnum;
1801 enum lval_type r_lval;
1802 CORE_ADDR r_addr;
1803 CORE_ADDR prev_cfm, prev_bsp, prev_bof;
1804 CORE_ADDR addr = 0;
1805 if (regnum >= V32_REGNUM)
1806 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1807 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1808 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1809 prev_cfm = extract_unsigned_integer (r_valuep, 8);
1810 ia64_frame_prev_register (next_frame, this_cache, IA64_BSP_REGNUM,
1811 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1812 prev_bsp = extract_unsigned_integer (r_valuep, 8);
1813 prev_bof = rse_address_add (prev_bsp, -(prev_cfm & 0x7f));
1814
1815 addr = rse_address_add (prev_bof, (regnum - IA64_GR32_REGNUM));
1816 *lvalp = lval_memory;
1817 *addrp = addr;
1818 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
1819 }
1820 }
1821 else
1822 {
1823 CORE_ADDR addr = 0;
1824 if (IA64_FR32_REGNUM <= regnum && regnum <= IA64_FR127_REGNUM)
1825 {
1826 /* Fetch floating point register rename base from current
1827 frame marker for this frame. */
1828 int rrb_fr = (cache->cfm >> 25) & 0x7f;
1829
1830 /* Adjust the floating point register number to account for
1831 register rotation. */
1832 regnum = IA64_FR32_REGNUM
1833 + ((regnum - IA64_FR32_REGNUM) + rrb_fr) % 96;
1834 }
1835
1836 /* If we have stored a memory address, access the register. */
1837 addr = cache->saved_regs[regnum];
1838 if (addr != 0)
1839 {
1840 *lvalp = lval_memory;
1841 *addrp = addr;
1842 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
1843 }
1844 /* Otherwise, punt and get the current value of the register. */
1845 else
1846 frame_unwind_register (next_frame, regnum, valuep);
1847 }
1848
1849 if (gdbarch_debug >= 1)
1850 fprintf_unfiltered (gdb_stdlog,
1851 "regular prev register <%d> <%s> is 0x%s\n", regnum,
1852 (((unsigned) regnum <= IA64_NAT127_REGNUM)
1853 ? ia64_register_names[regnum] : "r??"),
1854 paddr_nz (extract_unsigned_integer (valuep, 8)));
1855 }
1856
1857 static const struct frame_unwind ia64_frame_unwind =
1858 {
1859 NORMAL_FRAME,
1860 &ia64_frame_this_id,
1861 &ia64_frame_prev_register
1862 };
1863
1864 static const struct frame_unwind *
ia64_frame_sniffer(struct frame_info * next_frame)1865 ia64_frame_sniffer (struct frame_info *next_frame)
1866 {
1867 return &ia64_frame_unwind;
1868 }
1869
1870 /* Signal trampolines. */
1871
1872 static void
ia64_sigtramp_frame_init_saved_regs(struct ia64_frame_cache * cache)1873 ia64_sigtramp_frame_init_saved_regs (struct ia64_frame_cache *cache)
1874 {
1875 if (SIGCONTEXT_REGISTER_ADDRESS)
1876 {
1877 int regno;
1878
1879 cache->saved_regs[IA64_VRAP_REGNUM] =
1880 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_IP_REGNUM);
1881 cache->saved_regs[IA64_CFM_REGNUM] =
1882 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CFM_REGNUM);
1883 cache->saved_regs[IA64_PSR_REGNUM] =
1884 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PSR_REGNUM);
1885 cache->saved_regs[IA64_BSP_REGNUM] =
1886 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_BSP_REGNUM);
1887 cache->saved_regs[IA64_RNAT_REGNUM] =
1888 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_RNAT_REGNUM);
1889 cache->saved_regs[IA64_CCV_REGNUM] =
1890 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CCV_REGNUM);
1891 cache->saved_regs[IA64_UNAT_REGNUM] =
1892 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_UNAT_REGNUM);
1893 cache->saved_regs[IA64_FPSR_REGNUM] =
1894 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_FPSR_REGNUM);
1895 cache->saved_regs[IA64_PFS_REGNUM] =
1896 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PFS_REGNUM);
1897 cache->saved_regs[IA64_LC_REGNUM] =
1898 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_LC_REGNUM);
1899 for (regno = IA64_GR1_REGNUM; regno <= IA64_GR31_REGNUM; regno++)
1900 cache->saved_regs[regno] =
1901 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
1902 for (regno = IA64_BR0_REGNUM; regno <= IA64_BR7_REGNUM; regno++)
1903 cache->saved_regs[regno] =
1904 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
1905 for (regno = IA64_FR2_REGNUM; regno <= IA64_FR31_REGNUM; regno++)
1906 cache->saved_regs[regno] =
1907 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
1908 }
1909 }
1910
1911 static struct ia64_frame_cache *
ia64_sigtramp_frame_cache(struct frame_info * next_frame,void ** this_cache)1912 ia64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
1913 {
1914 struct ia64_frame_cache *cache;
1915 CORE_ADDR addr;
1916 char buf[8];
1917 int i;
1918
1919 if (*this_cache)
1920 return *this_cache;
1921
1922 cache = ia64_alloc_frame_cache ();
1923
1924 frame_unwind_register (next_frame, sp_regnum, buf);
1925 /* Note that frame size is hard-coded below. We cannot calculate it
1926 via prologue examination. */
1927 cache->base = extract_unsigned_integer (buf, 8) + 16;
1928
1929 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1930 cache->bsp = extract_unsigned_integer (buf, 8);
1931
1932 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1933 cache->cfm = extract_unsigned_integer (buf, 8);
1934 cache->sof = cache->cfm & 0x7f;
1935
1936 ia64_sigtramp_frame_init_saved_regs (cache);
1937
1938 *this_cache = cache;
1939 return cache;
1940 }
1941
1942 static void
ia64_sigtramp_frame_this_id(struct frame_info * next_frame,void ** this_cache,struct frame_id * this_id)1943 ia64_sigtramp_frame_this_id (struct frame_info *next_frame,
1944 void **this_cache, struct frame_id *this_id)
1945 {
1946 struct ia64_frame_cache *cache =
1947 ia64_sigtramp_frame_cache (next_frame, this_cache);
1948
1949 (*this_id) = frame_id_build_special (cache->base, frame_pc_unwind (next_frame), cache->bsp);
1950 if (gdbarch_debug >= 1)
1951 fprintf_unfiltered (gdb_stdlog,
1952 "sigtramp frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
1953 paddr_nz (this_id->code_addr),
1954 paddr_nz (this_id->stack_addr),
1955 paddr_nz (cache->bsp), next_frame);
1956 }
1957
1958 static void
ia64_sigtramp_frame_prev_register(struct frame_info * next_frame,void ** this_cache,int regnum,int * optimizedp,enum lval_type * lvalp,CORE_ADDR * addrp,int * realnump,void * valuep)1959 ia64_sigtramp_frame_prev_register (struct frame_info *next_frame,
1960 void **this_cache,
1961 int regnum, int *optimizedp,
1962 enum lval_type *lvalp, CORE_ADDR *addrp,
1963 int *realnump, void *valuep)
1964 {
1965 char dummy_valp[MAX_REGISTER_SIZE];
1966 char buf[MAX_REGISTER_SIZE];
1967
1968 struct ia64_frame_cache *cache =
1969 ia64_sigtramp_frame_cache (next_frame, this_cache);
1970
1971 gdb_assert (regnum >= 0);
1972
1973 if (!target_has_registers)
1974 error ("No registers.");
1975
1976 *optimizedp = 0;
1977 *addrp = 0;
1978 *lvalp = not_lval;
1979 *realnump = -1;
1980
1981 /* Rather than check each time if valuep is non-null, supply a dummy buffer
1982 when valuep is not supplied. */
1983 if (!valuep)
1984 valuep = dummy_valp;
1985
1986 memset (valuep, 0, register_size (current_gdbarch, regnum));
1987
1988 if (regnum == IA64_IP_REGNUM)
1989 {
1990 CORE_ADDR pc = 0;
1991 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
1992
1993 if (addr != 0)
1994 {
1995 *lvalp = lval_memory;
1996 *addrp = addr;
1997 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
1998 pc = extract_unsigned_integer (buf, 8);
1999 }
2000 pc &= ~0xf;
2001 store_unsigned_integer (valuep, 8, pc);
2002 }
2003 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
2004 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
2005 {
2006 CORE_ADDR addr = 0;
2007 if (regnum >= V32_REGNUM)
2008 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
2009 addr = cache->saved_regs[regnum];
2010 if (addr != 0)
2011 {
2012 *lvalp = lval_memory;
2013 *addrp = addr;
2014 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
2015 }
2016 }
2017 else
2018 {
2019 /* All other registers not listed above. */
2020 CORE_ADDR addr = cache->saved_regs[regnum];
2021 if (addr != 0)
2022 {
2023 *lvalp = lval_memory;
2024 *addrp = addr;
2025 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
2026 }
2027 }
2028
2029 if (gdbarch_debug >= 1)
2030 fprintf_unfiltered (gdb_stdlog,
2031 "sigtramp prev register <%s> is 0x%s\n",
2032 (((unsigned) regnum <= IA64_NAT127_REGNUM)
2033 ? ia64_register_names[regnum] : "r??"),
2034 paddr_nz (extract_unsigned_integer (valuep, 8)));
2035 }
2036
2037 static const struct frame_unwind ia64_sigtramp_frame_unwind =
2038 {
2039 SIGTRAMP_FRAME,
2040 ia64_sigtramp_frame_this_id,
2041 ia64_sigtramp_frame_prev_register
2042 };
2043
2044 static const struct frame_unwind *
ia64_sigtramp_frame_sniffer(struct frame_info * next_frame)2045 ia64_sigtramp_frame_sniffer (struct frame_info *next_frame)
2046 {
2047 char *name;
2048 CORE_ADDR pc = frame_pc_unwind (next_frame);
2049
2050 find_pc_partial_function (pc, &name, NULL, NULL);
2051 if (legacy_pc_in_sigtramp (pc, name))
2052 return &ia64_sigtramp_frame_unwind;
2053
2054 return NULL;
2055 }
2056
2057
2058 static CORE_ADDR
ia64_frame_base_address(struct frame_info * next_frame,void ** this_cache)2059 ia64_frame_base_address (struct frame_info *next_frame, void **this_cache)
2060 {
2061 struct ia64_frame_cache *cache =
2062 ia64_frame_cache (next_frame, this_cache);
2063
2064 return cache->base;
2065 }
2066
2067 static const struct frame_base ia64_frame_base =
2068 {
2069 &ia64_frame_unwind,
2070 ia64_frame_base_address,
2071 ia64_frame_base_address,
2072 ia64_frame_base_address
2073 };
2074
2075 #ifdef HAVE_LIBUNWIND_IA64_H
2076
2077 struct ia64_unwind_table_entry
2078 {
2079 unw_word_t start_offset;
2080 unw_word_t end_offset;
2081 unw_word_t info_offset;
2082 };
2083
2084 static __inline__ uint64_t
ia64_rse_slot_num(uint64_t addr)2085 ia64_rse_slot_num (uint64_t addr)
2086 {
2087 return (addr >> 3) & 0x3f;
2088 }
2089
2090 /* Skip over a designated number of registers in the backing
2091 store, remembering every 64th position is for NAT. */
2092 static __inline__ uint64_t
ia64_rse_skip_regs(uint64_t addr,long num_regs)2093 ia64_rse_skip_regs (uint64_t addr, long num_regs)
2094 {
2095 long delta = ia64_rse_slot_num(addr) + num_regs;
2096
2097 if (num_regs < 0)
2098 delta -= 0x3e;
2099 return addr + ((num_regs + delta/0x3f) << 3);
2100 }
2101
2102 /* Gdb libunwind-frame callback function to convert from an ia64 gdb register
2103 number to a libunwind register number. */
2104 static int
ia64_gdb2uw_regnum(int regnum)2105 ia64_gdb2uw_regnum (int regnum)
2106 {
2107 if (regnum == sp_regnum)
2108 return UNW_IA64_SP;
2109 else if (regnum == IA64_BSP_REGNUM)
2110 return UNW_IA64_BSP;
2111 else if ((unsigned) (regnum - IA64_GR0_REGNUM) < 128)
2112 return UNW_IA64_GR + (regnum - IA64_GR0_REGNUM);
2113 else if ((unsigned) (regnum - V32_REGNUM) < 95)
2114 return UNW_IA64_GR + 32 + (regnum - V32_REGNUM);
2115 else if ((unsigned) (regnum - IA64_FR0_REGNUM) < 128)
2116 return UNW_IA64_FR + (regnum - IA64_FR0_REGNUM);
2117 else if ((unsigned) (regnum - IA64_PR0_REGNUM) < 64)
2118 return -1;
2119 else if ((unsigned) (regnum - IA64_BR0_REGNUM) < 8)
2120 return UNW_IA64_BR + (regnum - IA64_BR0_REGNUM);
2121 else if (regnum == IA64_PR_REGNUM)
2122 return UNW_IA64_PR;
2123 else if (regnum == IA64_IP_REGNUM)
2124 return UNW_REG_IP;
2125 else if (regnum == IA64_CFM_REGNUM)
2126 return UNW_IA64_CFM;
2127 else if ((unsigned) (regnum - IA64_AR0_REGNUM) < 128)
2128 return UNW_IA64_AR + (regnum - IA64_AR0_REGNUM);
2129 else if ((unsigned) (regnum - IA64_NAT0_REGNUM) < 128)
2130 return UNW_IA64_NAT + (regnum - IA64_NAT0_REGNUM);
2131 else
2132 return -1;
2133 }
2134
2135 /* Gdb libunwind-frame callback function to convert from a libunwind register
2136 number to a ia64 gdb register number. */
2137 static int
ia64_uw2gdb_regnum(int uw_regnum)2138 ia64_uw2gdb_regnum (int uw_regnum)
2139 {
2140 if (uw_regnum == UNW_IA64_SP)
2141 return sp_regnum;
2142 else if (uw_regnum == UNW_IA64_BSP)
2143 return IA64_BSP_REGNUM;
2144 else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 32)
2145 return IA64_GR0_REGNUM + (uw_regnum - UNW_IA64_GR);
2146 else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 128)
2147 return V32_REGNUM + (uw_regnum - (IA64_GR0_REGNUM + 32));
2148 else if ((unsigned) (uw_regnum - UNW_IA64_FR) < 128)
2149 return IA64_FR0_REGNUM + (uw_regnum - UNW_IA64_FR);
2150 else if ((unsigned) (uw_regnum - UNW_IA64_BR) < 8)
2151 return IA64_BR0_REGNUM + (uw_regnum - UNW_IA64_BR);
2152 else if (uw_regnum == UNW_IA64_PR)
2153 return IA64_PR_REGNUM;
2154 else if (uw_regnum == UNW_REG_IP)
2155 return IA64_IP_REGNUM;
2156 else if (uw_regnum == UNW_IA64_CFM)
2157 return IA64_CFM_REGNUM;
2158 else if ((unsigned) (uw_regnum - UNW_IA64_AR) < 128)
2159 return IA64_AR0_REGNUM + (uw_regnum - UNW_IA64_AR);
2160 else if ((unsigned) (uw_regnum - UNW_IA64_NAT) < 128)
2161 return IA64_NAT0_REGNUM + (uw_regnum - UNW_IA64_NAT);
2162 else
2163 return -1;
2164 }
2165
2166 /* Gdb libunwind-frame callback function to reveal if register is a float
2167 register or not. */
2168 static int
ia64_is_fpreg(int uw_regnum)2169 ia64_is_fpreg (int uw_regnum)
2170 {
2171 return unw_is_fpreg (uw_regnum);
2172 }
2173
2174 /* Libunwind callback accessor function for general registers. */
2175 static int
ia64_access_reg(unw_addr_space_t as,unw_regnum_t uw_regnum,unw_word_t * val,int write,void * arg)2176 ia64_access_reg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_word_t *val,
2177 int write, void *arg)
2178 {
2179 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2180 unw_word_t bsp, sof, sol, cfm, psr, ip;
2181 struct frame_info *next_frame = arg;
2182 long new_sof, old_sof;
2183 char buf[MAX_REGISTER_SIZE];
2184
2185 if (write)
2186 {
2187 if (regnum < 0)
2188 /* ignore writes to pseudo-registers such as UNW_IA64_PROC_STARTI. */
2189 return 0;
2190
2191 switch (uw_regnum)
2192 {
2193 case UNW_REG_IP:
2194 ia64_write_pc (*val, inferior_ptid);
2195 break;
2196
2197 case UNW_IA64_AR_BSPSTORE:
2198 write_register (IA64_BSP_REGNUM, *val);
2199 break;
2200
2201 case UNW_IA64_AR_BSP:
2202 case UNW_IA64_BSP:
2203 /* Account for the fact that ptrace() expects bsp to point
2204 after the current register frame. */
2205 cfm = read_register (IA64_CFM_REGNUM);
2206 sof = (cfm & 0x7f);
2207 bsp = ia64_rse_skip_regs (*val, sof);
2208 write_register (IA64_BSP_REGNUM, bsp);
2209 break;
2210
2211 case UNW_IA64_CFM:
2212 /* If we change CFM, we need to adjust ptrace's notion of
2213 bsp accordingly, so that the real bsp remains
2214 unchanged. */
2215 bsp = read_register (IA64_BSP_REGNUM);
2216 cfm = read_register (IA64_CFM_REGNUM);
2217 old_sof = (cfm & 0x7f);
2218 new_sof = (*val & 0x7f);
2219 if (old_sof != new_sof)
2220 {
2221 bsp = ia64_rse_skip_regs (bsp, -old_sof + new_sof);
2222 write_register (IA64_BSP_REGNUM, bsp);
2223 }
2224 write_register (IA64_CFM_REGNUM, *val);
2225 break;
2226
2227 default:
2228 write_register (regnum, *val);
2229 break;
2230 }
2231 if (gdbarch_debug >= 1)
2232 fprintf_unfiltered (gdb_stdlog,
2233 " access_reg: to cache: %4s=0x%s\n",
2234 (((unsigned) regnum <= IA64_NAT127_REGNUM)
2235 ? ia64_register_names[regnum] : "r??"),
2236 paddr_nz (*val));
2237 }
2238 else
2239 {
2240 switch (uw_regnum)
2241 {
2242 case UNW_REG_IP:
2243 /* Libunwind expects to see the pc value which means the slot number
2244 from the psr must be merged with the ip word address. */
2245 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
2246 ip = extract_unsigned_integer (buf, 8);
2247 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
2248 psr = extract_unsigned_integer (buf, 8);
2249 *val = ip | ((psr >> 41) & 0x3);
2250 break;
2251
2252 case UNW_IA64_AR_BSP:
2253 /* Libunwind expects to see the beginning of the current register
2254 frame so we must account for the fact that ptrace() will return a value
2255 for bsp that points *after* the current register frame. */
2256 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2257 bsp = extract_unsigned_integer (buf, 8);
2258 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
2259 cfm = extract_unsigned_integer (buf, 8);
2260 sof = (cfm & 0x7f);
2261 *val = ia64_rse_skip_regs (bsp, -sof);
2262 break;
2263
2264 case UNW_IA64_AR_BSPSTORE:
2265 /* Libunwind wants bspstore to be after the current register frame.
2266 This is what ptrace() and gdb treats as the regular bsp value. */
2267 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2268 *val = extract_unsigned_integer (buf, 8);
2269 break;
2270
2271 default:
2272 /* For all other registers, just unwind the value directly. */
2273 frame_unwind_register (next_frame, regnum, buf);
2274 *val = extract_unsigned_integer (buf, 8);
2275 break;
2276 }
2277
2278 if (gdbarch_debug >= 1)
2279 fprintf_unfiltered (gdb_stdlog,
2280 " access_reg: from cache: %4s=0x%s\n",
2281 (((unsigned) regnum <= IA64_NAT127_REGNUM)
2282 ? ia64_register_names[regnum] : "r??"),
2283 paddr_nz (*val));
2284 }
2285 return 0;
2286 }
2287
2288 /* Libunwind callback accessor function for floating-point registers. */
2289 static int
ia64_access_fpreg(unw_addr_space_t as,unw_regnum_t uw_regnum,unw_fpreg_t * val,int write,void * arg)2290 ia64_access_fpreg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_fpreg_t *val,
2291 int write, void *arg)
2292 {
2293 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2294
2295 if (write)
2296 regcache_cooked_write (current_regcache, regnum, (char *) val);
2297 else
2298 regcache_cooked_read (current_regcache, regnum, (char *) val);
2299 return 0;
2300 }
2301
2302 /* Libunwind callback accessor function for accessing memory. */
2303 static int
ia64_access_mem(unw_addr_space_t as,unw_word_t addr,unw_word_t * val,int write,void * arg)2304 ia64_access_mem (unw_addr_space_t as,
2305 unw_word_t addr, unw_word_t *val,
2306 int write, void *arg)
2307 {
2308 /* XXX do we need to normalize byte-order here? */
2309 if (write)
2310 return target_write_memory (addr, (char *) val, sizeof (unw_word_t));
2311 else
2312 return target_read_memory (addr, (char *) val, sizeof (unw_word_t));
2313 }
2314
2315 /* Call low-level function to access the kernel unwind table. */
2316 static int
getunwind_table(void * buf,size_t len)2317 getunwind_table (void *buf, size_t len)
2318 {
2319 LONGEST x;
2320 x = target_read_partial (¤t_target, TARGET_OBJECT_UNWIND_TABLE, NULL,
2321 buf, 0, len);
2322
2323 return (int)x;
2324 }
2325
2326 /* Get the kernel unwind table. */
2327 static int
get_kernel_table(unw_word_t ip,unw_dyn_info_t * di)2328 get_kernel_table (unw_word_t ip, unw_dyn_info_t *di)
2329 {
2330 size_t size;
2331 struct ia64_table_entry
2332 {
2333 uint64_t start_offset;
2334 uint64_t end_offset;
2335 uint64_t info_offset;
2336 };
2337 static struct ia64_table_entry *ktab = NULL, *etab;
2338
2339 if (!ktab)
2340 {
2341 size = getunwind_table (NULL, 0);
2342 if ((int)size < 0)
2343 return -UNW_ENOINFO;
2344 ktab = xmalloc (size);
2345 getunwind_table (ktab, size);
2346
2347 /* Determine length of kernel's unwind table and relocate
2348 it's entries. */
2349 for (etab = ktab; etab->start_offset; ++etab)
2350 etab->info_offset += (uint64_t) ktab;
2351 }
2352
2353 if (ip < ktab[0].start_offset || ip >= etab[-1].end_offset)
2354 return -UNW_ENOINFO;
2355
2356 di->format = UNW_INFO_FORMAT_TABLE;
2357 di->gp = 0;
2358 di->start_ip = ktab[0].start_offset;
2359 di->end_ip = etab[-1].end_offset;
2360 di->u.ti.name_ptr = (unw_word_t) "<kernel>";
2361 di->u.ti.segbase = 0;
2362 di->u.ti.table_len = ((char *) etab - (char *) ktab) / sizeof (unw_word_t);
2363 di->u.ti.table_data = (unw_word_t *) ktab;
2364
2365 if (gdbarch_debug >= 1)
2366 fprintf_unfiltered (gdb_stdlog, "get_kernel_table: found table `%s': "
2367 "segbase=0x%s, length=%s, gp=0x%s\n",
2368 (char *) di->u.ti.name_ptr,
2369 paddr_nz (di->u.ti.segbase),
2370 paddr_u (di->u.ti.table_len),
2371 paddr_nz (di->gp));
2372 return 0;
2373 }
2374
2375 /* Find the unwind table entry for a specified address. */
2376 static int
ia64_find_unwind_table(struct objfile * objfile,unw_word_t ip,unw_dyn_info_t * dip,void ** buf)2377 ia64_find_unwind_table (struct objfile *objfile, unw_word_t ip,
2378 unw_dyn_info_t *dip, void **buf)
2379 {
2380 Elf_Internal_Phdr *phdr, *p_text = NULL, *p_unwind = NULL;
2381 Elf_Internal_Ehdr *ehdr;
2382 unw_word_t segbase = 0;
2383 CORE_ADDR load_base;
2384 bfd *bfd;
2385 int i;
2386
2387 bfd = objfile->obfd;
2388
2389 ehdr = elf_tdata (bfd)->elf_header;
2390 phdr = elf_tdata (bfd)->phdr;
2391
2392 load_base = ANOFFSET (objfile->section_offsets, SECT_OFF_TEXT (objfile));
2393
2394 for (i = 0; i < ehdr->e_phnum; ++i)
2395 {
2396 switch (phdr[i].p_type)
2397 {
2398 case PT_LOAD:
2399 if ((unw_word_t) (ip - load_base - phdr[i].p_vaddr)
2400 < phdr[i].p_memsz)
2401 p_text = phdr + i;
2402 break;
2403
2404 case PT_IA_64_UNWIND:
2405 p_unwind = phdr + i;
2406 break;
2407
2408 default:
2409 break;
2410 }
2411 }
2412
2413 if (!p_text || !p_unwind
2414 /* Verify that the segment that contains the IP also contains
2415 the static unwind table. If not, we are dealing with
2416 runtime-generated code, for which we have no info here. */
2417 || (p_unwind->p_vaddr - p_text->p_vaddr) >= p_text->p_memsz)
2418 return -UNW_ENOINFO;
2419
2420 segbase = p_text->p_vaddr + load_base;
2421
2422 dip->start_ip = segbase;
2423 dip->end_ip = dip->start_ip + p_text->p_memsz;
2424 dip->gp = FIND_GLOBAL_POINTER (ip);
2425 dip->format = UNW_INFO_FORMAT_REMOTE_TABLE;
2426 dip->u.rti.name_ptr = (unw_word_t) bfd_get_filename (bfd);
2427 dip->u.rti.segbase = segbase;
2428 dip->u.rti.table_len = p_unwind->p_memsz / sizeof (unw_word_t);
2429 dip->u.rti.table_data = p_unwind->p_vaddr + load_base;
2430
2431 return 0;
2432 }
2433
2434 /* Libunwind callback accessor function to acquire procedure unwind-info. */
2435 static int
ia64_find_proc_info_x(unw_addr_space_t as,unw_word_t ip,unw_proc_info_t * pi,int need_unwind_info,void * arg)2436 ia64_find_proc_info_x (unw_addr_space_t as, unw_word_t ip, unw_proc_info_t *pi,
2437 int need_unwind_info, void *arg)
2438 {
2439 struct obj_section *sec = find_pc_section (ip);
2440 unw_dyn_info_t di;
2441 int ret;
2442 void *buf = NULL;
2443
2444 if (!sec)
2445 {
2446 /* XXX This only works if the host and the target architecture are
2447 both ia64 and if the have (more or less) the same kernel
2448 version. */
2449 if (get_kernel_table (ip, &di) < 0)
2450 return -UNW_ENOINFO;
2451
2452 if (gdbarch_debug >= 1)
2453 fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: 0x%s -> "
2454 "(name=`%s',segbase=0x%s,start=0x%s,end=0x%s,gp=0x%s,"
2455 "length=%s,data=0x%s)\n",
2456 paddr_nz (ip), (char *)di.u.ti.name_ptr,
2457 paddr_nz (di.u.ti.segbase),
2458 paddr_nz (di.start_ip), paddr_nz (di.end_ip),
2459 paddr_nz (di.gp),
2460 paddr_u (di.u.ti.table_len),
2461 paddr_nz ((CORE_ADDR)di.u.ti.table_data));
2462 }
2463 else
2464 {
2465 ret = ia64_find_unwind_table (sec->objfile, ip, &di, &buf);
2466 if (ret < 0)
2467 return ret;
2468
2469 if (gdbarch_debug >= 1)
2470 fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: 0x%s -> "
2471 "(name=`%s',segbase=0x%s,start=0x%s,end=0x%s,gp=0x%s,"
2472 "length=%s,data=0x%s)\n",
2473 paddr_nz (ip), (char *)di.u.rti.name_ptr,
2474 paddr_nz (di.u.rti.segbase),
2475 paddr_nz (di.start_ip), paddr_nz (di.end_ip),
2476 paddr_nz (di.gp),
2477 paddr_u (di.u.rti.table_len),
2478 paddr_nz (di.u.rti.table_data));
2479 }
2480
2481 ret = libunwind_search_unwind_table (&as, ip, &di, pi, need_unwind_info,
2482 arg);
2483
2484 /* We no longer need the dyn info storage so free it. */
2485 xfree (buf);
2486
2487 return ret;
2488 }
2489
2490 /* Libunwind callback accessor function for cleanup. */
2491 static void
ia64_put_unwind_info(unw_addr_space_t as,unw_proc_info_t * pip,void * arg)2492 ia64_put_unwind_info (unw_addr_space_t as,
2493 unw_proc_info_t *pip, void *arg)
2494 {
2495 /* Nothing required for now. */
2496 }
2497
2498 /* Libunwind callback accessor function to get head of the dynamic
2499 unwind-info registration list. */
2500 static int
ia64_get_dyn_info_list(unw_addr_space_t as,unw_word_t * dilap,void * arg)2501 ia64_get_dyn_info_list (unw_addr_space_t as,
2502 unw_word_t *dilap, void *arg)
2503 {
2504 struct obj_section *text_sec;
2505 struct objfile *objfile;
2506 unw_word_t ip, addr;
2507 unw_dyn_info_t di;
2508 int ret;
2509
2510 if (!libunwind_is_initialized ())
2511 return -UNW_ENOINFO;
2512
2513 for (objfile = object_files; objfile; objfile = objfile->next)
2514 {
2515 void *buf = NULL;
2516
2517 text_sec = objfile->sections + SECT_OFF_TEXT (objfile);
2518 ip = text_sec->addr;
2519 ret = ia64_find_unwind_table (objfile, ip, &di, &buf);
2520 if (ret >= 0)
2521 {
2522 addr = libunwind_find_dyn_list (as, &di, arg);
2523 /* We no longer need the dyn info storage so free it. */
2524 xfree (buf);
2525
2526 if (addr)
2527 {
2528 if (gdbarch_debug >= 1)
2529 fprintf_unfiltered (gdb_stdlog,
2530 "dynamic unwind table in objfile %s "
2531 "at 0x%s (gp=0x%s)\n",
2532 bfd_get_filename (objfile->obfd),
2533 paddr_nz (addr), paddr_nz (di.gp));
2534 *dilap = addr;
2535 return 0;
2536 }
2537 }
2538 }
2539 return -UNW_ENOINFO;
2540 }
2541
2542
2543 /* Frame interface functions for libunwind. */
2544
2545 static void
ia64_libunwind_frame_this_id(struct frame_info * next_frame,void ** this_cache,struct frame_id * this_id)2546 ia64_libunwind_frame_this_id (struct frame_info *next_frame, void **this_cache,
2547 struct frame_id *this_id)
2548 {
2549 char buf[8];
2550 CORE_ADDR bsp;
2551 struct frame_id id;
2552
2553 libunwind_frame_this_id (next_frame, this_cache, &id);
2554
2555 /* We must add the bsp as the special address for frame comparison purposes. */
2556 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2557 bsp = extract_unsigned_integer (buf, 8);
2558
2559 (*this_id) = frame_id_build_special (id.stack_addr, id.code_addr, bsp);
2560
2561 if (gdbarch_debug >= 1)
2562 fprintf_unfiltered (gdb_stdlog,
2563 "libunwind frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
2564 paddr_nz (id.code_addr), paddr_nz (id.stack_addr),
2565 paddr_nz (bsp), next_frame);
2566 }
2567
2568 static void
ia64_libunwind_frame_prev_register(struct frame_info * next_frame,void ** this_cache,int regnum,int * optimizedp,enum lval_type * lvalp,CORE_ADDR * addrp,int * realnump,void * valuep)2569 ia64_libunwind_frame_prev_register (struct frame_info *next_frame,
2570 void **this_cache,
2571 int regnum, int *optimizedp,
2572 enum lval_type *lvalp, CORE_ADDR *addrp,
2573 int *realnump, void *valuep)
2574 {
2575 int reg = regnum;
2576
2577 if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
2578 reg = IA64_PR_REGNUM;
2579 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
2580 reg = IA64_UNAT_REGNUM;
2581
2582 /* Let libunwind do most of the work. */
2583 libunwind_frame_prev_register (next_frame, this_cache, reg,
2584 optimizedp, lvalp, addrp, realnump, valuep);
2585
2586 /* No more to do if the value is not supposed to be supplied. */
2587 if (!valuep)
2588 return;
2589
2590 if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
2591 {
2592 ULONGEST prN_val;
2593
2594 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
2595 {
2596 int rrb_pr = 0;
2597 ULONGEST cfm;
2598 unsigned char buf[MAX_REGISTER_SIZE];
2599
2600 /* Fetch predicate register rename base from current frame
2601 marker for this frame. */
2602 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
2603 cfm = extract_unsigned_integer (buf, 8);
2604 rrb_pr = (cfm >> 32) & 0x3f;
2605
2606 /* Adjust the register number to account for register rotation. */
2607 regnum = VP16_REGNUM
2608 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
2609 }
2610 prN_val = extract_bit_field ((unsigned char *) valuep,
2611 regnum - VP0_REGNUM, 1);
2612 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), prN_val);
2613 }
2614 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
2615 {
2616 ULONGEST unatN_val;
2617
2618 unatN_val = extract_bit_field ((unsigned char *) valuep,
2619 regnum - IA64_NAT0_REGNUM, 1);
2620 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
2621 unatN_val);
2622 }
2623 else if (regnum == IA64_BSP_REGNUM)
2624 {
2625 char cfm_valuep[MAX_REGISTER_SIZE];
2626 int cfm_optim;
2627 int cfm_realnum;
2628 enum lval_type cfm_lval;
2629 CORE_ADDR cfm_addr;
2630 CORE_ADDR bsp, prev_cfm, prev_bsp;
2631
2632 /* We want to calculate the previous bsp as the end of the previous register stack frame.
2633 This corresponds to what the hardware bsp register will be if we pop the frame
2634 back which is why we might have been called. We know that libunwind will pass us back
2635 the beginning of the current frame so we should just add sof to it. */
2636 prev_bsp = extract_unsigned_integer (valuep, 8);
2637 libunwind_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
2638 &cfm_optim, &cfm_lval, &cfm_addr, &cfm_realnum, cfm_valuep);
2639 prev_cfm = extract_unsigned_integer (cfm_valuep, 8);
2640 prev_bsp = rse_address_add (prev_bsp, (prev_cfm & 0x7f));
2641
2642 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
2643 prev_bsp);
2644 }
2645
2646 if (gdbarch_debug >= 1)
2647 fprintf_unfiltered (gdb_stdlog,
2648 "libunwind prev register <%s> is 0x%s\n",
2649 (((unsigned) regnum <= IA64_NAT127_REGNUM)
2650 ? ia64_register_names[regnum] : "r??"),
2651 paddr_nz (extract_unsigned_integer (valuep, 8)));
2652 }
2653
2654 static const struct frame_unwind ia64_libunwind_frame_unwind =
2655 {
2656 NORMAL_FRAME,
2657 ia64_libunwind_frame_this_id,
2658 ia64_libunwind_frame_prev_register
2659 };
2660
2661 static const struct frame_unwind *
ia64_libunwind_frame_sniffer(struct frame_info * next_frame)2662 ia64_libunwind_frame_sniffer (struct frame_info *next_frame)
2663 {
2664 if (libunwind_is_initialized () && libunwind_frame_sniffer (next_frame))
2665 return &ia64_libunwind_frame_unwind;
2666
2667 return NULL;
2668 }
2669
2670 /* Set of libunwind callback acccessor functions. */
2671 static unw_accessors_t ia64_unw_accessors =
2672 {
2673 ia64_find_proc_info_x,
2674 ia64_put_unwind_info,
2675 ia64_get_dyn_info_list,
2676 ia64_access_mem,
2677 ia64_access_reg,
2678 ia64_access_fpreg,
2679 /* resume */
2680 /* get_proc_name */
2681 };
2682
2683 /* Set of ia64 gdb libunwind-frame callbacks and data for generic libunwind-frame code to use. */
2684 static struct libunwind_descr ia64_libunwind_descr =
2685 {
2686 ia64_gdb2uw_regnum,
2687 ia64_uw2gdb_regnum,
2688 ia64_is_fpreg,
2689 &ia64_unw_accessors,
2690 };
2691
2692 #endif /* HAVE_LIBUNWIND_IA64_H */
2693
2694 /* Should we use DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS instead of
2695 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc and TYPE
2696 is the type (which is known to be struct, union or array). */
2697 int
ia64_use_struct_convention(int gcc_p,struct type * type)2698 ia64_use_struct_convention (int gcc_p, struct type *type)
2699 {
2700 struct type *float_elt_type;
2701
2702 /* HFAs are structures (or arrays) consisting entirely of floating
2703 point values of the same length. Up to 8 of these are returned
2704 in registers. Don't use the struct convention when this is the
2705 case. */
2706 float_elt_type = is_float_or_hfa_type (type);
2707 if (float_elt_type != NULL
2708 && TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type) <= 8)
2709 return 0;
2710
2711 /* Other structs of length 32 or less are returned in r8-r11.
2712 Don't use the struct convention for those either. */
2713 return TYPE_LENGTH (type) > 32;
2714 }
2715
2716 void
ia64_extract_return_value(struct type * type,struct regcache * regcache,void * valbuf)2717 ia64_extract_return_value (struct type *type, struct regcache *regcache, void *valbuf)
2718 {
2719 struct type *float_elt_type;
2720
2721 float_elt_type = is_float_or_hfa_type (type);
2722 if (float_elt_type != NULL)
2723 {
2724 char from[MAX_REGISTER_SIZE];
2725 int offset = 0;
2726 int regnum = IA64_FR8_REGNUM;
2727 int n = TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type);
2728
2729 while (n-- > 0)
2730 {
2731 regcache_cooked_read (regcache, regnum, from);
2732 convert_typed_floating (from, builtin_type_ia64_ext,
2733 (char *)valbuf + offset, float_elt_type);
2734 offset += TYPE_LENGTH (float_elt_type);
2735 regnum++;
2736 }
2737 }
2738 else
2739 {
2740 ULONGEST val;
2741 int offset = 0;
2742 int regnum = IA64_GR8_REGNUM;
2743 int reglen = TYPE_LENGTH (ia64_register_type (NULL, IA64_GR8_REGNUM));
2744 int n = TYPE_LENGTH (type) / reglen;
2745 int m = TYPE_LENGTH (type) % reglen;
2746
2747 while (n-- > 0)
2748 {
2749 ULONGEST val;
2750 regcache_cooked_read_unsigned (regcache, regnum, &val);
2751 memcpy ((char *)valbuf + offset, &val, reglen);
2752 offset += reglen;
2753 regnum++;
2754 }
2755
2756 if (m)
2757 {
2758 regcache_cooked_read_unsigned (regcache, regnum, &val);
2759 memcpy ((char *)valbuf + offset, &val, m);
2760 }
2761 }
2762 }
2763
2764 CORE_ADDR
ia64_extract_struct_value_address(struct regcache * regcache)2765 ia64_extract_struct_value_address (struct regcache *regcache)
2766 {
2767 error ("ia64_extract_struct_value_address called and cannot get struct value address");
2768 return 0;
2769 }
2770
2771
2772 static int
is_float_or_hfa_type_recurse(struct type * t,struct type ** etp)2773 is_float_or_hfa_type_recurse (struct type *t, struct type **etp)
2774 {
2775 switch (TYPE_CODE (t))
2776 {
2777 case TYPE_CODE_FLT:
2778 if (*etp)
2779 return TYPE_LENGTH (*etp) == TYPE_LENGTH (t);
2780 else
2781 {
2782 *etp = t;
2783 return 1;
2784 }
2785 break;
2786 case TYPE_CODE_ARRAY:
2787 return
2788 is_float_or_hfa_type_recurse (check_typedef (TYPE_TARGET_TYPE (t)),
2789 etp);
2790 break;
2791 case TYPE_CODE_STRUCT:
2792 {
2793 int i;
2794
2795 for (i = 0; i < TYPE_NFIELDS (t); i++)
2796 if (!is_float_or_hfa_type_recurse
2797 (check_typedef (TYPE_FIELD_TYPE (t, i)), etp))
2798 return 0;
2799 return 1;
2800 }
2801 break;
2802 default:
2803 return 0;
2804 break;
2805 }
2806 }
2807
2808 /* Determine if the given type is one of the floating point types or
2809 and HFA (which is a struct, array, or combination thereof whose
2810 bottom-most elements are all of the same floating point type). */
2811
2812 static struct type *
is_float_or_hfa_type(struct type * t)2813 is_float_or_hfa_type (struct type *t)
2814 {
2815 struct type *et = 0;
2816
2817 return is_float_or_hfa_type_recurse (t, &et) ? et : 0;
2818 }
2819
2820
2821 /* Return 1 if the alignment of T is such that the next even slot
2822 should be used. Return 0, if the next available slot should
2823 be used. (See section 8.5.1 of the IA-64 Software Conventions
2824 and Runtime manual). */
2825
2826 static int
slot_alignment_is_next_even(struct type * t)2827 slot_alignment_is_next_even (struct type *t)
2828 {
2829 switch (TYPE_CODE (t))
2830 {
2831 case TYPE_CODE_INT:
2832 case TYPE_CODE_FLT:
2833 if (TYPE_LENGTH (t) > 8)
2834 return 1;
2835 else
2836 return 0;
2837 case TYPE_CODE_ARRAY:
2838 return
2839 slot_alignment_is_next_even (check_typedef (TYPE_TARGET_TYPE (t)));
2840 case TYPE_CODE_STRUCT:
2841 {
2842 int i;
2843
2844 for (i = 0; i < TYPE_NFIELDS (t); i++)
2845 if (slot_alignment_is_next_even
2846 (check_typedef (TYPE_FIELD_TYPE (t, i))))
2847 return 1;
2848 return 0;
2849 }
2850 default:
2851 return 0;
2852 }
2853 }
2854
2855 /* Attempt to find (and return) the global pointer for the given
2856 function.
2857
2858 This is a rather nasty bit of code searchs for the .dynamic section
2859 in the objfile corresponding to the pc of the function we're trying
2860 to call. Once it finds the addresses at which the .dynamic section
2861 lives in the child process, it scans the Elf64_Dyn entries for a
2862 DT_PLTGOT tag. If it finds one of these, the corresponding
2863 d_un.d_ptr value is the global pointer. */
2864
2865 static CORE_ADDR
generic_elf_find_global_pointer(CORE_ADDR faddr)2866 generic_elf_find_global_pointer (CORE_ADDR faddr)
2867 {
2868 struct obj_section *faddr_sect;
2869
2870 faddr_sect = find_pc_section (faddr);
2871 if (faddr_sect != NULL)
2872 {
2873 struct obj_section *osect;
2874
2875 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
2876 {
2877 if (strcmp (osect->the_bfd_section->name, ".dynamic") == 0)
2878 break;
2879 }
2880
2881 if (osect < faddr_sect->objfile->sections_end)
2882 {
2883 CORE_ADDR addr;
2884
2885 addr = osect->addr;
2886 while (addr < osect->endaddr)
2887 {
2888 int status;
2889 LONGEST tag;
2890 char buf[8];
2891
2892 status = target_read_memory (addr, buf, sizeof (buf));
2893 if (status != 0)
2894 break;
2895 tag = extract_signed_integer (buf, sizeof (buf));
2896
2897 if (tag == DT_PLTGOT)
2898 {
2899 CORE_ADDR global_pointer;
2900
2901 status = target_read_memory (addr + 8, buf, sizeof (buf));
2902 if (status != 0)
2903 break;
2904 global_pointer = extract_unsigned_integer (buf, sizeof (buf));
2905
2906 /* The payoff... */
2907 return global_pointer;
2908 }
2909
2910 if (tag == DT_NULL)
2911 break;
2912
2913 addr += 16;
2914 }
2915 }
2916 }
2917 return 0;
2918 }
2919
2920 /* Given a function's address, attempt to find (and return) the
2921 corresponding (canonical) function descriptor. Return 0 if
2922 not found. */
2923 static CORE_ADDR
find_extant_func_descr(CORE_ADDR faddr)2924 find_extant_func_descr (CORE_ADDR faddr)
2925 {
2926 struct obj_section *faddr_sect;
2927
2928 /* Return early if faddr is already a function descriptor. */
2929 faddr_sect = find_pc_section (faddr);
2930 if (faddr_sect && strcmp (faddr_sect->the_bfd_section->name, ".opd") == 0)
2931 return faddr;
2932
2933 if (faddr_sect != NULL)
2934 {
2935 struct obj_section *osect;
2936 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
2937 {
2938 if (strcmp (osect->the_bfd_section->name, ".opd") == 0)
2939 break;
2940 }
2941
2942 if (osect < faddr_sect->objfile->sections_end)
2943 {
2944 CORE_ADDR addr;
2945
2946 addr = osect->addr;
2947 while (addr < osect->endaddr)
2948 {
2949 int status;
2950 LONGEST faddr2;
2951 char buf[8];
2952
2953 status = target_read_memory (addr, buf, sizeof (buf));
2954 if (status != 0)
2955 break;
2956 faddr2 = extract_signed_integer (buf, sizeof (buf));
2957
2958 if (faddr == faddr2)
2959 return addr;
2960
2961 addr += 16;
2962 }
2963 }
2964 }
2965 return 0;
2966 }
2967
2968 /* Attempt to find a function descriptor corresponding to the
2969 given address. If none is found, construct one on the
2970 stack using the address at fdaptr. */
2971
2972 static CORE_ADDR
find_func_descr(CORE_ADDR faddr,CORE_ADDR * fdaptr)2973 find_func_descr (CORE_ADDR faddr, CORE_ADDR *fdaptr)
2974 {
2975 CORE_ADDR fdesc;
2976
2977 fdesc = find_extant_func_descr (faddr);
2978
2979 if (fdesc == 0)
2980 {
2981 CORE_ADDR global_pointer;
2982 char buf[16];
2983
2984 fdesc = *fdaptr;
2985 *fdaptr += 16;
2986
2987 global_pointer = FIND_GLOBAL_POINTER (faddr);
2988
2989 if (global_pointer == 0)
2990 global_pointer = read_register (IA64_GR1_REGNUM);
2991
2992 store_unsigned_integer (buf, 8, faddr);
2993 store_unsigned_integer (buf + 8, 8, global_pointer);
2994
2995 write_memory (fdesc, buf, 16);
2996 }
2997
2998 return fdesc;
2999 }
3000
3001 /* Use the following routine when printing out function pointers
3002 so the user can see the function address rather than just the
3003 function descriptor. */
3004 static CORE_ADDR
ia64_convert_from_func_ptr_addr(struct gdbarch * gdbarch,CORE_ADDR addr,struct target_ops * targ)3005 ia64_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr,
3006 struct target_ops *targ)
3007 {
3008 struct obj_section *s;
3009
3010 s = find_pc_section (addr);
3011
3012 /* check if ADDR points to a function descriptor. */
3013 if (s && strcmp (s->the_bfd_section->name, ".opd") == 0)
3014 return read_memory_unsigned_integer (addr, 8);
3015
3016 return addr;
3017 }
3018
3019 static CORE_ADDR
ia64_frame_align(struct gdbarch * gdbarch,CORE_ADDR sp)3020 ia64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
3021 {
3022 return sp & ~0xfLL;
3023 }
3024
3025 static CORE_ADDR
ia64_push_dummy_call(struct gdbarch * gdbarch,struct value * function,struct regcache * regcache,CORE_ADDR bp_addr,int nargs,struct value ** args,CORE_ADDR sp,int struct_return,CORE_ADDR struct_addr)3026 ia64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3027 struct regcache *regcache, CORE_ADDR bp_addr,
3028 int nargs, struct value **args, CORE_ADDR sp,
3029 int struct_return, CORE_ADDR struct_addr)
3030 {
3031 int argno;
3032 struct value *arg;
3033 struct type *type;
3034 int len, argoffset;
3035 int nslots, rseslots, memslots, slotnum, nfuncargs;
3036 int floatreg;
3037 CORE_ADDR bsp, cfm, pfs, new_bsp, funcdescaddr, pc, global_pointer;
3038 CORE_ADDR func_addr = find_function_addr (function, NULL);
3039
3040 nslots = 0;
3041 nfuncargs = 0;
3042 /* Count the number of slots needed for the arguments. */
3043 for (argno = 0; argno < nargs; argno++)
3044 {
3045 arg = args[argno];
3046 type = check_typedef (VALUE_TYPE (arg));
3047 len = TYPE_LENGTH (type);
3048
3049 if ((nslots & 1) && slot_alignment_is_next_even (type))
3050 nslots++;
3051
3052 if (TYPE_CODE (type) == TYPE_CODE_FUNC)
3053 nfuncargs++;
3054
3055 nslots += (len + 7) / 8;
3056 }
3057
3058 /* Divvy up the slots between the RSE and the memory stack. */
3059 rseslots = (nslots > 8) ? 8 : nslots;
3060 memslots = nslots - rseslots;
3061
3062 /* Allocate a new RSE frame. */
3063 cfm = read_register (IA64_CFM_REGNUM);
3064
3065 bsp = read_register (IA64_BSP_REGNUM);
3066 new_bsp = rse_address_add (bsp, rseslots);
3067 write_register (IA64_BSP_REGNUM, new_bsp);
3068
3069 pfs = read_register (IA64_PFS_REGNUM);
3070 pfs &= 0xc000000000000000LL;
3071 pfs |= (cfm & 0xffffffffffffLL);
3072 write_register (IA64_PFS_REGNUM, pfs);
3073
3074 cfm &= 0xc000000000000000LL;
3075 cfm |= rseslots;
3076 write_register (IA64_CFM_REGNUM, cfm);
3077
3078 /* We will attempt to find function descriptors in the .opd segment,
3079 but if we can't we'll construct them ourselves. That being the
3080 case, we'll need to reserve space on the stack for them. */
3081 funcdescaddr = sp - nfuncargs * 16;
3082 funcdescaddr &= ~0xfLL;
3083
3084 /* Adjust the stack pointer to it's new value. The calling conventions
3085 require us to have 16 bytes of scratch, plus whatever space is
3086 necessary for the memory slots and our function descriptors. */
3087 sp = sp - 16 - (memslots + nfuncargs) * 8;
3088 sp &= ~0xfLL; /* Maintain 16 byte alignment. */
3089
3090 /* Place the arguments where they belong. The arguments will be
3091 either placed in the RSE backing store or on the memory stack.
3092 In addition, floating point arguments or HFAs are placed in
3093 floating point registers. */
3094 slotnum = 0;
3095 floatreg = IA64_FR8_REGNUM;
3096 for (argno = 0; argno < nargs; argno++)
3097 {
3098 struct type *float_elt_type;
3099
3100 arg = args[argno];
3101 type = check_typedef (VALUE_TYPE (arg));
3102 len = TYPE_LENGTH (type);
3103
3104 /* Special handling for function parameters. */
3105 if (len == 8
3106 && TYPE_CODE (type) == TYPE_CODE_PTR
3107 && TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)
3108 {
3109 char val_buf[8];
3110
3111 store_unsigned_integer (val_buf, 8,
3112 find_func_descr (extract_unsigned_integer (VALUE_CONTENTS (arg), 8),
3113 &funcdescaddr));
3114 if (slotnum < rseslots)
3115 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
3116 else
3117 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
3118 slotnum++;
3119 continue;
3120 }
3121
3122 /* Normal slots. */
3123
3124 /* Skip odd slot if necessary... */
3125 if ((slotnum & 1) && slot_alignment_is_next_even (type))
3126 slotnum++;
3127
3128 argoffset = 0;
3129 while (len > 0)
3130 {
3131 char val_buf[8];
3132
3133 memset (val_buf, 0, 8);
3134 memcpy (val_buf, VALUE_CONTENTS (arg) + argoffset, (len > 8) ? 8 : len);
3135
3136 if (slotnum < rseslots)
3137 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
3138 else
3139 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
3140
3141 argoffset += 8;
3142 len -= 8;
3143 slotnum++;
3144 }
3145
3146 /* Handle floating point types (including HFAs). */
3147 float_elt_type = is_float_or_hfa_type (type);
3148 if (float_elt_type != NULL)
3149 {
3150 argoffset = 0;
3151 len = TYPE_LENGTH (type);
3152 while (len > 0 && floatreg < IA64_FR16_REGNUM)
3153 {
3154 char to[MAX_REGISTER_SIZE];
3155 convert_typed_floating (VALUE_CONTENTS (arg) + argoffset, float_elt_type,
3156 to, builtin_type_ia64_ext);
3157 regcache_cooked_write (regcache, floatreg, (void *)to);
3158 floatreg++;
3159 argoffset += TYPE_LENGTH (float_elt_type);
3160 len -= TYPE_LENGTH (float_elt_type);
3161 }
3162 }
3163 }
3164
3165 /* Store the struct return value in r8 if necessary. */
3166 if (struct_return)
3167 {
3168 regcache_cooked_write_unsigned (regcache, IA64_GR8_REGNUM, (ULONGEST)struct_addr);
3169 }
3170
3171 global_pointer = FIND_GLOBAL_POINTER (func_addr);
3172
3173 if (global_pointer != 0)
3174 write_register (IA64_GR1_REGNUM, global_pointer);
3175
3176 write_register (IA64_BR0_REGNUM, bp_addr);
3177
3178 write_register (sp_regnum, sp);
3179
3180 return sp;
3181 }
3182
3183 static struct frame_id
ia64_unwind_dummy_id(struct gdbarch * gdbarch,struct frame_info * next_frame)3184 ia64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
3185 {
3186 char buf[8];
3187 CORE_ADDR sp, bsp;
3188
3189 frame_unwind_register (next_frame, sp_regnum, buf);
3190 sp = extract_unsigned_integer (buf, 8);
3191
3192 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
3193 bsp = extract_unsigned_integer (buf, 8);
3194
3195 if (gdbarch_debug >= 1)
3196 fprintf_unfiltered (gdb_stdlog,
3197 "dummy frame id: code 0x%s, stack 0x%s, special 0x%s\n",
3198 paddr_nz (frame_pc_unwind (next_frame)),
3199 paddr_nz (sp), paddr_nz (bsp));
3200
3201 return frame_id_build_special (sp, frame_pc_unwind (next_frame), bsp);
3202 }
3203
3204 static CORE_ADDR
ia64_unwind_pc(struct gdbarch * gdbarch,struct frame_info * next_frame)3205 ia64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
3206 {
3207 char buf[8];
3208 CORE_ADDR ip, psr, pc;
3209
3210 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
3211 ip = extract_unsigned_integer (buf, 8);
3212 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
3213 psr = extract_unsigned_integer (buf, 8);
3214
3215 pc = (ip & ~0xf) | ((psr >> 41) & 3);
3216 return pc;
3217 }
3218
3219 static void
ia64_store_return_value(struct type * type,struct regcache * regcache,const void * valbuf)3220 ia64_store_return_value (struct type *type, struct regcache *regcache, const void *valbuf)
3221 {
3222 if (TYPE_CODE (type) == TYPE_CODE_FLT)
3223 {
3224 char to[MAX_REGISTER_SIZE];
3225 convert_typed_floating (valbuf, type, to, builtin_type_ia64_ext);
3226 regcache_cooked_write (regcache, IA64_FR8_REGNUM, (void *)to);
3227 target_store_registers (IA64_FR8_REGNUM);
3228 }
3229 else
3230 regcache_cooked_write (regcache, IA64_GR8_REGNUM, valbuf);
3231 }
3232
3233 static void
ia64_remote_translate_xfer_address(struct gdbarch * gdbarch,struct regcache * regcache,CORE_ADDR memaddr,int nr_bytes,CORE_ADDR * targ_addr,int * targ_len)3234 ia64_remote_translate_xfer_address (struct gdbarch *gdbarch,
3235 struct regcache *regcache,
3236 CORE_ADDR memaddr, int nr_bytes,
3237 CORE_ADDR *targ_addr, int *targ_len)
3238 {
3239 *targ_addr = memaddr;
3240 *targ_len = nr_bytes;
3241 }
3242
3243 static int
ia64_print_insn(bfd_vma memaddr,struct disassemble_info * info)3244 ia64_print_insn (bfd_vma memaddr, struct disassemble_info *info)
3245 {
3246 info->bytes_per_line = SLOT_MULTIPLIER;
3247 return print_insn_ia64 (memaddr, info);
3248 }
3249
3250 static struct gdbarch *
ia64_gdbarch_init(struct gdbarch_info info,struct gdbarch_list * arches)3251 ia64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3252 {
3253 struct gdbarch *gdbarch;
3254 struct gdbarch_tdep *tdep;
3255
3256 /* If there is already a candidate, use it. */
3257 arches = gdbarch_list_lookup_by_info (arches, &info);
3258 if (arches != NULL)
3259 return arches->gdbarch;
3260
3261 tdep = xmalloc (sizeof (struct gdbarch_tdep));
3262 gdbarch = gdbarch_alloc (&info, tdep);
3263
3264 /* Set the method of obtaining the sigcontext addresses at which
3265 registers are saved. The method of checking to see if
3266 native_find_global_pointer is nonzero to indicate that we're
3267 on AIX is kind of hokey, but I can't think of a better way
3268 to do it. */
3269 if (info.osabi == GDB_OSABI_LINUX)
3270 tdep->sigcontext_register_address = ia64_linux_sigcontext_register_address;
3271 else if (native_find_global_pointer != 0)
3272 tdep->sigcontext_register_address = ia64_aix_sigcontext_register_address;
3273 else
3274 tdep->sigcontext_register_address = 0;
3275
3276 /* We know that GNU/Linux won't have to resort to the
3277 native_find_global_pointer hackery. But that's the only one we
3278 know about so far, so if native_find_global_pointer is set to
3279 something non-zero, then use it. Otherwise fall back to using
3280 generic_elf_find_global_pointer. This arrangement should (in
3281 theory) allow us to cross debug GNU/Linux binaries from an AIX
3282 machine. */
3283 if (info.osabi == GDB_OSABI_LINUX)
3284 tdep->find_global_pointer = generic_elf_find_global_pointer;
3285 else if (native_find_global_pointer != 0)
3286 tdep->find_global_pointer = native_find_global_pointer;
3287 else
3288 tdep->find_global_pointer = generic_elf_find_global_pointer;
3289
3290 /* Define the ia64 floating-point format to gdb. */
3291 builtin_type_ia64_ext =
3292 init_type (TYPE_CODE_FLT, 128 / 8,
3293 0, "builtin_type_ia64_ext", NULL);
3294 TYPE_FLOATFORMAT (builtin_type_ia64_ext) = &floatformat_ia64_ext;
3295
3296 /* According to the ia64 specs, instructions that store long double
3297 floats in memory use a long-double format different than that
3298 used in the floating registers. The memory format matches the
3299 x86 extended float format which is 80 bits. An OS may choose to
3300 use this format (e.g. GNU/Linux) or choose to use a different
3301 format for storing long doubles (e.g. HPUX). In the latter case,
3302 the setting of the format may be moved/overridden in an
3303 OS-specific tdep file. */
3304 set_gdbarch_long_double_format (gdbarch, &floatformat_i387_ext);
3305
3306 set_gdbarch_short_bit (gdbarch, 16);
3307 set_gdbarch_int_bit (gdbarch, 32);
3308 set_gdbarch_long_bit (gdbarch, 64);
3309 set_gdbarch_long_long_bit (gdbarch, 64);
3310 set_gdbarch_float_bit (gdbarch, 32);
3311 set_gdbarch_double_bit (gdbarch, 64);
3312 set_gdbarch_long_double_bit (gdbarch, 128);
3313 set_gdbarch_ptr_bit (gdbarch, 64);
3314
3315 set_gdbarch_num_regs (gdbarch, NUM_IA64_RAW_REGS);
3316 set_gdbarch_num_pseudo_regs (gdbarch, LAST_PSEUDO_REGNUM - FIRST_PSEUDO_REGNUM);
3317 set_gdbarch_sp_regnum (gdbarch, sp_regnum);
3318 set_gdbarch_fp0_regnum (gdbarch, IA64_FR0_REGNUM);
3319
3320 set_gdbarch_register_name (gdbarch, ia64_register_name);
3321 /* FIXME: Following interface should not be needed, however, without it recurse.exp
3322 gets a number of extra failures. */
3323 set_gdbarch_deprecated_register_size (gdbarch, 8);
3324 set_gdbarch_register_type (gdbarch, ia64_register_type);
3325
3326 set_gdbarch_pseudo_register_read (gdbarch, ia64_pseudo_register_read);
3327 set_gdbarch_pseudo_register_write (gdbarch, ia64_pseudo_register_write);
3328 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, ia64_dwarf_reg_to_regnum);
3329 set_gdbarch_register_reggroup_p (gdbarch, ia64_register_reggroup_p);
3330 set_gdbarch_convert_register_p (gdbarch, ia64_convert_register_p);
3331 set_gdbarch_register_to_value (gdbarch, ia64_register_to_value);
3332 set_gdbarch_value_to_register (gdbarch, ia64_value_to_register);
3333
3334 set_gdbarch_skip_prologue (gdbarch, ia64_skip_prologue);
3335
3336 set_gdbarch_deprecated_use_struct_convention (gdbarch, ia64_use_struct_convention);
3337 set_gdbarch_extract_return_value (gdbarch, ia64_extract_return_value);
3338
3339 set_gdbarch_store_return_value (gdbarch, ia64_store_return_value);
3340 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, ia64_extract_struct_value_address);
3341
3342 set_gdbarch_memory_insert_breakpoint (gdbarch, ia64_memory_insert_breakpoint);
3343 set_gdbarch_memory_remove_breakpoint (gdbarch, ia64_memory_remove_breakpoint);
3344 set_gdbarch_breakpoint_from_pc (gdbarch, ia64_breakpoint_from_pc);
3345 set_gdbarch_read_pc (gdbarch, ia64_read_pc);
3346 if (info.osabi == GDB_OSABI_LINUX)
3347 set_gdbarch_write_pc (gdbarch, ia64_linux_write_pc);
3348 else
3349 set_gdbarch_write_pc (gdbarch, ia64_write_pc);
3350
3351 /* Settings for calling functions in the inferior. */
3352 set_gdbarch_push_dummy_call (gdbarch, ia64_push_dummy_call);
3353 set_gdbarch_frame_align (gdbarch, ia64_frame_align);
3354 set_gdbarch_unwind_dummy_id (gdbarch, ia64_unwind_dummy_id);
3355
3356 set_gdbarch_unwind_pc (gdbarch, ia64_unwind_pc);
3357 frame_unwind_append_sniffer (gdbarch, ia64_sigtramp_frame_sniffer);
3358 #ifdef HAVE_LIBUNWIND_IA64_H
3359 frame_unwind_append_sniffer (gdbarch, ia64_libunwind_frame_sniffer);
3360 libunwind_frame_set_descr (gdbarch, &ia64_libunwind_descr);
3361 #endif
3362 frame_unwind_append_sniffer (gdbarch, ia64_frame_sniffer);
3363 frame_base_set_default (gdbarch, &ia64_frame_base);
3364
3365 /* Settings that should be unnecessary. */
3366 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3367
3368 set_gdbarch_remote_translate_xfer_address (
3369 gdbarch, ia64_remote_translate_xfer_address);
3370
3371 set_gdbarch_print_insn (gdbarch, ia64_print_insn);
3372 set_gdbarch_convert_from_func_ptr_addr (gdbarch, ia64_convert_from_func_ptr_addr);
3373
3374 return gdbarch;
3375 }
3376
3377 extern initialize_file_ftype _initialize_ia64_tdep; /* -Wmissing-prototypes */
3378
3379 void
_initialize_ia64_tdep(void)3380 _initialize_ia64_tdep (void)
3381 {
3382 register_gdbarch_init (bfd_arch_ia64, ia64_gdbarch_init);
3383 }
3384