1 /* $NetBSD: radeon_ni.c,v 1.3 2021/12/18 23:45:43 riastradh Exp $ */
2
3 /*
4 * Copyright 2010 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Alex Deucher
25 */
26
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: radeon_ni.c,v 1.3 2021/12/18 23:45:43 riastradh Exp $");
29
30 #include <linux/firmware.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/slab.h>
34
35 #include <drm/radeon_drm.h>
36
37 #include "atom.h"
38 #include "cayman_blit_shaders.h"
39 #include "clearstate_cayman.h"
40 #include "ni_reg.h"
41 #include "nid.h"
42 #include "radeon.h"
43 #include "radeon_asic.h"
44 #include "radeon_audio.h"
45 #include "radeon_ucode.h"
46
47 #include <linux/nbsd-namespace.h>
48
49 /*
50 * Indirect registers accessor
51 */
tn_smc_rreg(struct radeon_device * rdev,u32 reg)52 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
53 {
54 unsigned long flags;
55 u32 r;
56
57 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
58 WREG32(TN_SMC_IND_INDEX_0, (reg));
59 r = RREG32(TN_SMC_IND_DATA_0);
60 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
61 return r;
62 }
63
tn_smc_wreg(struct radeon_device * rdev,u32 reg,u32 v)64 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
65 {
66 unsigned long flags;
67
68 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
69 WREG32(TN_SMC_IND_INDEX_0, (reg));
70 WREG32(TN_SMC_IND_DATA_0, (v));
71 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
72 }
73
74 static const u32 tn_rlc_save_restore_register_list[] =
75 {
76 0x98fc,
77 0x98f0,
78 0x9834,
79 0x9838,
80 0x9870,
81 0x9874,
82 0x8a14,
83 0x8b24,
84 0x8bcc,
85 0x8b10,
86 0x8c30,
87 0x8d00,
88 0x8d04,
89 0x8c00,
90 0x8c04,
91 0x8c10,
92 0x8c14,
93 0x8d8c,
94 0x8cf0,
95 0x8e38,
96 0x9508,
97 0x9688,
98 0x9608,
99 0x960c,
100 0x9610,
101 0x9614,
102 0x88c4,
103 0x8978,
104 0x88d4,
105 0x900c,
106 0x9100,
107 0x913c,
108 0x90e8,
109 0x9354,
110 0xa008,
111 0x98f8,
112 0x9148,
113 0x914c,
114 0x3f94,
115 0x98f4,
116 0x9b7c,
117 0x3f8c,
118 0x8950,
119 0x8954,
120 0x8a18,
121 0x8b28,
122 0x9144,
123 0x3f90,
124 0x915c,
125 0x9160,
126 0x9178,
127 0x917c,
128 0x9180,
129 0x918c,
130 0x9190,
131 0x9194,
132 0x9198,
133 0x919c,
134 0x91a8,
135 0x91ac,
136 0x91b0,
137 0x91b4,
138 0x91b8,
139 0x91c4,
140 0x91c8,
141 0x91cc,
142 0x91d0,
143 0x91d4,
144 0x91e0,
145 0x91e4,
146 0x91ec,
147 0x91f0,
148 0x91f4,
149 0x9200,
150 0x9204,
151 0x929c,
152 0x8030,
153 0x9150,
154 0x9a60,
155 0x920c,
156 0x9210,
157 0x9228,
158 0x922c,
159 0x9244,
160 0x9248,
161 0x91e8,
162 0x9294,
163 0x9208,
164 0x9224,
165 0x9240,
166 0x9220,
167 0x923c,
168 0x9258,
169 0x9744,
170 0xa200,
171 0xa204,
172 0xa208,
173 0xa20c,
174 0x8d58,
175 0x9030,
176 0x9034,
177 0x9038,
178 0x903c,
179 0x9040,
180 0x9654,
181 0x897c,
182 0xa210,
183 0xa214,
184 0x9868,
185 0xa02c,
186 0x9664,
187 0x9698,
188 0x949c,
189 0x8e10,
190 0x8e18,
191 0x8c50,
192 0x8c58,
193 0x8c60,
194 0x8c68,
195 0x89b4,
196 0x9830,
197 0x802c,
198 };
199
200 extern bool evergreen_is_display_hung(struct radeon_device *rdev);
201 extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
202 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
203 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
204 extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
205 extern void evergreen_mc_program(struct radeon_device *rdev);
206 extern void evergreen_irq_suspend(struct radeon_device *rdev);
207 extern int evergreen_mc_init(struct radeon_device *rdev);
208 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
209 extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
210 extern void evergreen_program_aspm(struct radeon_device *rdev);
211 extern void sumo_rlc_fini(struct radeon_device *rdev);
212 extern int sumo_rlc_init(struct radeon_device *rdev);
213 extern void evergreen_gpu_pci_config_reset(struct radeon_device *rdev);
214
215 /* Firmware Names */
216 MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
217 MODULE_FIRMWARE("radeon/BARTS_me.bin");
218 MODULE_FIRMWARE("radeon/BARTS_mc.bin");
219 MODULE_FIRMWARE("radeon/BARTS_smc.bin");
220 MODULE_FIRMWARE("radeon/BTC_rlc.bin");
221 MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
222 MODULE_FIRMWARE("radeon/TURKS_me.bin");
223 MODULE_FIRMWARE("radeon/TURKS_mc.bin");
224 MODULE_FIRMWARE("radeon/TURKS_smc.bin");
225 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
226 MODULE_FIRMWARE("radeon/CAICOS_me.bin");
227 MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
228 MODULE_FIRMWARE("radeon/CAICOS_smc.bin");
229 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
230 MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
231 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
232 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
233 MODULE_FIRMWARE("radeon/CAYMAN_smc.bin");
234 MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
235 MODULE_FIRMWARE("radeon/ARUBA_me.bin");
236 MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
237
238
239 static const u32 cayman_golden_registers2[] =
240 {
241 0x3e5c, 0xffffffff, 0x00000000,
242 0x3e48, 0xffffffff, 0x00000000,
243 0x3e4c, 0xffffffff, 0x00000000,
244 0x3e64, 0xffffffff, 0x00000000,
245 0x3e50, 0xffffffff, 0x00000000,
246 0x3e60, 0xffffffff, 0x00000000
247 };
248
249 static const u32 cayman_golden_registers[] =
250 {
251 0x5eb4, 0xffffffff, 0x00000002,
252 0x5e78, 0x8f311ff1, 0x001000f0,
253 0x3f90, 0xffff0000, 0xff000000,
254 0x9148, 0xffff0000, 0xff000000,
255 0x3f94, 0xffff0000, 0xff000000,
256 0x914c, 0xffff0000, 0xff000000,
257 0xc78, 0x00000080, 0x00000080,
258 0xbd4, 0x70073777, 0x00011003,
259 0xd02c, 0xbfffff1f, 0x08421000,
260 0xd0b8, 0x73773777, 0x02011003,
261 0x5bc0, 0x00200000, 0x50100000,
262 0x98f8, 0x33773777, 0x02011003,
263 0x98fc, 0xffffffff, 0x76541032,
264 0x7030, 0x31000311, 0x00000011,
265 0x2f48, 0x33773777, 0x42010001,
266 0x6b28, 0x00000010, 0x00000012,
267 0x7728, 0x00000010, 0x00000012,
268 0x10328, 0x00000010, 0x00000012,
269 0x10f28, 0x00000010, 0x00000012,
270 0x11b28, 0x00000010, 0x00000012,
271 0x12728, 0x00000010, 0x00000012,
272 0x240c, 0x000007ff, 0x00000000,
273 0x8a14, 0xf000001f, 0x00000007,
274 0x8b24, 0x3fff3fff, 0x00ff0fff,
275 0x8b10, 0x0000ff0f, 0x00000000,
276 0x28a4c, 0x07ffffff, 0x06000000,
277 0x10c, 0x00000001, 0x00010003,
278 0xa02c, 0xffffffff, 0x0000009b,
279 0x913c, 0x0000010f, 0x01000100,
280 0x8c04, 0xf8ff00ff, 0x40600060,
281 0x28350, 0x00000f01, 0x00000000,
282 0x9508, 0x3700001f, 0x00000002,
283 0x960c, 0xffffffff, 0x54763210,
284 0x88c4, 0x001f3ae3, 0x00000082,
285 0x88d0, 0xffffffff, 0x0f40df40,
286 0x88d4, 0x0000001f, 0x00000010,
287 0x8974, 0xffffffff, 0x00000000
288 };
289
290 static const u32 dvst_golden_registers2[] =
291 {
292 0x8f8, 0xffffffff, 0,
293 0x8fc, 0x00380000, 0,
294 0x8f8, 0xffffffff, 1,
295 0x8fc, 0x0e000000, 0
296 };
297
298 static const u32 dvst_golden_registers[] =
299 {
300 0x690, 0x3fff3fff, 0x20c00033,
301 0x918c, 0x0fff0fff, 0x00010006,
302 0x91a8, 0x0fff0fff, 0x00010006,
303 0x9150, 0xffffdfff, 0x6e944040,
304 0x917c, 0x0fff0fff, 0x00030002,
305 0x9198, 0x0fff0fff, 0x00030002,
306 0x915c, 0x0fff0fff, 0x00010000,
307 0x3f90, 0xffff0001, 0xff000000,
308 0x9178, 0x0fff0fff, 0x00070000,
309 0x9194, 0x0fff0fff, 0x00070000,
310 0x9148, 0xffff0001, 0xff000000,
311 0x9190, 0x0fff0fff, 0x00090008,
312 0x91ac, 0x0fff0fff, 0x00090008,
313 0x3f94, 0xffff0000, 0xff000000,
314 0x914c, 0xffff0000, 0xff000000,
315 0x929c, 0x00000fff, 0x00000001,
316 0x55e4, 0xff607fff, 0xfc000100,
317 0x8a18, 0xff000fff, 0x00000100,
318 0x8b28, 0xff000fff, 0x00000100,
319 0x9144, 0xfffc0fff, 0x00000100,
320 0x6ed8, 0x00010101, 0x00010000,
321 0x9830, 0xffffffff, 0x00000000,
322 0x9834, 0xf00fffff, 0x00000400,
323 0x9838, 0xfffffffe, 0x00000000,
324 0xd0c0, 0xff000fff, 0x00000100,
325 0xd02c, 0xbfffff1f, 0x08421000,
326 0xd0b8, 0x73773777, 0x12010001,
327 0x5bb0, 0x000000f0, 0x00000070,
328 0x98f8, 0x73773777, 0x12010001,
329 0x98fc, 0xffffffff, 0x00000010,
330 0x9b7c, 0x00ff0000, 0x00fc0000,
331 0x8030, 0x00001f0f, 0x0000100a,
332 0x2f48, 0x73773777, 0x12010001,
333 0x2408, 0x00030000, 0x000c007f,
334 0x8a14, 0xf000003f, 0x00000007,
335 0x8b24, 0x3fff3fff, 0x00ff0fff,
336 0x8b10, 0x0000ff0f, 0x00000000,
337 0x28a4c, 0x07ffffff, 0x06000000,
338 0x4d8, 0x00000fff, 0x00000100,
339 0xa008, 0xffffffff, 0x00010000,
340 0x913c, 0xffff03ff, 0x01000100,
341 0x8c00, 0x000000ff, 0x00000003,
342 0x8c04, 0xf8ff00ff, 0x40600060,
343 0x8cf0, 0x1fff1fff, 0x08e00410,
344 0x28350, 0x00000f01, 0x00000000,
345 0x9508, 0xf700071f, 0x00000002,
346 0x960c, 0xffffffff, 0x54763210,
347 0x20ef8, 0x01ff01ff, 0x00000002,
348 0x20e98, 0xfffffbff, 0x00200000,
349 0x2015c, 0xffffffff, 0x00000f40,
350 0x88c4, 0x001f3ae3, 0x00000082,
351 0x8978, 0x3fffffff, 0x04050140,
352 0x88d4, 0x0000001f, 0x00000010,
353 0x8974, 0xffffffff, 0x00000000
354 };
355
356 static const u32 scrapper_golden_registers[] =
357 {
358 0x690, 0x3fff3fff, 0x20c00033,
359 0x918c, 0x0fff0fff, 0x00010006,
360 0x918c, 0x0fff0fff, 0x00010006,
361 0x91a8, 0x0fff0fff, 0x00010006,
362 0x91a8, 0x0fff0fff, 0x00010006,
363 0x9150, 0xffffdfff, 0x6e944040,
364 0x9150, 0xffffdfff, 0x6e944040,
365 0x917c, 0x0fff0fff, 0x00030002,
366 0x917c, 0x0fff0fff, 0x00030002,
367 0x9198, 0x0fff0fff, 0x00030002,
368 0x9198, 0x0fff0fff, 0x00030002,
369 0x915c, 0x0fff0fff, 0x00010000,
370 0x915c, 0x0fff0fff, 0x00010000,
371 0x3f90, 0xffff0001, 0xff000000,
372 0x3f90, 0xffff0001, 0xff000000,
373 0x9178, 0x0fff0fff, 0x00070000,
374 0x9178, 0x0fff0fff, 0x00070000,
375 0x9194, 0x0fff0fff, 0x00070000,
376 0x9194, 0x0fff0fff, 0x00070000,
377 0x9148, 0xffff0001, 0xff000000,
378 0x9148, 0xffff0001, 0xff000000,
379 0x9190, 0x0fff0fff, 0x00090008,
380 0x9190, 0x0fff0fff, 0x00090008,
381 0x91ac, 0x0fff0fff, 0x00090008,
382 0x91ac, 0x0fff0fff, 0x00090008,
383 0x3f94, 0xffff0000, 0xff000000,
384 0x3f94, 0xffff0000, 0xff000000,
385 0x914c, 0xffff0000, 0xff000000,
386 0x914c, 0xffff0000, 0xff000000,
387 0x929c, 0x00000fff, 0x00000001,
388 0x929c, 0x00000fff, 0x00000001,
389 0x55e4, 0xff607fff, 0xfc000100,
390 0x8a18, 0xff000fff, 0x00000100,
391 0x8a18, 0xff000fff, 0x00000100,
392 0x8b28, 0xff000fff, 0x00000100,
393 0x8b28, 0xff000fff, 0x00000100,
394 0x9144, 0xfffc0fff, 0x00000100,
395 0x9144, 0xfffc0fff, 0x00000100,
396 0x6ed8, 0x00010101, 0x00010000,
397 0x9830, 0xffffffff, 0x00000000,
398 0x9830, 0xffffffff, 0x00000000,
399 0x9834, 0xf00fffff, 0x00000400,
400 0x9834, 0xf00fffff, 0x00000400,
401 0x9838, 0xfffffffe, 0x00000000,
402 0x9838, 0xfffffffe, 0x00000000,
403 0xd0c0, 0xff000fff, 0x00000100,
404 0xd02c, 0xbfffff1f, 0x08421000,
405 0xd02c, 0xbfffff1f, 0x08421000,
406 0xd0b8, 0x73773777, 0x12010001,
407 0xd0b8, 0x73773777, 0x12010001,
408 0x5bb0, 0x000000f0, 0x00000070,
409 0x98f8, 0x73773777, 0x12010001,
410 0x98f8, 0x73773777, 0x12010001,
411 0x98fc, 0xffffffff, 0x00000010,
412 0x98fc, 0xffffffff, 0x00000010,
413 0x9b7c, 0x00ff0000, 0x00fc0000,
414 0x9b7c, 0x00ff0000, 0x00fc0000,
415 0x8030, 0x00001f0f, 0x0000100a,
416 0x8030, 0x00001f0f, 0x0000100a,
417 0x2f48, 0x73773777, 0x12010001,
418 0x2f48, 0x73773777, 0x12010001,
419 0x2408, 0x00030000, 0x000c007f,
420 0x8a14, 0xf000003f, 0x00000007,
421 0x8a14, 0xf000003f, 0x00000007,
422 0x8b24, 0x3fff3fff, 0x00ff0fff,
423 0x8b24, 0x3fff3fff, 0x00ff0fff,
424 0x8b10, 0x0000ff0f, 0x00000000,
425 0x8b10, 0x0000ff0f, 0x00000000,
426 0x28a4c, 0x07ffffff, 0x06000000,
427 0x28a4c, 0x07ffffff, 0x06000000,
428 0x4d8, 0x00000fff, 0x00000100,
429 0x4d8, 0x00000fff, 0x00000100,
430 0xa008, 0xffffffff, 0x00010000,
431 0xa008, 0xffffffff, 0x00010000,
432 0x913c, 0xffff03ff, 0x01000100,
433 0x913c, 0xffff03ff, 0x01000100,
434 0x90e8, 0x001fffff, 0x010400c0,
435 0x8c00, 0x000000ff, 0x00000003,
436 0x8c00, 0x000000ff, 0x00000003,
437 0x8c04, 0xf8ff00ff, 0x40600060,
438 0x8c04, 0xf8ff00ff, 0x40600060,
439 0x8c30, 0x0000000f, 0x00040005,
440 0x8cf0, 0x1fff1fff, 0x08e00410,
441 0x8cf0, 0x1fff1fff, 0x08e00410,
442 0x900c, 0x00ffffff, 0x0017071f,
443 0x28350, 0x00000f01, 0x00000000,
444 0x28350, 0x00000f01, 0x00000000,
445 0x9508, 0xf700071f, 0x00000002,
446 0x9508, 0xf700071f, 0x00000002,
447 0x9688, 0x00300000, 0x0017000f,
448 0x960c, 0xffffffff, 0x54763210,
449 0x960c, 0xffffffff, 0x54763210,
450 0x20ef8, 0x01ff01ff, 0x00000002,
451 0x20e98, 0xfffffbff, 0x00200000,
452 0x2015c, 0xffffffff, 0x00000f40,
453 0x88c4, 0x001f3ae3, 0x00000082,
454 0x88c4, 0x001f3ae3, 0x00000082,
455 0x8978, 0x3fffffff, 0x04050140,
456 0x8978, 0x3fffffff, 0x04050140,
457 0x88d4, 0x0000001f, 0x00000010,
458 0x88d4, 0x0000001f, 0x00000010,
459 0x8974, 0xffffffff, 0x00000000,
460 0x8974, 0xffffffff, 0x00000000
461 };
462
ni_init_golden_registers(struct radeon_device * rdev)463 static void ni_init_golden_registers(struct radeon_device *rdev)
464 {
465 switch (rdev->family) {
466 case CHIP_CAYMAN:
467 radeon_program_register_sequence(rdev,
468 cayman_golden_registers,
469 (const u32)ARRAY_SIZE(cayman_golden_registers));
470 radeon_program_register_sequence(rdev,
471 cayman_golden_registers2,
472 (const u32)ARRAY_SIZE(cayman_golden_registers2));
473 break;
474 case CHIP_ARUBA:
475 if ((rdev->pdev->device == 0x9900) ||
476 (rdev->pdev->device == 0x9901) ||
477 (rdev->pdev->device == 0x9903) ||
478 (rdev->pdev->device == 0x9904) ||
479 (rdev->pdev->device == 0x9905) ||
480 (rdev->pdev->device == 0x9906) ||
481 (rdev->pdev->device == 0x9907) ||
482 (rdev->pdev->device == 0x9908) ||
483 (rdev->pdev->device == 0x9909) ||
484 (rdev->pdev->device == 0x990A) ||
485 (rdev->pdev->device == 0x990B) ||
486 (rdev->pdev->device == 0x990C) ||
487 (rdev->pdev->device == 0x990D) ||
488 (rdev->pdev->device == 0x990E) ||
489 (rdev->pdev->device == 0x990F) ||
490 (rdev->pdev->device == 0x9910) ||
491 (rdev->pdev->device == 0x9913) ||
492 (rdev->pdev->device == 0x9917) ||
493 (rdev->pdev->device == 0x9918)) {
494 radeon_program_register_sequence(rdev,
495 dvst_golden_registers,
496 (const u32)ARRAY_SIZE(dvst_golden_registers));
497 radeon_program_register_sequence(rdev,
498 dvst_golden_registers2,
499 (const u32)ARRAY_SIZE(dvst_golden_registers2));
500 } else {
501 radeon_program_register_sequence(rdev,
502 scrapper_golden_registers,
503 (const u32)ARRAY_SIZE(scrapper_golden_registers));
504 radeon_program_register_sequence(rdev,
505 dvst_golden_registers2,
506 (const u32)ARRAY_SIZE(dvst_golden_registers2));
507 }
508 break;
509 default:
510 break;
511 }
512 }
513
514 #define BTC_IO_MC_REGS_SIZE 29
515
516 static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
517 {0x00000077, 0xff010100},
518 {0x00000078, 0x00000000},
519 {0x00000079, 0x00001434},
520 {0x0000007a, 0xcc08ec08},
521 {0x0000007b, 0x00040000},
522 {0x0000007c, 0x000080c0},
523 {0x0000007d, 0x09000000},
524 {0x0000007e, 0x00210404},
525 {0x00000081, 0x08a8e800},
526 {0x00000082, 0x00030444},
527 {0x00000083, 0x00000000},
528 {0x00000085, 0x00000001},
529 {0x00000086, 0x00000002},
530 {0x00000087, 0x48490000},
531 {0x00000088, 0x20244647},
532 {0x00000089, 0x00000005},
533 {0x0000008b, 0x66030000},
534 {0x0000008c, 0x00006603},
535 {0x0000008d, 0x00000100},
536 {0x0000008f, 0x00001c0a},
537 {0x00000090, 0xff000001},
538 {0x00000094, 0x00101101},
539 {0x00000095, 0x00000fff},
540 {0x00000096, 0x00116fff},
541 {0x00000097, 0x60010000},
542 {0x00000098, 0x10010000},
543 {0x00000099, 0x00006000},
544 {0x0000009a, 0x00001000},
545 {0x0000009f, 0x00946a00}
546 };
547
548 static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
549 {0x00000077, 0xff010100},
550 {0x00000078, 0x00000000},
551 {0x00000079, 0x00001434},
552 {0x0000007a, 0xcc08ec08},
553 {0x0000007b, 0x00040000},
554 {0x0000007c, 0x000080c0},
555 {0x0000007d, 0x09000000},
556 {0x0000007e, 0x00210404},
557 {0x00000081, 0x08a8e800},
558 {0x00000082, 0x00030444},
559 {0x00000083, 0x00000000},
560 {0x00000085, 0x00000001},
561 {0x00000086, 0x00000002},
562 {0x00000087, 0x48490000},
563 {0x00000088, 0x20244647},
564 {0x00000089, 0x00000005},
565 {0x0000008b, 0x66030000},
566 {0x0000008c, 0x00006603},
567 {0x0000008d, 0x00000100},
568 {0x0000008f, 0x00001c0a},
569 {0x00000090, 0xff000001},
570 {0x00000094, 0x00101101},
571 {0x00000095, 0x00000fff},
572 {0x00000096, 0x00116fff},
573 {0x00000097, 0x60010000},
574 {0x00000098, 0x10010000},
575 {0x00000099, 0x00006000},
576 {0x0000009a, 0x00001000},
577 {0x0000009f, 0x00936a00}
578 };
579
580 static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
581 {0x00000077, 0xff010100},
582 {0x00000078, 0x00000000},
583 {0x00000079, 0x00001434},
584 {0x0000007a, 0xcc08ec08},
585 {0x0000007b, 0x00040000},
586 {0x0000007c, 0x000080c0},
587 {0x0000007d, 0x09000000},
588 {0x0000007e, 0x00210404},
589 {0x00000081, 0x08a8e800},
590 {0x00000082, 0x00030444},
591 {0x00000083, 0x00000000},
592 {0x00000085, 0x00000001},
593 {0x00000086, 0x00000002},
594 {0x00000087, 0x48490000},
595 {0x00000088, 0x20244647},
596 {0x00000089, 0x00000005},
597 {0x0000008b, 0x66030000},
598 {0x0000008c, 0x00006603},
599 {0x0000008d, 0x00000100},
600 {0x0000008f, 0x00001c0a},
601 {0x00000090, 0xff000001},
602 {0x00000094, 0x00101101},
603 {0x00000095, 0x00000fff},
604 {0x00000096, 0x00116fff},
605 {0x00000097, 0x60010000},
606 {0x00000098, 0x10010000},
607 {0x00000099, 0x00006000},
608 {0x0000009a, 0x00001000},
609 {0x0000009f, 0x00916a00}
610 };
611
612 static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
613 {0x00000077, 0xff010100},
614 {0x00000078, 0x00000000},
615 {0x00000079, 0x00001434},
616 {0x0000007a, 0xcc08ec08},
617 {0x0000007b, 0x00040000},
618 {0x0000007c, 0x000080c0},
619 {0x0000007d, 0x09000000},
620 {0x0000007e, 0x00210404},
621 {0x00000081, 0x08a8e800},
622 {0x00000082, 0x00030444},
623 {0x00000083, 0x00000000},
624 {0x00000085, 0x00000001},
625 {0x00000086, 0x00000002},
626 {0x00000087, 0x48490000},
627 {0x00000088, 0x20244647},
628 {0x00000089, 0x00000005},
629 {0x0000008b, 0x66030000},
630 {0x0000008c, 0x00006603},
631 {0x0000008d, 0x00000100},
632 {0x0000008f, 0x00001c0a},
633 {0x00000090, 0xff000001},
634 {0x00000094, 0x00101101},
635 {0x00000095, 0x00000fff},
636 {0x00000096, 0x00116fff},
637 {0x00000097, 0x60010000},
638 {0x00000098, 0x10010000},
639 {0x00000099, 0x00006000},
640 {0x0000009a, 0x00001000},
641 {0x0000009f, 0x00976b00}
642 };
643
ni_mc_load_microcode(struct radeon_device * rdev)644 int ni_mc_load_microcode(struct radeon_device *rdev)
645 {
646 const __be32 *fw_data;
647 u32 mem_type, running, blackout = 0;
648 const u32 *io_mc_regs;
649 int i, ucode_size, regs_size;
650
651 if (!rdev->mc_fw)
652 return -EINVAL;
653
654 switch (rdev->family) {
655 case CHIP_BARTS:
656 io_mc_regs = &barts_io_mc_regs[0][0];
657 ucode_size = BTC_MC_UCODE_SIZE;
658 regs_size = BTC_IO_MC_REGS_SIZE;
659 break;
660 case CHIP_TURKS:
661 io_mc_regs = &turks_io_mc_regs[0][0];
662 ucode_size = BTC_MC_UCODE_SIZE;
663 regs_size = BTC_IO_MC_REGS_SIZE;
664 break;
665 case CHIP_CAICOS:
666 default:
667 io_mc_regs = &caicos_io_mc_regs[0][0];
668 ucode_size = BTC_MC_UCODE_SIZE;
669 regs_size = BTC_IO_MC_REGS_SIZE;
670 break;
671 case CHIP_CAYMAN:
672 io_mc_regs = &cayman_io_mc_regs[0][0];
673 ucode_size = CAYMAN_MC_UCODE_SIZE;
674 regs_size = BTC_IO_MC_REGS_SIZE;
675 break;
676 }
677
678 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
679 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
680
681 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
682 if (running) {
683 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
684 WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
685 }
686
687 /* reset the engine and set to writable */
688 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
689 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
690
691 /* load mc io regs */
692 for (i = 0; i < regs_size; i++) {
693 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
694 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
695 }
696 /* load the MC ucode */
697 fw_data = (const __be32 *)rdev->mc_fw->data;
698 for (i = 0; i < ucode_size; i++)
699 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
700
701 /* put the engine back into the active state */
702 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
703 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
704 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
705
706 /* wait for training to complete */
707 for (i = 0; i < rdev->usec_timeout; i++) {
708 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
709 break;
710 udelay(1);
711 }
712
713 if (running)
714 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
715 }
716
717 return 0;
718 }
719
ni_init_microcode(struct radeon_device * rdev)720 int ni_init_microcode(struct radeon_device *rdev)
721 {
722 const char *chip_name;
723 const char *rlc_chip_name;
724 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
725 size_t smc_req_size = 0;
726 char fw_name[30];
727 int err;
728
729 DRM_DEBUG("\n");
730
731 switch (rdev->family) {
732 case CHIP_BARTS:
733 chip_name = "BARTS";
734 rlc_chip_name = "BTC";
735 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
736 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
737 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
738 mc_req_size = BTC_MC_UCODE_SIZE * 4;
739 smc_req_size = ALIGN(BARTS_SMC_UCODE_SIZE, 4);
740 break;
741 case CHIP_TURKS:
742 chip_name = "TURKS";
743 rlc_chip_name = "BTC";
744 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
745 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
746 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
747 mc_req_size = BTC_MC_UCODE_SIZE * 4;
748 smc_req_size = ALIGN(TURKS_SMC_UCODE_SIZE, 4);
749 break;
750 case CHIP_CAICOS:
751 chip_name = "CAICOS";
752 rlc_chip_name = "BTC";
753 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
754 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
755 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
756 mc_req_size = BTC_MC_UCODE_SIZE * 4;
757 smc_req_size = ALIGN(CAICOS_SMC_UCODE_SIZE, 4);
758 break;
759 case CHIP_CAYMAN:
760 chip_name = "CAYMAN";
761 rlc_chip_name = "CAYMAN";
762 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
763 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
764 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
765 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
766 smc_req_size = ALIGN(CAYMAN_SMC_UCODE_SIZE, 4);
767 break;
768 case CHIP_ARUBA:
769 chip_name = "ARUBA";
770 rlc_chip_name = "ARUBA";
771 /* pfp/me same size as CAYMAN */
772 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
773 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
774 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
775 mc_req_size = 0;
776 break;
777 default: BUG();
778 }
779
780 DRM_INFO("Loading %s Microcode\n", chip_name);
781
782 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
783 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
784 if (err)
785 goto out;
786 if (rdev->pfp_fw->size != pfp_req_size) {
787 pr_err("ni_cp: Bogus length %zu in firmware \"%s\"\n",
788 rdev->pfp_fw->size, fw_name);
789 err = -EINVAL;
790 goto out;
791 }
792
793 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
794 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
795 if (err)
796 goto out;
797 if (rdev->me_fw->size != me_req_size) {
798 pr_err("ni_cp: Bogus length %zu in firmware \"%s\"\n",
799 rdev->me_fw->size, fw_name);
800 err = -EINVAL;
801 }
802
803 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
804 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
805 if (err)
806 goto out;
807 if (rdev->rlc_fw->size != rlc_req_size) {
808 pr_err("ni_rlc: Bogus length %zu in firmware \"%s\"\n",
809 rdev->rlc_fw->size, fw_name);
810 err = -EINVAL;
811 }
812
813 /* no MC ucode on TN */
814 if (!(rdev->flags & RADEON_IS_IGP)) {
815 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
816 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
817 if (err)
818 goto out;
819 if (rdev->mc_fw->size != mc_req_size) {
820 pr_err("ni_mc: Bogus length %zu in firmware \"%s\"\n",
821 rdev->mc_fw->size, fw_name);
822 err = -EINVAL;
823 }
824 }
825
826 if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN)) {
827 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
828 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
829 if (err) {
830 pr_err("smc: error loading firmware \"%s\"\n", fw_name);
831 release_firmware(rdev->smc_fw);
832 rdev->smc_fw = NULL;
833 err = 0;
834 } else if (rdev->smc_fw->size != smc_req_size) {
835 pr_err("ni_mc: Bogus length %zu in firmware \"%s\"\n",
836 rdev->mc_fw->size, fw_name);
837 err = -EINVAL;
838 }
839 }
840
841 out:
842 if (err) {
843 if (err != -EINVAL)
844 pr_err("ni_cp: Failed to load firmware \"%s\"\n",
845 fw_name);
846 release_firmware(rdev->pfp_fw);
847 rdev->pfp_fw = NULL;
848 release_firmware(rdev->me_fw);
849 rdev->me_fw = NULL;
850 release_firmware(rdev->rlc_fw);
851 rdev->rlc_fw = NULL;
852 release_firmware(rdev->mc_fw);
853 rdev->mc_fw = NULL;
854 }
855 return err;
856 }
857
858 /**
859 * cayman_get_allowed_info_register - fetch the register for the info ioctl
860 *
861 * @rdev: radeon_device pointer
862 * @reg: register offset in bytes
863 * @val: register value
864 *
865 * Returns 0 for success or -EINVAL for an invalid register
866 *
867 */
cayman_get_allowed_info_register(struct radeon_device * rdev,u32 reg,u32 * val)868 int cayman_get_allowed_info_register(struct radeon_device *rdev,
869 u32 reg, u32 *val)
870 {
871 switch (reg) {
872 case GRBM_STATUS:
873 case GRBM_STATUS_SE0:
874 case GRBM_STATUS_SE1:
875 case SRBM_STATUS:
876 case SRBM_STATUS2:
877 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET):
878 case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET):
879 case UVD_STATUS:
880 *val = RREG32(reg);
881 return 0;
882 default:
883 return -EINVAL;
884 }
885 }
886
tn_get_temp(struct radeon_device * rdev)887 int tn_get_temp(struct radeon_device *rdev)
888 {
889 u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff;
890 int actual_temp = (temp / 8) - 49;
891
892 return actual_temp * 1000;
893 }
894
895 /*
896 * Core functions
897 */
cayman_gpu_init(struct radeon_device * rdev)898 static void cayman_gpu_init(struct radeon_device *rdev)
899 {
900 u32 gb_addr_config = 0;
901 u32 mc_shared_chmap __unused, mc_arb_ramcfg;
902 u32 cgts_tcc_disable;
903 u32 sx_debug_1;
904 u32 smx_dc_ctl0;
905 u32 cgts_sm_ctrl_reg;
906 u32 hdp_host_path_cntl;
907 u32 tmp;
908 u32 disabled_rb_mask;
909 int i, j;
910
911 switch (rdev->family) {
912 case CHIP_CAYMAN:
913 rdev->config.cayman.max_shader_engines = 2;
914 rdev->config.cayman.max_pipes_per_simd = 4;
915 rdev->config.cayman.max_tile_pipes = 8;
916 rdev->config.cayman.max_simds_per_se = 12;
917 rdev->config.cayman.max_backends_per_se = 4;
918 rdev->config.cayman.max_texture_channel_caches = 8;
919 rdev->config.cayman.max_gprs = 256;
920 rdev->config.cayman.max_threads = 256;
921 rdev->config.cayman.max_gs_threads = 32;
922 rdev->config.cayman.max_stack_entries = 512;
923 rdev->config.cayman.sx_num_of_sets = 8;
924 rdev->config.cayman.sx_max_export_size = 256;
925 rdev->config.cayman.sx_max_export_pos_size = 64;
926 rdev->config.cayman.sx_max_export_smx_size = 192;
927 rdev->config.cayman.max_hw_contexts = 8;
928 rdev->config.cayman.sq_num_cf_insts = 2;
929
930 rdev->config.cayman.sc_prim_fifo_size = 0x100;
931 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
932 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
933 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN;
934 break;
935 case CHIP_ARUBA:
936 default:
937 rdev->config.cayman.max_shader_engines = 1;
938 rdev->config.cayman.max_pipes_per_simd = 4;
939 rdev->config.cayman.max_tile_pipes = 2;
940 if ((rdev->pdev->device == 0x9900) ||
941 (rdev->pdev->device == 0x9901) ||
942 (rdev->pdev->device == 0x9905) ||
943 (rdev->pdev->device == 0x9906) ||
944 (rdev->pdev->device == 0x9907) ||
945 (rdev->pdev->device == 0x9908) ||
946 (rdev->pdev->device == 0x9909) ||
947 (rdev->pdev->device == 0x990B) ||
948 (rdev->pdev->device == 0x990C) ||
949 (rdev->pdev->device == 0x990F) ||
950 (rdev->pdev->device == 0x9910) ||
951 (rdev->pdev->device == 0x9917) ||
952 (rdev->pdev->device == 0x9999) ||
953 (rdev->pdev->device == 0x999C)) {
954 rdev->config.cayman.max_simds_per_se = 6;
955 rdev->config.cayman.max_backends_per_se = 2;
956 rdev->config.cayman.max_hw_contexts = 8;
957 rdev->config.cayman.sx_max_export_size = 256;
958 rdev->config.cayman.sx_max_export_pos_size = 64;
959 rdev->config.cayman.sx_max_export_smx_size = 192;
960 } else if ((rdev->pdev->device == 0x9903) ||
961 (rdev->pdev->device == 0x9904) ||
962 (rdev->pdev->device == 0x990A) ||
963 (rdev->pdev->device == 0x990D) ||
964 (rdev->pdev->device == 0x990E) ||
965 (rdev->pdev->device == 0x9913) ||
966 (rdev->pdev->device == 0x9918) ||
967 (rdev->pdev->device == 0x999D)) {
968 rdev->config.cayman.max_simds_per_se = 4;
969 rdev->config.cayman.max_backends_per_se = 2;
970 rdev->config.cayman.max_hw_contexts = 8;
971 rdev->config.cayman.sx_max_export_size = 256;
972 rdev->config.cayman.sx_max_export_pos_size = 64;
973 rdev->config.cayman.sx_max_export_smx_size = 192;
974 } else if ((rdev->pdev->device == 0x9919) ||
975 (rdev->pdev->device == 0x9990) ||
976 (rdev->pdev->device == 0x9991) ||
977 (rdev->pdev->device == 0x9994) ||
978 (rdev->pdev->device == 0x9995) ||
979 (rdev->pdev->device == 0x9996) ||
980 (rdev->pdev->device == 0x999A) ||
981 (rdev->pdev->device == 0x99A0)) {
982 rdev->config.cayman.max_simds_per_se = 3;
983 rdev->config.cayman.max_backends_per_se = 1;
984 rdev->config.cayman.max_hw_contexts = 4;
985 rdev->config.cayman.sx_max_export_size = 128;
986 rdev->config.cayman.sx_max_export_pos_size = 32;
987 rdev->config.cayman.sx_max_export_smx_size = 96;
988 } else {
989 rdev->config.cayman.max_simds_per_se = 2;
990 rdev->config.cayman.max_backends_per_se = 1;
991 rdev->config.cayman.max_hw_contexts = 4;
992 rdev->config.cayman.sx_max_export_size = 128;
993 rdev->config.cayman.sx_max_export_pos_size = 32;
994 rdev->config.cayman.sx_max_export_smx_size = 96;
995 }
996 rdev->config.cayman.max_texture_channel_caches = 2;
997 rdev->config.cayman.max_gprs = 256;
998 rdev->config.cayman.max_threads = 256;
999 rdev->config.cayman.max_gs_threads = 32;
1000 rdev->config.cayman.max_stack_entries = 512;
1001 rdev->config.cayman.sx_num_of_sets = 8;
1002 rdev->config.cayman.sq_num_cf_insts = 2;
1003
1004 rdev->config.cayman.sc_prim_fifo_size = 0x40;
1005 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
1006 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
1007 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN;
1008 break;
1009 }
1010
1011 /* Initialize HDP */
1012 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1013 WREG32((0x2c14 + j), 0x00000000);
1014 WREG32((0x2c18 + j), 0x00000000);
1015 WREG32((0x2c1c + j), 0x00000000);
1016 WREG32((0x2c20 + j), 0x00000000);
1017 WREG32((0x2c24 + j), 0x00000000);
1018 }
1019
1020 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1021 WREG32(SRBM_INT_CNTL, 0x1);
1022 WREG32(SRBM_INT_ACK, 0x1);
1023
1024 evergreen_fix_pci_max_read_req_size(rdev);
1025
1026 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1027 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1028
1029 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1030 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1031 if (rdev->config.cayman.mem_row_size_in_kb > 4)
1032 rdev->config.cayman.mem_row_size_in_kb = 4;
1033 /* XXX use MC settings? */
1034 rdev->config.cayman.shader_engine_tile_size = 32;
1035 rdev->config.cayman.num_gpus = 1;
1036 rdev->config.cayman.multi_gpu_tile_size = 64;
1037
1038 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
1039 rdev->config.cayman.num_tile_pipes = (1 << tmp);
1040 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
1041 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
1042 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
1043 rdev->config.cayman.num_shader_engines = tmp + 1;
1044 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
1045 rdev->config.cayman.num_gpus = tmp + 1;
1046 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
1047 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
1048 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
1049 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
1050
1051
1052 /* setup tiling info dword. gb_addr_config is not adequate since it does
1053 * not have bank info, so create a custom tiling dword.
1054 * bits 3:0 num_pipes
1055 * bits 7:4 num_banks
1056 * bits 11:8 group_size
1057 * bits 15:12 row_size
1058 */
1059 rdev->config.cayman.tile_config = 0;
1060 switch (rdev->config.cayman.num_tile_pipes) {
1061 case 1:
1062 default:
1063 rdev->config.cayman.tile_config |= (0 << 0);
1064 break;
1065 case 2:
1066 rdev->config.cayman.tile_config |= (1 << 0);
1067 break;
1068 case 4:
1069 rdev->config.cayman.tile_config |= (2 << 0);
1070 break;
1071 case 8:
1072 rdev->config.cayman.tile_config |= (3 << 0);
1073 break;
1074 }
1075
1076 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
1077 if (rdev->flags & RADEON_IS_IGP)
1078 rdev->config.cayman.tile_config |= 1 << 4;
1079 else {
1080 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1081 case 0: /* four banks */
1082 rdev->config.cayman.tile_config |= 0 << 4;
1083 break;
1084 case 1: /* eight banks */
1085 rdev->config.cayman.tile_config |= 1 << 4;
1086 break;
1087 case 2: /* sixteen banks */
1088 default:
1089 rdev->config.cayman.tile_config |= 2 << 4;
1090 break;
1091 }
1092 }
1093 rdev->config.cayman.tile_config |=
1094 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1095 rdev->config.cayman.tile_config |=
1096 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1097
1098 tmp = 0;
1099 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {
1100 u32 rb_disable_bitmap;
1101
1102 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1103 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1104 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
1105 tmp <<= 4;
1106 tmp |= rb_disable_bitmap;
1107 }
1108 /* enabled rb are just the one not disabled :) */
1109 disabled_rb_mask = tmp;
1110 tmp = 0;
1111 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
1112 tmp |= (1 << i);
1113 /* if all the backends are disabled, fix it up here */
1114 if ((disabled_rb_mask & tmp) == tmp) {
1115 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
1116 disabled_rb_mask &= ~(1 << i);
1117 }
1118
1119 for (i = 0; i < rdev->config.cayman.max_shader_engines; i++) {
1120 u32 simd_disable_bitmap;
1121
1122 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1123 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1124 simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16;
1125 simd_disable_bitmap |= 0xffffffff << rdev->config.cayman.max_simds_per_se;
1126 tmp <<= 16;
1127 tmp |= simd_disable_bitmap;
1128 }
1129 rdev->config.cayman.active_simds = hweight32(~tmp);
1130
1131 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1132 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1133
1134 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1135 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1136 if (ASIC_IS_DCE6(rdev))
1137 WREG32(DMIF_ADDR_CALC, gb_addr_config);
1138 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1139 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1140 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1141 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
1142 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1143 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1144
1145 if ((rdev->config.cayman.max_backends_per_se == 1) &&
1146 (rdev->flags & RADEON_IS_IGP)) {
1147 if ((disabled_rb_mask & 3) == 2) {
1148 /* RB1 disabled, RB0 enabled */
1149 tmp = 0x00000000;
1150 } else {
1151 /* RB0 disabled, RB1 enabled */
1152 tmp = 0x11111111;
1153 }
1154 } else {
1155 tmp = gb_addr_config & NUM_PIPES_MASK;
1156 tmp = r6xx_remap_render_backend(rdev, tmp,
1157 rdev->config.cayman.max_backends_per_se *
1158 rdev->config.cayman.max_shader_engines,
1159 CAYMAN_MAX_BACKENDS, disabled_rb_mask);
1160 }
1161 rdev->config.cayman.backend_map = tmp;
1162 WREG32(GB_BACKEND_MAP, tmp);
1163
1164 cgts_tcc_disable = 0xffff0000;
1165 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
1166 cgts_tcc_disable &= ~(1 << (16 + i));
1167 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
1168 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
1169 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
1170 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
1171
1172 /* reprogram the shader complex */
1173 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
1174 for (i = 0; i < 16; i++)
1175 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
1176 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
1177
1178 /* set HW defaults for 3D engine */
1179 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1180
1181 sx_debug_1 = RREG32(SX_DEBUG_1);
1182 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1183 WREG32(SX_DEBUG_1, sx_debug_1);
1184
1185 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1186 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1187 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
1188 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1189
1190 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
1191
1192 /* need to be explicitly zero-ed */
1193 WREG32(VGT_OFFCHIP_LDS_BASE, 0);
1194 WREG32(SQ_LSTMP_RING_BASE, 0);
1195 WREG32(SQ_HSTMP_RING_BASE, 0);
1196 WREG32(SQ_ESTMP_RING_BASE, 0);
1197 WREG32(SQ_GSTMP_RING_BASE, 0);
1198 WREG32(SQ_VSTMP_RING_BASE, 0);
1199 WREG32(SQ_PSTMP_RING_BASE, 0);
1200
1201 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
1202
1203 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
1204 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
1205 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
1206
1207 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
1208 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
1209 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
1210
1211
1212 WREG32(VGT_NUM_INSTANCES, 1);
1213
1214 WREG32(CP_PERFMON_CNTL, 0);
1215
1216 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
1217 FETCH_FIFO_HIWATER(0x4) |
1218 DONE_FIFO_HIWATER(0xe0) |
1219 ALU_UPDATE_FIFO_HIWATER(0x8)));
1220
1221 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
1222 WREG32(SQ_CONFIG, (VC_ENABLE |
1223 EXPORT_SRC_C |
1224 GFX_PRIO(0) |
1225 CS1_PRIO(0) |
1226 CS2_PRIO(1)));
1227 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
1228
1229 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1230 FORCE_EOV_MAX_REZ_CNT(255)));
1231
1232 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1233 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1234
1235 WREG32(VGT_GS_VERTEX_REUSE, 16);
1236 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1237
1238 WREG32(CB_PERF_CTR0_SEL_0, 0);
1239 WREG32(CB_PERF_CTR0_SEL_1, 0);
1240 WREG32(CB_PERF_CTR1_SEL_0, 0);
1241 WREG32(CB_PERF_CTR1_SEL_1, 0);
1242 WREG32(CB_PERF_CTR2_SEL_0, 0);
1243 WREG32(CB_PERF_CTR2_SEL_1, 0);
1244 WREG32(CB_PERF_CTR3_SEL_0, 0);
1245 WREG32(CB_PERF_CTR3_SEL_1, 0);
1246
1247 tmp = RREG32(HDP_MISC_CNTL);
1248 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1249 WREG32(HDP_MISC_CNTL, tmp);
1250
1251 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1252 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1253
1254 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1255
1256 udelay(50);
1257
1258 /* set clockgating golden values on TN */
1259 if (rdev->family == CHIP_ARUBA) {
1260 tmp = RREG32_CG(CG_CGTT_LOCAL_0);
1261 tmp &= ~0x00380000;
1262 WREG32_CG(CG_CGTT_LOCAL_0, tmp);
1263 tmp = RREG32_CG(CG_CGTT_LOCAL_1);
1264 tmp &= ~0x0e000000;
1265 WREG32_CG(CG_CGTT_LOCAL_1, tmp);
1266 }
1267 }
1268
1269 /*
1270 * GART
1271 */
cayman_pcie_gart_tlb_flush(struct radeon_device * rdev)1272 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
1273 {
1274 /* flush hdp cache */
1275 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1276
1277 /* bits 0-7 are the VM contexts0-7 */
1278 WREG32(VM_INVALIDATE_REQUEST, 1);
1279 }
1280
cayman_pcie_gart_enable(struct radeon_device * rdev)1281 static int cayman_pcie_gart_enable(struct radeon_device *rdev)
1282 {
1283 int i, r;
1284
1285 if (rdev->gart.robj == NULL) {
1286 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1287 return -EINVAL;
1288 }
1289 r = radeon_gart_table_vram_pin(rdev);
1290 if (r)
1291 return r;
1292 /* Setup TLB control */
1293 WREG32(MC_VM_MX_L1_TLB_CNTL,
1294 (0xA << 7) |
1295 ENABLE_L1_TLB |
1296 ENABLE_L1_FRAGMENT_PROCESSING |
1297 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1298 ENABLE_ADVANCED_DRIVER_MODEL |
1299 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1300 /* Setup L2 cache */
1301 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
1302 ENABLE_L2_FRAGMENT_PROCESSING |
1303 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1304 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1305 EFFECTIVE_L2_QUEUE_SIZE(7) |
1306 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1307 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
1308 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1309 BANK_SELECT(6) |
1310 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1311 /* setup context0 */
1312 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1313 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1314 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1315 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1316 (u32)(rdev->dummy_page.addr >> 12));
1317 WREG32(VM_CONTEXT0_CNTL2, 0);
1318 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1319 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1320
1321 WREG32(0x15D4, 0);
1322 WREG32(0x15D8, 0);
1323 WREG32(0x15DC, 0);
1324
1325 /* empty context1-7 */
1326 /* Assign the pt base to something valid for now; the pts used for
1327 * the VMs are determined by the application and setup and assigned
1328 * on the fly in the vm part of radeon_gart.c
1329 */
1330 for (i = 1; i < 8; i++) {
1331 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
1332 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2),
1333 rdev->vm_manager.max_pfn - 1);
1334 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
1335 rdev->vm_manager.saved_table_addr[i]);
1336 }
1337
1338 /* enable context1-7 */
1339 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
1340 (u32)(rdev->dummy_page.addr >> 12));
1341 WREG32(VM_CONTEXT1_CNTL2, 4);
1342 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
1343 PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) |
1344 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1345 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
1346 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1347 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
1348 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
1349 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
1350 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
1351 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
1352 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
1353 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
1354 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1355 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
1356
1357 cayman_pcie_gart_tlb_flush(rdev);
1358 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1359 (unsigned)(rdev->mc.gtt_size >> 20),
1360 (unsigned long long)rdev->gart.table_addr);
1361 rdev->gart.ready = true;
1362 return 0;
1363 }
1364
cayman_pcie_gart_disable(struct radeon_device * rdev)1365 static void cayman_pcie_gart_disable(struct radeon_device *rdev)
1366 {
1367 unsigned i;
1368
1369 for (i = 1; i < 8; ++i) {
1370 rdev->vm_manager.saved_table_addr[i] = RREG32(
1371 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2));
1372 }
1373
1374 /* Disable all tables */
1375 WREG32(VM_CONTEXT0_CNTL, 0);
1376 WREG32(VM_CONTEXT1_CNTL, 0);
1377 /* Setup TLB control */
1378 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
1379 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1380 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1381 /* Setup L2 cache */
1382 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1383 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1384 EFFECTIVE_L2_QUEUE_SIZE(7) |
1385 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1386 WREG32(VM_L2_CNTL2, 0);
1387 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1388 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1389 radeon_gart_table_vram_unpin(rdev);
1390 }
1391
cayman_pcie_gart_fini(struct radeon_device * rdev)1392 static void cayman_pcie_gart_fini(struct radeon_device *rdev)
1393 {
1394 cayman_pcie_gart_disable(rdev);
1395 radeon_gart_table_vram_free(rdev);
1396 radeon_gart_fini(rdev);
1397 }
1398
cayman_cp_int_cntl_setup(struct radeon_device * rdev,int ring,u32 cp_int_cntl)1399 void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
1400 int ring, u32 cp_int_cntl)
1401 {
1402 WREG32(SRBM_GFX_CNTL, RINGID(ring));
1403 WREG32(CP_INT_CNTL, cp_int_cntl);
1404 }
1405
1406 /*
1407 * CP.
1408 */
cayman_fence_ring_emit(struct radeon_device * rdev,struct radeon_fence * fence)1409 void cayman_fence_ring_emit(struct radeon_device *rdev,
1410 struct radeon_fence *fence)
1411 {
1412 struct radeon_ring *ring = &rdev->ring[fence->ring];
1413 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1414 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |
1415 PACKET3_SH_ACTION_ENA;
1416
1417 /* flush read cache over gart for this vmid */
1418 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1419 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);
1420 radeon_ring_write(ring, 0xFFFFFFFF);
1421 radeon_ring_write(ring, 0);
1422 radeon_ring_write(ring, 10); /* poll interval */
1423 /* EVENT_WRITE_EOP - flush caches, send int */
1424 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1425 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
1426 radeon_ring_write(ring, lower_32_bits(addr));
1427 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1428 radeon_ring_write(ring, fence->seq);
1429 radeon_ring_write(ring, 0);
1430 }
1431
cayman_ring_ib_execute(struct radeon_device * rdev,struct radeon_ib * ib)1432 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1433 {
1434 struct radeon_ring *ring = &rdev->ring[ib->ring];
1435 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0;
1436 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |
1437 PACKET3_SH_ACTION_ENA;
1438
1439 /* set to DX10/11 mode */
1440 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1441 radeon_ring_write(ring, 1);
1442
1443 if (ring->rptr_save_reg) {
1444 uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
1445 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1446 radeon_ring_write(ring, ((ring->rptr_save_reg -
1447 PACKET3_SET_CONFIG_REG_START) >> 2));
1448 radeon_ring_write(ring, next_rptr);
1449 }
1450
1451 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1452 radeon_ring_write(ring,
1453 #ifdef __BIG_ENDIAN
1454 (2 << 0) |
1455 #endif
1456 (ib->gpu_addr & 0xFFFFFFFC));
1457 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1458 radeon_ring_write(ring, ib->length_dw | (vm_id << 24));
1459
1460 /* flush read cache over gart for this vmid */
1461 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1462 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);
1463 radeon_ring_write(ring, 0xFFFFFFFF);
1464 radeon_ring_write(ring, 0);
1465 radeon_ring_write(ring, (vm_id << 24) | 10); /* poll interval */
1466 }
1467
cayman_cp_enable(struct radeon_device * rdev,bool enable)1468 static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
1469 {
1470 if (enable)
1471 WREG32(CP_ME_CNTL, 0);
1472 else {
1473 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
1474 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1475 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1476 WREG32(SCRATCH_UMSK, 0);
1477 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1478 }
1479 }
1480
cayman_gfx_get_rptr(struct radeon_device * rdev,struct radeon_ring * ring)1481 u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
1482 struct radeon_ring *ring)
1483 {
1484 u32 rptr;
1485
1486 if (rdev->wb.enabled)
1487 rptr = rdev->wb.wb[ring->rptr_offs/4];
1488 else {
1489 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX)
1490 rptr = RREG32(CP_RB0_RPTR);
1491 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX)
1492 rptr = RREG32(CP_RB1_RPTR);
1493 else
1494 rptr = RREG32(CP_RB2_RPTR);
1495 }
1496
1497 return rptr;
1498 }
1499
cayman_gfx_get_wptr(struct radeon_device * rdev,struct radeon_ring * ring)1500 u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
1501 struct radeon_ring *ring)
1502 {
1503 u32 wptr;
1504
1505 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX)
1506 wptr = RREG32(CP_RB0_WPTR);
1507 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX)
1508 wptr = RREG32(CP_RB1_WPTR);
1509 else
1510 wptr = RREG32(CP_RB2_WPTR);
1511
1512 return wptr;
1513 }
1514
cayman_gfx_set_wptr(struct radeon_device * rdev,struct radeon_ring * ring)1515 void cayman_gfx_set_wptr(struct radeon_device *rdev,
1516 struct radeon_ring *ring)
1517 {
1518 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) {
1519 WREG32(CP_RB0_WPTR, ring->wptr);
1520 (void)RREG32(CP_RB0_WPTR);
1521 } else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) {
1522 WREG32(CP_RB1_WPTR, ring->wptr);
1523 (void)RREG32(CP_RB1_WPTR);
1524 } else {
1525 WREG32(CP_RB2_WPTR, ring->wptr);
1526 (void)RREG32(CP_RB2_WPTR);
1527 }
1528 }
1529
cayman_cp_load_microcode(struct radeon_device * rdev)1530 static int cayman_cp_load_microcode(struct radeon_device *rdev)
1531 {
1532 const __be32 *fw_data;
1533 int i;
1534
1535 if (!rdev->me_fw || !rdev->pfp_fw)
1536 return -EINVAL;
1537
1538 cayman_cp_enable(rdev, false);
1539
1540 fw_data = (const __be32 *)rdev->pfp_fw->data;
1541 WREG32(CP_PFP_UCODE_ADDR, 0);
1542 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
1543 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1544 WREG32(CP_PFP_UCODE_ADDR, 0);
1545
1546 fw_data = (const __be32 *)rdev->me_fw->data;
1547 WREG32(CP_ME_RAM_WADDR, 0);
1548 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
1549 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1550
1551 WREG32(CP_PFP_UCODE_ADDR, 0);
1552 WREG32(CP_ME_RAM_WADDR, 0);
1553 WREG32(CP_ME_RAM_RADDR, 0);
1554 return 0;
1555 }
1556
cayman_cp_start(struct radeon_device * rdev)1557 static int cayman_cp_start(struct radeon_device *rdev)
1558 {
1559 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1560 int r, i;
1561
1562 r = radeon_ring_lock(rdev, ring, 7);
1563 if (r) {
1564 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1565 return r;
1566 }
1567 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1568 radeon_ring_write(ring, 0x1);
1569 radeon_ring_write(ring, 0x0);
1570 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
1571 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1572 radeon_ring_write(ring, 0);
1573 radeon_ring_write(ring, 0);
1574 radeon_ring_unlock_commit(rdev, ring, false);
1575
1576 cayman_cp_enable(rdev, true);
1577
1578 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
1579 if (r) {
1580 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1581 return r;
1582 }
1583
1584 /* setup clear context state */
1585 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1586 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1587
1588 for (i = 0; i < cayman_default_size; i++)
1589 radeon_ring_write(ring, cayman_default_state[i]);
1590
1591 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1592 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1593
1594 /* set clear context state */
1595 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1596 radeon_ring_write(ring, 0);
1597
1598 /* SQ_VTX_BASE_VTX_LOC */
1599 radeon_ring_write(ring, 0xc0026f00);
1600 radeon_ring_write(ring, 0x00000000);
1601 radeon_ring_write(ring, 0x00000000);
1602 radeon_ring_write(ring, 0x00000000);
1603
1604 /* Clear consts */
1605 radeon_ring_write(ring, 0xc0036f00);
1606 radeon_ring_write(ring, 0x00000bc4);
1607 radeon_ring_write(ring, 0xffffffff);
1608 radeon_ring_write(ring, 0xffffffff);
1609 radeon_ring_write(ring, 0xffffffff);
1610
1611 radeon_ring_write(ring, 0xc0026900);
1612 radeon_ring_write(ring, 0x00000316);
1613 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1614 radeon_ring_write(ring, 0x00000010); /* */
1615
1616 radeon_ring_unlock_commit(rdev, ring, false);
1617
1618 /* XXX init other rings */
1619
1620 return 0;
1621 }
1622
cayman_cp_fini(struct radeon_device * rdev)1623 static void cayman_cp_fini(struct radeon_device *rdev)
1624 {
1625 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1626 cayman_cp_enable(rdev, false);
1627 radeon_ring_fini(rdev, ring);
1628 radeon_scratch_free(rdev, ring->rptr_save_reg);
1629 }
1630
cayman_cp_resume(struct radeon_device * rdev)1631 static int cayman_cp_resume(struct radeon_device *rdev)
1632 {
1633 static const int ridx[] = {
1634 RADEON_RING_TYPE_GFX_INDEX,
1635 CAYMAN_RING_TYPE_CP1_INDEX,
1636 CAYMAN_RING_TYPE_CP2_INDEX
1637 };
1638 static const unsigned cp_rb_cntl[] = {
1639 CP_RB0_CNTL,
1640 CP_RB1_CNTL,
1641 CP_RB2_CNTL,
1642 };
1643 static const unsigned cp_rb_rptr_addr[] = {
1644 CP_RB0_RPTR_ADDR,
1645 CP_RB1_RPTR_ADDR,
1646 CP_RB2_RPTR_ADDR
1647 };
1648 static const unsigned cp_rb_rptr_addr_hi[] = {
1649 CP_RB0_RPTR_ADDR_HI,
1650 CP_RB1_RPTR_ADDR_HI,
1651 CP_RB2_RPTR_ADDR_HI
1652 };
1653 static const unsigned cp_rb_base[] = {
1654 CP_RB0_BASE,
1655 CP_RB1_BASE,
1656 CP_RB2_BASE
1657 };
1658 static const unsigned cp_rb_rptr[] = {
1659 CP_RB0_RPTR,
1660 CP_RB1_RPTR,
1661 CP_RB2_RPTR
1662 };
1663 static const unsigned cp_rb_wptr[] = {
1664 CP_RB0_WPTR,
1665 CP_RB1_WPTR,
1666 CP_RB2_WPTR
1667 };
1668 struct radeon_ring *ring;
1669 int i, r;
1670
1671 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1672 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1673 SOFT_RESET_PA |
1674 SOFT_RESET_SH |
1675 SOFT_RESET_VGT |
1676 SOFT_RESET_SPI |
1677 SOFT_RESET_SX));
1678 RREG32(GRBM_SOFT_RESET);
1679 mdelay(15);
1680 WREG32(GRBM_SOFT_RESET, 0);
1681 RREG32(GRBM_SOFT_RESET);
1682
1683 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1684 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1685
1686 /* Set the write pointer delay */
1687 WREG32(CP_RB_WPTR_DELAY, 0);
1688
1689 WREG32(CP_DEBUG, (1 << 27));
1690
1691 /* set the wb address whether it's enabled or not */
1692 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1693 WREG32(SCRATCH_UMSK, 0xff);
1694
1695 for (i = 0; i < 3; ++i) {
1696 uint32_t rb_cntl;
1697 uint64_t addr;
1698
1699 /* Set ring buffer size */
1700 ring = &rdev->ring[ridx[i]];
1701 rb_cntl = order_base_2(ring->ring_size / 8);
1702 rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8;
1703 #ifdef __BIG_ENDIAN
1704 rb_cntl |= BUF_SWAP_32BIT;
1705 #endif
1706 WREG32(cp_rb_cntl[i], rb_cntl);
1707
1708 /* set the wb address whether it's enabled or not */
1709 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET;
1710 WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC);
1711 WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);
1712 }
1713
1714 /* set the rb base addr, this causes an internal reset of ALL rings */
1715 for (i = 0; i < 3; ++i) {
1716 ring = &rdev->ring[ridx[i]];
1717 WREG32(cp_rb_base[i], ring->gpu_addr >> 8);
1718 }
1719
1720 for (i = 0; i < 3; ++i) {
1721 /* Initialize the ring buffer's read and write pointers */
1722 ring = &rdev->ring[ridx[i]];
1723 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
1724
1725 ring->wptr = 0;
1726 WREG32(cp_rb_rptr[i], 0);
1727 WREG32(cp_rb_wptr[i], ring->wptr);
1728
1729 mdelay(1);
1730 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
1731 }
1732
1733 /* start the rings */
1734 cayman_cp_start(rdev);
1735 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1736 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1737 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1738 /* this only test cp0 */
1739 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1740 if (r) {
1741 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1742 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1743 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1744 return r;
1745 }
1746
1747 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
1748 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1749
1750 return 0;
1751 }
1752
cayman_gpu_check_soft_reset(struct radeon_device * rdev)1753 u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev)
1754 {
1755 u32 reset_mask = 0;
1756 u32 tmp;
1757
1758 /* GRBM_STATUS */
1759 tmp = RREG32(GRBM_STATUS);
1760 if (tmp & (PA_BUSY | SC_BUSY |
1761 SH_BUSY | SX_BUSY |
1762 TA_BUSY | VGT_BUSY |
1763 DB_BUSY | CB_BUSY |
1764 GDS_BUSY | SPI_BUSY |
1765 IA_BUSY | IA_BUSY_NO_DMA))
1766 reset_mask |= RADEON_RESET_GFX;
1767
1768 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
1769 CP_BUSY | CP_COHERENCY_BUSY))
1770 reset_mask |= RADEON_RESET_CP;
1771
1772 if (tmp & GRBM_EE_BUSY)
1773 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1774
1775 /* DMA_STATUS_REG 0 */
1776 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
1777 if (!(tmp & DMA_IDLE))
1778 reset_mask |= RADEON_RESET_DMA;
1779
1780 /* DMA_STATUS_REG 1 */
1781 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
1782 if (!(tmp & DMA_IDLE))
1783 reset_mask |= RADEON_RESET_DMA1;
1784
1785 /* SRBM_STATUS2 */
1786 tmp = RREG32(SRBM_STATUS2);
1787 if (tmp & DMA_BUSY)
1788 reset_mask |= RADEON_RESET_DMA;
1789
1790 if (tmp & DMA1_BUSY)
1791 reset_mask |= RADEON_RESET_DMA1;
1792
1793 /* SRBM_STATUS */
1794 tmp = RREG32(SRBM_STATUS);
1795 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
1796 reset_mask |= RADEON_RESET_RLC;
1797
1798 if (tmp & IH_BUSY)
1799 reset_mask |= RADEON_RESET_IH;
1800
1801 if (tmp & SEM_BUSY)
1802 reset_mask |= RADEON_RESET_SEM;
1803
1804 if (tmp & GRBM_RQ_PENDING)
1805 reset_mask |= RADEON_RESET_GRBM;
1806
1807 if (tmp & VMC_BUSY)
1808 reset_mask |= RADEON_RESET_VMC;
1809
1810 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
1811 MCC_BUSY | MCD_BUSY))
1812 reset_mask |= RADEON_RESET_MC;
1813
1814 if (evergreen_is_display_hung(rdev))
1815 reset_mask |= RADEON_RESET_DISPLAY;
1816
1817 /* VM_L2_STATUS */
1818 tmp = RREG32(VM_L2_STATUS);
1819 if (tmp & L2_BUSY)
1820 reset_mask |= RADEON_RESET_VMC;
1821
1822 /* Skip MC reset as it's mostly likely not hung, just busy */
1823 if (reset_mask & RADEON_RESET_MC) {
1824 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1825 reset_mask &= ~RADEON_RESET_MC;
1826 }
1827
1828 return reset_mask;
1829 }
1830
cayman_gpu_soft_reset(struct radeon_device * rdev,u32 reset_mask)1831 static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1832 {
1833 struct evergreen_mc_save save;
1834 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1835 u32 tmp;
1836
1837 if (reset_mask == 0)
1838 return;
1839
1840 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1841
1842 evergreen_print_gpu_status_regs(rdev);
1843 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
1844 RREG32(0x14F8));
1845 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1846 RREG32(0x14D8));
1847 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1848 RREG32(0x14FC));
1849 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1850 RREG32(0x14DC));
1851
1852 /* Disable CP parsing/prefetching */
1853 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1854
1855 if (reset_mask & RADEON_RESET_DMA) {
1856 /* dma0 */
1857 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1858 tmp &= ~DMA_RB_ENABLE;
1859 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
1860 }
1861
1862 if (reset_mask & RADEON_RESET_DMA1) {
1863 /* dma1 */
1864 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1865 tmp &= ~DMA_RB_ENABLE;
1866 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
1867 }
1868
1869 udelay(50);
1870
1871 evergreen_mc_stop(rdev, &save);
1872 if (evergreen_mc_wait_for_idle(rdev)) {
1873 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1874 }
1875
1876 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1877 grbm_soft_reset = SOFT_RESET_CB |
1878 SOFT_RESET_DB |
1879 SOFT_RESET_GDS |
1880 SOFT_RESET_PA |
1881 SOFT_RESET_SC |
1882 SOFT_RESET_SPI |
1883 SOFT_RESET_SH |
1884 SOFT_RESET_SX |
1885 SOFT_RESET_TC |
1886 SOFT_RESET_TA |
1887 SOFT_RESET_VGT |
1888 SOFT_RESET_IA;
1889 }
1890
1891 if (reset_mask & RADEON_RESET_CP) {
1892 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
1893
1894 srbm_soft_reset |= SOFT_RESET_GRBM;
1895 }
1896
1897 if (reset_mask & RADEON_RESET_DMA)
1898 srbm_soft_reset |= SOFT_RESET_DMA;
1899
1900 if (reset_mask & RADEON_RESET_DMA1)
1901 srbm_soft_reset |= SOFT_RESET_DMA1;
1902
1903 if (reset_mask & RADEON_RESET_DISPLAY)
1904 srbm_soft_reset |= SOFT_RESET_DC;
1905
1906 if (reset_mask & RADEON_RESET_RLC)
1907 srbm_soft_reset |= SOFT_RESET_RLC;
1908
1909 if (reset_mask & RADEON_RESET_SEM)
1910 srbm_soft_reset |= SOFT_RESET_SEM;
1911
1912 if (reset_mask & RADEON_RESET_IH)
1913 srbm_soft_reset |= SOFT_RESET_IH;
1914
1915 if (reset_mask & RADEON_RESET_GRBM)
1916 srbm_soft_reset |= SOFT_RESET_GRBM;
1917
1918 if (reset_mask & RADEON_RESET_VMC)
1919 srbm_soft_reset |= SOFT_RESET_VMC;
1920
1921 if (!(rdev->flags & RADEON_IS_IGP)) {
1922 if (reset_mask & RADEON_RESET_MC)
1923 srbm_soft_reset |= SOFT_RESET_MC;
1924 }
1925
1926 if (grbm_soft_reset) {
1927 tmp = RREG32(GRBM_SOFT_RESET);
1928 tmp |= grbm_soft_reset;
1929 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
1930 WREG32(GRBM_SOFT_RESET, tmp);
1931 tmp = RREG32(GRBM_SOFT_RESET);
1932
1933 udelay(50);
1934
1935 tmp &= ~grbm_soft_reset;
1936 WREG32(GRBM_SOFT_RESET, tmp);
1937 tmp = RREG32(GRBM_SOFT_RESET);
1938 }
1939
1940 if (srbm_soft_reset) {
1941 tmp = RREG32(SRBM_SOFT_RESET);
1942 tmp |= srbm_soft_reset;
1943 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1944 WREG32(SRBM_SOFT_RESET, tmp);
1945 tmp = RREG32(SRBM_SOFT_RESET);
1946
1947 udelay(50);
1948
1949 tmp &= ~srbm_soft_reset;
1950 WREG32(SRBM_SOFT_RESET, tmp);
1951 tmp = RREG32(SRBM_SOFT_RESET);
1952 }
1953
1954 /* Wait a little for things to settle down */
1955 udelay(50);
1956
1957 evergreen_mc_resume(rdev, &save);
1958 udelay(50);
1959
1960 evergreen_print_gpu_status_regs(rdev);
1961 }
1962
cayman_asic_reset(struct radeon_device * rdev,bool hard)1963 int cayman_asic_reset(struct radeon_device *rdev, bool hard)
1964 {
1965 u32 reset_mask;
1966
1967 if (hard) {
1968 evergreen_gpu_pci_config_reset(rdev);
1969 return 0;
1970 }
1971
1972 reset_mask = cayman_gpu_check_soft_reset(rdev);
1973
1974 if (reset_mask)
1975 r600_set_bios_scratch_engine_hung(rdev, true);
1976
1977 cayman_gpu_soft_reset(rdev, reset_mask);
1978
1979 reset_mask = cayman_gpu_check_soft_reset(rdev);
1980
1981 if (reset_mask)
1982 evergreen_gpu_pci_config_reset(rdev);
1983
1984 r600_set_bios_scratch_engine_hung(rdev, false);
1985
1986 return 0;
1987 }
1988
1989 /**
1990 * cayman_gfx_is_lockup - Check if the GFX engine is locked up
1991 *
1992 * @rdev: radeon_device pointer
1993 * @ring: radeon_ring structure holding ring information
1994 *
1995 * Check if the GFX engine is locked up.
1996 * Returns true if the engine appears to be locked up, false if not.
1997 */
cayman_gfx_is_lockup(struct radeon_device * rdev,struct radeon_ring * ring)1998 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1999 {
2000 u32 reset_mask = cayman_gpu_check_soft_reset(rdev);
2001
2002 if (!(reset_mask & (RADEON_RESET_GFX |
2003 RADEON_RESET_COMPUTE |
2004 RADEON_RESET_CP))) {
2005 radeon_ring_lockup_update(rdev, ring);
2006 return false;
2007 }
2008 return radeon_ring_test_lockup(rdev, ring);
2009 }
2010
cayman_uvd_init(struct radeon_device * rdev)2011 static void cayman_uvd_init(struct radeon_device *rdev)
2012 {
2013 int r;
2014
2015 if (!rdev->has_uvd)
2016 return;
2017
2018 r = radeon_uvd_init(rdev);
2019 if (r) {
2020 dev_err(rdev->dev, "failed UVD (%d) init.\n", r);
2021 /*
2022 * At this point rdev->uvd.vcpu_bo is NULL which trickles down
2023 * to early fails uvd_v2_2_resume() and thus nothing happens
2024 * there. So it is pointless to try to go through that code
2025 * hence why we disable uvd here.
2026 */
2027 rdev->has_uvd = false;
2028 return;
2029 }
2030 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
2031 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
2032 }
2033
cayman_uvd_start(struct radeon_device * rdev)2034 static void cayman_uvd_start(struct radeon_device *rdev)
2035 {
2036 int r;
2037
2038 if (!rdev->has_uvd)
2039 return;
2040
2041 r = uvd_v2_2_resume(rdev);
2042 if (r) {
2043 dev_err(rdev->dev, "failed UVD resume (%d).\n", r);
2044 goto error;
2045 }
2046 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
2047 if (r) {
2048 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);
2049 goto error;
2050 }
2051 return;
2052
2053 error:
2054 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
2055 }
2056
cayman_uvd_resume(struct radeon_device * rdev)2057 static void cayman_uvd_resume(struct radeon_device *rdev)
2058 {
2059 struct radeon_ring *ring;
2060 int r;
2061
2062 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size)
2063 return;
2064
2065 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2066 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));
2067 if (r) {
2068 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r);
2069 return;
2070 }
2071 r = uvd_v1_0_init(rdev);
2072 if (r) {
2073 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r);
2074 return;
2075 }
2076 }
2077
cayman_vce_init(struct radeon_device * rdev)2078 static void cayman_vce_init(struct radeon_device *rdev)
2079 {
2080 int r;
2081
2082 /* Only set for CHIP_ARUBA */
2083 if (!rdev->has_vce)
2084 return;
2085
2086 r = radeon_vce_init(rdev);
2087 if (r) {
2088 dev_err(rdev->dev, "failed VCE (%d) init.\n", r);
2089 /*
2090 * At this point rdev->vce.vcpu_bo is NULL which trickles down
2091 * to early fails cayman_vce_start() and thus nothing happens
2092 * there. So it is pointless to try to go through that code
2093 * hence why we disable vce here.
2094 */
2095 rdev->has_vce = false;
2096 return;
2097 }
2098 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_obj = NULL;
2099 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE1_INDEX], 4096);
2100 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_obj = NULL;
2101 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE2_INDEX], 4096);
2102 }
2103
cayman_vce_start(struct radeon_device * rdev)2104 static void cayman_vce_start(struct radeon_device *rdev)
2105 {
2106 int r;
2107
2108 if (!rdev->has_vce)
2109 return;
2110
2111 r = radeon_vce_resume(rdev);
2112 if (r) {
2113 dev_err(rdev->dev, "failed VCE resume (%d).\n", r);
2114 goto error;
2115 }
2116 r = vce_v1_0_resume(rdev);
2117 if (r) {
2118 dev_err(rdev->dev, "failed VCE resume (%d).\n", r);
2119 goto error;
2120 }
2121 r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE1_INDEX);
2122 if (r) {
2123 dev_err(rdev->dev, "failed initializing VCE1 fences (%d).\n", r);
2124 goto error;
2125 }
2126 r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE2_INDEX);
2127 if (r) {
2128 dev_err(rdev->dev, "failed initializing VCE2 fences (%d).\n", r);
2129 goto error;
2130 }
2131 return;
2132
2133 error:
2134 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0;
2135 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0;
2136 }
2137
cayman_vce_resume(struct radeon_device * rdev)2138 static void cayman_vce_resume(struct radeon_device *rdev)
2139 {
2140 struct radeon_ring *ring;
2141 int r;
2142
2143 if (!rdev->has_vce || !rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size)
2144 return;
2145
2146 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
2147 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0);
2148 if (r) {
2149 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r);
2150 return;
2151 }
2152 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
2153 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0);
2154 if (r) {
2155 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r);
2156 return;
2157 }
2158 r = vce_v1_0_init(rdev);
2159 if (r) {
2160 dev_err(rdev->dev, "failed initializing VCE (%d).\n", r);
2161 return;
2162 }
2163 }
2164
cayman_startup(struct radeon_device * rdev)2165 static int cayman_startup(struct radeon_device *rdev)
2166 {
2167 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2168 int r;
2169
2170 /* enable pcie gen2 link */
2171 evergreen_pcie_gen2_enable(rdev);
2172 /* enable aspm */
2173 evergreen_program_aspm(rdev);
2174
2175 /* scratch needs to be initialized before MC */
2176 r = r600_vram_scratch_init(rdev);
2177 if (r)
2178 return r;
2179
2180 evergreen_mc_program(rdev);
2181
2182 if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) {
2183 r = ni_mc_load_microcode(rdev);
2184 if (r) {
2185 DRM_ERROR("Failed to load MC firmware!\n");
2186 return r;
2187 }
2188 }
2189
2190 r = cayman_pcie_gart_enable(rdev);
2191 if (r)
2192 return r;
2193 cayman_gpu_init(rdev);
2194
2195 /* allocate rlc buffers */
2196 if (rdev->flags & RADEON_IS_IGP) {
2197 rdev->rlc.reg_list = tn_rlc_save_restore_register_list;
2198 rdev->rlc.reg_list_size =
2199 (u32)ARRAY_SIZE(tn_rlc_save_restore_register_list);
2200 rdev->rlc.cs_data = cayman_cs_data;
2201 r = sumo_rlc_init(rdev);
2202 if (r) {
2203 DRM_ERROR("Failed to init rlc BOs!\n");
2204 return r;
2205 }
2206 }
2207
2208 /* allocate wb buffer */
2209 r = radeon_wb_init(rdev);
2210 if (r)
2211 return r;
2212
2213 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2214 if (r) {
2215 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2216 return r;
2217 }
2218
2219 cayman_uvd_start(rdev);
2220 cayman_vce_start(rdev);
2221
2222 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
2223 if (r) {
2224 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2225 return r;
2226 }
2227
2228 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
2229 if (r) {
2230 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2231 return r;
2232 }
2233
2234 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
2235 if (r) {
2236 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2237 return r;
2238 }
2239
2240 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
2241 if (r) {
2242 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2243 return r;
2244 }
2245
2246 /* Enable IRQ */
2247 if (!rdev->irq.installed) {
2248 r = radeon_irq_kms_init(rdev);
2249 if (r)
2250 return r;
2251 }
2252
2253 r = r600_irq_init(rdev);
2254 if (r) {
2255 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2256 radeon_irq_kms_fini(rdev);
2257 return r;
2258 }
2259 evergreen_irq_set(rdev);
2260
2261 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
2262 RADEON_CP_PACKET2);
2263 if (r)
2264 return r;
2265
2266 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2267 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
2268 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2269 if (r)
2270 return r;
2271
2272 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
2273 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
2274 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2275 if (r)
2276 return r;
2277
2278 r = cayman_cp_load_microcode(rdev);
2279 if (r)
2280 return r;
2281 r = cayman_cp_resume(rdev);
2282 if (r)
2283 return r;
2284
2285 r = cayman_dma_resume(rdev);
2286 if (r)
2287 return r;
2288
2289 cayman_uvd_resume(rdev);
2290 cayman_vce_resume(rdev);
2291
2292 r = radeon_ib_pool_init(rdev);
2293 if (r) {
2294 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2295 return r;
2296 }
2297
2298 r = radeon_vm_manager_init(rdev);
2299 if (r) {
2300 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
2301 return r;
2302 }
2303
2304 r = radeon_audio_init(rdev);
2305 if (r)
2306 return r;
2307
2308 return 0;
2309 }
2310
cayman_resume(struct radeon_device * rdev)2311 int cayman_resume(struct radeon_device *rdev)
2312 {
2313 int r;
2314
2315 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2316 * posting will perform necessary task to bring back GPU into good
2317 * shape.
2318 */
2319 /* post card */
2320 atom_asic_init(rdev->mode_info.atom_context);
2321
2322 /* init golden registers */
2323 ni_init_golden_registers(rdev);
2324
2325 if (rdev->pm.pm_method == PM_METHOD_DPM)
2326 radeon_pm_resume(rdev);
2327
2328 rdev->accel_working = true;
2329 r = cayman_startup(rdev);
2330 if (r) {
2331 DRM_ERROR("cayman startup failed on resume\n");
2332 rdev->accel_working = false;
2333 return r;
2334 }
2335 return r;
2336 }
2337
cayman_suspend(struct radeon_device * rdev)2338 int cayman_suspend(struct radeon_device *rdev)
2339 {
2340 radeon_pm_suspend(rdev);
2341 radeon_audio_fini(rdev);
2342 radeon_vm_manager_fini(rdev);
2343 cayman_cp_enable(rdev, false);
2344 cayman_dma_stop(rdev);
2345 if (rdev->has_uvd) {
2346 uvd_v1_0_fini(rdev);
2347 radeon_uvd_suspend(rdev);
2348 }
2349 evergreen_irq_suspend(rdev);
2350 radeon_wb_disable(rdev);
2351 cayman_pcie_gart_disable(rdev);
2352 return 0;
2353 }
2354
2355 /* Plan is to move initialization in that function and use
2356 * helper function so that radeon_device_init pretty much
2357 * do nothing more than calling asic specific function. This
2358 * should also allow to remove a bunch of callback function
2359 * like vram_info.
2360 */
cayman_init(struct radeon_device * rdev)2361 int cayman_init(struct radeon_device *rdev)
2362 {
2363 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2364 int r;
2365
2366 /* Read BIOS */
2367 if (!radeon_get_bios(rdev)) {
2368 if (ASIC_IS_AVIVO(rdev))
2369 return -EINVAL;
2370 }
2371 /* Must be an ATOMBIOS */
2372 if (!rdev->is_atom_bios) {
2373 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
2374 return -EINVAL;
2375 }
2376 r = radeon_atombios_init(rdev);
2377 if (r)
2378 return r;
2379
2380 /* Post card if necessary */
2381 if (!radeon_card_posted(rdev)) {
2382 if (!rdev->bios) {
2383 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2384 return -EINVAL;
2385 }
2386 DRM_INFO("GPU not posted. posting now...\n");
2387 atom_asic_init(rdev->mode_info.atom_context);
2388 }
2389 /* init golden registers */
2390 ni_init_golden_registers(rdev);
2391 /* Initialize scratch registers */
2392 r600_scratch_init(rdev);
2393 /* Initialize surface registers */
2394 radeon_surface_init(rdev);
2395 /* Initialize clocks */
2396 radeon_get_clock_info(rdev->ddev);
2397 /* Fence driver */
2398 r = radeon_fence_driver_init(rdev);
2399 if (r)
2400 return r;
2401 /* initialize memory controller */
2402 r = evergreen_mc_init(rdev);
2403 if (r)
2404 return r;
2405 /* Memory manager */
2406 r = radeon_bo_init(rdev);
2407 if (r)
2408 return r;
2409
2410 if (rdev->flags & RADEON_IS_IGP) {
2411 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2412 r = ni_init_microcode(rdev);
2413 if (r) {
2414 DRM_ERROR("Failed to load firmware!\n");
2415 return r;
2416 }
2417 }
2418 } else {
2419 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
2420 r = ni_init_microcode(rdev);
2421 if (r) {
2422 DRM_ERROR("Failed to load firmware!\n");
2423 return r;
2424 }
2425 }
2426 }
2427
2428 /* Initialize power management */
2429 radeon_pm_init(rdev);
2430
2431 ring->ring_obj = NULL;
2432 r600_ring_init(rdev, ring, 1024 * 1024);
2433
2434 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2435 ring->ring_obj = NULL;
2436 r600_ring_init(rdev, ring, 64 * 1024);
2437
2438 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
2439 ring->ring_obj = NULL;
2440 r600_ring_init(rdev, ring, 64 * 1024);
2441
2442 cayman_uvd_init(rdev);
2443 cayman_vce_init(rdev);
2444
2445 rdev->ih.ring_obj = NULL;
2446 r600_ih_ring_init(rdev, 64 * 1024);
2447
2448 r = r600_pcie_gart_init(rdev);
2449 if (r)
2450 return r;
2451
2452 rdev->accel_working = true;
2453 r = cayman_startup(rdev);
2454 if (r) {
2455 dev_err(rdev->dev, "disabling GPU acceleration\n");
2456 cayman_cp_fini(rdev);
2457 cayman_dma_fini(rdev);
2458 r600_irq_fini(rdev);
2459 if (rdev->flags & RADEON_IS_IGP)
2460 sumo_rlc_fini(rdev);
2461 radeon_wb_fini(rdev);
2462 radeon_ib_pool_fini(rdev);
2463 radeon_vm_manager_fini(rdev);
2464 radeon_irq_kms_fini(rdev);
2465 cayman_pcie_gart_fini(rdev);
2466 rdev->accel_working = false;
2467 }
2468
2469 /* Don't start up if the MC ucode is missing.
2470 * The default clocks and voltages before the MC ucode
2471 * is loaded are not suffient for advanced operations.
2472 *
2473 * We can skip this check for TN, because there is no MC
2474 * ucode.
2475 */
2476 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
2477 DRM_ERROR("radeon: MC ucode required for NI+.\n");
2478 return -EINVAL;
2479 }
2480
2481 return 0;
2482 }
2483
cayman_fini(struct radeon_device * rdev)2484 void cayman_fini(struct radeon_device *rdev)
2485 {
2486 radeon_pm_fini(rdev);
2487 cayman_cp_fini(rdev);
2488 cayman_dma_fini(rdev);
2489 r600_irq_fini(rdev);
2490 if (rdev->flags & RADEON_IS_IGP)
2491 sumo_rlc_fini(rdev);
2492 radeon_wb_fini(rdev);
2493 radeon_vm_manager_fini(rdev);
2494 radeon_ib_pool_fini(rdev);
2495 radeon_irq_kms_fini(rdev);
2496 uvd_v1_0_fini(rdev);
2497 radeon_uvd_fini(rdev);
2498 if (rdev->has_vce)
2499 radeon_vce_fini(rdev);
2500 cayman_pcie_gart_fini(rdev);
2501 r600_vram_scratch_fini(rdev);
2502 radeon_gem_fini(rdev);
2503 radeon_fence_driver_fini(rdev);
2504 radeon_bo_fini(rdev);
2505 radeon_atombios_fini(rdev);
2506 kfree(rdev->bios);
2507 rdev->bios = NULL;
2508 }
2509
2510 /*
2511 * vm
2512 */
cayman_vm_init(struct radeon_device * rdev)2513 int cayman_vm_init(struct radeon_device *rdev)
2514 {
2515 /* number of VMs */
2516 rdev->vm_manager.nvm = 8;
2517 /* base offset of vram pages */
2518 if (rdev->flags & RADEON_IS_IGP) {
2519 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
2520 tmp <<= 22;
2521 rdev->vm_manager.vram_base_offset = tmp;
2522 } else
2523 rdev->vm_manager.vram_base_offset = 0;
2524 return 0;
2525 }
2526
cayman_vm_fini(struct radeon_device * rdev)2527 void cayman_vm_fini(struct radeon_device *rdev)
2528 {
2529 }
2530
2531 /**
2532 * cayman_vm_decode_fault - print human readable fault info
2533 *
2534 * @rdev: radeon_device pointer
2535 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
2536 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
2537 *
2538 * Print human readable fault information (cayman/TN).
2539 */
cayman_vm_decode_fault(struct radeon_device * rdev,u32 status,u32 addr)2540 void cayman_vm_decode_fault(struct radeon_device *rdev,
2541 u32 status, u32 addr)
2542 {
2543 u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
2544 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
2545 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
2546 const char *block;
2547
2548 switch (mc_id) {
2549 case 32:
2550 case 16:
2551 case 96:
2552 case 80:
2553 case 160:
2554 case 144:
2555 case 224:
2556 case 208:
2557 block = "CB";
2558 break;
2559 case 33:
2560 case 17:
2561 case 97:
2562 case 81:
2563 case 161:
2564 case 145:
2565 case 225:
2566 case 209:
2567 block = "CB_FMASK";
2568 break;
2569 case 34:
2570 case 18:
2571 case 98:
2572 case 82:
2573 case 162:
2574 case 146:
2575 case 226:
2576 case 210:
2577 block = "CB_CMASK";
2578 break;
2579 case 35:
2580 case 19:
2581 case 99:
2582 case 83:
2583 case 163:
2584 case 147:
2585 case 227:
2586 case 211:
2587 block = "CB_IMMED";
2588 break;
2589 case 36:
2590 case 20:
2591 case 100:
2592 case 84:
2593 case 164:
2594 case 148:
2595 case 228:
2596 case 212:
2597 block = "DB";
2598 break;
2599 case 37:
2600 case 21:
2601 case 101:
2602 case 85:
2603 case 165:
2604 case 149:
2605 case 229:
2606 case 213:
2607 block = "DB_HTILE";
2608 break;
2609 case 38:
2610 case 22:
2611 case 102:
2612 case 86:
2613 case 166:
2614 case 150:
2615 case 230:
2616 case 214:
2617 block = "SX";
2618 break;
2619 case 39:
2620 case 23:
2621 case 103:
2622 case 87:
2623 case 167:
2624 case 151:
2625 case 231:
2626 case 215:
2627 block = "DB_STEN";
2628 break;
2629 case 40:
2630 case 24:
2631 case 104:
2632 case 88:
2633 case 232:
2634 case 216:
2635 case 168:
2636 case 152:
2637 block = "TC_TFETCH";
2638 break;
2639 case 41:
2640 case 25:
2641 case 105:
2642 case 89:
2643 case 233:
2644 case 217:
2645 case 169:
2646 case 153:
2647 block = "TC_VFETCH";
2648 break;
2649 case 42:
2650 case 26:
2651 case 106:
2652 case 90:
2653 case 234:
2654 case 218:
2655 case 170:
2656 case 154:
2657 block = "VC";
2658 break;
2659 case 112:
2660 block = "CP";
2661 break;
2662 case 113:
2663 case 114:
2664 block = "SH";
2665 break;
2666 case 115:
2667 block = "VGT";
2668 break;
2669 case 178:
2670 block = "IH";
2671 break;
2672 case 51:
2673 block = "RLC";
2674 break;
2675 case 55:
2676 block = "DMA";
2677 break;
2678 case 56:
2679 block = "HDP";
2680 break;
2681 default:
2682 block = "unknown";
2683 break;
2684 }
2685
2686 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
2687 protections, vmid, addr,
2688 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
2689 block, mc_id);
2690 }
2691
2692 /**
2693 * cayman_vm_flush - vm flush using the CP
2694 *
2695 * @rdev: radeon_device pointer
2696 *
2697 * Update the page table base and flush the VM TLB
2698 * using the CP (cayman-si).
2699 */
cayman_vm_flush(struct radeon_device * rdev,struct radeon_ring * ring,unsigned vm_id,uint64_t pd_addr)2700 void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
2701 unsigned vm_id, uint64_t pd_addr)
2702 {
2703 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2), 0));
2704 radeon_ring_write(ring, pd_addr >> 12);
2705
2706 /* flush hdp cache */
2707 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
2708 radeon_ring_write(ring, 0x1);
2709
2710 /* bits 0-7 are the VM contexts0-7 */
2711 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
2712 radeon_ring_write(ring, 1 << vm_id);
2713
2714 /* wait for the invalidate to complete */
2715 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2716 radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
2717 WAIT_REG_MEM_ENGINE(0))); /* me */
2718 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
2719 radeon_ring_write(ring, 0);
2720 radeon_ring_write(ring, 0); /* ref */
2721 radeon_ring_write(ring, 0); /* mask */
2722 radeon_ring_write(ring, 0x20); /* poll interval */
2723
2724 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2725 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2726 radeon_ring_write(ring, 0x0);
2727 }
2728
tn_set_vce_clocks(struct radeon_device * rdev,u32 evclk,u32 ecclk)2729 int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk)
2730 {
2731 struct atom_clock_dividers dividers;
2732 int r, i;
2733
2734 r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
2735 ecclk, false, ÷rs);
2736 if (r)
2737 return r;
2738
2739 for (i = 0; i < 100; i++) {
2740 if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS)
2741 break;
2742 mdelay(10);
2743 }
2744 if (i == 100)
2745 return -ETIMEDOUT;
2746
2747 WREG32_P(CG_ECLK_CNTL, dividers.post_div, ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK));
2748
2749 for (i = 0; i < 100; i++) {
2750 if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS)
2751 break;
2752 mdelay(10);
2753 }
2754 if (i == 100)
2755 return -ETIMEDOUT;
2756
2757 return 0;
2758 }
2759