1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright(c) 2020 Intel Corporation. */
3
4 #ifndef __CXL_H__
5 #define __CXL_H__
6
7 #include <linux/libnvdimm.h>
8 #include <linux/bitfield.h>
9 #include <linux/notifier.h>
10 #include <linux/bitops.h>
11 #include <linux/log2.h>
12 #include <linux/node.h>
13 #include <linux/io.h>
14
15 extern const struct nvdimm_security_ops *cxl_security_ops;
16
17 /**
18 * DOC: cxl objects
19 *
20 * The CXL core objects like ports, decoders, and regions are shared
21 * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers
22 * (port-driver, region-driver, nvdimm object-drivers... etc).
23 */
24
25 /* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */
26 #define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K
27
28 /* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/
29 #define CXL_CM_OFFSET 0x1000
30 #define CXL_CM_CAP_HDR_OFFSET 0x0
31 #define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0)
32 #define CM_CAP_HDR_CAP_ID 1
33 #define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16)
34 #define CM_CAP_HDR_CAP_VERSION 1
35 #define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20)
36 #define CM_CAP_HDR_CACHE_MEM_VERSION 1
37 #define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24)
38 #define CXL_CM_CAP_PTR_MASK GENMASK(31, 20)
39
40 #define CXL_CM_CAP_CAP_ID_RAS 0x2
41 #define CXL_CM_CAP_CAP_ID_HDM 0x5
42 #define CXL_CM_CAP_CAP_HDM_VERSION 1
43
44 /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */
45 #define CXL_HDM_DECODER_CAP_OFFSET 0x0
46 #define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0)
47 #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4)
48 #define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8)
49 #define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9)
50 #define CXL_HDM_DECODER_CTRL_OFFSET 0x4
51 #define CXL_HDM_DECODER_ENABLE BIT(1)
52 #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10)
53 #define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14)
54 #define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18)
55 #define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c)
56 #define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20)
57 #define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0)
58 #define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4)
59 #define CXL_HDM_DECODER0_CTRL_LOCK BIT(8)
60 #define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9)
61 #define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10)
62 #define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11)
63 #define CXL_HDM_DECODER0_CTRL_HOSTONLY BIT(12)
64 #define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24)
65 #define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28)
66 #define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i)
67 #define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i)
68
69 /* HDM decoder control register constants CXL 3.0 8.2.5.19.7 */
70 #define CXL_DECODER_MIN_GRANULARITY 256
71 #define CXL_DECODER_MAX_ENCODED_IG 6
72
cxl_hdm_decoder_count(u32 cap_hdr)73 static inline int cxl_hdm_decoder_count(u32 cap_hdr)
74 {
75 int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr);
76
77 return val ? val * 2 : 1;
78 }
79
80 /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */
eig_to_granularity(u16 eig,unsigned int * granularity)81 static inline int eig_to_granularity(u16 eig, unsigned int *granularity)
82 {
83 if (eig > CXL_DECODER_MAX_ENCODED_IG)
84 return -EINVAL;
85 *granularity = CXL_DECODER_MIN_GRANULARITY << eig;
86 return 0;
87 }
88
89 /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */
eiw_to_ways(u8 eiw,unsigned int * ways)90 static inline int eiw_to_ways(u8 eiw, unsigned int *ways)
91 {
92 switch (eiw) {
93 case 0 ... 4:
94 *ways = 1 << eiw;
95 break;
96 case 8 ... 10:
97 *ways = 3 << (eiw - 8);
98 break;
99 default:
100 return -EINVAL;
101 }
102
103 return 0;
104 }
105
granularity_to_eig(int granularity,u16 * eig)106 static inline int granularity_to_eig(int granularity, u16 *eig)
107 {
108 if (granularity > SZ_16K || granularity < CXL_DECODER_MIN_GRANULARITY ||
109 !is_power_of_2(granularity))
110 return -EINVAL;
111 *eig = ilog2(granularity) - 8;
112 return 0;
113 }
114
ways_to_eiw(unsigned int ways,u8 * eiw)115 static inline int ways_to_eiw(unsigned int ways, u8 *eiw)
116 {
117 if (ways > 16)
118 return -EINVAL;
119 if (is_power_of_2(ways)) {
120 *eiw = ilog2(ways);
121 return 0;
122 }
123 if (ways % 3)
124 return -EINVAL;
125 ways /= 3;
126 if (!is_power_of_2(ways))
127 return -EINVAL;
128 *eiw = ilog2(ways) + 8;
129 return 0;
130 }
131
132 /* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */
133 #define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET 0x0
134 #define CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0))
135 #define CXL_RAS_UNCORRECTABLE_MASK_OFFSET 0x4
136 #define CXL_RAS_UNCORRECTABLE_MASK_MASK (GENMASK(16, 14) | GENMASK(11, 0))
137 #define CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK BIT(8)
138 #define CXL_RAS_UNCORRECTABLE_SEVERITY_OFFSET 0x8
139 #define CXL_RAS_UNCORRECTABLE_SEVERITY_MASK (GENMASK(16, 14) | GENMASK(11, 0))
140 #define CXL_RAS_CORRECTABLE_STATUS_OFFSET 0xC
141 #define CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0)
142 #define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10
143 #define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0)
144 #define CXL_RAS_CAP_CONTROL_OFFSET 0x14
145 #define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0)
146 #define CXL_RAS_HEADER_LOG_OFFSET 0x18
147 #define CXL_RAS_CAPABILITY_LENGTH 0x58
148 #define CXL_HEADERLOG_SIZE SZ_512
149 #define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32)
150
151 /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */
152 #define CXLDEV_CAP_ARRAY_OFFSET 0x0
153 #define CXLDEV_CAP_ARRAY_CAP_ID 0
154 #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0)
155 #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32)
156 /* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */
157 #define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0)
158 /* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */
159 #define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1
160 #define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2
161 #define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3
162 #define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000
163
164 /* CXL 3.0 8.2.8.3.1 Event Status Register */
165 #define CXLDEV_DEV_EVENT_STATUS_OFFSET 0x00
166 #define CXLDEV_EVENT_STATUS_INFO BIT(0)
167 #define CXLDEV_EVENT_STATUS_WARN BIT(1)
168 #define CXLDEV_EVENT_STATUS_FAIL BIT(2)
169 #define CXLDEV_EVENT_STATUS_FATAL BIT(3)
170
171 #define CXLDEV_EVENT_STATUS_ALL (CXLDEV_EVENT_STATUS_INFO | \
172 CXLDEV_EVENT_STATUS_WARN | \
173 CXLDEV_EVENT_STATUS_FAIL | \
174 CXLDEV_EVENT_STATUS_FATAL)
175
176 /* CXL rev 3.0 section 8.2.9.2.4; Table 8-52 */
177 #define CXLDEV_EVENT_INT_MODE_MASK GENMASK(1, 0)
178 #define CXLDEV_EVENT_INT_MSGNUM_MASK GENMASK(7, 4)
179
180 /* CXL 2.0 8.2.8.4 Mailbox Registers */
181 #define CXLDEV_MBOX_CAPS_OFFSET 0x00
182 #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0)
183 #define CXLDEV_MBOX_CAP_BG_CMD_IRQ BIT(6)
184 #define CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK GENMASK(10, 7)
185 #define CXLDEV_MBOX_CTRL_OFFSET 0x04
186 #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0)
187 #define CXLDEV_MBOX_CTRL_BG_CMD_IRQ BIT(2)
188 #define CXLDEV_MBOX_CMD_OFFSET 0x08
189 #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0)
190 #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16)
191 #define CXLDEV_MBOX_STATUS_OFFSET 0x10
192 #define CXLDEV_MBOX_STATUS_BG_CMD BIT(0)
193 #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32)
194 #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18
195 #define CXLDEV_MBOX_BG_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0)
196 #define CXLDEV_MBOX_BG_CMD_COMMAND_PCT_MASK GENMASK_ULL(22, 16)
197 #define CXLDEV_MBOX_BG_CMD_COMMAND_RC_MASK GENMASK_ULL(47, 32)
198 #define CXLDEV_MBOX_BG_CMD_COMMAND_VENDOR_MASK GENMASK_ULL(63, 48)
199 #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20
200
201 /*
202 * Using struct_group() allows for per register-block-type helper routines,
203 * without requiring block-type agnostic code to include the prefix.
204 */
205 struct cxl_regs {
206 /*
207 * Common set of CXL Component register block base pointers
208 * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure
209 * @ras: CXL 2.0 8.2.5.9 CXL RAS Capability Structure
210 */
211 struct_group_tagged(cxl_component_regs, component,
212 void __iomem *hdm_decoder;
213 void __iomem *ras;
214 );
215 /*
216 * Common set of CXL Device register block base pointers
217 * @status: CXL 2.0 8.2.8.3 Device Status Registers
218 * @mbox: CXL 2.0 8.2.8.4 Mailbox Registers
219 * @memdev: CXL 2.0 8.2.8.5 Memory Device Registers
220 */
221 struct_group_tagged(cxl_device_regs, device_regs,
222 void __iomem *status, *mbox, *memdev;
223 );
224
225 struct_group_tagged(cxl_pmu_regs, pmu_regs,
226 void __iomem *pmu;
227 );
228
229 /*
230 * RCH downstream port specific RAS register
231 * @aer: CXL 3.0 8.2.1.1 RCH Downstream Port RCRB
232 */
233 struct_group_tagged(cxl_rch_regs, rch_regs,
234 void __iomem *dport_aer;
235 );
236 };
237
238 struct cxl_reg_map {
239 bool valid;
240 int id;
241 unsigned long offset;
242 unsigned long size;
243 };
244
245 struct cxl_component_reg_map {
246 struct cxl_reg_map hdm_decoder;
247 struct cxl_reg_map ras;
248 };
249
250 struct cxl_device_reg_map {
251 struct cxl_reg_map status;
252 struct cxl_reg_map mbox;
253 struct cxl_reg_map memdev;
254 };
255
256 struct cxl_pmu_reg_map {
257 struct cxl_reg_map pmu;
258 };
259
260 /**
261 * struct cxl_register_map - DVSEC harvested register block mapping parameters
262 * @host: device for devm operations and logging
263 * @base: virtual base of the register-block-BAR + @block_offset
264 * @resource: physical resource base of the register block
265 * @max_size: maximum mapping size to perform register search
266 * @reg_type: see enum cxl_regloc_type
267 * @component_map: cxl_reg_map for component registers
268 * @device_map: cxl_reg_maps for device registers
269 * @pmu_map: cxl_reg_maps for CXL Performance Monitoring Units
270 */
271 struct cxl_register_map {
272 struct device *host;
273 void __iomem *base;
274 resource_size_t resource;
275 resource_size_t max_size;
276 u8 reg_type;
277 union {
278 struct cxl_component_reg_map component_map;
279 struct cxl_device_reg_map device_map;
280 struct cxl_pmu_reg_map pmu_map;
281 };
282 };
283
284 void cxl_probe_component_regs(struct device *dev, void __iomem *base,
285 struct cxl_component_reg_map *map);
286 void cxl_probe_device_regs(struct device *dev, void __iomem *base,
287 struct cxl_device_reg_map *map);
288 int cxl_map_component_regs(const struct cxl_register_map *map,
289 struct cxl_component_regs *regs,
290 unsigned long map_mask);
291 int cxl_map_device_regs(const struct cxl_register_map *map,
292 struct cxl_device_regs *regs);
293 int cxl_map_pmu_regs(struct cxl_register_map *map, struct cxl_pmu_regs *regs);
294
295 enum cxl_regloc_type;
296 int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type);
297 int cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type,
298 struct cxl_register_map *map, int index);
299 int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
300 struct cxl_register_map *map);
301 int cxl_setup_regs(struct cxl_register_map *map);
302 struct cxl_dport;
303 resource_size_t cxl_rcd_component_reg_phys(struct device *dev,
304 struct cxl_dport *dport);
305
306 #define CXL_RESOURCE_NONE ((resource_size_t) -1)
307 #define CXL_TARGET_STRLEN 20
308
309 /*
310 * cxl_decoder flags that define the type of memory / devices this
311 * decoder supports as well as configuration lock status See "CXL 2.0
312 * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details.
313 * Additionally indicate whether decoder settings were autodetected,
314 * user customized.
315 */
316 #define CXL_DECODER_F_RAM BIT(0)
317 #define CXL_DECODER_F_PMEM BIT(1)
318 #define CXL_DECODER_F_TYPE2 BIT(2)
319 #define CXL_DECODER_F_TYPE3 BIT(3)
320 #define CXL_DECODER_F_LOCK BIT(4)
321 #define CXL_DECODER_F_ENABLE BIT(5)
322 #define CXL_DECODER_F_MASK GENMASK(5, 0)
323
324 enum cxl_decoder_type {
325 CXL_DECODER_DEVMEM = 2,
326 CXL_DECODER_HOSTONLYMEM = 3,
327 };
328
329 /*
330 * Current specification goes up to 8, double that seems a reasonable
331 * software max for the foreseeable future
332 */
333 #define CXL_DECODER_MAX_INTERLEAVE 16
334
335 #define CXL_QOS_CLASS_INVALID -1
336
337 /**
338 * struct cxl_decoder - Common CXL HDM Decoder Attributes
339 * @dev: this decoder's device
340 * @id: kernel device name id
341 * @hpa_range: Host physical address range mapped by this decoder
342 * @interleave_ways: number of cxl_dports in this decode
343 * @interleave_granularity: data stride per dport
344 * @target_type: accelerator vs expander (type2 vs type3) selector
345 * @region: currently assigned region for this decoder
346 * @flags: memory type capabilities and locking
347 * @commit: device/decoder-type specific callback to commit settings to hw
348 * @reset: device/decoder-type specific callback to reset hw settings
349 */
350 struct cxl_decoder {
351 struct device dev;
352 int id;
353 struct range hpa_range;
354 int interleave_ways;
355 int interleave_granularity;
356 enum cxl_decoder_type target_type;
357 struct cxl_region *region;
358 unsigned long flags;
359 int (*commit)(struct cxl_decoder *cxld);
360 int (*reset)(struct cxl_decoder *cxld);
361 };
362
363 /*
364 * CXL_DECODER_DEAD prevents endpoints from being reattached to regions
365 * while cxld_unregister() is running
366 */
367 enum cxl_decoder_mode {
368 CXL_DECODER_NONE,
369 CXL_DECODER_RAM,
370 CXL_DECODER_PMEM,
371 CXL_DECODER_MIXED,
372 CXL_DECODER_DEAD,
373 };
374
cxl_decoder_mode_name(enum cxl_decoder_mode mode)375 static inline const char *cxl_decoder_mode_name(enum cxl_decoder_mode mode)
376 {
377 static const char * const names[] = {
378 [CXL_DECODER_NONE] = "none",
379 [CXL_DECODER_RAM] = "ram",
380 [CXL_DECODER_PMEM] = "pmem",
381 [CXL_DECODER_MIXED] = "mixed",
382 };
383
384 if (mode >= CXL_DECODER_NONE && mode <= CXL_DECODER_MIXED)
385 return names[mode];
386 return "mixed";
387 }
388
389 /*
390 * Track whether this decoder is reserved for region autodiscovery, or
391 * free for userspace provisioning.
392 */
393 enum cxl_decoder_state {
394 CXL_DECODER_STATE_MANUAL,
395 CXL_DECODER_STATE_AUTO,
396 };
397
398 /**
399 * struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder
400 * @cxld: base cxl_decoder_object
401 * @dpa_res: actively claimed DPA span of this decoder
402 * @skip: offset into @dpa_res where @cxld.hpa_range maps
403 * @mode: which memory type / access-mode-partition this decoder targets
404 * @state: autodiscovery state
405 * @pos: interleave position in @cxld.region
406 */
407 struct cxl_endpoint_decoder {
408 struct cxl_decoder cxld;
409 struct resource *dpa_res;
410 resource_size_t skip;
411 enum cxl_decoder_mode mode;
412 enum cxl_decoder_state state;
413 int pos;
414 };
415
416 /**
417 * struct cxl_switch_decoder - Switch specific CXL HDM Decoder
418 * @cxld: base cxl_decoder object
419 * @nr_targets: number of elements in @target
420 * @target: active ordered target list in current decoder configuration
421 *
422 * The 'switch' decoder type represents the decoder instances of cxl_port's that
423 * route from the root of a CXL memory decode topology to the endpoints. They
424 * come in two flavors, root-level decoders, statically defined by platform
425 * firmware, and mid-level decoders, where interleave-granularity,
426 * interleave-width, and the target list are mutable.
427 */
428 struct cxl_switch_decoder {
429 struct cxl_decoder cxld;
430 int nr_targets;
431 struct cxl_dport *target[];
432 };
433
434 struct cxl_root_decoder;
435 typedef struct cxl_dport *(*cxl_calc_hb_fn)(struct cxl_root_decoder *cxlrd,
436 int pos);
437
438 /**
439 * struct cxl_root_decoder - Static platform CXL address decoder
440 * @res: host / parent resource for region allocations
441 * @region_id: region id for next region provisioning event
442 * @calc_hb: which host bridge covers the n'th position by granularity
443 * @platform_data: platform specific configuration data
444 * @range_lock: sync region autodiscovery by address range
445 * @qos_class: QoS performance class cookie
446 * @cxlsd: base cxl switch decoder
447 */
448 struct cxl_root_decoder {
449 struct resource *res;
450 atomic_t region_id;
451 cxl_calc_hb_fn calc_hb;
452 void *platform_data;
453 struct mutex range_lock;
454 int qos_class;
455 struct cxl_switch_decoder cxlsd;
456 };
457
458 /*
459 * enum cxl_config_state - State machine for region configuration
460 * @CXL_CONFIG_IDLE: Any sysfs attribute can be written freely
461 * @CXL_CONFIG_INTERLEAVE_ACTIVE: region size has been set, no more
462 * changes to interleave_ways or interleave_granularity
463 * @CXL_CONFIG_ACTIVE: All targets have been added the region is now
464 * active
465 * @CXL_CONFIG_RESET_PENDING: see commit_store()
466 * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware
467 */
468 enum cxl_config_state {
469 CXL_CONFIG_IDLE,
470 CXL_CONFIG_INTERLEAVE_ACTIVE,
471 CXL_CONFIG_ACTIVE,
472 CXL_CONFIG_RESET_PENDING,
473 CXL_CONFIG_COMMIT,
474 };
475
476 /**
477 * struct cxl_region_params - region settings
478 * @state: allow the driver to lockdown further parameter changes
479 * @uuid: unique id for persistent regions
480 * @interleave_ways: number of endpoints in the region
481 * @interleave_granularity: capacity each endpoint contributes to a stripe
482 * @res: allocated iomem capacity for this region
483 * @targets: active ordered targets in current decoder configuration
484 * @nr_targets: number of targets
485 *
486 * State transitions are protected by the cxl_region_rwsem
487 */
488 struct cxl_region_params {
489 enum cxl_config_state state;
490 uuid_t uuid;
491 int interleave_ways;
492 int interleave_granularity;
493 struct resource *res;
494 struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE];
495 int nr_targets;
496 };
497
498 /*
499 * Indicate whether this region has been assembled by autodetection or
500 * userspace assembly. Prevent endpoint decoders outside of automatic
501 * detection from being added to the region.
502 */
503 #define CXL_REGION_F_AUTO 0
504
505 /*
506 * Require that a committed region successfully complete a teardown once
507 * any of its associated decoders have been torn down. This maintains
508 * the commit state for the region since there are committed decoders,
509 * but blocks cxl_region_probe().
510 */
511 #define CXL_REGION_F_NEEDS_RESET 1
512
513 /**
514 * struct cxl_region - CXL region
515 * @dev: This region's device
516 * @id: This region's id. Id is globally unique across all regions
517 * @mode: Endpoint decoder allocation / access mode
518 * @type: Endpoint decoder target type
519 * @cxl_nvb: nvdimm bridge for coordinating @cxlr_pmem setup / shutdown
520 * @cxlr_pmem: (for pmem regions) cached copy of the nvdimm bridge
521 * @flags: Region state flags
522 * @params: active + config params for the region
523 * @coord: QoS access coordinates for the region
524 * @memory_notifier: notifier for setting the access coordinates to node
525 */
526 struct cxl_region {
527 struct device dev;
528 int id;
529 enum cxl_decoder_mode mode;
530 enum cxl_decoder_type type;
531 struct cxl_nvdimm_bridge *cxl_nvb;
532 struct cxl_pmem_region *cxlr_pmem;
533 unsigned long flags;
534 struct cxl_region_params params;
535 struct access_coordinate coord[ACCESS_COORDINATE_MAX];
536 struct notifier_block memory_notifier;
537 };
538
539 struct cxl_nvdimm_bridge {
540 int id;
541 struct device dev;
542 struct cxl_port *port;
543 struct nvdimm_bus *nvdimm_bus;
544 struct nvdimm_bus_descriptor nd_desc;
545 };
546
547 #define CXL_DEV_ID_LEN 19
548
549 struct cxl_nvdimm {
550 struct device dev;
551 struct cxl_memdev *cxlmd;
552 u8 dev_id[CXL_DEV_ID_LEN]; /* for nvdimm, string of 'serial' */
553 };
554
555 struct cxl_pmem_region_mapping {
556 struct cxl_memdev *cxlmd;
557 struct cxl_nvdimm *cxl_nvd;
558 u64 start;
559 u64 size;
560 int position;
561 };
562
563 struct cxl_pmem_region {
564 struct device dev;
565 struct cxl_region *cxlr;
566 struct nd_region *nd_region;
567 struct range hpa_range;
568 int nr_mappings;
569 struct cxl_pmem_region_mapping mapping[];
570 };
571
572 struct cxl_dax_region {
573 struct device dev;
574 struct cxl_region *cxlr;
575 struct range hpa_range;
576 };
577
578 /**
579 * struct cxl_port - logical collection of upstream port devices and
580 * downstream port devices to construct a CXL memory
581 * decode hierarchy.
582 * @dev: this port's device
583 * @uport_dev: PCI or platform device implementing the upstream port capability
584 * @host_bridge: Shortcut to the platform attach point for this port
585 * @id: id for port device-name
586 * @dports: cxl_dport instances referenced by decoders
587 * @endpoints: cxl_ep instances, endpoints that are a descendant of this port
588 * @regions: cxl_region_ref instances, regions mapped by this port
589 * @parent_dport: dport that points to this port in the parent
590 * @decoder_ida: allocator for decoder ids
591 * @reg_map: component and ras register mapping parameters
592 * @nr_dports: number of entries in @dports
593 * @hdm_end: track last allocated HDM decoder instance for allocation ordering
594 * @commit_end: cursor to track highest committed decoder for commit ordering
595 * @dead: last ep has been removed, force port re-creation
596 * @depth: How deep this port is relative to the root. depth 0 is the root.
597 * @cdat: Cached CDAT data
598 * @cdat_available: Should a CDAT attribute be available in sysfs
599 * @pci_latency: Upstream latency in picoseconds
600 */
601 struct cxl_port {
602 struct device dev;
603 struct device *uport_dev;
604 struct device *host_bridge;
605 int id;
606 struct xarray dports;
607 struct xarray endpoints;
608 struct xarray regions;
609 struct cxl_dport *parent_dport;
610 struct ida decoder_ida;
611 struct cxl_register_map reg_map;
612 int nr_dports;
613 int hdm_end;
614 int commit_end;
615 bool dead;
616 unsigned int depth;
617 struct cxl_cdat {
618 void *table;
619 size_t length;
620 } cdat;
621 bool cdat_available;
622 long pci_latency;
623 };
624
625 /**
626 * struct cxl_root - logical collection of root cxl_port items
627 *
628 * @port: cxl_port member
629 * @ops: cxl root operations
630 */
631 struct cxl_root {
632 struct cxl_port port;
633 const struct cxl_root_ops *ops;
634 };
635
636 static inline struct cxl_root *
to_cxl_root(const struct cxl_port * port)637 to_cxl_root(const struct cxl_port *port)
638 {
639 return container_of(port, struct cxl_root, port);
640 }
641
642 struct cxl_root_ops {
643 int (*qos_class)(struct cxl_root *cxl_root,
644 struct access_coordinate *coord, int entries,
645 int *qos_class);
646 };
647
648 static inline struct cxl_dport *
cxl_find_dport_by_dev(struct cxl_port * port,const struct device * dport_dev)649 cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev)
650 {
651 return xa_load(&port->dports, (unsigned long)dport_dev);
652 }
653
654 struct cxl_rcrb_info {
655 resource_size_t base;
656 u16 aer_cap;
657 };
658
659 /**
660 * struct cxl_dport - CXL downstream port
661 * @dport_dev: PCI bridge or firmware device representing the downstream link
662 * @reg_map: component and ras register mapping parameters
663 * @port_id: unique hardware identifier for dport in decoder target list
664 * @rcrb: Data about the Root Complex Register Block layout
665 * @rch: Indicate whether this dport was enumerated in RCH or VH mode
666 * @port: reference to cxl_port that contains this downstream port
667 * @regs: Dport parsed register blocks
668 * @coord: access coordinates (bandwidth and latency performance attributes)
669 * @link_latency: calculated PCIe downstream latency
670 */
671 struct cxl_dport {
672 struct device *dport_dev;
673 struct cxl_register_map reg_map;
674 int port_id;
675 struct cxl_rcrb_info rcrb;
676 bool rch;
677 struct cxl_port *port;
678 struct cxl_regs regs;
679 struct access_coordinate coord[ACCESS_COORDINATE_MAX];
680 long link_latency;
681 };
682
683 /**
684 * struct cxl_ep - track an endpoint's interest in a port
685 * @ep: device that hosts a generic CXL endpoint (expander or accelerator)
686 * @dport: which dport routes to this endpoint on @port
687 * @next: cxl switch port across the link attached to @dport NULL if
688 * attached to an endpoint
689 */
690 struct cxl_ep {
691 struct device *ep;
692 struct cxl_dport *dport;
693 struct cxl_port *next;
694 };
695
696 /**
697 * struct cxl_region_ref - track a region's interest in a port
698 * @port: point in topology to install this reference
699 * @decoder: decoder assigned for @region in @port
700 * @region: region for this reference
701 * @endpoints: cxl_ep references for region members beneath @port
702 * @nr_targets_set: track how many targets have been programmed during setup
703 * @nr_eps: number of endpoints beneath @port
704 * @nr_targets: number of distinct targets needed to reach @nr_eps
705 */
706 struct cxl_region_ref {
707 struct cxl_port *port;
708 struct cxl_decoder *decoder;
709 struct cxl_region *region;
710 struct xarray endpoints;
711 int nr_targets_set;
712 int nr_eps;
713 int nr_targets;
714 };
715
716 /*
717 * The platform firmware device hosting the root is also the top of the
718 * CXL port topology. All other CXL ports have another CXL port as their
719 * parent and their ->uport_dev / host device is out-of-line of the port
720 * ancestry.
721 */
is_cxl_root(struct cxl_port * port)722 static inline bool is_cxl_root(struct cxl_port *port)
723 {
724 return port->uport_dev == port->dev.parent;
725 }
726
727 int cxl_num_decoders_committed(struct cxl_port *port);
728 bool is_cxl_port(const struct device *dev);
729 struct cxl_port *to_cxl_port(const struct device *dev);
730 struct pci_bus;
731 int devm_cxl_register_pci_bus(struct device *host, struct device *uport_dev,
732 struct pci_bus *bus);
733 struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port);
734 struct cxl_port *devm_cxl_add_port(struct device *host,
735 struct device *uport_dev,
736 resource_size_t component_reg_phys,
737 struct cxl_dport *parent_dport);
738 struct cxl_root *devm_cxl_add_root(struct device *host,
739 const struct cxl_root_ops *ops);
740 struct cxl_root *find_cxl_root(struct cxl_port *port);
741 void put_cxl_root(struct cxl_root *cxl_root);
742 DEFINE_FREE(put_cxl_root, struct cxl_root *, if (_T) put_cxl_root(_T))
743
744 int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd);
745 void cxl_bus_rescan(void);
746 void cxl_bus_drain(void);
747 struct cxl_port *cxl_pci_find_port(struct pci_dev *pdev,
748 struct cxl_dport **dport);
749 struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd,
750 struct cxl_dport **dport);
751 bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd);
752
753 struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port,
754 struct device *dport, int port_id,
755 resource_size_t component_reg_phys);
756 struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port,
757 struct device *dport_dev, int port_id,
758 resource_size_t rcrb);
759
760 #ifdef CONFIG_PCIEAER_CXL
761 void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport);
762 #else
cxl_setup_parent_dport(struct device * host,struct cxl_dport * dport)763 static inline void cxl_setup_parent_dport(struct device *host,
764 struct cxl_dport *dport) { }
765 #endif
766
767 struct cxl_decoder *to_cxl_decoder(struct device *dev);
768 struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev);
769 struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev);
770 struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev);
771 bool is_root_decoder(struct device *dev);
772 bool is_switch_decoder(struct device *dev);
773 bool is_endpoint_decoder(struct device *dev);
774 struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port,
775 unsigned int nr_targets,
776 cxl_calc_hb_fn calc_hb);
777 struct cxl_dport *cxl_hb_modulo(struct cxl_root_decoder *cxlrd, int pos);
778 struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port,
779 unsigned int nr_targets);
780 int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map);
781 struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port);
782 int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map);
783 int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld);
cxl_root_decoder_autoremove(struct device * host,struct cxl_root_decoder * cxlrd)784 static inline int cxl_root_decoder_autoremove(struct device *host,
785 struct cxl_root_decoder *cxlrd)
786 {
787 return cxl_decoder_autoremove(host, &cxlrd->cxlsd.cxld);
788 }
789 int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint);
790
791 /**
792 * struct cxl_endpoint_dvsec_info - Cached DVSEC info
793 * @mem_enabled: cached value of mem_enabled in the DVSEC at init time
794 * @ranges: Number of active HDM ranges this device uses.
795 * @port: endpoint port associated with this info instance
796 * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE
797 */
798 struct cxl_endpoint_dvsec_info {
799 bool mem_enabled;
800 int ranges;
801 struct cxl_port *port;
802 struct range dvsec_range[2];
803 };
804
805 struct cxl_hdm;
806 struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
807 struct cxl_endpoint_dvsec_info *info);
808 int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm,
809 struct cxl_endpoint_dvsec_info *info);
810 int devm_cxl_add_passthrough_decoder(struct cxl_port *port);
811 int cxl_dvsec_rr_decode(struct device *dev, int dvsec,
812 struct cxl_endpoint_dvsec_info *info);
813
814 bool is_cxl_region(struct device *dev);
815
816 extern struct bus_type cxl_bus_type;
817
818 struct cxl_driver {
819 const char *name;
820 int (*probe)(struct device *dev);
821 void (*remove)(struct device *dev);
822 struct device_driver drv;
823 int id;
824 };
825
to_cxl_drv(struct device_driver * drv)826 static inline struct cxl_driver *to_cxl_drv(struct device_driver *drv)
827 {
828 return container_of(drv, struct cxl_driver, drv);
829 }
830
831 int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner,
832 const char *modname);
833 #define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME)
834 void cxl_driver_unregister(struct cxl_driver *cxl_drv);
835
836 #define module_cxl_driver(__cxl_driver) \
837 module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister)
838
839 #define CXL_DEVICE_NVDIMM_BRIDGE 1
840 #define CXL_DEVICE_NVDIMM 2
841 #define CXL_DEVICE_PORT 3
842 #define CXL_DEVICE_ROOT 4
843 #define CXL_DEVICE_MEMORY_EXPANDER 5
844 #define CXL_DEVICE_REGION 6
845 #define CXL_DEVICE_PMEM_REGION 7
846 #define CXL_DEVICE_DAX_REGION 8
847 #define CXL_DEVICE_PMU 9
848
849 #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*")
850 #define CXL_MODALIAS_FMT "cxl:t%d"
851
852 struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev);
853 struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host,
854 struct cxl_port *port);
855 struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev);
856 bool is_cxl_nvdimm(struct device *dev);
857 bool is_cxl_nvdimm_bridge(struct device *dev);
858 int devm_cxl_add_nvdimm(struct cxl_memdev *cxlmd);
859 struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd);
860
861 #ifdef CONFIG_CXL_REGION
862 bool is_cxl_pmem_region(struct device *dev);
863 struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev);
864 int cxl_add_to_region(struct cxl_port *root,
865 struct cxl_endpoint_decoder *cxled);
866 struct cxl_dax_region *to_cxl_dax_region(struct device *dev);
867 #else
is_cxl_pmem_region(struct device * dev)868 static inline bool is_cxl_pmem_region(struct device *dev)
869 {
870 return false;
871 }
to_cxl_pmem_region(struct device * dev)872 static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev)
873 {
874 return NULL;
875 }
cxl_add_to_region(struct cxl_port * root,struct cxl_endpoint_decoder * cxled)876 static inline int cxl_add_to_region(struct cxl_port *root,
877 struct cxl_endpoint_decoder *cxled)
878 {
879 return 0;
880 }
to_cxl_dax_region(struct device * dev)881 static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev)
882 {
883 return NULL;
884 }
885 #endif
886
887 void cxl_endpoint_parse_cdat(struct cxl_port *port);
888 void cxl_switch_parse_cdat(struct cxl_port *port);
889
890 int cxl_endpoint_get_perf_coordinates(struct cxl_port *port,
891 struct access_coordinate *coord);
892 void cxl_region_perf_data_calculate(struct cxl_region *cxlr,
893 struct cxl_endpoint_decoder *cxled);
894
895 void cxl_memdev_update_perf(struct cxl_memdev *cxlmd);
896
897 void cxl_coordinates_combine(struct access_coordinate *out,
898 struct access_coordinate *c1,
899 struct access_coordinate *c2);
900
901 /*
902 * Unit test builds overrides this to __weak, find the 'strong' version
903 * of these symbols in tools/testing/cxl/.
904 */
905 #ifndef __mock
906 #define __mock static
907 #endif
908
909 #endif /* __CXL_H__ */
910