1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
5 */
6
7 #include <linux/acpi.h>
8 #include <linux/async.h>
9 #include <linux/blkdev.h>
10 #include <linux/blk-mq.h>
11 #include <linux/blk-mq-pci.h>
12 #include <linux/blk-integrity.h>
13 #include <linux/dmi.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/kstrtox.h>
18 #include <linux/memremap.h>
19 #include <linux/mm.h>
20 #include <linux/module.h>
21 #include <linux/mutex.h>
22 #include <linux/once.h>
23 #include <linux/pci.h>
24 #include <linux/suspend.h>
25 #include <linux/t10-pi.h>
26 #include <linux/types.h>
27 #include <linux/io-64-nonatomic-lo-hi.h>
28 #include <linux/io-64-nonatomic-hi-lo.h>
29 #include <linux/sed-opal.h>
30 #include <linux/pci-p2pdma.h>
31
32 #include "trace.h"
33 #include "nvme.h"
34
35 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
36 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
37
38 #define SGES_PER_PAGE (NVME_CTRL_PAGE_SIZE / sizeof(struct nvme_sgl_desc))
39
40 /*
41 * These can be higher, but we need to ensure that any command doesn't
42 * require an sg allocation that needs more than a page of data.
43 */
44 #define NVME_MAX_KB_SZ 8192
45 #define NVME_MAX_SEGS 128
46 #define NVME_MAX_NR_ALLOCATIONS 5
47
48 static int use_threaded_interrupts;
49 module_param(use_threaded_interrupts, int, 0444);
50
51 static bool use_cmb_sqes = true;
52 module_param(use_cmb_sqes, bool, 0444);
53 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
54
55 static unsigned int max_host_mem_size_mb = 128;
56 module_param(max_host_mem_size_mb, uint, 0444);
57 MODULE_PARM_DESC(max_host_mem_size_mb,
58 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
59
60 static unsigned int sgl_threshold = SZ_32K;
61 module_param(sgl_threshold, uint, 0644);
62 MODULE_PARM_DESC(sgl_threshold,
63 "Use SGLs when average request segment size is larger or equal to "
64 "this size. Use 0 to disable SGLs.");
65
66 #define NVME_PCI_MIN_QUEUE_SIZE 2
67 #define NVME_PCI_MAX_QUEUE_SIZE 4095
68 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
69 static const struct kernel_param_ops io_queue_depth_ops = {
70 .set = io_queue_depth_set,
71 .get = param_get_uint,
72 };
73
74 static unsigned int io_queue_depth = 1024;
75 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
76 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
77
io_queue_count_set(const char * val,const struct kernel_param * kp)78 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
79 {
80 unsigned int n;
81 int ret;
82
83 ret = kstrtouint(val, 10, &n);
84 if (ret != 0 || n > num_possible_cpus())
85 return -EINVAL;
86 return param_set_uint(val, kp);
87 }
88
89 static const struct kernel_param_ops io_queue_count_ops = {
90 .set = io_queue_count_set,
91 .get = param_get_uint,
92 };
93
94 static unsigned int write_queues;
95 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
96 MODULE_PARM_DESC(write_queues,
97 "Number of queues to use for writes. If not set, reads and writes "
98 "will share a queue set.");
99
100 static unsigned int poll_queues;
101 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
102 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
103
104 static bool noacpi;
105 module_param(noacpi, bool, 0444);
106 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
107
108 struct nvme_dev;
109 struct nvme_queue;
110
111 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
112 static void nvme_delete_io_queues(struct nvme_dev *dev);
113 static void nvme_update_attrs(struct nvme_dev *dev);
114
115 /*
116 * Represents an NVM Express device. Each nvme_dev is a PCI function.
117 */
118 struct nvme_dev {
119 struct nvme_queue *queues;
120 struct blk_mq_tag_set tagset;
121 struct blk_mq_tag_set admin_tagset;
122 u32 __iomem *dbs;
123 struct device *dev;
124 struct dma_pool *prp_page_pool;
125 struct dma_pool *prp_small_pool;
126 unsigned online_queues;
127 unsigned max_qid;
128 unsigned io_queues[HCTX_MAX_TYPES];
129 unsigned int num_vecs;
130 u32 q_depth;
131 int io_sqes;
132 u32 db_stride;
133 void __iomem *bar;
134 unsigned long bar_mapped_size;
135 struct mutex shutdown_lock;
136 bool subsystem;
137 u64 cmb_size;
138 bool cmb_use_sqes;
139 u32 cmbsz;
140 u32 cmbloc;
141 struct nvme_ctrl ctrl;
142 u32 last_ps;
143 bool hmb;
144
145 mempool_t *iod_mempool;
146
147 /* shadow doorbell buffer support: */
148 __le32 *dbbuf_dbs;
149 dma_addr_t dbbuf_dbs_dma_addr;
150 __le32 *dbbuf_eis;
151 dma_addr_t dbbuf_eis_dma_addr;
152
153 /* host memory buffer support: */
154 u64 host_mem_size;
155 u32 nr_host_mem_descs;
156 dma_addr_t host_mem_descs_dma;
157 struct nvme_host_mem_buf_desc *host_mem_descs;
158 void **host_mem_desc_bufs;
159 unsigned int nr_allocated_queues;
160 unsigned int nr_write_queues;
161 unsigned int nr_poll_queues;
162 };
163
io_queue_depth_set(const char * val,const struct kernel_param * kp)164 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
165 {
166 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
167 NVME_PCI_MAX_QUEUE_SIZE);
168 }
169
sq_idx(unsigned int qid,u32 stride)170 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
171 {
172 return qid * 2 * stride;
173 }
174
cq_idx(unsigned int qid,u32 stride)175 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
176 {
177 return (qid * 2 + 1) * stride;
178 }
179
to_nvme_dev(struct nvme_ctrl * ctrl)180 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
181 {
182 return container_of(ctrl, struct nvme_dev, ctrl);
183 }
184
185 /*
186 * An NVM Express queue. Each device has at least two (one for admin
187 * commands and one for I/O commands).
188 */
189 struct nvme_queue {
190 struct nvme_dev *dev;
191 spinlock_t sq_lock;
192 void *sq_cmds;
193 /* only used for poll queues: */
194 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
195 struct nvme_completion *cqes;
196 dma_addr_t sq_dma_addr;
197 dma_addr_t cq_dma_addr;
198 u32 __iomem *q_db;
199 u32 q_depth;
200 u16 cq_vector;
201 u16 sq_tail;
202 u16 last_sq_tail;
203 u16 cq_head;
204 u16 qid;
205 u8 cq_phase;
206 u8 sqes;
207 unsigned long flags;
208 #define NVMEQ_ENABLED 0
209 #define NVMEQ_SQ_CMB 1
210 #define NVMEQ_DELETE_ERROR 2
211 #define NVMEQ_POLLED 3
212 __le32 *dbbuf_sq_db;
213 __le32 *dbbuf_cq_db;
214 __le32 *dbbuf_sq_ei;
215 __le32 *dbbuf_cq_ei;
216 struct completion delete_done;
217 };
218
219 union nvme_descriptor {
220 struct nvme_sgl_desc *sg_list;
221 __le64 *prp_list;
222 };
223
224 /*
225 * The nvme_iod describes the data in an I/O.
226 *
227 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
228 * to the actual struct scatterlist.
229 */
230 struct nvme_iod {
231 struct nvme_request req;
232 struct nvme_command cmd;
233 bool aborted;
234 s8 nr_allocations; /* PRP list pool allocations. 0 means small
235 pool in use */
236 unsigned int dma_len; /* length of single DMA segment mapping */
237 dma_addr_t first_dma;
238 dma_addr_t meta_dma;
239 struct sg_table sgt;
240 union nvme_descriptor list[NVME_MAX_NR_ALLOCATIONS];
241 };
242
nvme_dbbuf_size(struct nvme_dev * dev)243 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
244 {
245 return dev->nr_allocated_queues * 8 * dev->db_stride;
246 }
247
nvme_dbbuf_dma_alloc(struct nvme_dev * dev)248 static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
249 {
250 unsigned int mem_size = nvme_dbbuf_size(dev);
251
252 if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP))
253 return;
254
255 if (dev->dbbuf_dbs) {
256 /*
257 * Clear the dbbuf memory so the driver doesn't observe stale
258 * values from the previous instantiation.
259 */
260 memset(dev->dbbuf_dbs, 0, mem_size);
261 memset(dev->dbbuf_eis, 0, mem_size);
262 return;
263 }
264
265 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
266 &dev->dbbuf_dbs_dma_addr,
267 GFP_KERNEL);
268 if (!dev->dbbuf_dbs)
269 goto fail;
270 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
271 &dev->dbbuf_eis_dma_addr,
272 GFP_KERNEL);
273 if (!dev->dbbuf_eis)
274 goto fail_free_dbbuf_dbs;
275 return;
276
277 fail_free_dbbuf_dbs:
278 dma_free_coherent(dev->dev, mem_size, dev->dbbuf_dbs,
279 dev->dbbuf_dbs_dma_addr);
280 dev->dbbuf_dbs = NULL;
281 fail:
282 dev_warn(dev->dev, "unable to allocate dma for dbbuf\n");
283 }
284
nvme_dbbuf_dma_free(struct nvme_dev * dev)285 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
286 {
287 unsigned int mem_size = nvme_dbbuf_size(dev);
288
289 if (dev->dbbuf_dbs) {
290 dma_free_coherent(dev->dev, mem_size,
291 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
292 dev->dbbuf_dbs = NULL;
293 }
294 if (dev->dbbuf_eis) {
295 dma_free_coherent(dev->dev, mem_size,
296 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
297 dev->dbbuf_eis = NULL;
298 }
299 }
300
nvme_dbbuf_init(struct nvme_dev * dev,struct nvme_queue * nvmeq,int qid)301 static void nvme_dbbuf_init(struct nvme_dev *dev,
302 struct nvme_queue *nvmeq, int qid)
303 {
304 if (!dev->dbbuf_dbs || !qid)
305 return;
306
307 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
308 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
309 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
310 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
311 }
312
nvme_dbbuf_free(struct nvme_queue * nvmeq)313 static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
314 {
315 if (!nvmeq->qid)
316 return;
317
318 nvmeq->dbbuf_sq_db = NULL;
319 nvmeq->dbbuf_cq_db = NULL;
320 nvmeq->dbbuf_sq_ei = NULL;
321 nvmeq->dbbuf_cq_ei = NULL;
322 }
323
nvme_dbbuf_set(struct nvme_dev * dev)324 static void nvme_dbbuf_set(struct nvme_dev *dev)
325 {
326 struct nvme_command c = { };
327 unsigned int i;
328
329 if (!dev->dbbuf_dbs)
330 return;
331
332 c.dbbuf.opcode = nvme_admin_dbbuf;
333 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
334 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
335
336 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
337 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
338 /* Free memory and continue on */
339 nvme_dbbuf_dma_free(dev);
340
341 for (i = 1; i <= dev->online_queues; i++)
342 nvme_dbbuf_free(&dev->queues[i]);
343 }
344 }
345
nvme_dbbuf_need_event(u16 event_idx,u16 new_idx,u16 old)346 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
347 {
348 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
349 }
350
351 /* Update dbbuf and return true if an MMIO is required */
nvme_dbbuf_update_and_check_event(u16 value,__le32 * dbbuf_db,volatile __le32 * dbbuf_ei)352 static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db,
353 volatile __le32 *dbbuf_ei)
354 {
355 if (dbbuf_db) {
356 u16 old_value, event_idx;
357
358 /*
359 * Ensure that the queue is written before updating
360 * the doorbell in memory
361 */
362 wmb();
363
364 old_value = le32_to_cpu(*dbbuf_db);
365 *dbbuf_db = cpu_to_le32(value);
366
367 /*
368 * Ensure that the doorbell is updated before reading the event
369 * index from memory. The controller needs to provide similar
370 * ordering to ensure the envent index is updated before reading
371 * the doorbell.
372 */
373 mb();
374
375 event_idx = le32_to_cpu(*dbbuf_ei);
376 if (!nvme_dbbuf_need_event(event_idx, value, old_value))
377 return false;
378 }
379
380 return true;
381 }
382
383 /*
384 * Will slightly overestimate the number of pages needed. This is OK
385 * as it only leads to a small amount of wasted memory for the lifetime of
386 * the I/O.
387 */
nvme_pci_npages_prp(void)388 static int nvme_pci_npages_prp(void)
389 {
390 unsigned max_bytes = (NVME_MAX_KB_SZ * 1024) + NVME_CTRL_PAGE_SIZE;
391 unsigned nprps = DIV_ROUND_UP(max_bytes, NVME_CTRL_PAGE_SIZE);
392 return DIV_ROUND_UP(8 * nprps, NVME_CTRL_PAGE_SIZE - 8);
393 }
394
nvme_admin_init_hctx(struct blk_mq_hw_ctx * hctx,void * data,unsigned int hctx_idx)395 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
396 unsigned int hctx_idx)
397 {
398 struct nvme_dev *dev = to_nvme_dev(data);
399 struct nvme_queue *nvmeq = &dev->queues[0];
400
401 WARN_ON(hctx_idx != 0);
402 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
403
404 hctx->driver_data = nvmeq;
405 return 0;
406 }
407
nvme_init_hctx(struct blk_mq_hw_ctx * hctx,void * data,unsigned int hctx_idx)408 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
409 unsigned int hctx_idx)
410 {
411 struct nvme_dev *dev = to_nvme_dev(data);
412 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
413
414 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
415 hctx->driver_data = nvmeq;
416 return 0;
417 }
418
nvme_pci_init_request(struct blk_mq_tag_set * set,struct request * req,unsigned int hctx_idx,unsigned int numa_node)419 static int nvme_pci_init_request(struct blk_mq_tag_set *set,
420 struct request *req, unsigned int hctx_idx,
421 unsigned int numa_node)
422 {
423 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
424
425 nvme_req(req)->ctrl = set->driver_data;
426 nvme_req(req)->cmd = &iod->cmd;
427 return 0;
428 }
429
queue_irq_offset(struct nvme_dev * dev)430 static int queue_irq_offset(struct nvme_dev *dev)
431 {
432 /* if we have more than 1 vec, admin queue offsets us by 1 */
433 if (dev->num_vecs > 1)
434 return 1;
435
436 return 0;
437 }
438
nvme_pci_map_queues(struct blk_mq_tag_set * set)439 static void nvme_pci_map_queues(struct blk_mq_tag_set *set)
440 {
441 struct nvme_dev *dev = to_nvme_dev(set->driver_data);
442 int i, qoff, offset;
443
444 offset = queue_irq_offset(dev);
445 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
446 struct blk_mq_queue_map *map = &set->map[i];
447
448 map->nr_queues = dev->io_queues[i];
449 if (!map->nr_queues) {
450 BUG_ON(i == HCTX_TYPE_DEFAULT);
451 continue;
452 }
453
454 /*
455 * The poll queue(s) doesn't have an IRQ (and hence IRQ
456 * affinity), so use the regular blk-mq cpu mapping
457 */
458 map->queue_offset = qoff;
459 if (i != HCTX_TYPE_POLL && offset)
460 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
461 else
462 blk_mq_map_queues(map);
463 qoff += map->nr_queues;
464 offset += map->nr_queues;
465 }
466 }
467
468 /*
469 * Write sq tail if we are asked to, or if the next command would wrap.
470 */
nvme_write_sq_db(struct nvme_queue * nvmeq,bool write_sq)471 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
472 {
473 if (!write_sq) {
474 u16 next_tail = nvmeq->sq_tail + 1;
475
476 if (next_tail == nvmeq->q_depth)
477 next_tail = 0;
478 if (next_tail != nvmeq->last_sq_tail)
479 return;
480 }
481
482 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
483 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
484 writel(nvmeq->sq_tail, nvmeq->q_db);
485 nvmeq->last_sq_tail = nvmeq->sq_tail;
486 }
487
nvme_sq_copy_cmd(struct nvme_queue * nvmeq,struct nvme_command * cmd)488 static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
489 struct nvme_command *cmd)
490 {
491 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
492 absolute_pointer(cmd), sizeof(*cmd));
493 if (++nvmeq->sq_tail == nvmeq->q_depth)
494 nvmeq->sq_tail = 0;
495 }
496
nvme_commit_rqs(struct blk_mq_hw_ctx * hctx)497 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
498 {
499 struct nvme_queue *nvmeq = hctx->driver_data;
500
501 spin_lock(&nvmeq->sq_lock);
502 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
503 nvme_write_sq_db(nvmeq, true);
504 spin_unlock(&nvmeq->sq_lock);
505 }
506
nvme_pci_use_sgls(struct nvme_dev * dev,struct request * req,int nseg)507 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req,
508 int nseg)
509 {
510 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
511 unsigned int avg_seg_size;
512
513 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
514
515 if (!nvme_ctrl_sgl_supported(&dev->ctrl))
516 return false;
517 if (!nvmeq->qid)
518 return false;
519 if (!sgl_threshold || avg_seg_size < sgl_threshold)
520 return false;
521 return true;
522 }
523
nvme_free_prps(struct nvme_dev * dev,struct request * req)524 static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
525 {
526 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
527 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
528 dma_addr_t dma_addr = iod->first_dma;
529 int i;
530
531 for (i = 0; i < iod->nr_allocations; i++) {
532 __le64 *prp_list = iod->list[i].prp_list;
533 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
534
535 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
536 dma_addr = next_dma_addr;
537 }
538 }
539
nvme_unmap_data(struct nvme_dev * dev,struct request * req)540 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
541 {
542 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
543
544 if (iod->dma_len) {
545 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
546 rq_dma_dir(req));
547 return;
548 }
549
550 WARN_ON_ONCE(!iod->sgt.nents);
551
552 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
553
554 if (iod->nr_allocations == 0)
555 dma_pool_free(dev->prp_small_pool, iod->list[0].sg_list,
556 iod->first_dma);
557 else if (iod->nr_allocations == 1)
558 dma_pool_free(dev->prp_page_pool, iod->list[0].sg_list,
559 iod->first_dma);
560 else
561 nvme_free_prps(dev, req);
562 mempool_free(iod->sgt.sgl, dev->iod_mempool);
563 }
564
nvme_print_sgl(struct scatterlist * sgl,int nents)565 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
566 {
567 int i;
568 struct scatterlist *sg;
569
570 for_each_sg(sgl, sg, nents, i) {
571 dma_addr_t phys = sg_phys(sg);
572 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
573 "dma_address:%pad dma_length:%d\n",
574 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
575 sg_dma_len(sg));
576 }
577 }
578
nvme_pci_setup_prps(struct nvme_dev * dev,struct request * req,struct nvme_rw_command * cmnd)579 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
580 struct request *req, struct nvme_rw_command *cmnd)
581 {
582 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
583 struct dma_pool *pool;
584 int length = blk_rq_payload_bytes(req);
585 struct scatterlist *sg = iod->sgt.sgl;
586 int dma_len = sg_dma_len(sg);
587 u64 dma_addr = sg_dma_address(sg);
588 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
589 __le64 *prp_list;
590 dma_addr_t prp_dma;
591 int nprps, i;
592
593 length -= (NVME_CTRL_PAGE_SIZE - offset);
594 if (length <= 0) {
595 iod->first_dma = 0;
596 goto done;
597 }
598
599 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
600 if (dma_len) {
601 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
602 } else {
603 sg = sg_next(sg);
604 dma_addr = sg_dma_address(sg);
605 dma_len = sg_dma_len(sg);
606 }
607
608 if (length <= NVME_CTRL_PAGE_SIZE) {
609 iod->first_dma = dma_addr;
610 goto done;
611 }
612
613 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
614 if (nprps <= (256 / 8)) {
615 pool = dev->prp_small_pool;
616 iod->nr_allocations = 0;
617 } else {
618 pool = dev->prp_page_pool;
619 iod->nr_allocations = 1;
620 }
621
622 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
623 if (!prp_list) {
624 iod->nr_allocations = -1;
625 return BLK_STS_RESOURCE;
626 }
627 iod->list[0].prp_list = prp_list;
628 iod->first_dma = prp_dma;
629 i = 0;
630 for (;;) {
631 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
632 __le64 *old_prp_list = prp_list;
633 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
634 if (!prp_list)
635 goto free_prps;
636 iod->list[iod->nr_allocations++].prp_list = prp_list;
637 prp_list[0] = old_prp_list[i - 1];
638 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
639 i = 1;
640 }
641 prp_list[i++] = cpu_to_le64(dma_addr);
642 dma_len -= NVME_CTRL_PAGE_SIZE;
643 dma_addr += NVME_CTRL_PAGE_SIZE;
644 length -= NVME_CTRL_PAGE_SIZE;
645 if (length <= 0)
646 break;
647 if (dma_len > 0)
648 continue;
649 if (unlikely(dma_len < 0))
650 goto bad_sgl;
651 sg = sg_next(sg);
652 dma_addr = sg_dma_address(sg);
653 dma_len = sg_dma_len(sg);
654 }
655 done:
656 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl));
657 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
658 return BLK_STS_OK;
659 free_prps:
660 nvme_free_prps(dev, req);
661 return BLK_STS_RESOURCE;
662 bad_sgl:
663 WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents),
664 "Invalid SGL for payload:%d nents:%d\n",
665 blk_rq_payload_bytes(req), iod->sgt.nents);
666 return BLK_STS_IOERR;
667 }
668
nvme_pci_sgl_set_data(struct nvme_sgl_desc * sge,struct scatterlist * sg)669 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
670 struct scatterlist *sg)
671 {
672 sge->addr = cpu_to_le64(sg_dma_address(sg));
673 sge->length = cpu_to_le32(sg_dma_len(sg));
674 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
675 }
676
nvme_pci_sgl_set_seg(struct nvme_sgl_desc * sge,dma_addr_t dma_addr,int entries)677 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
678 dma_addr_t dma_addr, int entries)
679 {
680 sge->addr = cpu_to_le64(dma_addr);
681 sge->length = cpu_to_le32(entries * sizeof(*sge));
682 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
683 }
684
nvme_pci_setup_sgls(struct nvme_dev * dev,struct request * req,struct nvme_rw_command * cmd)685 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
686 struct request *req, struct nvme_rw_command *cmd)
687 {
688 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
689 struct dma_pool *pool;
690 struct nvme_sgl_desc *sg_list;
691 struct scatterlist *sg = iod->sgt.sgl;
692 unsigned int entries = iod->sgt.nents;
693 dma_addr_t sgl_dma;
694 int i = 0;
695
696 /* setting the transfer type as SGL */
697 cmd->flags = NVME_CMD_SGL_METABUF;
698
699 if (entries == 1) {
700 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
701 return BLK_STS_OK;
702 }
703
704 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
705 pool = dev->prp_small_pool;
706 iod->nr_allocations = 0;
707 } else {
708 pool = dev->prp_page_pool;
709 iod->nr_allocations = 1;
710 }
711
712 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
713 if (!sg_list) {
714 iod->nr_allocations = -1;
715 return BLK_STS_RESOURCE;
716 }
717
718 iod->list[0].sg_list = sg_list;
719 iod->first_dma = sgl_dma;
720
721 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
722 do {
723 nvme_pci_sgl_set_data(&sg_list[i++], sg);
724 sg = sg_next(sg);
725 } while (--entries > 0);
726
727 return BLK_STS_OK;
728 }
729
nvme_setup_prp_simple(struct nvme_dev * dev,struct request * req,struct nvme_rw_command * cmnd,struct bio_vec * bv)730 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
731 struct request *req, struct nvme_rw_command *cmnd,
732 struct bio_vec *bv)
733 {
734 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
735 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
736 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
737
738 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
739 if (dma_mapping_error(dev->dev, iod->first_dma))
740 return BLK_STS_RESOURCE;
741 iod->dma_len = bv->bv_len;
742
743 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
744 if (bv->bv_len > first_prp_len)
745 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
746 else
747 cmnd->dptr.prp2 = 0;
748 return BLK_STS_OK;
749 }
750
nvme_setup_sgl_simple(struct nvme_dev * dev,struct request * req,struct nvme_rw_command * cmnd,struct bio_vec * bv)751 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
752 struct request *req, struct nvme_rw_command *cmnd,
753 struct bio_vec *bv)
754 {
755 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
756
757 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
758 if (dma_mapping_error(dev->dev, iod->first_dma))
759 return BLK_STS_RESOURCE;
760 iod->dma_len = bv->bv_len;
761
762 cmnd->flags = NVME_CMD_SGL_METABUF;
763 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
764 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
765 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
766 return BLK_STS_OK;
767 }
768
nvme_map_data(struct nvme_dev * dev,struct request * req,struct nvme_command * cmnd)769 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
770 struct nvme_command *cmnd)
771 {
772 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
773 blk_status_t ret = BLK_STS_RESOURCE;
774 int rc;
775
776 if (blk_rq_nr_phys_segments(req) == 1) {
777 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
778 struct bio_vec bv = req_bvec(req);
779
780 if (!is_pci_p2pdma_page(bv.bv_page)) {
781 if ((bv.bv_offset & (NVME_CTRL_PAGE_SIZE - 1)) +
782 bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
783 return nvme_setup_prp_simple(dev, req,
784 &cmnd->rw, &bv);
785
786 if (nvmeq->qid && sgl_threshold &&
787 nvme_ctrl_sgl_supported(&dev->ctrl))
788 return nvme_setup_sgl_simple(dev, req,
789 &cmnd->rw, &bv);
790 }
791 }
792
793 iod->dma_len = 0;
794 iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
795 if (!iod->sgt.sgl)
796 return BLK_STS_RESOURCE;
797 sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req));
798 iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl);
799 if (!iod->sgt.orig_nents)
800 goto out_free_sg;
801
802 rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req),
803 DMA_ATTR_NO_WARN);
804 if (rc) {
805 if (rc == -EREMOTEIO)
806 ret = BLK_STS_TARGET;
807 goto out_free_sg;
808 }
809
810 if (nvme_pci_use_sgls(dev, req, iod->sgt.nents))
811 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw);
812 else
813 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
814 if (ret != BLK_STS_OK)
815 goto out_unmap_sg;
816 return BLK_STS_OK;
817
818 out_unmap_sg:
819 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
820 out_free_sg:
821 mempool_free(iod->sgt.sgl, dev->iod_mempool);
822 return ret;
823 }
824
nvme_map_metadata(struct nvme_dev * dev,struct request * req,struct nvme_command * cmnd)825 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
826 struct nvme_command *cmnd)
827 {
828 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
829
830 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
831 rq_dma_dir(req), 0);
832 if (dma_mapping_error(dev->dev, iod->meta_dma))
833 return BLK_STS_IOERR;
834 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
835 return BLK_STS_OK;
836 }
837
nvme_prep_rq(struct nvme_dev * dev,struct request * req)838 static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
839 {
840 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
841 blk_status_t ret;
842
843 iod->aborted = false;
844 iod->nr_allocations = -1;
845 iod->sgt.nents = 0;
846
847 ret = nvme_setup_cmd(req->q->queuedata, req);
848 if (ret)
849 return ret;
850
851 if (blk_rq_nr_phys_segments(req)) {
852 ret = nvme_map_data(dev, req, &iod->cmd);
853 if (ret)
854 goto out_free_cmd;
855 }
856
857 if (blk_integrity_rq(req)) {
858 ret = nvme_map_metadata(dev, req, &iod->cmd);
859 if (ret)
860 goto out_unmap_data;
861 }
862
863 nvme_start_request(req);
864 return BLK_STS_OK;
865 out_unmap_data:
866 nvme_unmap_data(dev, req);
867 out_free_cmd:
868 nvme_cleanup_cmd(req);
869 return ret;
870 }
871
872 /*
873 * NOTE: ns is NULL when called on the admin queue.
874 */
nvme_queue_rq(struct blk_mq_hw_ctx * hctx,const struct blk_mq_queue_data * bd)875 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
876 const struct blk_mq_queue_data *bd)
877 {
878 struct nvme_queue *nvmeq = hctx->driver_data;
879 struct nvme_dev *dev = nvmeq->dev;
880 struct request *req = bd->rq;
881 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
882 blk_status_t ret;
883
884 /*
885 * We should not need to do this, but we're still using this to
886 * ensure we can drain requests on a dying queue.
887 */
888 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
889 return BLK_STS_IOERR;
890
891 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
892 return nvme_fail_nonready_command(&dev->ctrl, req);
893
894 ret = nvme_prep_rq(dev, req);
895 if (unlikely(ret))
896 return ret;
897 spin_lock(&nvmeq->sq_lock);
898 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
899 nvme_write_sq_db(nvmeq, bd->last);
900 spin_unlock(&nvmeq->sq_lock);
901 return BLK_STS_OK;
902 }
903
nvme_submit_cmds(struct nvme_queue * nvmeq,struct request ** rqlist)904 static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
905 {
906 spin_lock(&nvmeq->sq_lock);
907 while (!rq_list_empty(*rqlist)) {
908 struct request *req = rq_list_pop(rqlist);
909 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
910
911 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
912 }
913 nvme_write_sq_db(nvmeq, true);
914 spin_unlock(&nvmeq->sq_lock);
915 }
916
nvme_prep_rq_batch(struct nvme_queue * nvmeq,struct request * req)917 static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
918 {
919 /*
920 * We should not need to do this, but we're still using this to
921 * ensure we can drain requests on a dying queue.
922 */
923 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
924 return false;
925 if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
926 return false;
927
928 return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
929 }
930
nvme_queue_rqs(struct request ** rqlist)931 static void nvme_queue_rqs(struct request **rqlist)
932 {
933 struct request *req, *next, *prev = NULL;
934 struct request *requeue_list = NULL;
935
936 rq_list_for_each_safe(rqlist, req, next) {
937 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
938
939 if (!nvme_prep_rq_batch(nvmeq, req)) {
940 /* detach 'req' and add to remainder list */
941 rq_list_move(rqlist, &requeue_list, req, prev);
942
943 req = prev;
944 if (!req)
945 continue;
946 }
947
948 if (!next || req->mq_hctx != next->mq_hctx) {
949 /* detach rest of list, and submit */
950 req->rq_next = NULL;
951 nvme_submit_cmds(nvmeq, rqlist);
952 *rqlist = next;
953 prev = NULL;
954 } else
955 prev = req;
956 }
957
958 *rqlist = requeue_list;
959 }
960
nvme_pci_unmap_rq(struct request * req)961 static __always_inline void nvme_pci_unmap_rq(struct request *req)
962 {
963 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
964 struct nvme_dev *dev = nvmeq->dev;
965
966 if (blk_integrity_rq(req)) {
967 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
968
969 dma_unmap_page(dev->dev, iod->meta_dma,
970 rq_integrity_vec(req)->bv_len, rq_dma_dir(req));
971 }
972
973 if (blk_rq_nr_phys_segments(req))
974 nvme_unmap_data(dev, req);
975 }
976
nvme_pci_complete_rq(struct request * req)977 static void nvme_pci_complete_rq(struct request *req)
978 {
979 nvme_pci_unmap_rq(req);
980 nvme_complete_rq(req);
981 }
982
nvme_pci_complete_batch(struct io_comp_batch * iob)983 static void nvme_pci_complete_batch(struct io_comp_batch *iob)
984 {
985 nvme_complete_batch(iob, nvme_pci_unmap_rq);
986 }
987
988 /* We read the CQE phase first to check if the rest of the entry is valid */
nvme_cqe_pending(struct nvme_queue * nvmeq)989 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
990 {
991 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
992
993 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
994 }
995
nvme_ring_cq_doorbell(struct nvme_queue * nvmeq)996 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
997 {
998 u16 head = nvmeq->cq_head;
999
1000 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1001 nvmeq->dbbuf_cq_ei))
1002 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
1003 }
1004
nvme_queue_tagset(struct nvme_queue * nvmeq)1005 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1006 {
1007 if (!nvmeq->qid)
1008 return nvmeq->dev->admin_tagset.tags[0];
1009 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1010 }
1011
nvme_handle_cqe(struct nvme_queue * nvmeq,struct io_comp_batch * iob,u16 idx)1012 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1013 struct io_comp_batch *iob, u16 idx)
1014 {
1015 struct nvme_completion *cqe = &nvmeq->cqes[idx];
1016 __u16 command_id = READ_ONCE(cqe->command_id);
1017 struct request *req;
1018
1019 /*
1020 * AEN requests are special as they don't time out and can
1021 * survive any kind of queue freeze and often don't respond to
1022 * aborts. We don't even bother to allocate a struct request
1023 * for them but rather special case them here.
1024 */
1025 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1026 nvme_complete_async_event(&nvmeq->dev->ctrl,
1027 cqe->status, &cqe->result);
1028 return;
1029 }
1030
1031 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
1032 if (unlikely(!req)) {
1033 dev_warn(nvmeq->dev->ctrl.device,
1034 "invalid id %d completed on queue %d\n",
1035 command_id, le16_to_cpu(cqe->sq_id));
1036 return;
1037 }
1038
1039 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1040 if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1041 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1042 nvme_pci_complete_batch))
1043 nvme_pci_complete_rq(req);
1044 }
1045
nvme_update_cq_head(struct nvme_queue * nvmeq)1046 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1047 {
1048 u32 tmp = nvmeq->cq_head + 1;
1049
1050 if (tmp == nvmeq->q_depth) {
1051 nvmeq->cq_head = 0;
1052 nvmeq->cq_phase ^= 1;
1053 } else {
1054 nvmeq->cq_head = tmp;
1055 }
1056 }
1057
nvme_poll_cq(struct nvme_queue * nvmeq,struct io_comp_batch * iob)1058 static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1059 struct io_comp_batch *iob)
1060 {
1061 int found = 0;
1062
1063 while (nvme_cqe_pending(nvmeq)) {
1064 found++;
1065 /*
1066 * load-load control dependency between phase and the rest of
1067 * the cqe requires a full read memory barrier
1068 */
1069 dma_rmb();
1070 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
1071 nvme_update_cq_head(nvmeq);
1072 }
1073
1074 if (found)
1075 nvme_ring_cq_doorbell(nvmeq);
1076 return found;
1077 }
1078
nvme_irq(int irq,void * data)1079 static irqreturn_t nvme_irq(int irq, void *data)
1080 {
1081 struct nvme_queue *nvmeq = data;
1082 DEFINE_IO_COMP_BATCH(iob);
1083
1084 if (nvme_poll_cq(nvmeq, &iob)) {
1085 if (!rq_list_empty(iob.req_list))
1086 nvme_pci_complete_batch(&iob);
1087 return IRQ_HANDLED;
1088 }
1089 return IRQ_NONE;
1090 }
1091
nvme_irq_check(int irq,void * data)1092 static irqreturn_t nvme_irq_check(int irq, void *data)
1093 {
1094 struct nvme_queue *nvmeq = data;
1095
1096 if (nvme_cqe_pending(nvmeq))
1097 return IRQ_WAKE_THREAD;
1098 return IRQ_NONE;
1099 }
1100
1101 /*
1102 * Poll for completions for any interrupt driven queue
1103 * Can be called from any context.
1104 */
nvme_poll_irqdisable(struct nvme_queue * nvmeq)1105 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1106 {
1107 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1108
1109 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1110
1111 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1112 nvme_poll_cq(nvmeq, NULL);
1113 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1114 }
1115
nvme_poll(struct blk_mq_hw_ctx * hctx,struct io_comp_batch * iob)1116 static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
1117 {
1118 struct nvme_queue *nvmeq = hctx->driver_data;
1119 bool found;
1120
1121 if (!nvme_cqe_pending(nvmeq))
1122 return 0;
1123
1124 spin_lock(&nvmeq->cq_poll_lock);
1125 found = nvme_poll_cq(nvmeq, iob);
1126 spin_unlock(&nvmeq->cq_poll_lock);
1127
1128 return found;
1129 }
1130
nvme_pci_submit_async_event(struct nvme_ctrl * ctrl)1131 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1132 {
1133 struct nvme_dev *dev = to_nvme_dev(ctrl);
1134 struct nvme_queue *nvmeq = &dev->queues[0];
1135 struct nvme_command c = { };
1136
1137 c.common.opcode = nvme_admin_async_event;
1138 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1139
1140 spin_lock(&nvmeq->sq_lock);
1141 nvme_sq_copy_cmd(nvmeq, &c);
1142 nvme_write_sq_db(nvmeq, true);
1143 spin_unlock(&nvmeq->sq_lock);
1144 }
1145
adapter_delete_queue(struct nvme_dev * dev,u8 opcode,u16 id)1146 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1147 {
1148 struct nvme_command c = { };
1149
1150 c.delete_queue.opcode = opcode;
1151 c.delete_queue.qid = cpu_to_le16(id);
1152
1153 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1154 }
1155
adapter_alloc_cq(struct nvme_dev * dev,u16 qid,struct nvme_queue * nvmeq,s16 vector)1156 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1157 struct nvme_queue *nvmeq, s16 vector)
1158 {
1159 struct nvme_command c = { };
1160 int flags = NVME_QUEUE_PHYS_CONTIG;
1161
1162 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1163 flags |= NVME_CQ_IRQ_ENABLED;
1164
1165 /*
1166 * Note: we (ab)use the fact that the prp fields survive if no data
1167 * is attached to the request.
1168 */
1169 c.create_cq.opcode = nvme_admin_create_cq;
1170 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1171 c.create_cq.cqid = cpu_to_le16(qid);
1172 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1173 c.create_cq.cq_flags = cpu_to_le16(flags);
1174 c.create_cq.irq_vector = cpu_to_le16(vector);
1175
1176 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1177 }
1178
adapter_alloc_sq(struct nvme_dev * dev,u16 qid,struct nvme_queue * nvmeq)1179 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1180 struct nvme_queue *nvmeq)
1181 {
1182 struct nvme_ctrl *ctrl = &dev->ctrl;
1183 struct nvme_command c = { };
1184 int flags = NVME_QUEUE_PHYS_CONTIG;
1185
1186 /*
1187 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1188 * set. Since URGENT priority is zeroes, it makes all queues
1189 * URGENT.
1190 */
1191 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1192 flags |= NVME_SQ_PRIO_MEDIUM;
1193
1194 /*
1195 * Note: we (ab)use the fact that the prp fields survive if no data
1196 * is attached to the request.
1197 */
1198 c.create_sq.opcode = nvme_admin_create_sq;
1199 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1200 c.create_sq.sqid = cpu_to_le16(qid);
1201 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1202 c.create_sq.sq_flags = cpu_to_le16(flags);
1203 c.create_sq.cqid = cpu_to_le16(qid);
1204
1205 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1206 }
1207
adapter_delete_cq(struct nvme_dev * dev,u16 cqid)1208 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1209 {
1210 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1211 }
1212
adapter_delete_sq(struct nvme_dev * dev,u16 sqid)1213 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1214 {
1215 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1216 }
1217
abort_endio(struct request * req,blk_status_t error)1218 static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error)
1219 {
1220 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1221
1222 dev_warn(nvmeq->dev->ctrl.device,
1223 "Abort status: 0x%x", nvme_req(req)->status);
1224 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1225 blk_mq_free_request(req);
1226 return RQ_END_IO_NONE;
1227 }
1228
nvme_should_reset(struct nvme_dev * dev,u32 csts)1229 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1230 {
1231 /* If true, indicates loss of adapter communication, possibly by a
1232 * NVMe Subsystem reset.
1233 */
1234 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1235
1236 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1237 switch (nvme_ctrl_state(&dev->ctrl)) {
1238 case NVME_CTRL_RESETTING:
1239 case NVME_CTRL_CONNECTING:
1240 return false;
1241 default:
1242 break;
1243 }
1244
1245 /* We shouldn't reset unless the controller is on fatal error state
1246 * _or_ if we lost the communication with it.
1247 */
1248 if (!(csts & NVME_CSTS_CFS) && !nssro)
1249 return false;
1250
1251 return true;
1252 }
1253
nvme_warn_reset(struct nvme_dev * dev,u32 csts)1254 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1255 {
1256 /* Read a config register to help see what died. */
1257 u16 pci_status;
1258 int result;
1259
1260 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1261 &pci_status);
1262 if (result == PCIBIOS_SUCCESSFUL)
1263 dev_warn(dev->ctrl.device,
1264 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1265 csts, pci_status);
1266 else
1267 dev_warn(dev->ctrl.device,
1268 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1269 csts, result);
1270
1271 if (csts != ~0)
1272 return;
1273
1274 dev_warn(dev->ctrl.device,
1275 "Does your device have a faulty power saving mode enabled?\n");
1276 dev_warn(dev->ctrl.device,
1277 "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n");
1278 }
1279
nvme_timeout(struct request * req)1280 static enum blk_eh_timer_return nvme_timeout(struct request *req)
1281 {
1282 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1283 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1284 struct nvme_dev *dev = nvmeq->dev;
1285 struct request *abort_req;
1286 struct nvme_command cmd = { };
1287 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1288 u8 opcode;
1289
1290 if (nvme_state_terminal(&dev->ctrl))
1291 goto disable;
1292
1293 /* If PCI error recovery process is happening, we cannot reset or
1294 * the recovery mechanism will surely fail.
1295 */
1296 mb();
1297 if (pci_channel_offline(to_pci_dev(dev->dev)))
1298 return BLK_EH_RESET_TIMER;
1299
1300 /*
1301 * Reset immediately if the controller is failed
1302 */
1303 if (nvme_should_reset(dev, csts)) {
1304 nvme_warn_reset(dev, csts);
1305 goto disable;
1306 }
1307
1308 /*
1309 * Did we miss an interrupt?
1310 */
1311 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1312 nvme_poll(req->mq_hctx, NULL);
1313 else
1314 nvme_poll_irqdisable(nvmeq);
1315
1316 if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT) {
1317 dev_warn(dev->ctrl.device,
1318 "I/O tag %d (%04x) QID %d timeout, completion polled\n",
1319 req->tag, nvme_cid(req), nvmeq->qid);
1320 return BLK_EH_DONE;
1321 }
1322
1323 /*
1324 * Shutdown immediately if controller times out while starting. The
1325 * reset work will see the pci device disabled when it gets the forced
1326 * cancellation error. All outstanding requests are completed on
1327 * shutdown, so we return BLK_EH_DONE.
1328 */
1329 switch (nvme_ctrl_state(&dev->ctrl)) {
1330 case NVME_CTRL_CONNECTING:
1331 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1332 fallthrough;
1333 case NVME_CTRL_DELETING:
1334 dev_warn_ratelimited(dev->ctrl.device,
1335 "I/O tag %d (%04x) QID %d timeout, disable controller\n",
1336 req->tag, nvme_cid(req), nvmeq->qid);
1337 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1338 nvme_dev_disable(dev, true);
1339 return BLK_EH_DONE;
1340 case NVME_CTRL_RESETTING:
1341 return BLK_EH_RESET_TIMER;
1342 default:
1343 break;
1344 }
1345
1346 /*
1347 * Shutdown the controller immediately and schedule a reset if the
1348 * command was already aborted once before and still hasn't been
1349 * returned to the driver, or if this is the admin queue.
1350 */
1351 opcode = nvme_req(req)->cmd->common.opcode;
1352 if (!nvmeq->qid || iod->aborted) {
1353 dev_warn(dev->ctrl.device,
1354 "I/O tag %d (%04x) opcode %#x (%s) QID %d timeout, reset controller\n",
1355 req->tag, nvme_cid(req), opcode,
1356 nvme_opcode_str(nvmeq->qid, opcode), nvmeq->qid);
1357 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1358 goto disable;
1359 }
1360
1361 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1362 atomic_inc(&dev->ctrl.abort_limit);
1363 return BLK_EH_RESET_TIMER;
1364 }
1365 iod->aborted = true;
1366
1367 cmd.abort.opcode = nvme_admin_abort_cmd;
1368 cmd.abort.cid = nvme_cid(req);
1369 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1370
1371 dev_warn(nvmeq->dev->ctrl.device,
1372 "I/O tag %d (%04x) opcode %#x (%s) QID %d timeout, aborting req_op:%s(%u) size:%u\n",
1373 req->tag, nvme_cid(req), opcode, nvme_get_opcode_str(opcode),
1374 nvmeq->qid, blk_op_str(req_op(req)), req_op(req),
1375 blk_rq_bytes(req));
1376
1377 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1378 BLK_MQ_REQ_NOWAIT);
1379 if (IS_ERR(abort_req)) {
1380 atomic_inc(&dev->ctrl.abort_limit);
1381 return BLK_EH_RESET_TIMER;
1382 }
1383 nvme_init_request(abort_req, &cmd);
1384
1385 abort_req->end_io = abort_endio;
1386 abort_req->end_io_data = NULL;
1387 blk_execute_rq_nowait(abort_req, false);
1388
1389 /*
1390 * The aborted req will be completed on receiving the abort req.
1391 * We enable the timer again. If hit twice, it'll cause a device reset,
1392 * as the device then is in a faulty state.
1393 */
1394 return BLK_EH_RESET_TIMER;
1395
1396 disable:
1397 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) {
1398 if (nvme_state_terminal(&dev->ctrl))
1399 nvme_dev_disable(dev, true);
1400 return BLK_EH_DONE;
1401 }
1402
1403 nvme_dev_disable(dev, false);
1404 if (nvme_try_sched_reset(&dev->ctrl))
1405 nvme_unquiesce_io_queues(&dev->ctrl);
1406 return BLK_EH_DONE;
1407 }
1408
nvme_free_queue(struct nvme_queue * nvmeq)1409 static void nvme_free_queue(struct nvme_queue *nvmeq)
1410 {
1411 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1412 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1413 if (!nvmeq->sq_cmds)
1414 return;
1415
1416 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1417 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1418 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1419 } else {
1420 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1421 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1422 }
1423 }
1424
nvme_free_queues(struct nvme_dev * dev,int lowest)1425 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1426 {
1427 int i;
1428
1429 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1430 dev->ctrl.queue_count--;
1431 nvme_free_queue(&dev->queues[i]);
1432 }
1433 }
1434
nvme_suspend_queue(struct nvme_dev * dev,unsigned int qid)1435 static void nvme_suspend_queue(struct nvme_dev *dev, unsigned int qid)
1436 {
1437 struct nvme_queue *nvmeq = &dev->queues[qid];
1438
1439 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1440 return;
1441
1442 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1443 mb();
1444
1445 nvmeq->dev->online_queues--;
1446 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1447 nvme_quiesce_admin_queue(&nvmeq->dev->ctrl);
1448 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1449 pci_free_irq(to_pci_dev(dev->dev), nvmeq->cq_vector, nvmeq);
1450 }
1451
nvme_suspend_io_queues(struct nvme_dev * dev)1452 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1453 {
1454 int i;
1455
1456 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1457 nvme_suspend_queue(dev, i);
1458 }
1459
1460 /*
1461 * Called only on a device that has been disabled and after all other threads
1462 * that can check this device's completion queues have synced, except
1463 * nvme_poll(). This is the last chance for the driver to see a natural
1464 * completion before nvme_cancel_request() terminates all incomplete requests.
1465 */
nvme_reap_pending_cqes(struct nvme_dev * dev)1466 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1467 {
1468 int i;
1469
1470 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1471 spin_lock(&dev->queues[i].cq_poll_lock);
1472 nvme_poll_cq(&dev->queues[i], NULL);
1473 spin_unlock(&dev->queues[i].cq_poll_lock);
1474 }
1475 }
1476
nvme_cmb_qdepth(struct nvme_dev * dev,int nr_io_queues,int entry_size)1477 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1478 int entry_size)
1479 {
1480 int q_depth = dev->q_depth;
1481 unsigned q_size_aligned = roundup(q_depth * entry_size,
1482 NVME_CTRL_PAGE_SIZE);
1483
1484 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1485 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1486
1487 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1488 q_depth = div_u64(mem_per_q, entry_size);
1489
1490 /*
1491 * Ensure the reduced q_depth is above some threshold where it
1492 * would be better to map queues in system memory with the
1493 * original depth
1494 */
1495 if (q_depth < 64)
1496 return -ENOMEM;
1497 }
1498
1499 return q_depth;
1500 }
1501
nvme_alloc_sq_cmds(struct nvme_dev * dev,struct nvme_queue * nvmeq,int qid)1502 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1503 int qid)
1504 {
1505 struct pci_dev *pdev = to_pci_dev(dev->dev);
1506
1507 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1508 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1509 if (nvmeq->sq_cmds) {
1510 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1511 nvmeq->sq_cmds);
1512 if (nvmeq->sq_dma_addr) {
1513 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1514 return 0;
1515 }
1516
1517 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1518 }
1519 }
1520
1521 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1522 &nvmeq->sq_dma_addr, GFP_KERNEL);
1523 if (!nvmeq->sq_cmds)
1524 return -ENOMEM;
1525 return 0;
1526 }
1527
nvme_alloc_queue(struct nvme_dev * dev,int qid,int depth)1528 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1529 {
1530 struct nvme_queue *nvmeq = &dev->queues[qid];
1531
1532 if (dev->ctrl.queue_count > qid)
1533 return 0;
1534
1535 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1536 nvmeq->q_depth = depth;
1537 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1538 &nvmeq->cq_dma_addr, GFP_KERNEL);
1539 if (!nvmeq->cqes)
1540 goto free_nvmeq;
1541
1542 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1543 goto free_cqdma;
1544
1545 nvmeq->dev = dev;
1546 spin_lock_init(&nvmeq->sq_lock);
1547 spin_lock_init(&nvmeq->cq_poll_lock);
1548 nvmeq->cq_head = 0;
1549 nvmeq->cq_phase = 1;
1550 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1551 nvmeq->qid = qid;
1552 dev->ctrl.queue_count++;
1553
1554 return 0;
1555
1556 free_cqdma:
1557 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1558 nvmeq->cq_dma_addr);
1559 free_nvmeq:
1560 return -ENOMEM;
1561 }
1562
queue_request_irq(struct nvme_queue * nvmeq)1563 static int queue_request_irq(struct nvme_queue *nvmeq)
1564 {
1565 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1566 int nr = nvmeq->dev->ctrl.instance;
1567
1568 if (use_threaded_interrupts) {
1569 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1570 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1571 } else {
1572 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1573 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1574 }
1575 }
1576
nvme_init_queue(struct nvme_queue * nvmeq,u16 qid)1577 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1578 {
1579 struct nvme_dev *dev = nvmeq->dev;
1580
1581 nvmeq->sq_tail = 0;
1582 nvmeq->last_sq_tail = 0;
1583 nvmeq->cq_head = 0;
1584 nvmeq->cq_phase = 1;
1585 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1586 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1587 nvme_dbbuf_init(dev, nvmeq, qid);
1588 dev->online_queues++;
1589 wmb(); /* ensure the first interrupt sees the initialization */
1590 }
1591
1592 /*
1593 * Try getting shutdown_lock while setting up IO queues.
1594 */
nvme_setup_io_queues_trylock(struct nvme_dev * dev)1595 static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1596 {
1597 /*
1598 * Give up if the lock is being held by nvme_dev_disable.
1599 */
1600 if (!mutex_trylock(&dev->shutdown_lock))
1601 return -ENODEV;
1602
1603 /*
1604 * Controller is in wrong state, fail early.
1605 */
1606 if (nvme_ctrl_state(&dev->ctrl) != NVME_CTRL_CONNECTING) {
1607 mutex_unlock(&dev->shutdown_lock);
1608 return -ENODEV;
1609 }
1610
1611 return 0;
1612 }
1613
nvme_create_queue(struct nvme_queue * nvmeq,int qid,bool polled)1614 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1615 {
1616 struct nvme_dev *dev = nvmeq->dev;
1617 int result;
1618 u16 vector = 0;
1619
1620 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1621
1622 /*
1623 * A queue's vector matches the queue identifier unless the controller
1624 * has only one vector available.
1625 */
1626 if (!polled)
1627 vector = dev->num_vecs == 1 ? 0 : qid;
1628 else
1629 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1630
1631 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1632 if (result)
1633 return result;
1634
1635 result = adapter_alloc_sq(dev, qid, nvmeq);
1636 if (result < 0)
1637 return result;
1638 if (result)
1639 goto release_cq;
1640
1641 nvmeq->cq_vector = vector;
1642
1643 result = nvme_setup_io_queues_trylock(dev);
1644 if (result)
1645 return result;
1646 nvme_init_queue(nvmeq, qid);
1647 if (!polled) {
1648 result = queue_request_irq(nvmeq);
1649 if (result < 0)
1650 goto release_sq;
1651 }
1652
1653 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1654 mutex_unlock(&dev->shutdown_lock);
1655 return result;
1656
1657 release_sq:
1658 dev->online_queues--;
1659 mutex_unlock(&dev->shutdown_lock);
1660 adapter_delete_sq(dev, qid);
1661 release_cq:
1662 adapter_delete_cq(dev, qid);
1663 return result;
1664 }
1665
1666 static const struct blk_mq_ops nvme_mq_admin_ops = {
1667 .queue_rq = nvme_queue_rq,
1668 .complete = nvme_pci_complete_rq,
1669 .init_hctx = nvme_admin_init_hctx,
1670 .init_request = nvme_pci_init_request,
1671 .timeout = nvme_timeout,
1672 };
1673
1674 static const struct blk_mq_ops nvme_mq_ops = {
1675 .queue_rq = nvme_queue_rq,
1676 .queue_rqs = nvme_queue_rqs,
1677 .complete = nvme_pci_complete_rq,
1678 .commit_rqs = nvme_commit_rqs,
1679 .init_hctx = nvme_init_hctx,
1680 .init_request = nvme_pci_init_request,
1681 .map_queues = nvme_pci_map_queues,
1682 .timeout = nvme_timeout,
1683 .poll = nvme_poll,
1684 };
1685
nvme_dev_remove_admin(struct nvme_dev * dev)1686 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1687 {
1688 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1689 /*
1690 * If the controller was reset during removal, it's possible
1691 * user requests may be waiting on a stopped queue. Start the
1692 * queue to flush these to completion.
1693 */
1694 nvme_unquiesce_admin_queue(&dev->ctrl);
1695 nvme_remove_admin_tag_set(&dev->ctrl);
1696 }
1697 }
1698
db_bar_size(struct nvme_dev * dev,unsigned nr_io_queues)1699 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1700 {
1701 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1702 }
1703
nvme_remap_bar(struct nvme_dev * dev,unsigned long size)1704 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1705 {
1706 struct pci_dev *pdev = to_pci_dev(dev->dev);
1707
1708 if (size <= dev->bar_mapped_size)
1709 return 0;
1710 if (size > pci_resource_len(pdev, 0))
1711 return -ENOMEM;
1712 if (dev->bar)
1713 iounmap(dev->bar);
1714 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1715 if (!dev->bar) {
1716 dev->bar_mapped_size = 0;
1717 return -ENOMEM;
1718 }
1719 dev->bar_mapped_size = size;
1720 dev->dbs = dev->bar + NVME_REG_DBS;
1721
1722 return 0;
1723 }
1724
nvme_pci_configure_admin_queue(struct nvme_dev * dev)1725 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1726 {
1727 int result;
1728 u32 aqa;
1729 struct nvme_queue *nvmeq;
1730
1731 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1732 if (result < 0)
1733 return result;
1734
1735 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1736 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1737
1738 if (dev->subsystem &&
1739 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1740 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1741
1742 /*
1743 * If the device has been passed off to us in an enabled state, just
1744 * clear the enabled bit. The spec says we should set the 'shutdown
1745 * notification bits', but doing so may cause the device to complete
1746 * commands to the admin queue ... and we don't know what memory that
1747 * might be pointing at!
1748 */
1749 result = nvme_disable_ctrl(&dev->ctrl, false);
1750 if (result < 0)
1751 return result;
1752
1753 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1754 if (result)
1755 return result;
1756
1757 dev->ctrl.numa_node = dev_to_node(dev->dev);
1758
1759 nvmeq = &dev->queues[0];
1760 aqa = nvmeq->q_depth - 1;
1761 aqa |= aqa << 16;
1762
1763 writel(aqa, dev->bar + NVME_REG_AQA);
1764 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1765 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1766
1767 result = nvme_enable_ctrl(&dev->ctrl);
1768 if (result)
1769 return result;
1770
1771 nvmeq->cq_vector = 0;
1772 nvme_init_queue(nvmeq, 0);
1773 result = queue_request_irq(nvmeq);
1774 if (result) {
1775 dev->online_queues--;
1776 return result;
1777 }
1778
1779 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1780 return result;
1781 }
1782
nvme_create_io_queues(struct nvme_dev * dev)1783 static int nvme_create_io_queues(struct nvme_dev *dev)
1784 {
1785 unsigned i, max, rw_queues;
1786 int ret = 0;
1787
1788 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1789 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1790 ret = -ENOMEM;
1791 break;
1792 }
1793 }
1794
1795 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1796 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1797 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1798 dev->io_queues[HCTX_TYPE_READ];
1799 } else {
1800 rw_queues = max;
1801 }
1802
1803 for (i = dev->online_queues; i <= max; i++) {
1804 bool polled = i > rw_queues;
1805
1806 ret = nvme_create_queue(&dev->queues[i], i, polled);
1807 if (ret)
1808 break;
1809 }
1810
1811 /*
1812 * Ignore failing Create SQ/CQ commands, we can continue with less
1813 * than the desired amount of queues, and even a controller without
1814 * I/O queues can still be used to issue admin commands. This might
1815 * be useful to upgrade a buggy firmware for example.
1816 */
1817 return ret >= 0 ? 0 : ret;
1818 }
1819
nvme_cmb_size_unit(struct nvme_dev * dev)1820 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1821 {
1822 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1823
1824 return 1ULL << (12 + 4 * szu);
1825 }
1826
nvme_cmb_size(struct nvme_dev * dev)1827 static u32 nvme_cmb_size(struct nvme_dev *dev)
1828 {
1829 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1830 }
1831
nvme_map_cmb(struct nvme_dev * dev)1832 static void nvme_map_cmb(struct nvme_dev *dev)
1833 {
1834 u64 size, offset;
1835 resource_size_t bar_size;
1836 struct pci_dev *pdev = to_pci_dev(dev->dev);
1837 int bar;
1838
1839 if (dev->cmb_size)
1840 return;
1841
1842 if (NVME_CAP_CMBS(dev->ctrl.cap))
1843 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1844
1845 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1846 if (!dev->cmbsz)
1847 return;
1848 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1849
1850 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1851 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1852 bar = NVME_CMB_BIR(dev->cmbloc);
1853 bar_size = pci_resource_len(pdev, bar);
1854
1855 if (offset > bar_size)
1856 return;
1857
1858 /*
1859 * Tell the controller about the host side address mapping the CMB,
1860 * and enable CMB decoding for the NVMe 1.4+ scheme:
1861 */
1862 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1863 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1864 (pci_bus_address(pdev, bar) + offset),
1865 dev->bar + NVME_REG_CMBMSC);
1866 }
1867
1868 /*
1869 * Controllers may support a CMB size larger than their BAR,
1870 * for example, due to being behind a bridge. Reduce the CMB to
1871 * the reported size of the BAR
1872 */
1873 if (size > bar_size - offset)
1874 size = bar_size - offset;
1875
1876 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1877 dev_warn(dev->ctrl.device,
1878 "failed to register the CMB\n");
1879 return;
1880 }
1881
1882 dev->cmb_size = size;
1883 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1884
1885 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1886 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1887 pci_p2pmem_publish(pdev, true);
1888
1889 nvme_update_attrs(dev);
1890 }
1891
nvme_set_host_mem(struct nvme_dev * dev,u32 bits)1892 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1893 {
1894 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1895 u64 dma_addr = dev->host_mem_descs_dma;
1896 struct nvme_command c = { };
1897 int ret;
1898
1899 c.features.opcode = nvme_admin_set_features;
1900 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1901 c.features.dword11 = cpu_to_le32(bits);
1902 c.features.dword12 = cpu_to_le32(host_mem_size);
1903 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1904 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1905 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1906
1907 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1908 if (ret) {
1909 dev_warn(dev->ctrl.device,
1910 "failed to set host mem (err %d, flags %#x).\n",
1911 ret, bits);
1912 } else
1913 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1914
1915 return ret;
1916 }
1917
nvme_free_host_mem(struct nvme_dev * dev)1918 static void nvme_free_host_mem(struct nvme_dev *dev)
1919 {
1920 int i;
1921
1922 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1923 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1924 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
1925
1926 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1927 le64_to_cpu(desc->addr),
1928 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1929 }
1930
1931 kfree(dev->host_mem_desc_bufs);
1932 dev->host_mem_desc_bufs = NULL;
1933 dma_free_coherent(dev->dev,
1934 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1935 dev->host_mem_descs, dev->host_mem_descs_dma);
1936 dev->host_mem_descs = NULL;
1937 dev->nr_host_mem_descs = 0;
1938 }
1939
__nvme_alloc_host_mem(struct nvme_dev * dev,u64 preferred,u32 chunk_size)1940 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1941 u32 chunk_size)
1942 {
1943 struct nvme_host_mem_buf_desc *descs;
1944 u32 max_entries, len;
1945 dma_addr_t descs_dma;
1946 int i = 0;
1947 void **bufs;
1948 u64 size, tmp;
1949
1950 tmp = (preferred + chunk_size - 1);
1951 do_div(tmp, chunk_size);
1952 max_entries = tmp;
1953
1954 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1955 max_entries = dev->ctrl.hmmaxd;
1956
1957 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1958 &descs_dma, GFP_KERNEL);
1959 if (!descs)
1960 goto out;
1961
1962 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1963 if (!bufs)
1964 goto out_free_descs;
1965
1966 for (size = 0; size < preferred && i < max_entries; size += len) {
1967 dma_addr_t dma_addr;
1968
1969 len = min_t(u64, chunk_size, preferred - size);
1970 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1971 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1972 if (!bufs[i])
1973 break;
1974
1975 descs[i].addr = cpu_to_le64(dma_addr);
1976 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
1977 i++;
1978 }
1979
1980 if (!size)
1981 goto out_free_bufs;
1982
1983 dev->nr_host_mem_descs = i;
1984 dev->host_mem_size = size;
1985 dev->host_mem_descs = descs;
1986 dev->host_mem_descs_dma = descs_dma;
1987 dev->host_mem_desc_bufs = bufs;
1988 return 0;
1989
1990 out_free_bufs:
1991 while (--i >= 0) {
1992 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
1993
1994 dma_free_attrs(dev->dev, size, bufs[i],
1995 le64_to_cpu(descs[i].addr),
1996 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1997 }
1998
1999 kfree(bufs);
2000 out_free_descs:
2001 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2002 descs_dma);
2003 out:
2004 dev->host_mem_descs = NULL;
2005 return -ENOMEM;
2006 }
2007
nvme_alloc_host_mem(struct nvme_dev * dev,u64 min,u64 preferred)2008 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2009 {
2010 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2011 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2012 u64 chunk_size;
2013
2014 /* start big and work our way down */
2015 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2016 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2017 if (!min || dev->host_mem_size >= min)
2018 return 0;
2019 nvme_free_host_mem(dev);
2020 }
2021 }
2022
2023 return -ENOMEM;
2024 }
2025
nvme_setup_host_mem(struct nvme_dev * dev)2026 static int nvme_setup_host_mem(struct nvme_dev *dev)
2027 {
2028 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2029 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2030 u64 min = (u64)dev->ctrl.hmmin * 4096;
2031 u32 enable_bits = NVME_HOST_MEM_ENABLE;
2032 int ret;
2033
2034 if (!dev->ctrl.hmpre)
2035 return 0;
2036
2037 preferred = min(preferred, max);
2038 if (min > max) {
2039 dev_warn(dev->ctrl.device,
2040 "min host memory (%lld MiB) above limit (%d MiB).\n",
2041 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2042 nvme_free_host_mem(dev);
2043 return 0;
2044 }
2045
2046 /*
2047 * If we already have a buffer allocated check if we can reuse it.
2048 */
2049 if (dev->host_mem_descs) {
2050 if (dev->host_mem_size >= min)
2051 enable_bits |= NVME_HOST_MEM_RETURN;
2052 else
2053 nvme_free_host_mem(dev);
2054 }
2055
2056 if (!dev->host_mem_descs) {
2057 if (nvme_alloc_host_mem(dev, min, preferred)) {
2058 dev_warn(dev->ctrl.device,
2059 "failed to allocate host memory buffer.\n");
2060 return 0; /* controller must work without HMB */
2061 }
2062
2063 dev_info(dev->ctrl.device,
2064 "allocated %lld MiB host memory buffer.\n",
2065 dev->host_mem_size >> ilog2(SZ_1M));
2066 }
2067
2068 ret = nvme_set_host_mem(dev, enable_bits);
2069 if (ret)
2070 nvme_free_host_mem(dev);
2071 return ret;
2072 }
2073
cmb_show(struct device * dev,struct device_attribute * attr,char * buf)2074 static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2075 char *buf)
2076 {
2077 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2078
2079 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n",
2080 ndev->cmbloc, ndev->cmbsz);
2081 }
2082 static DEVICE_ATTR_RO(cmb);
2083
cmbloc_show(struct device * dev,struct device_attribute * attr,char * buf)2084 static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2085 char *buf)
2086 {
2087 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2088
2089 return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2090 }
2091 static DEVICE_ATTR_RO(cmbloc);
2092
cmbsz_show(struct device * dev,struct device_attribute * attr,char * buf)2093 static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2094 char *buf)
2095 {
2096 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2097
2098 return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2099 }
2100 static DEVICE_ATTR_RO(cmbsz);
2101
hmb_show(struct device * dev,struct device_attribute * attr,char * buf)2102 static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2103 char *buf)
2104 {
2105 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2106
2107 return sysfs_emit(buf, "%d\n", ndev->hmb);
2108 }
2109
hmb_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2110 static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2111 const char *buf, size_t count)
2112 {
2113 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2114 bool new;
2115 int ret;
2116
2117 if (kstrtobool(buf, &new) < 0)
2118 return -EINVAL;
2119
2120 if (new == ndev->hmb)
2121 return count;
2122
2123 if (new) {
2124 ret = nvme_setup_host_mem(ndev);
2125 } else {
2126 ret = nvme_set_host_mem(ndev, 0);
2127 if (!ret)
2128 nvme_free_host_mem(ndev);
2129 }
2130
2131 if (ret < 0)
2132 return ret;
2133
2134 return count;
2135 }
2136 static DEVICE_ATTR_RW(hmb);
2137
nvme_pci_attrs_are_visible(struct kobject * kobj,struct attribute * a,int n)2138 static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2139 struct attribute *a, int n)
2140 {
2141 struct nvme_ctrl *ctrl =
2142 dev_get_drvdata(container_of(kobj, struct device, kobj));
2143 struct nvme_dev *dev = to_nvme_dev(ctrl);
2144
2145 if (a == &dev_attr_cmb.attr ||
2146 a == &dev_attr_cmbloc.attr ||
2147 a == &dev_attr_cmbsz.attr) {
2148 if (!dev->cmbsz)
2149 return 0;
2150 }
2151 if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2152 return 0;
2153
2154 return a->mode;
2155 }
2156
2157 static struct attribute *nvme_pci_attrs[] = {
2158 &dev_attr_cmb.attr,
2159 &dev_attr_cmbloc.attr,
2160 &dev_attr_cmbsz.attr,
2161 &dev_attr_hmb.attr,
2162 NULL,
2163 };
2164
2165 static const struct attribute_group nvme_pci_dev_attrs_group = {
2166 .attrs = nvme_pci_attrs,
2167 .is_visible = nvme_pci_attrs_are_visible,
2168 };
2169
2170 static const struct attribute_group *nvme_pci_dev_attr_groups[] = {
2171 &nvme_dev_attrs_group,
2172 &nvme_pci_dev_attrs_group,
2173 NULL,
2174 };
2175
nvme_update_attrs(struct nvme_dev * dev)2176 static void nvme_update_attrs(struct nvme_dev *dev)
2177 {
2178 sysfs_update_group(&dev->ctrl.device->kobj, &nvme_pci_dev_attrs_group);
2179 }
2180
2181 /*
2182 * nirqs is the number of interrupts available for write and read
2183 * queues. The core already reserved an interrupt for the admin queue.
2184 */
nvme_calc_irq_sets(struct irq_affinity * affd,unsigned int nrirqs)2185 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2186 {
2187 struct nvme_dev *dev = affd->priv;
2188 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2189
2190 /*
2191 * If there is no interrupt available for queues, ensure that
2192 * the default queue is set to 1. The affinity set size is
2193 * also set to one, but the irq core ignores it for this case.
2194 *
2195 * If only one interrupt is available or 'write_queue' == 0, combine
2196 * write and read queues.
2197 *
2198 * If 'write_queues' > 0, ensure it leaves room for at least one read
2199 * queue.
2200 */
2201 if (!nrirqs) {
2202 nrirqs = 1;
2203 nr_read_queues = 0;
2204 } else if (nrirqs == 1 || !nr_write_queues) {
2205 nr_read_queues = 0;
2206 } else if (nr_write_queues >= nrirqs) {
2207 nr_read_queues = 1;
2208 } else {
2209 nr_read_queues = nrirqs - nr_write_queues;
2210 }
2211
2212 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2213 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2214 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2215 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2216 affd->nr_sets = nr_read_queues ? 2 : 1;
2217 }
2218
nvme_setup_irqs(struct nvme_dev * dev,unsigned int nr_io_queues)2219 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2220 {
2221 struct pci_dev *pdev = to_pci_dev(dev->dev);
2222 struct irq_affinity affd = {
2223 .pre_vectors = 1,
2224 .calc_sets = nvme_calc_irq_sets,
2225 .priv = dev,
2226 };
2227 unsigned int irq_queues, poll_queues;
2228 unsigned int flags = PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY;
2229
2230 /*
2231 * Poll queues don't need interrupts, but we need at least one I/O queue
2232 * left over for non-polled I/O.
2233 */
2234 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2235 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2236
2237 /*
2238 * Initialize for the single interrupt case, will be updated in
2239 * nvme_calc_irq_sets().
2240 */
2241 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2242 dev->io_queues[HCTX_TYPE_READ] = 0;
2243
2244 /*
2245 * We need interrupts for the admin queue and each non-polled I/O queue,
2246 * but some Apple controllers require all queues to use the first
2247 * vector.
2248 */
2249 irq_queues = 1;
2250 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2251 irq_queues += (nr_io_queues - poll_queues);
2252 if (dev->ctrl.quirks & NVME_QUIRK_BROKEN_MSI)
2253 flags &= ~PCI_IRQ_MSI;
2254 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, flags,
2255 &affd);
2256 }
2257
nvme_max_io_queues(struct nvme_dev * dev)2258 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2259 {
2260 /*
2261 * If tags are shared with admin queue (Apple bug), then
2262 * make sure we only use one IO queue.
2263 */
2264 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2265 return 1;
2266 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2267 }
2268
nvme_setup_io_queues(struct nvme_dev * dev)2269 static int nvme_setup_io_queues(struct nvme_dev *dev)
2270 {
2271 struct nvme_queue *adminq = &dev->queues[0];
2272 struct pci_dev *pdev = to_pci_dev(dev->dev);
2273 unsigned int nr_io_queues;
2274 unsigned long size;
2275 int result;
2276
2277 /*
2278 * Sample the module parameters once at reset time so that we have
2279 * stable values to work with.
2280 */
2281 dev->nr_write_queues = write_queues;
2282 dev->nr_poll_queues = poll_queues;
2283
2284 nr_io_queues = dev->nr_allocated_queues - 1;
2285 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2286 if (result < 0)
2287 return result;
2288
2289 if (nr_io_queues == 0)
2290 return 0;
2291
2292 /*
2293 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2294 * from set to unset. If there is a window to it is truely freed,
2295 * pci_free_irq_vectors() jumping into this window will crash.
2296 * And take lock to avoid racing with pci_free_irq_vectors() in
2297 * nvme_dev_disable() path.
2298 */
2299 result = nvme_setup_io_queues_trylock(dev);
2300 if (result)
2301 return result;
2302 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2303 pci_free_irq(pdev, 0, adminq);
2304
2305 if (dev->cmb_use_sqes) {
2306 result = nvme_cmb_qdepth(dev, nr_io_queues,
2307 sizeof(struct nvme_command));
2308 if (result > 0) {
2309 dev->q_depth = result;
2310 dev->ctrl.sqsize = result - 1;
2311 } else {
2312 dev->cmb_use_sqes = false;
2313 }
2314 }
2315
2316 do {
2317 size = db_bar_size(dev, nr_io_queues);
2318 result = nvme_remap_bar(dev, size);
2319 if (!result)
2320 break;
2321 if (!--nr_io_queues) {
2322 result = -ENOMEM;
2323 goto out_unlock;
2324 }
2325 } while (1);
2326 adminq->q_db = dev->dbs;
2327
2328 retry:
2329 /* Deregister the admin queue's interrupt */
2330 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2331 pci_free_irq(pdev, 0, adminq);
2332
2333 /*
2334 * If we enable msix early due to not intx, disable it again before
2335 * setting up the full range we need.
2336 */
2337 pci_free_irq_vectors(pdev);
2338
2339 result = nvme_setup_irqs(dev, nr_io_queues);
2340 if (result <= 0) {
2341 result = -EIO;
2342 goto out_unlock;
2343 }
2344
2345 dev->num_vecs = result;
2346 result = max(result - 1, 1);
2347 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2348
2349 /*
2350 * Should investigate if there's a performance win from allocating
2351 * more queues than interrupt vectors; it might allow the submission
2352 * path to scale better, even if the receive path is limited by the
2353 * number of interrupts.
2354 */
2355 result = queue_request_irq(adminq);
2356 if (result)
2357 goto out_unlock;
2358 set_bit(NVMEQ_ENABLED, &adminq->flags);
2359 mutex_unlock(&dev->shutdown_lock);
2360
2361 result = nvme_create_io_queues(dev);
2362 if (result || dev->online_queues < 2)
2363 return result;
2364
2365 if (dev->online_queues - 1 < dev->max_qid) {
2366 nr_io_queues = dev->online_queues - 1;
2367 nvme_delete_io_queues(dev);
2368 result = nvme_setup_io_queues_trylock(dev);
2369 if (result)
2370 return result;
2371 nvme_suspend_io_queues(dev);
2372 goto retry;
2373 }
2374 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2375 dev->io_queues[HCTX_TYPE_DEFAULT],
2376 dev->io_queues[HCTX_TYPE_READ],
2377 dev->io_queues[HCTX_TYPE_POLL]);
2378 return 0;
2379 out_unlock:
2380 mutex_unlock(&dev->shutdown_lock);
2381 return result;
2382 }
2383
nvme_del_queue_end(struct request * req,blk_status_t error)2384 static enum rq_end_io_ret nvme_del_queue_end(struct request *req,
2385 blk_status_t error)
2386 {
2387 struct nvme_queue *nvmeq = req->end_io_data;
2388
2389 blk_mq_free_request(req);
2390 complete(&nvmeq->delete_done);
2391 return RQ_END_IO_NONE;
2392 }
2393
nvme_del_cq_end(struct request * req,blk_status_t error)2394 static enum rq_end_io_ret nvme_del_cq_end(struct request *req,
2395 blk_status_t error)
2396 {
2397 struct nvme_queue *nvmeq = req->end_io_data;
2398
2399 if (error)
2400 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2401
2402 return nvme_del_queue_end(req, error);
2403 }
2404
nvme_delete_queue(struct nvme_queue * nvmeq,u8 opcode)2405 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2406 {
2407 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2408 struct request *req;
2409 struct nvme_command cmd = { };
2410
2411 cmd.delete_queue.opcode = opcode;
2412 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2413
2414 req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
2415 if (IS_ERR(req))
2416 return PTR_ERR(req);
2417 nvme_init_request(req, &cmd);
2418
2419 if (opcode == nvme_admin_delete_cq)
2420 req->end_io = nvme_del_cq_end;
2421 else
2422 req->end_io = nvme_del_queue_end;
2423 req->end_io_data = nvmeq;
2424
2425 init_completion(&nvmeq->delete_done);
2426 blk_execute_rq_nowait(req, false);
2427 return 0;
2428 }
2429
__nvme_delete_io_queues(struct nvme_dev * dev,u8 opcode)2430 static bool __nvme_delete_io_queues(struct nvme_dev *dev, u8 opcode)
2431 {
2432 int nr_queues = dev->online_queues - 1, sent = 0;
2433 unsigned long timeout;
2434
2435 retry:
2436 timeout = NVME_ADMIN_TIMEOUT;
2437 while (nr_queues > 0) {
2438 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2439 break;
2440 nr_queues--;
2441 sent++;
2442 }
2443 while (sent) {
2444 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2445
2446 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2447 timeout);
2448 if (timeout == 0)
2449 return false;
2450
2451 sent--;
2452 if (nr_queues)
2453 goto retry;
2454 }
2455 return true;
2456 }
2457
nvme_delete_io_queues(struct nvme_dev * dev)2458 static void nvme_delete_io_queues(struct nvme_dev *dev)
2459 {
2460 if (__nvme_delete_io_queues(dev, nvme_admin_delete_sq))
2461 __nvme_delete_io_queues(dev, nvme_admin_delete_cq);
2462 }
2463
nvme_pci_nr_maps(struct nvme_dev * dev)2464 static unsigned int nvme_pci_nr_maps(struct nvme_dev *dev)
2465 {
2466 if (dev->io_queues[HCTX_TYPE_POLL])
2467 return 3;
2468 if (dev->io_queues[HCTX_TYPE_READ])
2469 return 2;
2470 return 1;
2471 }
2472
nvme_pci_update_nr_queues(struct nvme_dev * dev)2473 static void nvme_pci_update_nr_queues(struct nvme_dev *dev)
2474 {
2475 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2476 /* free previously allocated queues that are no longer usable */
2477 nvme_free_queues(dev, dev->online_queues);
2478 }
2479
nvme_pci_enable(struct nvme_dev * dev)2480 static int nvme_pci_enable(struct nvme_dev *dev)
2481 {
2482 int result = -ENOMEM;
2483 struct pci_dev *pdev = to_pci_dev(dev->dev);
2484 unsigned int flags = PCI_IRQ_ALL_TYPES;
2485
2486 if (pci_enable_device_mem(pdev))
2487 return result;
2488
2489 pci_set_master(pdev);
2490
2491 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2492 result = -ENODEV;
2493 goto disable;
2494 }
2495
2496 /*
2497 * Some devices and/or platforms don't advertise or work with INTx
2498 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2499 * adjust this later.
2500 */
2501 if (dev->ctrl.quirks & NVME_QUIRK_BROKEN_MSI)
2502 flags &= ~PCI_IRQ_MSI;
2503 result = pci_alloc_irq_vectors(pdev, 1, 1, flags);
2504 if (result < 0)
2505 goto disable;
2506
2507 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2508
2509 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2510 io_queue_depth);
2511 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2512 dev->dbs = dev->bar + 4096;
2513
2514 /*
2515 * Some Apple controllers require a non-standard SQE size.
2516 * Interestingly they also seem to ignore the CC:IOSQES register
2517 * so we don't bother updating it here.
2518 */
2519 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2520 dev->io_sqes = 7;
2521 else
2522 dev->io_sqes = NVME_NVM_IOSQES;
2523
2524 /*
2525 * Temporary fix for the Apple controller found in the MacBook8,1 and
2526 * some MacBook7,1 to avoid controller resets and data loss.
2527 */
2528 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2529 dev->q_depth = 2;
2530 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2531 "set queue depth=%u to work around controller resets\n",
2532 dev->q_depth);
2533 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2534 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2535 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2536 dev->q_depth = 64;
2537 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2538 "set queue depth=%u\n", dev->q_depth);
2539 }
2540
2541 /*
2542 * Controllers with the shared tags quirk need the IO queue to be
2543 * big enough so that we get 32 tags for the admin queue
2544 */
2545 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2546 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2547 dev->q_depth = NVME_AQ_DEPTH + 2;
2548 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2549 dev->q_depth);
2550 }
2551 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2552
2553 nvme_map_cmb(dev);
2554
2555 pci_save_state(pdev);
2556
2557 result = nvme_pci_configure_admin_queue(dev);
2558 if (result)
2559 goto free_irq;
2560 return result;
2561
2562 free_irq:
2563 pci_free_irq_vectors(pdev);
2564 disable:
2565 pci_disable_device(pdev);
2566 return result;
2567 }
2568
nvme_dev_unmap(struct nvme_dev * dev)2569 static void nvme_dev_unmap(struct nvme_dev *dev)
2570 {
2571 if (dev->bar)
2572 iounmap(dev->bar);
2573 pci_release_mem_regions(to_pci_dev(dev->dev));
2574 }
2575
nvme_pci_ctrl_is_dead(struct nvme_dev * dev)2576 static bool nvme_pci_ctrl_is_dead(struct nvme_dev *dev)
2577 {
2578 struct pci_dev *pdev = to_pci_dev(dev->dev);
2579 u32 csts;
2580
2581 if (!pci_is_enabled(pdev) || !pci_device_is_present(pdev))
2582 return true;
2583 if (pdev->error_state != pci_channel_io_normal)
2584 return true;
2585
2586 csts = readl(dev->bar + NVME_REG_CSTS);
2587 return (csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY);
2588 }
2589
nvme_dev_disable(struct nvme_dev * dev,bool shutdown)2590 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2591 {
2592 enum nvme_ctrl_state state = nvme_ctrl_state(&dev->ctrl);
2593 struct pci_dev *pdev = to_pci_dev(dev->dev);
2594 bool dead;
2595
2596 mutex_lock(&dev->shutdown_lock);
2597 dead = nvme_pci_ctrl_is_dead(dev);
2598 if (state == NVME_CTRL_LIVE || state == NVME_CTRL_RESETTING) {
2599 if (pci_is_enabled(pdev))
2600 nvme_start_freeze(&dev->ctrl);
2601 /*
2602 * Give the controller a chance to complete all entered requests
2603 * if doing a safe shutdown.
2604 */
2605 if (!dead && shutdown)
2606 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2607 }
2608
2609 nvme_quiesce_io_queues(&dev->ctrl);
2610
2611 if (!dead && dev->ctrl.queue_count > 0) {
2612 nvme_delete_io_queues(dev);
2613 nvme_disable_ctrl(&dev->ctrl, shutdown);
2614 nvme_poll_irqdisable(&dev->queues[0]);
2615 }
2616 nvme_suspend_io_queues(dev);
2617 nvme_suspend_queue(dev, 0);
2618 pci_free_irq_vectors(pdev);
2619 if (pci_is_enabled(pdev))
2620 pci_disable_device(pdev);
2621 nvme_reap_pending_cqes(dev);
2622
2623 nvme_cancel_tagset(&dev->ctrl);
2624 nvme_cancel_admin_tagset(&dev->ctrl);
2625
2626 /*
2627 * The driver will not be starting up queues again if shutting down so
2628 * must flush all entered requests to their failed completion to avoid
2629 * deadlocking blk-mq hot-cpu notifier.
2630 */
2631 if (shutdown) {
2632 nvme_unquiesce_io_queues(&dev->ctrl);
2633 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2634 nvme_unquiesce_admin_queue(&dev->ctrl);
2635 }
2636 mutex_unlock(&dev->shutdown_lock);
2637 }
2638
nvme_disable_prepare_reset(struct nvme_dev * dev,bool shutdown)2639 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2640 {
2641 if (!nvme_wait_reset(&dev->ctrl))
2642 return -EBUSY;
2643 nvme_dev_disable(dev, shutdown);
2644 return 0;
2645 }
2646
nvme_setup_prp_pools(struct nvme_dev * dev)2647 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2648 {
2649 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2650 NVME_CTRL_PAGE_SIZE,
2651 NVME_CTRL_PAGE_SIZE, 0);
2652 if (!dev->prp_page_pool)
2653 return -ENOMEM;
2654
2655 /* Optimisation for I/Os between 4k and 128k */
2656 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2657 256, 256, 0);
2658 if (!dev->prp_small_pool) {
2659 dma_pool_destroy(dev->prp_page_pool);
2660 return -ENOMEM;
2661 }
2662 return 0;
2663 }
2664
nvme_release_prp_pools(struct nvme_dev * dev)2665 static void nvme_release_prp_pools(struct nvme_dev *dev)
2666 {
2667 dma_pool_destroy(dev->prp_page_pool);
2668 dma_pool_destroy(dev->prp_small_pool);
2669 }
2670
nvme_pci_alloc_iod_mempool(struct nvme_dev * dev)2671 static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev)
2672 {
2673 size_t alloc_size = sizeof(struct scatterlist) * NVME_MAX_SEGS;
2674
2675 dev->iod_mempool = mempool_create_node(1,
2676 mempool_kmalloc, mempool_kfree,
2677 (void *)alloc_size, GFP_KERNEL,
2678 dev_to_node(dev->dev));
2679 if (!dev->iod_mempool)
2680 return -ENOMEM;
2681 return 0;
2682 }
2683
nvme_free_tagset(struct nvme_dev * dev)2684 static void nvme_free_tagset(struct nvme_dev *dev)
2685 {
2686 if (dev->tagset.tags)
2687 nvme_remove_io_tag_set(&dev->ctrl);
2688 dev->ctrl.tagset = NULL;
2689 }
2690
2691 /* pairs with nvme_pci_alloc_dev */
nvme_pci_free_ctrl(struct nvme_ctrl * ctrl)2692 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2693 {
2694 struct nvme_dev *dev = to_nvme_dev(ctrl);
2695
2696 nvme_free_tagset(dev);
2697 put_device(dev->dev);
2698 kfree(dev->queues);
2699 kfree(dev);
2700 }
2701
nvme_reset_work(struct work_struct * work)2702 static void nvme_reset_work(struct work_struct *work)
2703 {
2704 struct nvme_dev *dev =
2705 container_of(work, struct nvme_dev, ctrl.reset_work);
2706 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2707 int result;
2708
2709 if (nvme_ctrl_state(&dev->ctrl) != NVME_CTRL_RESETTING) {
2710 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2711 dev->ctrl.state);
2712 result = -ENODEV;
2713 goto out;
2714 }
2715
2716 /*
2717 * If we're called to reset a live controller first shut it down before
2718 * moving on.
2719 */
2720 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2721 nvme_dev_disable(dev, false);
2722 nvme_sync_queues(&dev->ctrl);
2723
2724 mutex_lock(&dev->shutdown_lock);
2725 result = nvme_pci_enable(dev);
2726 if (result)
2727 goto out_unlock;
2728 nvme_unquiesce_admin_queue(&dev->ctrl);
2729 mutex_unlock(&dev->shutdown_lock);
2730
2731 /*
2732 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2733 * initializing procedure here.
2734 */
2735 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2736 dev_warn(dev->ctrl.device,
2737 "failed to mark controller CONNECTING\n");
2738 result = -EBUSY;
2739 goto out;
2740 }
2741
2742 result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend);
2743 if (result)
2744 goto out;
2745
2746 nvme_dbbuf_dma_alloc(dev);
2747
2748 result = nvme_setup_host_mem(dev);
2749 if (result < 0)
2750 goto out;
2751
2752 result = nvme_setup_io_queues(dev);
2753 if (result)
2754 goto out;
2755
2756 /*
2757 * Freeze and update the number of I/O queues as thos might have
2758 * changed. If there are no I/O queues left after this reset, keep the
2759 * controller around but remove all namespaces.
2760 */
2761 if (dev->online_queues > 1) {
2762 nvme_dbbuf_set(dev);
2763 nvme_unquiesce_io_queues(&dev->ctrl);
2764 nvme_wait_freeze(&dev->ctrl);
2765 nvme_pci_update_nr_queues(dev);
2766 nvme_unfreeze(&dev->ctrl);
2767 } else {
2768 dev_warn(dev->ctrl.device, "IO queues lost\n");
2769 nvme_mark_namespaces_dead(&dev->ctrl);
2770 nvme_unquiesce_io_queues(&dev->ctrl);
2771 nvme_remove_namespaces(&dev->ctrl);
2772 nvme_free_tagset(dev);
2773 }
2774
2775 /*
2776 * If only admin queue live, keep it to do further investigation or
2777 * recovery.
2778 */
2779 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2780 dev_warn(dev->ctrl.device,
2781 "failed to mark controller live state\n");
2782 result = -ENODEV;
2783 goto out;
2784 }
2785
2786 nvme_start_ctrl(&dev->ctrl);
2787 return;
2788
2789 out_unlock:
2790 mutex_unlock(&dev->shutdown_lock);
2791 out:
2792 /*
2793 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2794 * may be holding this pci_dev's device lock.
2795 */
2796 dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n",
2797 result);
2798 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2799 nvme_dev_disable(dev, true);
2800 nvme_sync_queues(&dev->ctrl);
2801 nvme_mark_namespaces_dead(&dev->ctrl);
2802 nvme_unquiesce_io_queues(&dev->ctrl);
2803 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2804 }
2805
nvme_pci_reg_read32(struct nvme_ctrl * ctrl,u32 off,u32 * val)2806 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2807 {
2808 *val = readl(to_nvme_dev(ctrl)->bar + off);
2809 return 0;
2810 }
2811
nvme_pci_reg_write32(struct nvme_ctrl * ctrl,u32 off,u32 val)2812 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2813 {
2814 writel(val, to_nvme_dev(ctrl)->bar + off);
2815 return 0;
2816 }
2817
nvme_pci_reg_read64(struct nvme_ctrl * ctrl,u32 off,u64 * val)2818 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2819 {
2820 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2821 return 0;
2822 }
2823
nvme_pci_get_address(struct nvme_ctrl * ctrl,char * buf,int size)2824 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2825 {
2826 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2827
2828 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2829 }
2830
nvme_pci_print_device_info(struct nvme_ctrl * ctrl)2831 static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
2832 {
2833 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2834 struct nvme_subsystem *subsys = ctrl->subsys;
2835
2836 dev_err(ctrl->device,
2837 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
2838 pdev->vendor, pdev->device,
2839 nvme_strlen(subsys->model, sizeof(subsys->model)),
2840 subsys->model, nvme_strlen(subsys->firmware_rev,
2841 sizeof(subsys->firmware_rev)),
2842 subsys->firmware_rev);
2843 }
2844
nvme_pci_supports_pci_p2pdma(struct nvme_ctrl * ctrl)2845 static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl)
2846 {
2847 struct nvme_dev *dev = to_nvme_dev(ctrl);
2848
2849 return dma_pci_p2pdma_supported(dev->dev);
2850 }
2851
2852 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2853 .name = "pcie",
2854 .module = THIS_MODULE,
2855 .flags = NVME_F_METADATA_SUPPORTED,
2856 .dev_attr_groups = nvme_pci_dev_attr_groups,
2857 .reg_read32 = nvme_pci_reg_read32,
2858 .reg_write32 = nvme_pci_reg_write32,
2859 .reg_read64 = nvme_pci_reg_read64,
2860 .free_ctrl = nvme_pci_free_ctrl,
2861 .submit_async_event = nvme_pci_submit_async_event,
2862 .get_address = nvme_pci_get_address,
2863 .print_device_info = nvme_pci_print_device_info,
2864 .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma,
2865 };
2866
nvme_dev_map(struct nvme_dev * dev)2867 static int nvme_dev_map(struct nvme_dev *dev)
2868 {
2869 struct pci_dev *pdev = to_pci_dev(dev->dev);
2870
2871 if (pci_request_mem_regions(pdev, "nvme"))
2872 return -ENODEV;
2873
2874 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2875 goto release;
2876
2877 return 0;
2878 release:
2879 pci_release_mem_regions(pdev);
2880 return -ENODEV;
2881 }
2882
check_vendor_combination_bug(struct pci_dev * pdev)2883 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2884 {
2885 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2886 /*
2887 * Several Samsung devices seem to drop off the PCIe bus
2888 * randomly when APST is on and uses the deepest sleep state.
2889 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2890 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2891 * 950 PRO 256GB", but it seems to be restricted to two Dell
2892 * laptops.
2893 */
2894 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2895 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2896 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2897 return NVME_QUIRK_NO_DEEPEST_PS;
2898 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2899 /*
2900 * Samsung SSD 960 EVO drops off the PCIe bus after system
2901 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2902 * within few minutes after bootup on a Coffee Lake board -
2903 * ASUS PRIME Z370-A
2904 */
2905 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2906 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2907 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2908 return NVME_QUIRK_NO_APST;
2909 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2910 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2911 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2912 /*
2913 * Forcing to use host managed nvme power settings for
2914 * lowest idle power with quick resume latency on
2915 * Samsung and Toshiba SSDs based on suspend behavior
2916 * on Coffee Lake board for LENOVO C640
2917 */
2918 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2919 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2920 return NVME_QUIRK_SIMPLE_SUSPEND;
2921 } else if (pdev->vendor == 0x2646 && (pdev->device == 0x2263 ||
2922 pdev->device == 0x500f)) {
2923 /*
2924 * Exclude some Kingston NV1 and A2000 devices from
2925 * NVME_QUIRK_SIMPLE_SUSPEND. Do a full suspend to save a
2926 * lot fo energy with s2idle sleep on some TUXEDO platforms.
2927 */
2928 if (dmi_match(DMI_BOARD_NAME, "NS5X_NS7XAU") ||
2929 dmi_match(DMI_BOARD_NAME, "NS5x_7xAU") ||
2930 dmi_match(DMI_BOARD_NAME, "NS5x_7xPU") ||
2931 dmi_match(DMI_BOARD_NAME, "PH4PRX1_PH6PRX1"))
2932 return NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND;
2933 }
2934
2935 return 0;
2936 }
2937
nvme_pci_alloc_dev(struct pci_dev * pdev,const struct pci_device_id * id)2938 static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev,
2939 const struct pci_device_id *id)
2940 {
2941 unsigned long quirks = id->driver_data;
2942 int node = dev_to_node(&pdev->dev);
2943 struct nvme_dev *dev;
2944 int ret = -ENOMEM;
2945
2946 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2947 if (!dev)
2948 return ERR_PTR(-ENOMEM);
2949 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2950 mutex_init(&dev->shutdown_lock);
2951
2952 dev->nr_write_queues = write_queues;
2953 dev->nr_poll_queues = poll_queues;
2954 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2955 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2956 sizeof(struct nvme_queue), GFP_KERNEL, node);
2957 if (!dev->queues)
2958 goto out_free_dev;
2959
2960 dev->dev = get_device(&pdev->dev);
2961
2962 quirks |= check_vendor_combination_bug(pdev);
2963 if (!noacpi &&
2964 !(quirks & NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND) &&
2965 acpi_storage_d3(&pdev->dev)) {
2966 /*
2967 * Some systems use a bios work around to ask for D3 on
2968 * platforms that support kernel managed suspend.
2969 */
2970 dev_info(&pdev->dev,
2971 "platform quirk: setting simple suspend\n");
2972 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2973 }
2974 ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2975 quirks);
2976 if (ret)
2977 goto out_put_device;
2978
2979 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2980 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48));
2981 else
2982 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2983 dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1);
2984 dma_set_max_seg_size(&pdev->dev, 0xffffffff);
2985
2986 /*
2987 * Limit the max command size to prevent iod->sg allocations going
2988 * over a single page.
2989 */
2990 dev->ctrl.max_hw_sectors = min_t(u32,
2991 NVME_MAX_KB_SZ << 1, dma_opt_mapping_size(&pdev->dev) >> 9);
2992 dev->ctrl.max_segments = NVME_MAX_SEGS;
2993
2994 /*
2995 * There is no support for SGLs for metadata (yet), so we are limited to
2996 * a single integrity segment for the separate metadata pointer.
2997 */
2998 dev->ctrl.max_integrity_segments = 1;
2999 return dev;
3000
3001 out_put_device:
3002 put_device(dev->dev);
3003 kfree(dev->queues);
3004 out_free_dev:
3005 kfree(dev);
3006 return ERR_PTR(ret);
3007 }
3008
nvme_probe(struct pci_dev * pdev,const struct pci_device_id * id)3009 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3010 {
3011 struct nvme_dev *dev;
3012 int result = -ENOMEM;
3013
3014 dev = nvme_pci_alloc_dev(pdev, id);
3015 if (IS_ERR(dev))
3016 return PTR_ERR(dev);
3017
3018 result = nvme_dev_map(dev);
3019 if (result)
3020 goto out_uninit_ctrl;
3021
3022 result = nvme_setup_prp_pools(dev);
3023 if (result)
3024 goto out_dev_unmap;
3025
3026 result = nvme_pci_alloc_iod_mempool(dev);
3027 if (result)
3028 goto out_release_prp_pools;
3029
3030 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3031
3032 result = nvme_pci_enable(dev);
3033 if (result)
3034 goto out_release_iod_mempool;
3035
3036 result = nvme_alloc_admin_tag_set(&dev->ctrl, &dev->admin_tagset,
3037 &nvme_mq_admin_ops, sizeof(struct nvme_iod));
3038 if (result)
3039 goto out_disable;
3040
3041 /*
3042 * Mark the controller as connecting before sending admin commands to
3043 * allow the timeout handler to do the right thing.
3044 */
3045 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
3046 dev_warn(dev->ctrl.device,
3047 "failed to mark controller CONNECTING\n");
3048 result = -EBUSY;
3049 goto out_disable;
3050 }
3051
3052 result = nvme_init_ctrl_finish(&dev->ctrl, false);
3053 if (result)
3054 goto out_disable;
3055
3056 nvme_dbbuf_dma_alloc(dev);
3057
3058 result = nvme_setup_host_mem(dev);
3059 if (result < 0)
3060 goto out_disable;
3061
3062 result = nvme_setup_io_queues(dev);
3063 if (result)
3064 goto out_disable;
3065
3066 if (dev->online_queues > 1) {
3067 nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops,
3068 nvme_pci_nr_maps(dev), sizeof(struct nvme_iod));
3069 nvme_dbbuf_set(dev);
3070 }
3071
3072 if (!dev->ctrl.tagset)
3073 dev_warn(dev->ctrl.device, "IO queues not created\n");
3074
3075 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
3076 dev_warn(dev->ctrl.device,
3077 "failed to mark controller live state\n");
3078 result = -ENODEV;
3079 goto out_disable;
3080 }
3081
3082 pci_set_drvdata(pdev, dev);
3083
3084 nvme_start_ctrl(&dev->ctrl);
3085 nvme_put_ctrl(&dev->ctrl);
3086 flush_work(&dev->ctrl.scan_work);
3087 return 0;
3088
3089 out_disable:
3090 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3091 nvme_dev_disable(dev, true);
3092 nvme_free_host_mem(dev);
3093 nvme_dev_remove_admin(dev);
3094 nvme_dbbuf_dma_free(dev);
3095 nvme_free_queues(dev, 0);
3096 out_release_iod_mempool:
3097 mempool_destroy(dev->iod_mempool);
3098 out_release_prp_pools:
3099 nvme_release_prp_pools(dev);
3100 out_dev_unmap:
3101 nvme_dev_unmap(dev);
3102 out_uninit_ctrl:
3103 nvme_uninit_ctrl(&dev->ctrl);
3104 nvme_put_ctrl(&dev->ctrl);
3105 return result;
3106 }
3107
nvme_reset_prepare(struct pci_dev * pdev)3108 static void nvme_reset_prepare(struct pci_dev *pdev)
3109 {
3110 struct nvme_dev *dev = pci_get_drvdata(pdev);
3111
3112 /*
3113 * We don't need to check the return value from waiting for the reset
3114 * state as pci_dev device lock is held, making it impossible to race
3115 * with ->remove().
3116 */
3117 nvme_disable_prepare_reset(dev, false);
3118 nvme_sync_queues(&dev->ctrl);
3119 }
3120
nvme_reset_done(struct pci_dev * pdev)3121 static void nvme_reset_done(struct pci_dev *pdev)
3122 {
3123 struct nvme_dev *dev = pci_get_drvdata(pdev);
3124
3125 if (!nvme_try_sched_reset(&dev->ctrl))
3126 flush_work(&dev->ctrl.reset_work);
3127 }
3128
nvme_shutdown(struct pci_dev * pdev)3129 static void nvme_shutdown(struct pci_dev *pdev)
3130 {
3131 struct nvme_dev *dev = pci_get_drvdata(pdev);
3132
3133 nvme_disable_prepare_reset(dev, true);
3134 }
3135
3136 /*
3137 * The driver's remove may be called on a device in a partially initialized
3138 * state. This function must not have any dependencies on the device state in
3139 * order to proceed.
3140 */
nvme_remove(struct pci_dev * pdev)3141 static void nvme_remove(struct pci_dev *pdev)
3142 {
3143 struct nvme_dev *dev = pci_get_drvdata(pdev);
3144
3145 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3146 pci_set_drvdata(pdev, NULL);
3147
3148 if (!pci_device_is_present(pdev)) {
3149 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3150 nvme_dev_disable(dev, true);
3151 }
3152
3153 flush_work(&dev->ctrl.reset_work);
3154 nvme_stop_ctrl(&dev->ctrl);
3155 nvme_remove_namespaces(&dev->ctrl);
3156 nvme_dev_disable(dev, true);
3157 nvme_free_host_mem(dev);
3158 nvme_dev_remove_admin(dev);
3159 nvme_dbbuf_dma_free(dev);
3160 nvme_free_queues(dev, 0);
3161 mempool_destroy(dev->iod_mempool);
3162 nvme_release_prp_pools(dev);
3163 nvme_dev_unmap(dev);
3164 nvme_uninit_ctrl(&dev->ctrl);
3165 }
3166
3167 #ifdef CONFIG_PM_SLEEP
nvme_get_power_state(struct nvme_ctrl * ctrl,u32 * ps)3168 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3169 {
3170 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3171 }
3172
nvme_set_power_state(struct nvme_ctrl * ctrl,u32 ps)3173 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3174 {
3175 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3176 }
3177
nvme_resume(struct device * dev)3178 static int nvme_resume(struct device *dev)
3179 {
3180 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3181 struct nvme_ctrl *ctrl = &ndev->ctrl;
3182
3183 if (ndev->last_ps == U32_MAX ||
3184 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3185 goto reset;
3186 if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3187 goto reset;
3188
3189 return 0;
3190 reset:
3191 return nvme_try_sched_reset(ctrl);
3192 }
3193
nvme_suspend(struct device * dev)3194 static int nvme_suspend(struct device *dev)
3195 {
3196 struct pci_dev *pdev = to_pci_dev(dev);
3197 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3198 struct nvme_ctrl *ctrl = &ndev->ctrl;
3199 int ret = -EBUSY;
3200
3201 ndev->last_ps = U32_MAX;
3202
3203 /*
3204 * The platform does not remove power for a kernel managed suspend so
3205 * use host managed nvme power settings for lowest idle power if
3206 * possible. This should have quicker resume latency than a full device
3207 * shutdown. But if the firmware is involved after the suspend or the
3208 * device does not support any non-default power states, shut down the
3209 * device fully.
3210 *
3211 * If ASPM is not enabled for the device, shut down the device and allow
3212 * the PCI bus layer to put it into D3 in order to take the PCIe link
3213 * down, so as to allow the platform to achieve its minimum low-power
3214 * state (which may not be possible if the link is up).
3215 */
3216 if (pm_suspend_via_firmware() || !ctrl->npss ||
3217 !pcie_aspm_enabled(pdev) ||
3218 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3219 return nvme_disable_prepare_reset(ndev, true);
3220
3221 nvme_start_freeze(ctrl);
3222 nvme_wait_freeze(ctrl);
3223 nvme_sync_queues(ctrl);
3224
3225 if (nvme_ctrl_state(ctrl) != NVME_CTRL_LIVE)
3226 goto unfreeze;
3227
3228 /*
3229 * Host memory access may not be successful in a system suspend state,
3230 * but the specification allows the controller to access memory in a
3231 * non-operational power state.
3232 */
3233 if (ndev->hmb) {
3234 ret = nvme_set_host_mem(ndev, 0);
3235 if (ret < 0)
3236 goto unfreeze;
3237 }
3238
3239 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3240 if (ret < 0)
3241 goto unfreeze;
3242
3243 /*
3244 * A saved state prevents pci pm from generically controlling the
3245 * device's power. If we're using protocol specific settings, we don't
3246 * want pci interfering.
3247 */
3248 pci_save_state(pdev);
3249
3250 ret = nvme_set_power_state(ctrl, ctrl->npss);
3251 if (ret < 0)
3252 goto unfreeze;
3253
3254 if (ret) {
3255 /* discard the saved state */
3256 pci_load_saved_state(pdev, NULL);
3257
3258 /*
3259 * Clearing npss forces a controller reset on resume. The
3260 * correct value will be rediscovered then.
3261 */
3262 ret = nvme_disable_prepare_reset(ndev, true);
3263 ctrl->npss = 0;
3264 }
3265 unfreeze:
3266 nvme_unfreeze(ctrl);
3267 return ret;
3268 }
3269
nvme_simple_suspend(struct device * dev)3270 static int nvme_simple_suspend(struct device *dev)
3271 {
3272 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3273
3274 return nvme_disable_prepare_reset(ndev, true);
3275 }
3276
nvme_simple_resume(struct device * dev)3277 static int nvme_simple_resume(struct device *dev)
3278 {
3279 struct pci_dev *pdev = to_pci_dev(dev);
3280 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3281
3282 return nvme_try_sched_reset(&ndev->ctrl);
3283 }
3284
3285 static const struct dev_pm_ops nvme_dev_pm_ops = {
3286 .suspend = nvme_suspend,
3287 .resume = nvme_resume,
3288 .freeze = nvme_simple_suspend,
3289 .thaw = nvme_simple_resume,
3290 .poweroff = nvme_simple_suspend,
3291 .restore = nvme_simple_resume,
3292 };
3293 #endif /* CONFIG_PM_SLEEP */
3294
nvme_error_detected(struct pci_dev * pdev,pci_channel_state_t state)3295 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3296 pci_channel_state_t state)
3297 {
3298 struct nvme_dev *dev = pci_get_drvdata(pdev);
3299
3300 /*
3301 * A frozen channel requires a reset. When detected, this method will
3302 * shutdown the controller to quiesce. The controller will be restarted
3303 * after the slot reset through driver's slot_reset callback.
3304 */
3305 switch (state) {
3306 case pci_channel_io_normal:
3307 return PCI_ERS_RESULT_CAN_RECOVER;
3308 case pci_channel_io_frozen:
3309 dev_warn(dev->ctrl.device,
3310 "frozen state error detected, reset controller\n");
3311 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) {
3312 nvme_dev_disable(dev, true);
3313 return PCI_ERS_RESULT_DISCONNECT;
3314 }
3315 nvme_dev_disable(dev, false);
3316 return PCI_ERS_RESULT_NEED_RESET;
3317 case pci_channel_io_perm_failure:
3318 dev_warn(dev->ctrl.device,
3319 "failure state error detected, request disconnect\n");
3320 return PCI_ERS_RESULT_DISCONNECT;
3321 }
3322 return PCI_ERS_RESULT_NEED_RESET;
3323 }
3324
nvme_slot_reset(struct pci_dev * pdev)3325 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3326 {
3327 struct nvme_dev *dev = pci_get_drvdata(pdev);
3328
3329 dev_info(dev->ctrl.device, "restart after slot reset\n");
3330 pci_restore_state(pdev);
3331 if (!nvme_try_sched_reset(&dev->ctrl))
3332 nvme_unquiesce_io_queues(&dev->ctrl);
3333 return PCI_ERS_RESULT_RECOVERED;
3334 }
3335
nvme_error_resume(struct pci_dev * pdev)3336 static void nvme_error_resume(struct pci_dev *pdev)
3337 {
3338 struct nvme_dev *dev = pci_get_drvdata(pdev);
3339
3340 flush_work(&dev->ctrl.reset_work);
3341 }
3342
3343 static const struct pci_error_handlers nvme_err_handler = {
3344 .error_detected = nvme_error_detected,
3345 .slot_reset = nvme_slot_reset,
3346 .resume = nvme_error_resume,
3347 .reset_prepare = nvme_reset_prepare,
3348 .reset_done = nvme_reset_done,
3349 };
3350
3351 static const struct pci_device_id nvme_id_table[] = {
3352 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
3353 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3354 NVME_QUIRK_DEALLOCATE_ZEROES, },
3355 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
3356 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3357 NVME_QUIRK_DEALLOCATE_ZEROES, },
3358 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
3359 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3360 NVME_QUIRK_DEALLOCATE_ZEROES |
3361 NVME_QUIRK_IGNORE_DEV_SUBNQN |
3362 NVME_QUIRK_BOGUS_NID, },
3363 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
3364 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3365 NVME_QUIRK_DEALLOCATE_ZEROES, },
3366 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
3367 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3368 NVME_QUIRK_MEDIUM_PRIO_SQ |
3369 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3370 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3371 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3372 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3373 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
3374 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3375 NVME_QUIRK_DISABLE_WRITE_ZEROES |
3376 NVME_QUIRK_BOGUS_NID, },
3377 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */
3378 .driver_data = NVME_QUIRK_BOGUS_NID, },
3379 { PCI_DEVICE(0x126f, 0x2262), /* Silicon Motion generic */
3380 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3381 NVME_QUIRK_BOGUS_NID, },
3382 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
3383 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3384 NVME_QUIRK_BOGUS_NID, },
3385 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3386 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3387 NVME_QUIRK_NO_NS_DESC_LIST, },
3388 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3389 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3390 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3391 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3392 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3393 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3394 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3395 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3396 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3397 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3398 NVME_QUIRK_DISABLE_WRITE_ZEROES|
3399 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3400 { PCI_DEVICE(0x15b7, 0x5008), /* Sandisk SN530 */
3401 .driver_data = NVME_QUIRK_BROKEN_MSI },
3402 { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */
3403 .driver_data = NVME_QUIRK_BOGUS_NID, },
3404 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
3405 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3406 NVME_QUIRK_BOGUS_NID, },
3407 { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */
3408 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3409 { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */
3410 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3411 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3412 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3413 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3414 { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */
3415 .driver_data = NVME_QUIRK_BOGUS_NID, },
3416 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3417 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3418 NVME_QUIRK_BOGUS_NID, },
3419 { PCI_DEVICE(0x10ec, 0x5763), /* ADATA SX6000PNP */
3420 .driver_data = NVME_QUIRK_BOGUS_NID, },
3421 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3422 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3423 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3424 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
3425 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
3426 { PCI_DEVICE(0x1344, 0x6001), /* Micron Nitro NVMe */
3427 .driver_data = NVME_QUIRK_BOGUS_NID, },
3428 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3429 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3430 { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */
3431 .driver_data = NVME_QUIRK_BOGUS_NID, },
3432 { PCI_DEVICE(0x1c5c, 0x1D59), /* SK Hynix BC901 */
3433 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3434 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3435 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3436 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3437 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3438 { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */
3439 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES |
3440 NVME_QUIRK_BOGUS_NID, },
3441 { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */
3442 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3443 { PCI_DEVICE(0x144d, 0xa802), /* Samsung SM953 */
3444 .driver_data = NVME_QUIRK_BOGUS_NID, },
3445 { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */
3446 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3447 { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */
3448 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3449 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3450 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3451 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3452 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3453 { PCI_DEVICE(0x2646, 0x5013), /* Kingston KC3000, Kingston FURY Renegade */
3454 .driver_data = NVME_QUIRK_NO_SECONDARY_TEMP_THRESH, },
3455 { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */
3456 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3457 { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */
3458 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3459 { PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */
3460 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3461 { PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */
3462 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3463 { PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */
3464 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3465 { PCI_DEVICE(0x1f40, 0x1202), /* Netac Technologies Co. NV3000 NVMe SSD */
3466 .driver_data = NVME_QUIRK_BOGUS_NID, },
3467 { PCI_DEVICE(0x1f40, 0x5236), /* Netac Technologies Co. NV7000 NVMe SSD */
3468 .driver_data = NVME_QUIRK_BOGUS_NID, },
3469 { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */
3470 .driver_data = NVME_QUIRK_BOGUS_NID, },
3471 { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */
3472 .driver_data = NVME_QUIRK_BOGUS_NID, },
3473 { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */
3474 .driver_data = NVME_QUIRK_BOGUS_NID, },
3475 { PCI_DEVICE(0x1e4B, 0x1602), /* MAXIO MAP1602 */
3476 .driver_data = NVME_QUIRK_BOGUS_NID, },
3477 { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */
3478 .driver_data = NVME_QUIRK_BOGUS_NID, },
3479 { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */
3480 .driver_data = NVME_QUIRK_BOGUS_NID, },
3481 { PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */
3482 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3483 { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */
3484 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3485 { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */
3486 .driver_data = NVME_QUIRK_BOGUS_NID, },
3487 { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */
3488 .driver_data = NVME_QUIRK_BOGUS_NID, },
3489 { PCI_DEVICE(0x1d97, 0x1d97), /* Lexar NM620 */
3490 .driver_data = NVME_QUIRK_BOGUS_NID, },
3491 { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */
3492 .driver_data = NVME_QUIRK_BOGUS_NID |
3493 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3494 { PCI_DEVICE(0x10ec, 0x5763), /* TEAMGROUP T-FORCE CARDEA ZERO Z330 SSD */
3495 .driver_data = NVME_QUIRK_BOGUS_NID, },
3496 { PCI_DEVICE(0x1e4b, 0x1602), /* HS-SSD-FUTURE 2048G */
3497 .driver_data = NVME_QUIRK_BOGUS_NID, },
3498 { PCI_DEVICE(0x10ec, 0x5765), /* TEAMGROUP MP33 2TB SSD */
3499 .driver_data = NVME_QUIRK_BOGUS_NID, },
3500 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3501 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3502 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3503 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3504 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3505 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3506 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3507 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3508 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3509 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3510 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3511 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3512 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3513 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3514 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3515 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3516 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3517 NVME_QUIRK_128_BYTES_SQES |
3518 NVME_QUIRK_SHARED_TAGS |
3519 NVME_QUIRK_SKIP_CID_GEN |
3520 NVME_QUIRK_IDENTIFY_CNS },
3521 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3522 { 0, }
3523 };
3524 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3525
3526 static struct pci_driver nvme_driver = {
3527 .name = "nvme",
3528 .id_table = nvme_id_table,
3529 .probe = nvme_probe,
3530 .remove = nvme_remove,
3531 .shutdown = nvme_shutdown,
3532 .driver = {
3533 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
3534 #ifdef CONFIG_PM_SLEEP
3535 .pm = &nvme_dev_pm_ops,
3536 #endif
3537 },
3538 .sriov_configure = pci_sriov_configure_simple,
3539 .err_handler = &nvme_err_handler,
3540 };
3541
nvme_init(void)3542 static int __init nvme_init(void)
3543 {
3544 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3545 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3546 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3547 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3548 BUILD_BUG_ON(NVME_MAX_SEGS > SGES_PER_PAGE);
3549 BUILD_BUG_ON(sizeof(struct scatterlist) * NVME_MAX_SEGS > PAGE_SIZE);
3550 BUILD_BUG_ON(nvme_pci_npages_prp() > NVME_MAX_NR_ALLOCATIONS);
3551
3552 return pci_register_driver(&nvme_driver);
3553 }
3554
nvme_exit(void)3555 static void __exit nvme_exit(void)
3556 {
3557 pci_unregister_driver(&nvme_driver);
3558 flush_workqueue(nvme_wq);
3559 }
3560
3561 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3562 MODULE_LICENSE("GPL");
3563 MODULE_VERSION("1.0");
3564 MODULE_DESCRIPTION("NVMe host PCIe transport driver");
3565 module_init(nvme_init);
3566 module_exit(nvme_exit);
3567