1 /* $NetBSD: nouveau_nvkm_engine_disp_piornv50.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $ */
2
3 /*
4 * Copyright 2012 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 */
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_disp_piornv50.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $");
28
29 #include "ior.h"
30 #include "head.h"
31
32 #include <subdev/i2c.h>
33 #include <subdev/timer.h>
34
35 static void
nv50_pior_clock(struct nvkm_ior * pior)36 nv50_pior_clock(struct nvkm_ior *pior)
37 {
38 struct nvkm_device *device = pior->disp->engine.subdev.device;
39 const u32 poff = nv50_ior_base(pior);
40 nvkm_mask(device, 0x614380 + poff, 0x00000707, 0x00000001);
41 }
42
43 static int
nv50_pior_dp_links(struct nvkm_ior * pior,struct nvkm_i2c_aux * aux)44 nv50_pior_dp_links(struct nvkm_ior *pior, struct nvkm_i2c_aux *aux)
45 {
46 int ret = nvkm_i2c_aux_lnk_ctl(aux, pior->dp.nr, pior->dp.bw,
47 pior->dp.ef);
48 if (ret)
49 return ret;
50 return 1;
51 }
52
53 static void
nv50_pior_power_wait(struct nvkm_device * device,u32 poff)54 nv50_pior_power_wait(struct nvkm_device *device, u32 poff)
55 {
56 nvkm_msec(device, 2000,
57 if (!(nvkm_rd32(device, 0x61e004 + poff) & 0x80000000))
58 break;
59 );
60 }
61
62 static void
nv50_pior_power(struct nvkm_ior * pior,bool normal,bool pu,bool data,bool vsync,bool hsync)63 nv50_pior_power(struct nvkm_ior *pior, bool normal, bool pu,
64 bool data, bool vsync, bool hsync)
65 {
66 struct nvkm_device *device = pior->disp->engine.subdev.device;
67 const u32 poff = nv50_ior_base(pior);
68 const u32 shift = normal ? 0 : 16;
69 const u32 state = 0x80000000 | (0x00000001 * !!pu) << shift;
70 const u32 field = 0x80000000 | (0x00000101 << shift);
71
72 nv50_pior_power_wait(device, poff);
73 nvkm_mask(device, 0x61e004 + poff, field, state);
74 nv50_pior_power_wait(device, poff);
75 }
76
77 void
nv50_pior_depth(struct nvkm_ior * ior,struct nvkm_ior_state * state,u32 ctrl)78 nv50_pior_depth(struct nvkm_ior *ior, struct nvkm_ior_state *state, u32 ctrl)
79 {
80 /* GF119 moves this information to per-head methods, which is
81 * a lot more convenient, and where our shared code expect it.
82 */
83 if (state->head && state == &ior->asy) {
84 struct nvkm_head *head =
85 nvkm_head_find(ior->disp, __ffs(state->head));
86 if (!WARN_ON(!head)) {
87 struct nvkm_head_state *state = &head->asy;
88 switch ((ctrl & 0x000f0000) >> 16) {
89 case 6: state->or.depth = 30; break;
90 case 5: state->or.depth = 24; break;
91 case 2: state->or.depth = 18; break;
92 case 0: state->or.depth = 18; break; /*XXX*/
93 default:
94 state->or.depth = 18;
95 WARN_ON(1);
96 break;
97 }
98 }
99 }
100 }
101
102 static void
nv50_pior_state(struct nvkm_ior * pior,struct nvkm_ior_state * state)103 nv50_pior_state(struct nvkm_ior *pior, struct nvkm_ior_state *state)
104 {
105 struct nvkm_device *device = pior->disp->engine.subdev.device;
106 const u32 coff = pior->id * 8 + (state == &pior->arm) * 4;
107 u32 ctrl = nvkm_rd32(device, 0x610b80 + coff);
108
109 state->proto_evo = (ctrl & 0x00000f00) >> 8;
110 state->rgdiv = 1;
111 switch (state->proto_evo) {
112 case 0: state->proto = TMDS; break;
113 default:
114 state->proto = UNKNOWN;
115 break;
116 }
117
118 state->head = ctrl & 0x00000003;
119 nv50_pior_depth(pior, state, ctrl);
120 }
121
122 static const struct nvkm_ior_func
123 nv50_pior = {
124 .state = nv50_pior_state,
125 .power = nv50_pior_power,
126 .clock = nv50_pior_clock,
127 .dp = {
128 .links = nv50_pior_dp_links,
129 },
130 };
131
132 int
nv50_pior_new(struct nvkm_disp * disp,int id)133 nv50_pior_new(struct nvkm_disp *disp, int id)
134 {
135 return nvkm_ior_new_(&nv50_pior, disp, PIOR, id);
136 }
137
138 int
nv50_pior_cnt(struct nvkm_disp * disp,unsigned long * pmask)139 nv50_pior_cnt(struct nvkm_disp *disp, unsigned long *pmask)
140 {
141 struct nvkm_device *device = disp->engine.subdev.device;
142 *pmask = (nvkm_rd32(device, 0x610184) & 0x70000000) >> 28;
143 return 3;
144 }
145