1 /** @file
2
3 Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
4 Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
5
6 SPDX-License-Identifier: BSD-2-Clause-Patent
7
8 **/
9
10 #include "ogma_config.h"
11 #include "ogma_internal.h"
12 #include "ogma_basic_access.h"
13 #include "ogma_misc_internal.h"
14
15 #include <Library/IoLib.h>
16
17 ogma_global_t ogma_global = {
18 OGMA_FALSE,
19 0,
20 NULL
21 };
22
23
24 static const ogma_uint32 hw_ver_reg_addr = OGMA_REG_ADDR_HW_VER;
25 static const ogma_uint32 mc_ver_reg_addr = OGMA_REG_ADDR_MC_VER;
26
27 static const ogma_uint32 desc_ring_irq_status_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
28 OGMA_REG_ADDR_NRM_TX_STATUS,
29 OGMA_REG_ADDR_NRM_RX_STATUS,
30 };
31
32 static const ogma_uint32 desc_ring_config_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
33 OGMA_REG_ADDR_NRM_TX_CONFIG,
34 OGMA_REG_ADDR_NRM_RX_CONFIG,
35
36 };
37
38
39 /* Internal function definition*/
40 #ifndef OGMA_CONFIG_DISABLE_CLK_CTRL
41 STATIC void ogma_set_clk_en_reg (
42 ogma_ctrl_t *ctrl_p
43 );
44 #endif /* OGMA_CONFIG_DISABLE_CLK_CTRL */
45 STATIC void ogma_global_init ( void);
46
47 STATIC ogma_err_t ogma_probe_hardware (
48 void *base_addr
49 );
50
51 STATIC void ogma_reset_hardware (
52 ogma_ctrl_t *ctrl_p
53 );
54
55 STATIC void ogma_set_microcode(
56 ogma_ctrl_t *ctrl_p,
57 const void *dma_hm_mc_addr,
58 ogma_uint32 dma_hm_mc_len,
59 const void *dma_mh_mc_addr,
60 ogma_uint32 dma_mh_mc_len,
61 const void *pktc_mc_addr,
62 ogma_uint32 pktc_mc_len
63 );
64
65 STATIC ogma_uint32 ogma_calc_pkt_ctrl_reg_param (
66 const ogma_pkt_ctrl_param_t *pkt_ctrl_param_p
67 );
68
69 STATIC void ogma_internal_terminate (
70 ogma_ctrl_t *ctrl_p
71 );
72
73 #ifdef OGMA_CONFIG_DISABLE_CLK_CTRL
74
75 #define ogma_set_clk_en_reg( ctrl_p)
76
77 #else /* OGMA_CONFIG_DISABLE_CLK_CTRL */
ogma_set_clk_en_reg(ogma_ctrl_t * ctrl_p)78 STATIC void ogma_set_clk_en_reg (
79 ogma_ctrl_t *ctrl_p
80 )
81 {
82 ogma_uint32 value = 0;
83
84 if ( ctrl_p->clk_ctrl.mac_req_num != 0) {
85 value |= OGMA_CLK_EN_REG_DOM_G;
86 }
87
88 ogma_write_reg( ctrl_p, OGMA_REG_ADDR_CLK_EN, value);
89 }
90 #endif /* OGMA_CONFIG_DISABLE_CLK_CTRL */
91
ogma_push_clk_req(ogma_ctrl_t * ctrl_p,ogma_uint32 domain)92 void ogma_push_clk_req (
93 ogma_ctrl_t *ctrl_p,
94 ogma_uint32 domain
95 )
96 {
97 pfdep_hard_lock_ctx_t clk_ctrl_hard_lock_ctx;
98
99 pfdep_acquire_hard_lock (
100 &ctrl_p->clk_ctrl_hard_lock,
101 &clk_ctrl_hard_lock_ctx);
102
103 if ( ( domain & OGMA_CLK_EN_REG_DOM_G) != 0) {
104 ++ctrl_p->clk_ctrl.mac_req_num;
105 }
106
107 ogma_set_clk_en_reg( ctrl_p);
108
109 pfdep_release_hard_lock(
110 &ctrl_p->clk_ctrl_hard_lock,
111 &clk_ctrl_hard_lock_ctx);
112 }
113
ogma_pop_clk_req(ogma_ctrl_t * ctrl_p,ogma_uint32 domain)114 void ogma_pop_clk_req(
115 ogma_ctrl_t *ctrl_p,
116 ogma_uint32 domain
117 )
118 {
119 pfdep_hard_lock_ctx_t clk_ctrl_hard_lock_ctx;
120
121 pfdep_acquire_hard_lock(
122 &ctrl_p->clk_ctrl_hard_lock,
123 &clk_ctrl_hard_lock_ctx);
124
125 if ( ( domain & OGMA_CLK_EN_REG_DOM_G) != 0) {
126 --ctrl_p->clk_ctrl.mac_req_num;
127 }
128
129 ogma_set_clk_en_reg( ctrl_p);
130
131 pfdep_release_hard_lock(
132 &ctrl_p->clk_ctrl_hard_lock,
133 &clk_ctrl_hard_lock_ctx);
134 }
135
136 /* Internal function */
ogma_global_init(void)137 STATIC void ogma_global_init ( void)
138 {
139 ogma_global.valid_flag = OGMA_TRUE;
140 }
141
ogma_probe_hardware(void * base_addr)142 STATIC ogma_err_t ogma_probe_hardware (
143 void *base_addr
144 )
145 {
146
147 ogma_uint32 value;
148
149 /* Read HW_VER Register */
150 value = pfdep_iomem_read((void *)
151 ((pfdep_cpu_addr_t)base_addr +
152 (OGMA_REG_ADDR_HW_VER << 2)));
153
154 if ( value != OGMA_VER_NETSEC) {
155 pfdep_print(PFDEP_DEBUG_LEVEL_WARNING,
156 "Hardware version check warning. Actual:0x%08x, Expected:0x%08x\n",
157 (unsigned int)value,
158 (unsigned int)OGMA_VER_NETSEC);
159 }
160
161 if ( OGMA_VER_MAJOR_NUM(value) != OGMA_VER_MAJOR_NUM(OGMA_VER_NETSEC) ) {
162 pfdep_print(PFDEP_DEBUG_LEVEL_FATAL,
163 "Hardware Major version check failed. Actual:0x%08x, Expected:0x%08x\n",
164 (unsigned int)OGMA_VER_MAJOR_NUM(value),
165 (unsigned int)OGMA_VER_MAJOR_NUM(OGMA_VER_NETSEC) );
166 return OGMA_ERR_NOTAVAIL;
167 }
168
169 /* Print hardware version information. */
170 pfdep_print(PFDEP_DEBUG_LEVEL_NOTICE,
171 "NETSEC found. Hardware version: %08x\n",
172 value);
173
174
175 return OGMA_ERR_OK;
176 }
177
ogma_reset_hardware(ogma_ctrl_t * ctrl_p)178 STATIC void ogma_reset_hardware (
179 ogma_ctrl_t *ctrl_p
180 )
181 {
182 ogma_write_reg( ctrl_p,
183 OGMA_REG_ADDR_CLK_EN,
184 OGMA_CLK_EN_REG_DOM_ALL);
185
186
187 /*
188 * Stop dma engines if cores are enabled
189 */
190 if (ogma_read_reg(ctrl_p, OGMA_REG_ADDR_DIS_CORE) == 0) {
191
192 ogma_write_reg( ctrl_p,
193 OGMA_REG_ADDR_DMA_HM_CTRL,
194 OGMA_DMA_CTRL_REG_STOP);
195
196 ogma_write_reg( ctrl_p,
197 OGMA_REG_ADDR_DMA_MH_CTRL,
198 OGMA_DMA_CTRL_REG_STOP);
199
200 while ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_DMA_HM_CTRL)
201 & OGMA_DMA_CTRL_REG_STOP) != 0) {
202 ;
203 }
204
205 while ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_DMA_MH_CTRL)
206 & OGMA_DMA_CTRL_REG_STOP) != 0) {
207 ;
208 }
209 }
210
211 if ( ctrl_p->param.use_gmac_flag) {
212
213 /* Reset F_GMAC4MT */
214 ogma_set_mac_reg( ctrl_p,
215 OGMA_GMAC_REG_ADDR_BMR,
216 OGMA_GMAC_BMR_REG_RESET);
217
218 }
219
220 ogma_write_reg( ctrl_p,
221 OGMA_REG_ADDR_SOFT_RST,
222 OGMA_SOFT_RST_REG_RESET);
223
224 ogma_write_reg( ctrl_p,
225 OGMA_REG_ADDR_SOFT_RST,
226 OGMA_SOFT_RST_REG_RUN);
227
228 ogma_write_reg( ctrl_p,
229 OGMA_REG_ADDR_COM_INIT,
230 OGMA_COM_INIT_REG_ALL);
231
232 while (ogma_read_reg(ctrl_p, OGMA_REG_ADDR_COM_INIT) != 0) {
233 ;
234 }
235
236 if ( ctrl_p->param.use_gmac_flag) {
237
238
239 /* MAC desc init */
240 ogma_write_reg( ctrl_p,
241 OGMA_REG_ADDR_MAC_DESC_INIT,
242 OGMA_MAC_DESC_INIT_REG_INIT);
243
244 /* Wait MAC desc init done */
245 while ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_DESC_INIT)
246 & OGMA_MAC_DESC_INIT_REG_INIT) != 0) {
247 ;
248 }
249
250
251 /* set MAC_INTF_SEL */
252 ogma_write_reg( ctrl_p,
253 OGMA_REG_ADDR_MAC_INTF_SEL,
254 ctrl_p->param.gmac_config.phy_interface);
255
256
257 }
258 }
259
260 #define OGMA_ROUND_UP(numerator,denominator) (((numerator) + (denominator)) - 1 / (denominator))
261
ogma_set_microcode(ogma_ctrl_t * ctrl_p,const void * dma_hm_mc_addr,ogma_uint32 dma_hm_mc_len,const void * dma_mh_mc_addr,ogma_uint32 dma_mh_mc_len,const void * pktc_mc_addr,ogma_uint32 pktc_mc_len)262 STATIC void ogma_set_microcode (
263 ogma_ctrl_t *ctrl_p,
264 const void *dma_hm_mc_addr,
265 ogma_uint32 dma_hm_mc_len,
266 const void *dma_mh_mc_addr,
267 ogma_uint32 dma_mh_mc_len,
268 const void *pktc_mc_addr,
269 ogma_uint32 pktc_mc_len
270 )
271 {
272 ogma_uint i;
273
274 const UINT32 *dmac_hm_cmd_data = (const UINT32 *)dma_hm_mc_addr;
275 const UINT32 *dmac_mh_cmd_data = (const UINT32 *)dma_mh_mc_addr;
276 const UINT32 *core_cmd_data = (const UINT32 *)pktc_mc_addr;
277
278 /* Loads microcodes to microengines. */
279 for( i = 0; i < dma_hm_mc_len; i++) {
280 UINT32 data = MmioRead32((UINTN)dmac_hm_cmd_data);
281 ogma_write_reg( ctrl_p,
282 OGMA_REG_ADDR_DMAC_HM_CMD_BUF,
283 data );
284 dmac_hm_cmd_data++;
285 }
286
287 for( i = 0; i < dma_mh_mc_len; i++) {
288 UINT32 data = MmioRead32((UINTN)dmac_mh_cmd_data);
289 ogma_write_reg( ctrl_p,
290 OGMA_REG_ADDR_DMAC_MH_CMD_BUF,
291 data );
292 dmac_mh_cmd_data++;
293 }
294
295 for( i = 0; i < pktc_mc_len; i++) {
296 UINT32 data = MmioRead32((UINTN)core_cmd_data);
297 ogma_write_reg( ctrl_p,
298 OGMA_REG_ADDR_PKTC_CMD_BUF,
299 data );
300 core_cmd_data++;
301 }
302
303 }
304
ogma_calc_pkt_ctrl_reg_param(const ogma_pkt_ctrl_param_t * pkt_ctrl_param_p)305 STATIC ogma_uint32 ogma_calc_pkt_ctrl_reg_param (
306 const ogma_pkt_ctrl_param_t *pkt_ctrl_param_p
307 )
308 {
309 ogma_uint32 param = 0;
310
311 if ( pkt_ctrl_param_p->log_chksum_er_flag) {
312 param |= OGMA_PKT_CTRL_REG_LOG_CHKSUM_ER;
313 }
314
315 if ( pkt_ctrl_param_p->log_hd_imcomplete_flag) {
316 param |= OGMA_PKT_CTRL_REG_LOG_HD_INCOMPLETE;
317 }
318
319 if ( pkt_ctrl_param_p->log_hd_er_flag) {
320 param |= OGMA_PKT_CTRL_REG_LOG_HD_ER;
321 }
322
323 if ( pkt_ctrl_param_p->drp_no_match_flag) {
324 param |= OGMA_PKT_CTRL_REG_DRP_NO_MATCH;
325 }
326
327 return param;
328 }
329
330 STATIC
331 void
ogma_pre_init_microengine(ogma_handle_t ogma_handle)332 ogma_pre_init_microengine (
333 ogma_handle_t ogma_handle
334 )
335 {
336 UINT16 Data;
337
338 /* Remove dormant settings */
339 Data = ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) &
340 ~((1U << OGMA_PHY_CONTROL_REG_POWER_DOWN) |
341 (1U << OGMA_PHY_CONTROL_REG_ISOLATE));
342
343 ogma_set_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL, Data);
344
345 while ((ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) &
346 ((1U << OGMA_PHY_CONTROL_REG_POWER_DOWN) |
347 (1U << OGMA_PHY_CONTROL_REG_ISOLATE))) != 0);
348
349 /* Put phy in loopback mode to guarantee RXCLK input */
350 Data |= (1U << OGMA_PHY_CONTROL_REG_LOOPBACK);
351
352 ogma_set_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL, Data);
353
354 while ((ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) &
355 (1U << OGMA_PHY_CONTROL_REG_LOOPBACK)) == 0);
356 }
357
358 STATIC
359 void
ogma_post_init_microengine(IN ogma_handle_t ogma_handle)360 ogma_post_init_microengine (
361 IN ogma_handle_t ogma_handle
362 )
363 {
364 UINT16 Data;
365
366 /* Get phy back to normal operation */
367 Data = ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) &
368 ~(1U << OGMA_PHY_CONTROL_REG_LOOPBACK);
369
370 ogma_set_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL, Data);
371
372 while ((ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) &
373 (1U << OGMA_PHY_CONTROL_REG_LOOPBACK)) != 0);
374
375 Data |= (1U << OGMA_PHY_CONTROL_REG_RESET);
376
377 /* Apply software reset */
378 ogma_set_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL, Data);
379
380 while ((ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) &
381 (1U << OGMA_PHY_CONTROL_REG_RESET)) != 0);
382 }
383
ogma_init(void * base_addr,pfdep_dev_handle_t dev_handle,const ogma_param_t * param_p,const void * dma_hm_mc_addr,ogma_uint32 dma_hm_mc_len,const void * dma_mh_mc_addr,ogma_uint32 dma_mh_mc_len,const void * pktc_mc_addr,ogma_uint32 pktc_mc_len,ogma_handle_t * ogma_handle_p)384 ogma_err_t ogma_init (
385 void *base_addr,
386 pfdep_dev_handle_t dev_handle,
387 const ogma_param_t *param_p,
388 const void *dma_hm_mc_addr,
389 ogma_uint32 dma_hm_mc_len,
390 const void *dma_mh_mc_addr,
391 ogma_uint32 dma_mh_mc_len,
392 const void *pktc_mc_addr,
393 ogma_uint32 pktc_mc_len,
394 ogma_handle_t *ogma_handle_p
395 )
396 {
397 ogma_int i;
398 ogma_uint32 domain = 0, value;
399 ogma_err_t ogma_err;
400 ogma_ctrl_t *ctrl_p = NULL;
401
402 ogma_bool inten_reg_hard_lock_init_flag = OGMA_FALSE;
403 ogma_bool clk_ctrl_hard_lock_init_flag = OGMA_FALSE;
404
405 ogma_bool all_lock_init_done_flag = OGMA_FALSE;
406
407 pfdep_err_t pfdep_err;
408
409 if ( ( param_p == NULL) ||
410 ( ogma_handle_p == NULL) ) {
411 return OGMA_ERR_PARAM;
412 }
413
414 if ( ogma_global.list_entry_num + 1 > OGMA_INSTANCE_NUM_MAX) {
415 return OGMA_ERR_INVALID;
416 }
417
418 if ((! param_p->desc_ring_param[OGMA_DESC_RING_ID_NRM_TX].valid_flag) &&
419 (! param_p->desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].valid_flag)) {
420 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
421 "An error occurred at ogma_init.\n"
422 "Please set invalid packet desc_ring_param valid_flag.\n");
423 return OGMA_ERR_DATA;
424 }
425
426 if ( param_p->use_gmac_flag) {
427 if ( ( param_p->gmac_config.phy_interface !=
428 OGMA_PHY_INTERFACE_GMII) &&
429 ( param_p->gmac_config.phy_interface !=
430 OGMA_PHY_INTERFACE_RGMII) &&
431 ( param_p->gmac_config.phy_interface !=
432 OGMA_PHY_INTERFACE_RMII) ) {
433 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
434 "An error occurred at ogma_init.\n"
435 "Please set phy_interface to valid value.\n");
436 return OGMA_ERR_DATA;
437 }
438 } else {
439 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
440 "An error occurred at ogma_init.\n"
441 "Please set use_gmac_flag OGMA_TRUE.\n");
442 return OGMA_ERR_DATA;
443 }
444
445 if ( param_p->phy_addr >= 32) {
446 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
447 "Error: phy_addr out of range\n");
448 return OGMA_ERR_DATA;
449 }
450
451 ogma_err = ogma_probe_hardware( base_addr);
452
453 if ( ogma_err != OGMA_ERR_OK) {
454 return ogma_err;
455 }
456
457 if ( !ogma_global.valid_flag) {
458 ogma_global_init();
459 }
460
461 if ( ( ctrl_p = pfdep_malloc( sizeof( ogma_ctrl_t) ) ) == NULL) {
462 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
463 "An error occurred at ogma_init.\n"
464 "Failed to ogma_handle memory allocation.\n");
465 return OGMA_ERR_ALLOC;
466 }
467
468 pfdep_memset( ctrl_p, 0, sizeof( ogma_ctrl_t) );
469
470 ctrl_p->base_addr = base_addr;
471
472 ctrl_p->dev_handle = dev_handle;
473
474 pfdep_memcpy( ( void *)&ctrl_p->param,
475 ( void *)param_p,
476 sizeof( ogma_param_t) );
477
478 /* Initialize hardware lock */
479 pfdep_err = pfdep_init_hard_lock( &ctrl_p->inten_reg_hard_lock);
480 if ( pfdep_err != PFDEP_ERR_OK) {
481 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
482 "An error occurred at ogma_init.\n"
483 "Failed to inten_reg_hard_lock's initialization.\n");
484 ogma_err = OGMA_ERR_ALLOC;
485 goto err;
486 }
487 inten_reg_hard_lock_init_flag = OGMA_TRUE;
488
489 pfdep_err = pfdep_init_hard_lock( &ctrl_p->clk_ctrl_hard_lock);
490 if ( pfdep_err != PFDEP_ERR_OK) {
491 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
492 "An error occurred at ogma_init.\n"
493 "Failed to clk_ctrl_hard_lock's initialization.\n");
494 ogma_err = OGMA_ERR_ALLOC;
495 goto err;
496 }
497 clk_ctrl_hard_lock_init_flag = OGMA_TRUE;
498
499 all_lock_init_done_flag = OGMA_TRUE;
500
501 pfdep_err = pfdep_dma_malloc( dev_handle,
502 OGMA_DUMMY_DESC_ENTRY_LEN,
503 &ctrl_p->dummy_desc_entry_addr,
504 &ctrl_p->dummy_desc_entry_phys_addr);
505
506 if ( pfdep_err != PFDEP_ERR_OK) {
507 ogma_err = OGMA_ERR_ALLOC;
508 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
509 "An error occurred at ogma_init.\n"
510 "Failed to dummy_desc_entry's memory allocation.\n");
511 goto err;
512 }
513
514 /* clear dummy desc entry */
515 pfdep_memset( ctrl_p->dummy_desc_entry_addr,
516 0,
517 OGMA_DUMMY_DESC_ENTRY_LEN);
518
519 ogma_reset_hardware( ctrl_p);
520
521 if ( param_p->use_gmac_flag) {
522 domain |= OGMA_CLK_EN_REG_DOM_G;
523 }
524
525 ogma_push_clk_req( ctrl_p, domain);
526
527 /* set PKT_CTRL */
528 value = ogma_calc_pkt_ctrl_reg_param( ¶m_p->pkt_ctrl_param);
529
530 ogma_write_reg( ctrl_p,
531 OGMA_REG_ADDR_PKT_CTRL,
532 value);
533
534 if ( param_p->use_jumbo_pkt_flag) {
535
536 ctrl_p->rx_pkt_buf_len = OGMA_RX_JUMBO_PKT_BUF_LEN;
537
538 value = ogma_read_reg( ctrl_p,
539 OGMA_REG_ADDR_PKT_CTRL);
540
541 value |= OGMA_PKT_CTRL_REG_EN_JUMBO;
542
543 ogma_write_reg( ctrl_p,
544 OGMA_REG_ADDR_PKT_CTRL,
545 value);
546 } else {
547
548 ctrl_p->rx_pkt_buf_len = OGMA_RX_PKT_BUF_LEN;
549
550 }
551
552 /* set pkt desc ring config */
553 for ( i = 0; i <= OGMA_DESC_RING_ID_MAX; i++) {
554 if ( ctrl_p->param.desc_ring_param[i].valid_flag) {
555 value =
556 ( ctrl_p->param.desc_ring_param[i].tmr_mode_flag <<
557 OGMA_REG_DESC_RING_CONFIG_TMR_MODE) |
558 ( ctrl_p->param.desc_ring_param[i].little_endian_flag <<
559 OGMA_REG_DESC_RING_CONFIG_DAT_ENDIAN) ;
560
561 ogma_write_reg( ctrl_p,
562 desc_ring_config_reg_addr[i],
563 value);
564
565 }
566 }
567
568 /* set microengines */
569 ogma_set_microcode(ctrl_p,
570 dma_hm_mc_addr,
571 dma_hm_mc_len,
572 dma_mh_mc_addr,
573 dma_mh_mc_len,
574 pktc_mc_addr,
575 pktc_mc_len);
576
577 /* alloc desc_ring*/
578 for( i = 0; i <= OGMA_DESC_RING_ID_MAX; i++) {
579 ogma_err = ogma_alloc_desc_ring( ctrl_p, (ogma_desc_ring_id_t)i);
580 if ( ogma_err != OGMA_ERR_OK) {
581 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
582 "An error occurred at ogma_init.\n"
583 "Failed to ring id NO.%d memory allocation.\n",
584 i);
585 goto err;
586 }
587 }
588
589 if ( param_p->desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].valid_flag) {
590 if ( ( ogma_err = ogma_setup_rx_desc_ring(
591 ctrl_p,
592 &ctrl_p->desc_ring[OGMA_DESC_RING_ID_NRM_RX] ) )
593 != OGMA_ERR_OK) {
594 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
595 "An error occurred at ogma_init.\n"
596 "Failed to NRM_RX packet memory allocation.\n");
597 goto err;
598 }
599 }
600
601 /* microengines need domain G */
602 ogma_push_clk_req( ctrl_p, OGMA_CLK_EN_REG_DOM_G);
603
604 /* set DMA tmr ctrl*/
605 ogma_write_reg( ctrl_p, OGMA_REG_ADDR_DMA_TMR_CTRL,
606 ( ogma_uint32)( ( OGMA_CONFIG_CLK_HZ / OGMA_CLK_MHZ) - 1) );
607
608 /*
609 * Do pre-initialization tasks for microengine
610 *
611 * In particular, we put phy in loopback mode
612 * in order to make sure RXCLK keeps provided to mac
613 * irrespective of phy link status,
614 * which is required for microengine intialization.
615 * This will be disabled once microengine initialization complete.
616 */
617 ogma_pre_init_microengine (ctrl_p);
618
619 /* start microengines */
620 ogma_write_reg( ctrl_p, OGMA_REG_ADDR_DIS_CORE, 0);
621
622 if ( pfdep_msleep(1) != PFDEP_ERR_OK) {
623 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
624 "An error occurred at ogma_init.\n"
625 "Failed to waiting for microcode initialize end.\n");
626 ogma_err = OGMA_ERR_INTERRUPT;
627 goto err;
628 }
629
630 /* check microcode load end & start core */
631 value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_STATUS);
632
633 if ( ( value & OGMA_TOP_IRQ_REG_ME_START) == 0) {
634 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
635 "An error occurred at ogma_init.\n"
636 "Failed to microcode loading.\n");
637 ogma_err = OGMA_ERR_INVALID;
638 goto err;
639 }
640
641 /*
642 * Do post-initialization tasks for microengine
643 *
644 * We put phy in normal mode and apply reset.
645 */
646 ogma_post_init_microengine (ctrl_p);
647
648 /* clear microcode load end status */
649 ogma_write_reg( ctrl_p, OGMA_REG_ADDR_TOP_STATUS,
650 OGMA_TOP_IRQ_REG_ME_START);
651
652 ogma_pop_clk_req( ctrl_p, OGMA_CLK_EN_REG_DOM_G);
653
654 ctrl_p->core_enabled_flag = OGMA_TRUE;
655
656 ctrl_p->next_p = ogma_global.list_head_p;
657
658 ogma_global.list_head_p = ctrl_p;
659
660 ++ogma_global.list_entry_num;
661
662 *ogma_handle_p = ctrl_p;
663
664 #if 1
665 {
666
667 #define OGMA_PKT_CTRL_REG_MODE_TAIKI (1UL << 28)
668 #define OGMA_DMA_MH_CTRL_REG_MODE_TRANS (1UL << 20)
669 #define OGMA_TOP_IRQ_REG_MODE_TRANS_COMP (1UL << 4)
670 #define OGMA_MODE_TRANS_COMP_IRQ_T2N (1UL << 19)
671
672 /* Read Pkt ctrl register */
673 value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_CTRL);
674 value |= OGMA_PKT_CTRL_REG_MODE_TAIKI;
675
676 /* change to noromal mode */
677 ogma_write_reg( ctrl_p,
678 OGMA_REG_ADDR_DMA_MH_CTRL,
679 OGMA_DMA_MH_CTRL_REG_MODE_TRANS);
680
681 ogma_write_reg( ctrl_p,
682 OGMA_REG_ADDR_PKT_CTRL,
683 value);
684
685 while ((ogma_read_reg(ctrl_p, OGMA_REG_ADDR_MODE_TRANS_COMP_STATUS) &
686 OGMA_MODE_TRANS_COMP_IRQ_T2N) == 0) {
687 ;
688 }
689
690 }
691 #endif
692
693 /* Print microcode version information. */
694 pfdep_print(PFDEP_DEBUG_LEVEL_NOTICE,
695 "Microcode version: %08x\n",
696 ogma_read_reg( ctrl_p,
697 mc_ver_reg_addr) );
698
699 return OGMA_ERR_OK;
700
701 err:
702 if ( !all_lock_init_done_flag) {
703
704
705 if ( clk_ctrl_hard_lock_init_flag) {
706 pfdep_uninit_hard_lock( &ctrl_p->clk_ctrl_hard_lock);
707 }
708
709 if ( inten_reg_hard_lock_init_flag) {
710 pfdep_uninit_hard_lock( &ctrl_p->inten_reg_hard_lock);
711 }
712
713 } else {
714
715 ogma_internal_terminate( ctrl_p);
716
717 }
718
719 pfdep_free( ctrl_p);
720
721 return ogma_err;
722 }
723
ogma_internal_terminate(ogma_ctrl_t * ctrl_p)724 STATIC void ogma_internal_terminate (
725 ogma_ctrl_t *ctrl_p
726 )
727 {
728 ogma_int i;
729
730 ogma_reset_hardware( ctrl_p);
731
732 /* free desc_ring */
733 for( i = 0; i <= OGMA_DESC_RING_ID_MAX; i++) {
734 ogma_free_desc_ring( ctrl_p, &ctrl_p->desc_ring[i] );
735 }
736
737 if ( ctrl_p->dummy_desc_entry_addr != NULL) {
738 pfdep_dma_free( ctrl_p->dev_handle,
739 OGMA_DUMMY_DESC_ENTRY_LEN,
740 ctrl_p->dummy_desc_entry_addr,
741 ctrl_p->dummy_desc_entry_phys_addr);
742 }
743
744 pfdep_uninit_hard_lock ( &ctrl_p->inten_reg_hard_lock);
745
746
747 pfdep_uninit_hard_lock ( &ctrl_p->clk_ctrl_hard_lock);
748
749 }
750
ogma_terminate(ogma_handle_t ogma_handle)751 void ogma_terminate (
752 ogma_handle_t ogma_handle
753 )
754 {
755
756 ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
757 ogma_ctrl_t *tmp_ctrl_p = NULL, *old_tmp_ctrl_p = NULL;
758 ogma_uint32 domain = 0;
759
760 if ( ( ctrl_p == NULL) ||
761 ( ogma_global.list_entry_num == 0) ) {
762 return;
763 }
764
765 pfdep_assert( ogma_global.list_head_p != NULL);
766
767 if ( ctrl_p->param.use_gmac_flag) {
768 domain |= OGMA_CLK_EN_REG_DOM_G;
769 }
770
771 /* pop domain clock */
772 ogma_pop_clk_req( ctrl_p, domain);
773
774 tmp_ctrl_p = ogma_global.list_head_p;
775
776 while(1) {
777 if ( tmp_ctrl_p == NULL) {
778 /* Could not found ctrl_p specified from the list */
779 return;
780 }
781 if ( ctrl_p == tmp_ctrl_p) {
782 if ( old_tmp_ctrl_p != NULL) {
783 old_tmp_ctrl_p->next_p = ctrl_p->next_p;
784 } else {
785 ogma_global.list_head_p = ctrl_p->next_p;
786 }
787 break;
788 }
789 old_tmp_ctrl_p = tmp_ctrl_p;
790 tmp_ctrl_p = tmp_ctrl_p->next_p;
791 }
792
793 ogma_internal_terminate( ctrl_p);
794
795 --ogma_global.list_entry_num;
796
797 pfdep_free( ctrl_p);
798 return;
799 }
800
ogma_enable_top_irq(ogma_handle_t ogma_handle,ogma_uint32 irq_factor)801 ogma_err_t ogma_enable_top_irq (
802 ogma_handle_t ogma_handle,
803 ogma_uint32 irq_factor
804 )
805 {
806 ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
807
808
809 if ( ctrl_p == NULL) {
810 return OGMA_ERR_PARAM;
811 }
812
813 /* set irq_factor*/
814 ogma_write_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN_SET, irq_factor);
815
816 return OGMA_ERR_OK;
817 }
818
ogma_disable_top_irq(ogma_handle_t ogma_handle,ogma_uint32 irq_factor)819 ogma_err_t ogma_disable_top_irq (
820 ogma_handle_t ogma_handle,
821 ogma_uint32 irq_factor
822 )
823 {
824 ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
825
826 if ( ctrl_p == NULL) {
827 return OGMA_ERR_PARAM;
828 }
829
830 /* clear irq_factor*/
831 ogma_write_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN_CLR, irq_factor);
832
833 return OGMA_ERR_OK;
834 }
835
ogma_enable_desc_ring_irq(ogma_handle_t ogma_handle,ogma_desc_ring_id_t ring_id,ogma_uint32 irq_factor)836 ogma_err_t ogma_enable_desc_ring_irq (
837 ogma_handle_t ogma_handle,
838 ogma_desc_ring_id_t ring_id,
839 ogma_uint32 irq_factor
840 )
841 {
842 ogma_err_t ogma_err = OGMA_ERR_OK;
843 ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
844 ogma_desc_ring_t *desc_ring_p;
845
846 pfdep_err_t pfdep_err;
847 pfdep_soft_lock_ctx_t soft_lock_ctx;
848
849 if ( ctrl_p == NULL) {
850 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
851 "An error occurred at ogma_enable_desc_ring_irq.\n"
852 "Please set valid ogma_handle.\n");
853 return OGMA_ERR_PARAM;
854 }
855
856 if ( ring_id > OGMA_DESC_RING_ID_MAX) {
857 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
858 "An error occurred at ogma_enable_desc_ring_irq.\n"
859 "Please select ring id number between 0 and %d.\n",
860 OGMA_DESC_RING_ID_MAX);
861 return OGMA_ERR_PARAM;
862 }
863
864 if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
865 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
866 "An error occurred at ogma_enable_desc_ring_irq.\n"
867 "Please select valid desc ring.\n");
868 return OGMA_ERR_NOTAVAIL;
869 }
870
871 desc_ring_p = &ctrl_p->desc_ring[ring_id];
872
873 /* get soft lock */
874 pfdep_err = pfdep_acquire_soft_lock (
875 &desc_ring_p->soft_lock,
876 &soft_lock_ctx);
877
878 if ( pfdep_err != PFDEP_ERR_OK) {
879 return OGMA_ERR_INTERRUPT;
880 }
881
882 if ( !desc_ring_p->running_flag) {
883 pfdep_release_soft_lock( &desc_ring_p->soft_lock,
884 &soft_lock_ctx);
885 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
886 "An error occurred at ogma_enable_desc_ring_irq.\n"
887 "Please select running desc ring.\n");
888 return OGMA_ERR_NOTAVAIL;
889 }
890
891 /* set irq_factor*/
892 ogma_write_reg( ctrl_p,
893 desc_ring_irq_inten_set_reg_addr[ring_id],
894 irq_factor);
895
896 /* free soft_lock*/
897 pfdep_release_soft_lock( &desc_ring_p->soft_lock,
898 &soft_lock_ctx);
899 return ogma_err;
900 }
901
ogma_disable_desc_ring_irq(ogma_handle_t ogma_handle,ogma_desc_ring_id_t ring_id,ogma_uint32 irq_factor)902 ogma_err_t ogma_disable_desc_ring_irq (
903 ogma_handle_t ogma_handle,
904 ogma_desc_ring_id_t ring_id,
905 ogma_uint32 irq_factor
906 )
907 {
908 ogma_err_t ogma_err = OGMA_ERR_OK;
909 ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
910
911 if ( ctrl_p == NULL) {
912 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
913 "An error occurred at ogma_disable_desc_ring_irq.\n"
914 "Please set valid ogma_handle.\n");
915 return OGMA_ERR_PARAM;
916 }
917
918 if ( ring_id > OGMA_DESC_RING_ID_MAX) {
919 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
920 "An error occurred at ogma_disable_desc_ring_irq.\n"
921 "Please select ring id number between 0 and %d.\n",
922 OGMA_DESC_RING_ID_MAX);
923 return OGMA_ERR_PARAM;
924 }
925
926 if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
927 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
928 "An error occurred at ogma_disable_desc_ring_irq.\n"
929 "Please select valid desc ring.\n");
930 return OGMA_ERR_NOTAVAIL;
931 }
932
933 /* Clear irq factor*/
934 ogma_write_reg( ctrl_p,
935 desc_ring_irq_inten_clr_reg_addr[ring_id],
936 irq_factor);
937
938 return ogma_err;
939 }
940
ogma_enable_pkt_irq(ogma_handle_t ogma_handle,ogma_uint32 irq_factor)941 ogma_err_t ogma_enable_pkt_irq (
942 ogma_handle_t ogma_handle,
943 ogma_uint32 irq_factor
944 )
945 {
946 ogma_err_t ogma_err = OGMA_ERR_OK;
947 ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
948
949 if ( ctrl_p == NULL) {
950 return OGMA_ERR_PARAM;
951 }
952
953 /* set irq_factor*/
954 ogma_write_reg( ctrl_p, OGMA_REG_ADDR_PKT_INTEN_SET,
955 ( irq_factor & OGMA_PKT_IRQ_ALL) );
956
957 return ogma_err;
958 }
959
ogma_disable_pkt_irq(ogma_handle_t ogma_handle,ogma_uint32 irq_factor)960 ogma_err_t ogma_disable_pkt_irq (
961 ogma_handle_t ogma_handle,
962 ogma_uint32 irq_factor
963 )
964 {
965 ogma_err_t ogma_err = OGMA_ERR_OK;
966 ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
967
968 if ( ctrl_p == NULL) {
969 return OGMA_ERR_PARAM;
970 }
971
972 /* clear irq_factor*/
973 ogma_write_reg( ctrl_p,
974 OGMA_REG_ADDR_PKT_INTEN_CLR,
975 ( irq_factor & OGMA_PKT_IRQ_ALL) );
976
977 return ogma_err;
978 }
979
980
ogma_get_top_irq_enable(ogma_handle_t ogma_handle)981 ogma_uint32 ogma_get_top_irq_enable (
982 ogma_handle_t ogma_handle
983 )
984 {
985 ogma_uint32 value;
986 ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
987
988 if ( ctrl_p == NULL) {
989 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
990 "An error occurred at ogma_get_top_irq_enable.\n"
991 "Please set valid ogma_handle.\n");
992 return 0;
993 }
994
995 value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN);
996
997 return value;
998
999 }
1000
1001
ogma_get_top_irq_status(ogma_handle_t ogma_handle,ogma_bool mask_flag)1002 ogma_uint32 ogma_get_top_irq_status (
1003 ogma_handle_t ogma_handle,
1004 ogma_bool mask_flag
1005 )
1006 {
1007 ogma_uint32 value;
1008 ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
1009
1010 if ( ctrl_p == NULL) {
1011 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
1012 "An error occurred at ogma_get_top_irq_status.\n"
1013 "Please set valid ogma_handle.\n");
1014 return 0;
1015 }
1016
1017 value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_STATUS);
1018
1019 if ( mask_flag) {
1020 value &= ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN);
1021 }
1022
1023 return value;
1024 }
1025
ogma_clear_top_irq_status(ogma_handle_t ogma_handle,ogma_uint32 value)1026 ogma_err_t ogma_clear_top_irq_status (
1027 ogma_handle_t ogma_handle,
1028 ogma_uint32 value
1029 )
1030 {
1031 ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
1032
1033 if ( ctrl_p == NULL) {
1034 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
1035 "An error occurred at ogma_clear_top_irq_status.\n"
1036 "Please set valid ogma_handle.\n");
1037 return OGMA_ERR_PARAM;
1038 }
1039
1040 /* Write clear irq top status */
1041 ogma_write_reg( ctrl_p,
1042 OGMA_REG_ADDR_TOP_STATUS,
1043
1044 ( value & OGMA_TOP_IRQ_REG_ME_START) );
1045
1046 return OGMA_ERR_OK;
1047 }
1048
ogma_get_desc_ring_irq_enable(ogma_handle_t ogma_handle,ogma_desc_ring_id_t ring_id)1049 ogma_uint32 ogma_get_desc_ring_irq_enable (
1050 ogma_handle_t ogma_handle,
1051 ogma_desc_ring_id_t ring_id
1052 )
1053 {
1054 ogma_uint32 value;
1055 ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
1056
1057 if ( ctrl_p == NULL) {
1058 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
1059 "An error occurred at ogma_get_desc_ring_irq_enable.\n"
1060 "Please set valid ogma_handle.\n");
1061 return 0;
1062 }
1063
1064 if ( ring_id > OGMA_DESC_RING_ID_MAX) {
1065 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
1066 "An error occurred at ogma_get_desc_ring_irq_enable.\n"
1067 "Please select ring id number between 0 and %d.\n",
1068 OGMA_DESC_RING_ID_MAX);
1069 return 0;
1070 }
1071
1072 if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
1073 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
1074 "An error occurred at ogma_get_desc_ring_irq_enable.\n"
1075 "Please select valid desc ring.\n");
1076 return 0;
1077 }
1078
1079 value = ogma_read_reg( ctrl_p,
1080 desc_ring_irq_inten_reg_addr[ring_id] );
1081
1082 return value;
1083 }
1084
1085
ogma_get_desc_ring_irq_status(ogma_handle_t ogma_handle,ogma_desc_ring_id_t ring_id,ogma_bool mask_flag)1086 ogma_uint32 ogma_get_desc_ring_irq_status (
1087 ogma_handle_t ogma_handle,
1088 ogma_desc_ring_id_t ring_id,
1089 ogma_bool mask_flag
1090 )
1091 {
1092 ogma_uint32 value;
1093 ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
1094
1095 if ( ctrl_p == NULL) {
1096 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
1097 "An error occurred at ogma_get_desc_ring_irq_status.\n"
1098 "Please set valid ogma_handle.\n");
1099 return 0;
1100 }
1101
1102 if ( ring_id > OGMA_DESC_RING_ID_MAX) {
1103 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
1104 "An error occurred at ogma_get_desc_ring_irq_status.\n"
1105 "Please select ring id number between 0 and %d.\n",
1106 OGMA_DESC_RING_ID_MAX);
1107 return 0;
1108 }
1109
1110 if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
1111 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
1112 "An error occurred at ogma_get_desc_ring_irq_status.\n"
1113 "Please select valid desc ring.\n");
1114 return 0;
1115 }
1116
1117 value = ogma_read_reg( ctrl_p,
1118 desc_ring_irq_status_reg_addr[ring_id] );
1119
1120 if ( mask_flag) {
1121 value &= ogma_read_reg( ctrl_p,
1122 desc_ring_irq_inten_reg_addr[ring_id] );
1123 }
1124
1125 return value;
1126 }
1127
1128
1129
ogma_clear_desc_ring_irq_status(ogma_handle_t ogma_handle,ogma_desc_ring_id_t ring_id,ogma_uint32 value)1130 ogma_err_t ogma_clear_desc_ring_irq_status (
1131 ogma_handle_t ogma_handle,
1132 ogma_desc_ring_id_t ring_id,
1133 ogma_uint32 value
1134 )
1135 {
1136
1137 ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
1138
1139 if ( ctrl_p == NULL) {
1140 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
1141 "An error occurred at ogma_clear_desc_ring_irq_status.\n"
1142 "Please set valid ogma_handle.\n");
1143 return OGMA_ERR_PARAM;
1144 }
1145
1146 if ( ring_id > OGMA_DESC_RING_ID_MAX) {
1147 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
1148 "An error occurred at ogma_clear_desc_ring_irq_status.\n"
1149 "Please select ring id number between 0 and %d.\n",
1150 OGMA_DESC_RING_ID_MAX);
1151 return OGMA_ERR_PARAM;
1152 }
1153
1154 if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
1155 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
1156 "An error occurred at ogma_clear_desc_ring_irq_status.\n"
1157 "Please select valid desc ring.\n");
1158 return OGMA_ERR_NOTAVAIL;
1159 }
1160
1161 /* Write clear descring irq status */
1162 ogma_write_reg( ctrl_p,
1163 desc_ring_irq_status_reg_addr[ring_id],
1164 ( value & ( OGMA_CH_IRQ_REG_EMPTY |
1165 OGMA_CH_IRQ_REG_ERR) ) );
1166
1167 return OGMA_ERR_OK;
1168
1169 }
1170
1171
ogma_get_pkt_irq_enable(ogma_handle_t ogma_handle)1172 ogma_uint32 ogma_get_pkt_irq_enable (
1173 ogma_handle_t ogma_handle
1174 )
1175 {
1176 ogma_uint32 value;
1177 ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
1178
1179
1180 if ( ctrl_p == NULL) {
1181 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
1182 "An error occurred at ogma_get_pkt_irq_enable.\n"
1183 "Please set valid ogma_handle.\n");
1184 return 0;
1185 }
1186
1187 value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_INTEN);
1188
1189 value &= OGMA_PKT_IRQ_ALL;
1190
1191 return value;
1192
1193 }
1194
ogma_get_pkt_irq_status(ogma_handle_t ogma_handle,ogma_bool mask_flag)1195 ogma_uint32 ogma_get_pkt_irq_status (
1196 ogma_handle_t ogma_handle,
1197 ogma_bool mask_flag
1198 )
1199 {
1200 ogma_uint32 value;
1201 ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
1202
1203 if ( ctrl_p == NULL) {
1204 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
1205 "An error occurred at ogma_get_pkt_irq_statusnon_clear.\n"
1206 "Please set valid ogma_handle.\n");
1207 return 0;
1208 }
1209
1210 value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_STATUS);
1211
1212 if ( mask_flag) {
1213 value &= ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_INTEN);
1214 }
1215
1216 return value;
1217 }
1218
ogma_clear_pkt_irq_status(ogma_handle_t ogma_handle,ogma_uint32 value)1219 ogma_err_t ogma_clear_pkt_irq_status (
1220 ogma_handle_t ogma_handle,
1221 ogma_uint32 value
1222 )
1223 {
1224 ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
1225
1226 if ( ctrl_p == NULL) {
1227 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
1228 "An error occurred at ogma_clear_pkt_irq_status.\n"
1229 "Please set valid ogma_handle.\n");
1230 return OGMA_ERR_PARAM;
1231 }
1232
1233 /* Write clear irq pkt status */
1234 ogma_write_reg( ctrl_p,
1235 OGMA_REG_ADDR_PKT_STATUS,
1236 ( value & ( ( OGMA_PKT_IRQ_MAC_ER |
1237 OGMA_PKT_IRQ_JUMBO_ER |
1238 OGMA_PKT_IRQ_CHKSUM_ER |
1239 OGMA_PKT_IRQ_HD_INCOMPLETE |
1240 OGMA_PKT_IRQ_HD_ER |
1241 OGMA_PKT_IRQ_DRP_NO_MATCH) ) ) );
1242
1243 return OGMA_ERR_OK;
1244 }
1245
1246 #ifdef OGMA_CONFIG_REC_STAT
ogma_get_stat_info(ogma_handle_t ogma_handle,ogma_stat_info_t * stat_info_p,ogma_bool clear_flag)1247 ogma_err_t ogma_get_stat_info (
1248 ogma_handle_t ogma_handle,
1249 ogma_stat_info_t *stat_info_p,
1250 ogma_bool clear_flag
1251 )
1252 {
1253
1254 ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
1255
1256 if ( ( ctrl_p == NULL) || (stat_info_p == NULL) ) {
1257 return OGMA_ERR_PARAM;
1258 }
1259
1260 pfdep_memcpy( stat_info_p,
1261 &ctrl_p->stat_info,
1262 sizeof( ogma_stat_info_t) );
1263
1264
1265 if ( clear_flag) {
1266 pfdep_memset( &ctrl_p->stat_info, 0, sizeof( ogma_stat_info_t) );
1267 }
1268
1269 return OGMA_ERR_OK;
1270
1271 }
1272 #endif /* OGMA_CONFIG_REC_STAT */
1273
ogma_get_hw_ver(ogma_handle_t ogma_handle)1274 ogma_uint32 ogma_get_hw_ver (
1275 ogma_handle_t ogma_handle
1276 )
1277 {
1278 ogma_uint32 value;
1279 ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
1280
1281 if ( ctrl_p == NULL) {
1282 return 0;
1283 }
1284
1285 value = ogma_read_reg( ctrl_p,
1286 hw_ver_reg_addr);
1287
1288 return value;
1289 }
1290
1291
ogma_get_mcr_ver(ogma_handle_t ogma_handle)1292 ogma_uint32 ogma_get_mcr_ver (
1293 ogma_handle_t ogma_handle
1294 )
1295 {
1296 ogma_uint32 value;
1297 ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
1298
1299 if ( ctrl_p == NULL) {
1300 return 0;
1301 }
1302
1303 value = ogma_read_reg( ctrl_p,
1304 mc_ver_reg_addr);
1305
1306 return value;
1307 }
1308
ogma_get_mac_irq_enable(ogma_handle_t ogma_handle)1309 ogma_uint32 ogma_get_mac_irq_enable (
1310 ogma_handle_t ogma_handle
1311 )
1312 {
1313 ogma_uint32 value;
1314 ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
1315
1316 if ( ctrl_p == NULL) {
1317 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
1318 "An error occurred at ogma_ogma_get_mac_irq_enable.\n"
1319 "Please set valid ogma_handle.\n");
1320 return 0;
1321 }
1322
1323 value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_INTEN);
1324
1325
1326 return value;
1327 }
1328
ogma_get_mac_irq_status(ogma_handle_t ogma_handle,ogma_bool mask_flag)1329 ogma_uint32 ogma_get_mac_irq_status (
1330 ogma_handle_t ogma_handle,
1331 ogma_bool mask_flag
1332 )
1333 {
1334 ogma_uint32 value;
1335 ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
1336
1337 if ( ctrl_p == NULL) {
1338 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
1339 "An error occurred at ogma_get_mac_irq_status.\n"
1340 "Please set valid ogma_handle.\n");
1341 return 0;
1342 }
1343
1344
1345 value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_STATUS);
1346
1347 if ( mask_flag) {
1348 value &= ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_INTEN);
1349 }
1350
1351
1352 return value;
1353 }
1354
ogma_clear_mac_irq_status(ogma_handle_t ogma_handle,ogma_uint32 value)1355 ogma_err_t ogma_clear_mac_irq_status (
1356 ogma_handle_t ogma_handle,
1357 ogma_uint32 value
1358 )
1359 {
1360 ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
1361
1362 if ( ctrl_p == NULL) {
1363 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
1364 "An error occurred at ogma_clear_mac_irq_status.\n"
1365 "Please set valid ogma_handle.\n");
1366 return OGMA_ERR_PARAM;
1367 }
1368
1369
1370 /* Commented out because no write-clear bit exists now. */
1371 #if 0
1372 ogma_write_reg( ctrl_p,
1373 OGMA_REG_ADDR_MAC_STATUS,
1374 ( value & /* T.B.D. */) );
1375 #endif
1376
1377
1378 return OGMA_ERR_OK;
1379
1380 }
1381
ogma_enable_mac_irq(ogma_handle_t ogma_handle,ogma_uint32 irq_factor)1382 ogma_err_t ogma_enable_mac_irq (
1383 ogma_handle_t ogma_handle,
1384 ogma_uint32 irq_factor
1385 )
1386 {
1387 ogma_uint32 value;
1388 ogma_err_t ogma_err = OGMA_ERR_OK;
1389 ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
1390 pfdep_hard_lock_ctx_t inten_reg_hard_lock_ctx;
1391
1392 if ( ctrl_p == NULL) {
1393 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
1394 "An error occurred at ogma_enable_mac_irq.\n"
1395 "Please set valid ogma_handle.\n");
1396 return OGMA_ERR_PARAM;
1397 }
1398
1399 /* get inten_reg_hard_lock */
1400 pfdep_acquire_hard_lock( &ctrl_p->inten_reg_hard_lock,
1401 &inten_reg_hard_lock_ctx);
1402
1403 value = ogma_read_reg( ctrl_p,
1404 OGMA_REG_ADDR_MAC_INTEN);
1405
1406 value |= irq_factor;
1407
1408 ogma_write_reg( ctrl_p,
1409 OGMA_REG_ADDR_MAC_INTEN,
1410 value);
1411
1412
1413 /* free inten_reg_hard_lock*/
1414 pfdep_release_hard_lock( &ctrl_p->inten_reg_hard_lock,
1415 &inten_reg_hard_lock_ctx);
1416 return ogma_err;
1417 }
1418
ogma_disable_mac_irq(ogma_handle_t ogma_handle,ogma_uint32 irq_factor)1419 ogma_err_t ogma_disable_mac_irq (
1420 ogma_handle_t ogma_handle,
1421 ogma_uint32 irq_factor
1422 )
1423 {
1424 ogma_uint32 value;
1425 ogma_err_t ogma_err = OGMA_ERR_OK;
1426 ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
1427
1428 pfdep_hard_lock_ctx_t inten_reg_hard_lock_ctx;
1429
1430
1431 if ( ctrl_p == NULL) {
1432 pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
1433 "An error occurred at ogma_disable_mac_irq.\n"
1434 "Please set valid ogma_handle.\n");
1435 return OGMA_ERR_PARAM;
1436 }
1437
1438 /* get inten_reg_hard_lock */
1439 pfdep_acquire_hard_lock( &ctrl_p->inten_reg_hard_lock,
1440 &inten_reg_hard_lock_ctx);
1441
1442 value = ogma_read_reg( ctrl_p,
1443 OGMA_REG_ADDR_MAC_INTEN);
1444
1445 value &= (~irq_factor);
1446
1447 ogma_write_reg( ctrl_p,
1448 OGMA_REG_ADDR_MAC_INTEN,
1449 value);
1450
1451
1452 /* free inten_reg_hard_lock*/
1453 pfdep_release_hard_lock( &ctrl_p->inten_reg_hard_lock,
1454 &inten_reg_hard_lock_ctx);
1455 return ogma_err;
1456
1457 }
1458