1 /* $OpenBSD: db_instruction.h,v 1.6 2024/11/02 09:34:06 miod Exp $ */ 2 /* $NetBSD: db_instruction.h,v 1.7 2001/04/26 03:10:44 ross Exp $ */ 3 4 /* 5 * Copyright (c) 1999 Christopher G. Demetriou. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Christopher G. Demetriou 18 * for the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Mach Operating System 36 * Copyright (c) 1993,1992 Carnegie Mellon University 37 * All Rights Reserved. 38 * 39 * Permission to use, copy, modify and distribute this software and its 40 * documentation is hereby granted, provided that both the copyright 41 * notice and this permission notice appear in all copies of the 42 * software, derivative works or modified versions, and any portions 43 * thereof, and that both notices appear in supporting documentation. 44 * 45 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 46 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 47 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 48 * 49 * Carnegie Mellon requests users of this software to return to 50 * 51 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 52 * School of Computer Science 53 * Carnegie Mellon University 54 * Pittsburgh PA 15213-3890 55 * 56 * any improvements or extensions that they make and grant Carnegie Mellon 57 * the rights to redistribute these changes. 58 */ 59 60 /* 61 * File: alpha_instruction.h 62 * Author: Alessandro Forin, Carnegie Mellon University 63 * Date: 11/91 64 * 65 * Alpha Instruction set definition 66 * 67 * Reference: "Alpha System Reference Manual", V4.0, April 1991 68 * 69 */ 70 71 #ifndef _ALPHA_INSTRUCTION_H_ 72 #define _ALPHA_INSTRUCTION_H_ 1 73 74 /* 75 * All instructions are in one of five formats: 76 * Memory, Branch, Operate, Floating-point Operate, PAL 77 * 78 * The original Mach sources attempted to use 'smarter' names 79 * for registers, which reflected source and destination. These 80 * definitions use the names from the Architecture Reference Manual, 81 * both for clarity and because you can't differentiate between 82 * 'source' and 'destinations' for some types of instructions (loads 83 * and stores; they'd be correct for one, but swapped for the other). 84 */ 85 86 87 typedef union { 88 /* 89 * All instructions are 32 bits wide 90 */ 91 unsigned int bits; 92 93 /* 94 * Generic instruction pseudo format; look at 95 * opcode to see how to interpret the rest. 96 */ 97 struct { 98 unsigned bits:26, 99 opcode:6; 100 } generic_format; 101 102 /* 103 * Memory instructions contain a 16 bit 104 * signed immediate value and two register 105 * specifiers 106 */ 107 struct { 108 signed short displacement; 109 unsigned rb : 5, 110 ra : 5, 111 opcode : 6; 112 } mem_format; 113 114 /* 115 * Branch instruction contain a 21 bit offset, 116 * which is sign-extended, shifted and combined 117 * with the PC to form a 64 bit destination address. 118 * 119 * In computed jump instructions the opcode is further 120 * specified in the offset field, the rest of it is 121 * used as branch target hint. The destination of the 122 * jump is the source register. 123 */ 124 struct { 125 signed int displacement : 21; 126 unsigned ra : 5, 127 opcode : 6; 128 } branch_format; 129 130 struct { 131 signed int hint : 14; 132 unsigned action : 2, 133 rb : 5, 134 ra : 5, 135 opcode : 6; 136 } jump_format; 137 138 139 /* 140 * Operate instructions are of two types, with 141 * a second source register or with a literal 142 * specifier. Bit 12 says which is which. 143 */ 144 struct { 145 unsigned rc : 5, 146 function : 7, 147 is_lit : 1, 148 sbz_or_litlo : 3, 149 rb_or_lithi : 5, 150 ra : 5, 151 opcode : 6; 152 } operate_generic_format; 153 154 struct { 155 unsigned rc : 5, 156 function : 7, 157 zero : 1, 158 sbz : 3, 159 rb : 5, 160 ra : 5, 161 opcode : 6; 162 } operate_reg_format; 163 164 struct { 165 unsigned rc : 5, 166 function : 7, 167 one : 1, 168 literal : 8, 169 ra : 5, 170 opcode : 6; 171 } operate_lit_format; 172 173 174 /* 175 * Floating point operate instruction are quite 176 * uniform in the encoding. As for the semantics.. 177 */ 178 struct { 179 unsigned fc : 5, 180 function : 11, 181 fb : 5, 182 fa : 5, 183 opcode : 6; 184 } float_format; 185 186 struct { 187 unsigned fc : 5, 188 opclass : 4, 189 src : 2, 190 rnd : 2, 191 trp : 3, 192 fb : 5, 193 fa : 5, 194 opcode : 6; 195 } float_detail; 196 197 /* 198 * PAL instructions just define the major opcode 199 */ 200 201 struct { 202 unsigned function : 26, 203 opcode : 6; 204 } pal_format; 205 206 } alpha_instruction; 207 208 /* 209 * 210 * Encoding of regular instructions (Appendix C op cit) 211 * 212 */ 213 214 /* OPCODE, bits 26..31 */ 215 216 #define op_pal 0x00 /* see PAL sub-table */ 217 /* 1..7 reserved */ 218 #define op_lda 0x08 219 #define op_ldah 0x09 220 #define op_ldbu 0x0a 221 #define op_ldq_u 0x0b 222 #define op_ldwu 0x0c 223 #define op_stw 0x0d 224 #define op_stb 0x0e 225 #define op_stq_u 0x0f 226 227 #define op_arit 0x10 /* see ARIT sub-table */ 228 #define op_logical 0x11 /* see LOGICAL sub-table */ 229 #define op_bit 0x12 /* see BIT sub-table */ 230 #define op_mul 0x13 /* see MUL sub-table */ 231 /* reserved */ 232 #define op_fix_float 0x14 /* if ALPHA_AMASK_FIX */ 233 #define op_vax_float 0x15 /* see FLOAT sub-table */ 234 #define op_ieee_float 0x16 /* see FLOAT sub-table */ 235 #define op_any_float 0x17 /* see FLOAT sub-table */ 236 237 #define op_special 0x18 /* see SPECIAL sub-table */ 238 #define op_pal19 0x19 /* reserved for pal code */ 239 #define op_j 0x1a /* see JUMP sub-table */ 240 #define op_pal1b 0x1b /* reserved for pal code */ 241 #define op_intmisc 0x1c /* see INTMISC sub-table */ 242 #define op_pal1d 0x1d /* reserved for pal code */ 243 #define op_pal1e 0x1e /* reserved for pal code */ 244 #define op_pal1f 0x1f /* reserved for pal code */ 245 246 #define op_ldf 0x20 247 #define op_ldg 0x21 248 #define op_lds 0x22 249 #define op_ldt 0x23 250 #define op_stf 0x24 251 #define op_stg 0x25 252 #define op_sts 0x26 253 #define op_stt 0x27 254 #define op_ldl 0x28 255 #define op_ldq 0x29 256 #define op_ldl_l 0x2a 257 #define op_ldq_l 0x2b 258 #define op_stl 0x2c 259 #define op_stq 0x2d 260 #define op_stl_c 0x2e 261 #define op_stq_c 0x2f 262 #define op_br 0x30 263 #define op_fbeq 0x31 264 #define op_fblt 0x32 265 #define op_fble 0x33 266 #define op_bsr 0x34 267 #define op_fbne 0x35 268 #define op_fbge 0x36 269 #define op_fbgt 0x37 270 #define op_blbc 0x38 271 #define op_beq 0x39 272 #define op_blt 0x3a 273 #define op_ble 0x3b 274 #define op_blbs 0x3c 275 #define op_bne 0x3d 276 #define op_bge 0x3e 277 #define op_bgt 0x3f 278 279 280 /* PAL, "function" opcodes (bits 0..25) */ 281 /* 282 * What we will implement is TBD. These are the unprivileged ones 283 * that we probably have to support for compat reasons. 284 */ 285 286 /* See <machine/pal.h> */ 287 288 /* ARIT, "function" opcodes (bits 5..11) */ 289 290 #define op_addl 0x00 291 #define op_s4addl 0x02 292 #define op_subl 0x09 293 #define op_s4subl 0x0b 294 #define op_cmpbge 0x0f 295 #define op_s8addl 0x12 296 #define op_s8subl 0x1b 297 #define op_cmpult 0x1d 298 #define op_addq 0x20 299 #define op_s4addq 0x22 300 #define op_subq 0x29 301 #define op_s4subq 0x2b 302 #define op_cmpeq 0x2d 303 #define op_s8addq 0x32 304 #define op_s8subq 0x3b 305 #define op_cmpule 0x3d 306 #define op_addl_v 0x40 307 #define op_subl_v 0x49 308 #define op_cmplt 0x4d 309 #define op_addq_v 0x60 310 #define op_subq_v 0x69 311 #define op_cmple 0x6d 312 313 314 /* LOGICAL, "function" opcodes (bits 5..11) */ 315 316 #define op_and 0x00 317 #define op_andnot 0x08 /* bic */ 318 #define op_cmovlbs 0x14 319 #define op_cmovlbc 0x16 320 #define op_or 0x20 /* bis */ 321 #define op_cmoveq 0x24 322 #define op_cmovne 0x26 323 #define op_ornot 0x28 324 #define op_xor 0x40 325 #define op_cmovlt 0x44 326 #define op_cmovge 0x46 327 #define op_xornot 0x48 /* eqv */ 328 #define op_amask 0x61 329 #define op_cmovle 0x64 330 #define op_cmovgt 0x66 331 #define op_implver 0x6c 332 333 /* BIT, "function" opcodes (bits 5..11) */ 334 335 #define op_mskbl 0x02 336 #define op_extbl 0x06 337 #define op_insbl 0x0b 338 #define op_mskwl 0x12 339 #define op_extwl 0x16 340 #define op_inswl 0x1b 341 #define op_mskll 0x22 342 #define op_extll 0x26 343 #define op_insll 0x2b 344 #define op_zap 0x30 345 #define op_zapnot 0x31 346 #define op_mskql 0x32 347 #define op_srl 0x34 348 #define op_extql 0x36 349 #define op_sll 0x39 350 #define op_insql 0x3b 351 #define op_sra 0x3c 352 #define op_mskwh 0x52 353 #define op_inswh 0x57 354 #define op_extwh 0x5a 355 #define op_msklh 0x62 356 #define op_inslh 0x67 357 #define op_extlh 0x6a 358 #define op_extqh 0x7a 359 #define op_insqh 0x77 360 #define op_mskqh 0x72 361 362 /* MUL, "function" opcodes (bits 5..11) */ 363 364 #define op_mull 0x00 365 #define op_mulq_v 0x60 366 #define op_mull_v 0x40 367 #define op_umulh 0x30 368 #define op_mulq 0x20 369 370 371 /* SPECIAL, "displacement" opcodes (bits 0..15) */ 372 373 #define op_trapb 0x0000 374 #define op_excb 0x0400 375 #define op_mb 0x4000 376 #define op_wmb 0x4400 377 #define op_fetch 0x8000 378 #define op_fetch_m 0xa000 379 #define op_rpcc 0xc000 380 #define op_rc 0xe000 381 #define op_ecb 0xe800 382 #define op_rs 0xf000 383 #define op_wh64 0xf800 384 385 /* JUMP, "action" opcodes (bits 14..15) */ 386 387 #define op_jmp 0x0 388 #define op_jsr 0x1 389 #define op_ret 0x2 390 #define op_jcr 0x3 391 392 /* INTMISC, "function" opcodes (operate format) */ 393 394 #define op_sextb 0x00 395 #define op_sextw 0x01 396 #define op_ctpop 0x30 397 #define op_perr 0x31 398 #define op_ctlz 0x32 399 #define op_cttz 0x33 400 #define op_unpkbw 0x34 401 #define op_unpkbl 0x35 402 #define op_pkwb 0x36 403 #define op_pklb 0x37 404 #define op_minsb8 0x38 405 #define op_minsw4 0x39 406 #define op_minub8 0x3a 407 #define op_minuw4 0x3b 408 #define op_maxub8 0x3c 409 #define op_maxuw4 0x3d 410 #define op_maxsb8 0x3e 411 #define op_maxsw4 0x3f 412 #define op_ftoit 0x70 413 #define op_ftois 0x78 414 415 /* 416 * 417 * Encoding of floating point instructions (pagg. C-5..6 op cit) 418 * 419 * Load and store operations use opcodes op_ldf..op_stt 420 */ 421 422 /* src encoding from function, 9..10 */ 423 #define op_src_sf 0 424 #define op_src_xd 1 425 #define op_src_tg 2 426 #define op_src_qq 3 427 428 /* any FLOAT, "function" opcodes (bits 5..11) */ 429 430 #define op_cvtlq 0x010 431 #define op_cpys 0x020 432 #define op_cpysn 0x021 433 #define op_cpyse 0x022 434 #define op_mt_fpcr 0x024 435 #define op_mf_fpcr 0x025 436 #define op_fcmoveq 0x02a 437 #define op_fcmovne 0x02b 438 #define op_fcmovlt 0x02c 439 #define op_fcmovge 0x02d 440 #define op_fcmovle 0x02e 441 #define op_fcmovgt 0x02f 442 #define op_cvtql 0x030 443 #define op_cvtql_v 0x130 444 #define op_cvtql_sv 0x530 445 446 447 /* ieee FLOAT, "function" opcodes (bits 5..11) */ 448 449 #define op_adds_c 0x000 450 #define op_subs_c 0x001 451 #define op_muls_c 0x002 452 #define op_divs_c 0x003 453 #define op_addt_c 0x020 454 #define op_subt_c 0x021 455 #define op_mult_c 0x022 456 #define op_divt_c 0x023 457 #define op_cvtts_c 0x02c 458 #define op_cvttq_c 0x02f 459 #define op_cvtqs_c 0x03c 460 #define op_cvtqt_c 0x03e 461 #define op_adds_m 0x040 462 #define op_subs_m 0x041 463 #define op_muls_m 0x042 464 #define op_divs_m 0x043 465 #define op_addt_m 0x060 466 #define op_subt_m 0x061 467 #define op_mult_m 0x062 468 #define op_divt_m 0x063 469 #define op_cvtts_m 0x06c 470 #define op_cvtqs_m 0x07c 471 #define op_cvtqt_m 0x07e 472 #define op_adds 0x080 473 #define op_subs 0x081 474 #define op_muls 0x082 475 #define op_divs 0x083 476 #define op_addt 0x0a0 477 #define op_subt 0x0a1 478 #define op_mult 0x0a2 479 #define op_divt 0x0a3 480 #define op_cmptun 0x0a4 481 #define op_cmpteq 0x0a5 482 #define op_cmptlt 0x0a6 483 #define op_cmptle 0x0a7 484 #define op_cvtts 0x0ac 485 #define op_cvttq 0x0af 486 #define op_cvtqs 0x0bc 487 #define op_cvtqt 0x0be 488 #define op_adds_d 0x0c0 489 #define op_subs_d 0x0c1 490 #define op_muls_d 0x0c2 491 #define op_divs_d 0x0c3 492 #define op_addt_d 0x0e0 493 #define op_subt_d 0x0e1 494 #define op_mult_d 0x0e2 495 #define op_divt_d 0x0e3 496 #define op_cvtts_d 0x0ec 497 #define op_cvtqs_d 0x0fc 498 #define op_cvtqt_d 0x0fe 499 #define op_adds_uc 0x100 500 #define op_subs_uc 0x101 501 #define op_muls_uc 0x102 502 #define op_divs_uc 0x103 503 #define op_addt_uc 0x120 504 #define op_subt_uc 0x121 505 #define op_mult_uc 0x122 506 #define op_divt_uc 0x123 507 #define op_cvtts_uc 0x12c 508 #define op_cvttq_vc 0x12f 509 #define op_adds_um 0x140 510 #define op_subs_um 0x141 511 #define op_muls_um 0x142 512 #define op_divs_um 0x143 513 #define op_addt_um 0x160 514 #define op_subt_um 0x161 515 #define op_mult_um 0x162 516 #define op_divt_um 0x163 517 #define op_cvtts_um 0x16c 518 #define op_adds_u 0x180 519 #define op_subs_u 0x181 520 #define op_muls_u 0x182 521 #define op_divs_u 0x183 522 #define op_addt_u 0x1a0 523 #define op_subt_u 0x1a1 524 #define op_mult_u 0x1a2 525 #define op_divt_u 0x1a3 526 #define op_cvtts_u 0x1ac 527 #define op_cvttq_v 0x1af 528 #define op_adds_ud 0x1c0 529 #define op_subs_ud 0x1c1 530 #define op_muls_ud 0x1c2 531 #define op_divs_ud 0x1c3 532 #define op_addt_ud 0x1e0 533 #define op_subt_ud 0x1e1 534 #define op_mult_ud 0x1e2 535 #define op_divt_ud 0x1e3 536 #define op_cvtts_ud 0x1ec 537 #define op_cvtst 0x2ac 538 #define op_adds_suc 0x500 539 #define op_subs_suc 0x501 540 #define op_muls_suc 0x502 541 #define op_divs_suc 0x503 542 #define op_addt_suc 0x520 543 #define op_subt_suc 0x521 544 #define op_mult_suc 0x522 545 #define op_divt_suc 0x523 546 #define op_cvtts_suc 0x52c 547 #define op_cvttq_svc 0x52f 548 #define op_adds_sum 0x540 549 #define op_subs_sum 0x541 550 #define op_muls_sum 0x542 551 #define op_divs_sum 0x543 552 #define op_addt_sum 0x560 553 #define op_subt_sum 0x561 554 #define op_mult_sum 0x562 555 #define op_divt_sum 0x563 556 #define op_cvtts_sum 0x56c 557 #define op_adds_su 0x580 558 #define op_subs_su 0x581 559 #define op_muls_su 0x582 560 #define op_divs_su 0x583 561 #define op_addt_su 0x5a0 562 #define op_subt_su 0x5a1 563 #define op_mult_su 0x5a2 564 #define op_divt_su 0x5a3 565 #define op_cmptun_su 0x5a4 566 #define op_cmpteq_su 0x5a5 567 #define op_cmptlt_su 0x5a6 568 #define op_cmptle_su 0x5a7 569 #define op_cvtts_su 0x5ac 570 #define op_cvttq_sv 0x5af 571 #define op_adds_sud 0x5c0 572 #define op_subs_sud 0x5c1 573 #define op_muls_sud 0x5c2 574 #define op_divs_sud 0x5c3 575 #define op_addt_sud 0x5e0 576 #define op_subt_sud 0x5e1 577 #define op_mult_sud 0x5e2 578 #define op_divt_sud 0x5e3 579 #define op_cvtts_sud 0x5ec 580 #define op_cvtst_u 0x6ac 581 #define op_adds_suic 0x700 582 #define op_subs_suic 0x701 583 #define op_muls_suic 0x702 584 #define op_divs_suic 0x703 585 #define op_addt_suic 0x720 586 #define op_subt_suic 0x721 587 #define op_mult_suic 0x722 588 #define op_divt_suic 0x723 589 #define op_cvtts_suic 0x72c 590 #define op_cvttq_svic 0x72f 591 #define op_cvtqs_suic 0x73c 592 #define op_cvtqt_suic 0x73e 593 #define op_adds_suim 0x740 594 #define op_subs_suim 0x741 595 #define op_muls_suim 0x742 596 #define op_divs_suim 0x743 597 #define op_addt_suim 0x760 598 #define op_subt_suim 0x761 599 #define op_mult_suim 0x762 600 #define op_divt_suim 0x763 601 #define op_cvtts_suim 0x76c 602 #define op_cvtqs_suim 0x77c 603 #define op_cvtqt_suim 0x77e 604 #define op_adds_sui 0x780 605 #define op_subs_sui 0x781 606 #define op_muls_sui 0x782 607 #define op_divs_sui 0x783 608 #define op_addt_sui 0x7a0 609 #define op_subt_sui 0x7a1 610 #define op_mult_sui 0x7a2 611 #define op_divt_sui 0x7a3 612 #define op_cvtts_sui 0x7ac 613 #define op_cvttq_svi 0x7af 614 #define op_cvtqs_sui 0x7bc 615 #define op_cvtqt_sui 0x7be 616 #define op_adds_suid 0x7c0 617 #define op_subs_suid 0x7c1 618 #define op_muls_suid 0x7c2 619 #define op_divs_suid 0x7c3 620 #define op_addt_suid 0x7e0 621 #define op_subt_suid 0x7e1 622 #define op_mult_suid 0x7e2 623 #define op_divt_suid 0x7e3 624 #define op_cvtts_suid 0x7ec 625 #define op_cvtqs_suid 0x7fc 626 #define op_cvtqt_suid 0x7fe 627 628 629 /* vax FLOAT, "function" opcodes (bits 5..11) */ 630 631 #define op_addf_c 0x000 632 #define op_subf_c 0x001 633 #define op_mulf_c 0x002 634 #define op_divf_c 0x003 635 #define op_cvtdg_c 0x01e 636 #define op_addg_c 0x020 637 #define op_subg_c 0x021 638 #define op_mulg_c 0x022 639 #define op_divg_c 0x023 640 #define op_cvtgf_c 0x02c 641 #define op_cvtgd_c 0x02d 642 #define op_cvtgqg_c 0x02f 643 #define op_cvtqf_c 0x03c 644 #define op_cvtqg_c 0x03e 645 #define op_addf 0x080 646 #define op_subf 0x081 647 #define op_mulf 0x082 648 #define op_divf 0x083 649 #define op_cvtdg 0x09e 650 #define op_addg 0x0a0 651 #define op_subg 0x0a1 652 #define op_mulg 0x0a2 653 #define op_divg 0x0a3 654 #define op_cmpgeq 0x0a5 655 #define op_cmpglt 0x0a6 656 #define op_cmpgle 0x0a7 657 #define op_cvtgf 0x0ac 658 #define op_cvtgd 0x0ad 659 #define op_cvtgq 0x0af 660 #define op_cvtqf 0x0bc 661 #define op_cvtqg 0x0be 662 #define op_addf_uc 0x100 663 #define op_subf_uc 0x101 664 #define op_mulf_uc 0x102 665 #define op_divf_uc 0x103 666 #define op_cvtdg_uc 0x11e 667 #define op_addg_uc 0x120 668 #define op_subg_uc 0x121 669 #define op_mulg_uc 0x122 670 #define op_divg_uc 0x123 671 #define op_cvtgf_uc 0x12c 672 #define op_cvtgd_uc 0x12d 673 #define op_cvtgqg_vc 0x12f 674 #define op_addf_u 0x180 675 #define op_subf_u 0x181 676 #define op_mulf_u 0x182 677 #define op_divf_u 0x183 678 #define op_cvtdg_u 0x19e 679 #define op_addg_u 0x1a0 680 #define op_subg_u 0x1a1 681 #define op_mulg_u 0x1a2 682 #define op_divg_u 0x1a3 683 #define op_cvtgf_u 0x1ac 684 #define op_cvtgd_u 0x1ad 685 #define op_cvtgqg_v 0x1af 686 #define op_addf_sc 0x400 687 #define op_subf_sc 0x401 688 #define op_mulf_sc 0x402 689 #define op_divf_sc 0x403 690 #define op_cvtdg_sc 0x41e 691 #define op_addg_sc 0x420 692 #define op_subg_sc 0x421 693 #define op_mulg_sc 0x422 694 #define op_divg_sc 0x423 695 #define op_cvtgf_sc 0x42c 696 #define op_cvtgd_sc 0x42d 697 #define op_cvtgqg_sc 0x42f 698 #define op_cvtqf_sc 0x43c 699 #define op_cvtqg_sc 0x43e 700 #define op_addf_s 0x480 701 #define op_subf_s 0x481 702 #define op_mulf_s 0x482 703 #define op_divf_s 0x483 704 #define op_cvtdg_s 0x49e 705 #define op_addg_s 0x4a0 706 #define op_subg_s 0x4a1 707 #define op_mulg_s 0x4a2 708 #define op_divg_s 0x4a3 709 #define op_cmpgeq_s 0x4a5 710 #define op_cmpglt_s 0x4a6 711 #define op_cmpgle_s 0x4a7 712 #define op_cvtgf_s 0x4ac 713 #define op_cvtgd_s 0x4ad 714 #define op_cvtgqg_s 0x4af 715 #define op_cvtqf_s 0x4bc 716 #define op_cvtqg_s 0x4be 717 #define op_addf_suc 0x500 718 #define op_subf_suc 0x501 719 #define op_mulf_suc 0x502 720 #define op_divf_suc 0x503 721 #define op_cvtdg_suc 0x51e 722 #define op_addg_suc 0x520 723 #define op_subg_suc 0x521 724 #define op_mulg_suc 0x522 725 #define op_divg_suc 0x523 726 #define op_cvtgf_suc 0x52c 727 #define op_cvtgd_suc 0x52d 728 #define op_cvtgqg_svc 0x52f 729 #define op_addf_su 0x580 730 #define op_subf_su 0x581 731 #define op_mulf_su 0x582 732 #define op_divf_su 0x583 733 #define op_cvtdg_su 0x59e 734 #define op_addg_su 0x5a0 735 #define op_subg_su 0x5a1 736 #define op_mulg_su 0x5a2 737 #define op_divg_su 0x5a3 738 #define op_cvtgf_su 0x5ac 739 #define op_cvtgd_su 0x5ad 740 #define op_cvtgqg_sv 0x5af 741 742 743 #endif /* _ALPHA_INSTRUCTION_H_ */ 744