1 /*
2 * OpenRISC gdb server stub
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 * Copyright (c) 2013 SUSE LINUX Products GmbH
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "gdbstub/helpers.h"
23
openrisc_cpu_gdb_read_register(CPUState * cs,GByteArray * mem_buf,int n)24 int openrisc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
25 {
26 CPUOpenRISCState *env = cpu_env(cs);
27
28 if (n < 32) {
29 return gdb_get_reg32(mem_buf, cpu_get_gpr(env, n));
30 } else {
31 switch (n) {
32 case 32: /* PPC */
33 return gdb_get_reg32(mem_buf, env->ppc);
34
35 case 33: /* NPC (equals PC) */
36 return gdb_get_reg32(mem_buf, env->pc);
37
38 case 34: /* SR */
39 return gdb_get_reg32(mem_buf, cpu_get_sr(env));
40
41 default:
42 break;
43 }
44 }
45 return 0;
46 }
47
openrisc_cpu_gdb_write_register(CPUState * cs,uint8_t * mem_buf,int n)48 int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
49 {
50 CPUClass *cc = CPU_GET_CLASS(cs);
51 CPUOpenRISCState *env = cpu_env(cs);
52 uint32_t tmp;
53
54 if (n > cc->gdb_num_core_regs) {
55 return 0;
56 }
57
58 tmp = ldl_p(mem_buf);
59
60 if (n < 32) {
61 cpu_set_gpr(env, n, tmp);
62 } else {
63 switch (n) {
64 case 32: /* PPC */
65 env->ppc = tmp;
66 break;
67
68 case 33: /* NPC (equals PC) */
69 /* If setting PC to something different,
70 also clear delayed branch status. */
71 if (env->pc != tmp) {
72 env->pc = tmp;
73 env->dflag = 0;
74 }
75 break;
76
77 case 34: /* SR */
78 cpu_set_sr(env, tmp);
79 break;
80
81 default:
82 break;
83 }
84 }
85 return 4;
86 }
87