1 /*
2 * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
3 * SPDX-License-Identifier: MIT
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24
25 /***************************** HW State Routines ***************************\
26 * *
27 * Module: os_stubs.c *
28 * Stubs for all the public stub routines *
29 \***************************************************************************/
30
31 #include "os/os_stub.h"
32
33 //
34 // Here's a little debugging tool. It is possible that some code is stubbed for
35 // certain OS's that shouldn't be. In debug mode, the stubs below will dump out
36 // a stub 'number' to help you identify any stubs that are getting called. You
37 // can then evaluate whether or not that is correct.
38 //
39 // Highest used STUB_CHECK is 237.
40 //
41 #if defined(DEBUG)
42 #define STUB_CHECK(n) _stubCallCheck(n)
43
44 int enableOsStubCallCheck = 0;
45
_stubCallCheck(int funcNumber)46 static void _stubCallCheck(int funcNumber)
47 {
48 if (enableOsStubCallCheck) {
49 NV_PRINTF(LEVEL_INFO, "STUB CALL: %d \r\n", funcNumber);
50 }
51 }
52
53 #else
54 #define STUB_CHECK(n)
55 #endif // DEBUG
56
57 struct OBJCL;
58
osQADbgRegistryInit(void)59 void osQADbgRegistryInit(void)
60 {
61 return;
62 }
63
stubOsnv_rdcr4(OBJOS * pOS)64 NvU32 stubOsnv_rdcr4(OBJOS *pOS)
65 {
66 STUB_CHECK(76);
67 return 0;
68 }
69
stubOsnv_rdxcr0(OBJOS * pOs)70 NvU64 stubOsnv_rdxcr0(OBJOS *pOs)
71 {
72 STUB_CHECK(237);
73 return 0;
74 }
75
stubOsnv_cpuid(OBJOS * pOS,int arg1,int arg2,NvU32 * arg3,NvU32 * arg4,NvU32 * arg5,NvU32 * arg6)76 int stubOsnv_cpuid(OBJOS *pOS, int arg1, int arg2, NvU32 *arg3,
77 NvU32 *arg4, NvU32 *arg5, NvU32 *arg6)
78 {
79 STUB_CHECK(77);
80 return 0;
81 }
82
stubOsnv_rdmsr(OBJOS * pOS,NvU32 arg1,NvU32 * arg2,NvU32 * arg3)83 NvU32 stubOsnv_rdmsr(OBJOS *pOS, NvU32 arg1, NvU32 *arg2, NvU32 *arg3)
84 {
85 STUB_CHECK(122);
86 return 0;
87 }
88
stubOsnv_wrmsr(OBJOS * pOS,NvU32 arg1,NvU32 arg2,NvU32 arg3)89 NvU32 stubOsnv_wrmsr(OBJOS *pOS, NvU32 arg1, NvU32 arg2, NvU32 arg3)
90 {
91 STUB_CHECK(123);
92 return 0;
93 }
94
osSimEscapeWrite(OBJGPU * pGpu,const char * path,NvU32 Index,NvU32 Size,NvU32 Value)95 NV_STATUS osSimEscapeWrite(OBJGPU *pGpu, const char *path, NvU32 Index, NvU32 Size, NvU32 Value)
96 {
97 return NV_ERR_GENERIC;
98 }
99
osSimEscapeWriteBuffer(OBJGPU * pGpu,const char * path,NvU32 Index,NvU32 Size,void * pBuffer)100 NV_STATUS osSimEscapeWriteBuffer(OBJGPU *pGpu, const char *path, NvU32 Index, NvU32 Size, void* pBuffer)
101 {
102 return NV_ERR_GENERIC;
103 }
104
osSimEscapeRead(OBJGPU * pGpu,const char * path,NvU32 Index,NvU32 Size,NvU32 * Value)105 NV_STATUS osSimEscapeRead(OBJGPU *pGpu, const char *path, NvU32 Index, NvU32 Size, NvU32 *Value)
106 {
107 return NV_ERR_GENERIC;
108 }
109
osSimEscapeReadBuffer(OBJGPU * pGpu,const char * path,NvU32 Index,NvU32 Size,void * pBuffer)110 NV_STATUS osSimEscapeReadBuffer(OBJGPU *pGpu, const char *path, NvU32 Index, NvU32 Size, void* pBuffer)
111 {
112 return NV_ERR_GENERIC;
113 }
114
osCallACPI_MXMX(OBJGPU * pGpu,NvU32 AcpiId,NvU8 * pInOut)115 NV_STATUS osCallACPI_MXMX(OBJGPU *pGpu, NvU32 AcpiId, NvU8 *pInOut)
116 {
117 return NV_ERR_NOT_SUPPORTED;
118 }
119
osCallACPI_BCL(OBJGPU * pGpu,NvU32 acpiId,NvU32 * pOut,NvU16 * size)120 NV_STATUS osCallACPI_BCL(OBJGPU *pGpu, NvU32 acpiId, NvU32 *pOut, NvU16 *size)
121 {
122 return NV_ERR_NOT_SUPPORTED;
123 }
124
osCallACPI_OPTM_GPUON(OBJGPU * pGpu)125 NV_STATUS osCallACPI_OPTM_GPUON(OBJGPU *pGpu)
126 {
127 return NV_ERR_NOT_SUPPORTED;
128 }
129
osCallACPI_NVHG_GPUON(OBJGPU * pGpu,NvU32 * pInOut)130 NV_STATUS osCallACPI_NVHG_GPUON(OBJGPU *pGpu, NvU32 *pInOut)
131 {
132 return NV_ERR_NOT_SUPPORTED;
133 }
134
osCallACPI_NVHG_GPUOFF(OBJGPU * pGpu,NvU32 * pInOut)135 NV_STATUS osCallACPI_NVHG_GPUOFF(OBJGPU *pGpu, NvU32 *pInOut)
136 {
137 return NV_ERR_NOT_SUPPORTED;
138 }
139
osCallACPI_NVHG_GPUSTA(OBJGPU * pGpu,NvU32 * pInOut)140 NV_STATUS osCallACPI_NVHG_GPUSTA(OBJGPU *pGpu, NvU32 *pInOut)
141 {
142 return NV_ERR_NOT_SUPPORTED;
143 }
144
osCallACPI_NVHG_MXDS(OBJGPU * pGpu,NvU32 AcpiId,NvU32 * pInOut)145 NV_STATUS osCallACPI_NVHG_MXDS(OBJGPU *pGpu, NvU32 AcpiId, NvU32 *pInOut)
146 {
147 return NV_ERR_NOT_SUPPORTED;
148 }
149
osCallACPI_NVHG_MXMX(OBJGPU * pGpu,NvU32 AcpiId,NvU32 * pInOut)150 NV_STATUS osCallACPI_NVHG_MXMX(OBJGPU *pGpu, NvU32 AcpiId, NvU32 *pInOut)
151 {
152 return NV_ERR_NOT_SUPPORTED;
153 }
154
osCallACPI_NVHG_DOS(OBJGPU * pGpu,NvU32 AcpiId,NvU32 * pInOut)155 NV_STATUS osCallACPI_NVHG_DOS(OBJGPU *pGpu, NvU32 AcpiId, NvU32 *pInOut)
156 {
157 return NV_ERR_NOT_SUPPORTED;
158 }
159
osCallACPI_NVHG_DCS(OBJGPU * pGpu,NvU32 AcpiId,NvU32 * pInOut)160 NV_STATUS osCallACPI_NVHG_DCS(OBJGPU *pGpu, NvU32 AcpiId, NvU32 *pInOut)
161 {
162 return NV_ERR_NOT_SUPPORTED;
163 }
164
osCallACPI_MXID(OBJGPU * pGpu,NvU32 ulAcpiId,NvU32 * pInOut)165 NV_STATUS osCallACPI_MXID(OBJGPU *pGpu, NvU32 ulAcpiId, NvU32 *pInOut)
166 {
167 return NV_ERR_NOT_SUPPORTED;
168 }
169
osCallACPI_LRST(OBJGPU * pGpu,NvU32 ulAcpiId,NvU32 * pInOut)170 NV_STATUS osCallACPI_LRST(OBJGPU *pGpu, NvU32 ulAcpiId, NvU32 *pInOut)
171 {
172 return NV_ERR_NOT_SUPPORTED;
173 }
174
osCheckCallback(OBJGPU * pGpu)175 NvBool osCheckCallback(OBJGPU *pGpu)
176 {
177 return NV_FALSE;
178 }
179
180 RC_CALLBACK_STATUS
osRCCallback(OBJGPU * pGpu,NvHandle hClient,NvHandle hDevice,NvHandle hFifo,NvHandle hChannel,NvU32 errorLevel,NvU32 errorType,NvU32 * data,void * pfnRmRCReenablePusher)181 osRCCallback
182 (
183 OBJGPU *pGpu,
184 NvHandle hClient, // IN The client RC is on
185 NvHandle hDevice, // IN The device RC is on
186 NvHandle hFifo, // IN The channel or TSG RC is on
187 NvHandle hChannel, // IN The channel RC is on
188 NvU32 errorLevel, // IN Error Level
189 NvU32 errorType, // IN Error type
190 NvU32 *data, // IN/OUT context of RC handler
191 void *pfnRmRCReenablePusher
192 )
193 {
194 return RC_CALLBACK_IGNORE;
195 }
196
osCheckCallback_v2(OBJGPU * pGpu)197 NvBool osCheckCallback_v2(OBJGPU *pGpu)
198 {
199 return NV_FALSE;
200 }
201
202 RC_CALLBACK_STATUS
osRCCallback_v2(OBJGPU * pGpu,NvHandle hClient,NvHandle hDevice,NvHandle hFifo,NvHandle hChannel,NvU32 errorLevel,NvU32 errorType,NvBool bDeferRcRequested,NvU32 * data,void * pfnRmRCReenablePusher)203 osRCCallback_v2
204 (
205 OBJGPU *pGpu,
206 NvHandle hClient, // IN The client RC is on
207 NvHandle hDevice, // IN The device RC is on
208 NvHandle hFifo, // IN The channel or TSG RC is on
209 NvHandle hChannel, // IN The channel RC is on
210 NvU32 errorLevel, // IN Error Level
211 NvU32 errorType, // IN Error type
212 NvBool bDeferRcRequested, // IN defer RC state
213 NvU32 *data, // IN/OUT context of RC handler
214 void *pfnRmRCReenablePusher
215 )
216 {
217 return RC_CALLBACK_IGNORE;
218 }
219
osSetupVBlank(OBJGPU * pGpu,void * pProc,void * pParm1,void * pParm2,NvU32 Head,void * pParm3)220 NV_STATUS osSetupVBlank(OBJGPU *pGpu, void * pProc,
221 void * pParm1, void * pParm2, NvU32 Head, void * pParm3)
222 {
223 return NV_OK;
224 }
225
stubOsObjectEventNotification(NvHandle hClient,NvHandle hObject,NvU32 hClass,PEVENTNOTIFICATION pNotifyEvent,NvU32 notifyIndex,void * pEventData,NvU32 eventDataSize)226 NV_STATUS stubOsObjectEventNotification(NvHandle hClient, NvHandle hObject, NvU32 hClass, PEVENTNOTIFICATION pNotifyEvent,
227 NvU32 notifyIndex, void * pEventData, NvU32 eventDataSize)
228 {
229 return NV_ERR_NOT_SUPPORTED;
230 }
231
232 RmPhysAddr
stubOsPageArrayGetPhysAddr(OS_GPU_INFO * pOsGpuInfo,void * pPageData,NvU32 pageIndex)233 stubOsPageArrayGetPhysAddr(OS_GPU_INFO *pOsGpuInfo, void* pPageData, NvU32 pageIndex)
234 {
235 NV_ASSERT(0);
236 return 0;
237 }
238
stubOsInternalReserveAllocCallback(NvU64 offset,NvU64 size,NvU32 gpuId)239 void stubOsInternalReserveAllocCallback(NvU64 offset, NvU64 size, NvU32 gpuId)
240 {
241 return;
242 }
243
stubOsInternalReserveFreeCallback(NvU64 offset,NvU32 gpuId)244 void stubOsInternalReserveFreeCallback(NvU64 offset, NvU32 gpuId)
245 {
246 return;
247 }
248
osGetCurrentProcessGfid(NvU32 * pGfid)249 NV_STATUS osGetCurrentProcessGfid(NvU32 *pGfid)
250 {
251 return NV_ERR_NOT_SUPPORTED;
252 }
253
osSetRegistryList(nv_reg_entry_t * pRegList)254 NV_STATUS osSetRegistryList(nv_reg_entry_t *pRegList)
255 {
256 return NV_ERR_NOT_SUPPORTED;
257 }
258
osGetRegistryList(void)259 nv_reg_entry_t *osGetRegistryList(void)
260 {
261 return NULL;
262 }
263
264 #if !(RMCFG_FEATURE_PLATFORM_UNIX || RMCFG_FEATURE_PLATFORM_DCE) || \
265 (RMCFG_FEATURE_PLATFORM_UNIX && !RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY)
osTegraSocGpioGetPinState(OS_GPU_INFO * pArg1,NvU32 arg2,NvU32 * pArg3)266 NV_STATUS osTegraSocGpioGetPinState(
267 OS_GPU_INFO *pArg1,
268 NvU32 arg2,
269 NvU32 *pArg3
270 )
271 {
272 return NV_ERR_NOT_SUPPORTED;
273 }
274
osTegraSocGpioSetPinState(OS_GPU_INFO * pArg1,NvU32 arg2,NvU32 arg3)275 void osTegraSocGpioSetPinState(
276 OS_GPU_INFO *pArg1,
277 NvU32 arg2,
278 NvU32 arg3
279 )
280 {
281 }
282
osTegraSocGpioSetPinDirection(OS_GPU_INFO * pArg1,NvU32 arg2,NvU32 arg3)283 NV_STATUS osTegraSocGpioSetPinDirection(
284 OS_GPU_INFO *pArg1,
285 NvU32 arg2,
286 NvU32 arg3
287 )
288 {
289 return NV_ERR_NOT_SUPPORTED;
290 }
291
osTegraSocGpioGetPinDirection(OS_GPU_INFO * pArg1,NvU32 arg2,NvU32 * pArg3)292 NV_STATUS osTegraSocGpioGetPinDirection(
293 OS_GPU_INFO *pArg1,
294 NvU32 arg2,
295 NvU32 *pArg3
296 )
297 {
298 return NV_ERR_NOT_SUPPORTED;
299 }
300
osTegraSocGpioGetPinNumber(OS_GPU_INFO * pArg1,NvU32 arg2,NvU32 * pArg3)301 NV_STATUS osTegraSocGpioGetPinNumber(
302 OS_GPU_INFO *pArg1,
303 NvU32 arg2,
304 NvU32 *pArg3
305 )
306 {
307 return NV_ERR_NOT_SUPPORTED;
308 }
309
osTegraSocGpioGetPinInterruptStatus(OS_GPU_INFO * pArg1,NvU32 arg2,NvU32 arg3,NvBool * pArg4)310 NV_STATUS osTegraSocGpioGetPinInterruptStatus(
311 OS_GPU_INFO *pArg1,
312 NvU32 arg2,
313 NvU32 arg3,
314 NvBool *pArg4
315 )
316 {
317 return NV_ERR_NOT_SUPPORTED;
318 }
319
osTegraSocGpioSetPinInterrupt(OS_GPU_INFO * pArg1,NvU32 arg2,NvU32 arg3)320 NV_STATUS osTegraSocGpioSetPinInterrupt(
321 OS_GPU_INFO *pArg1,
322 NvU32 arg2,
323 NvU32 arg3
324 )
325 {
326 return NV_ERR_NOT_SUPPORTED;
327 }
328
329 NV_STATUS
osTegraSocResetMipiCal(OS_GPU_INFO * pOsGpuInfo)330 osTegraSocResetMipiCal
331 (
332 OS_GPU_INFO *pOsGpuInfo
333 )
334 {
335 return NV_ERR_NOT_SUPPORTED;
336 }
337
osGetValidWindowHeadMask(OS_GPU_INFO * pArg1,NvU64 * pWindowHeadMask)338 NV_STATUS osGetValidWindowHeadMask
339 (
340 OS_GPU_INFO *pArg1,
341 NvU64 *pWindowHeadMask
342 )
343 {
344 return NV_ERR_NOT_SUPPORTED;
345 }
346
347 NvBool
osTegraSocIsDsiPanelConnected(OS_GPU_INFO * pOsGpuInfo)348 osTegraSocIsDsiPanelConnected
349 (
350 OS_GPU_INFO *pOsGpuInfo
351 )
352 {
353 return NV_FALSE;
354 }
355
356 NV_STATUS
osTegraSocDsiParsePanelProps(OS_GPU_INFO * pOsGpuInfo,void * dsiPanelInfo)357 osTegraSocDsiParsePanelProps
358 (
359 OS_GPU_INFO *pOsGpuInfo,
360 void *dsiPanelInfo
361 )
362 {
363 return NV_ERR_NOT_SUPPORTED;
364 }
365
366 NV_STATUS
osTegraSocDsiPanelEnable(OS_GPU_INFO * pOsGpuInfo,void * dsiPanelInfo)367 osTegraSocDsiPanelEnable
368 (
369 OS_GPU_INFO *pOsGpuInfo,
370 void *dsiPanelInfo
371 )
372 {
373 return NV_ERR_NOT_SUPPORTED;
374 }
375
376 NV_STATUS
osTegraSocDsiPanelReset(OS_GPU_INFO * pOsGpuInfo,void * dsiPanelInfo)377 osTegraSocDsiPanelReset
378 (
379 OS_GPU_INFO *pOsGpuInfo,
380 void *dsiPanelInfo
381 )
382 {
383 return NV_ERR_NOT_SUPPORTED;
384 }
385
386 void
osTegraSocDsiPanelDisable(OS_GPU_INFO * pOsGpuInfo,void * dsiPanelInfo)387 osTegraSocDsiPanelDisable
388 (
389 OS_GPU_INFO *pOsGpuInfo,
390 void *dsiPanelInfo
391 )
392 {
393 return;
394 }
395
396 void
osTegraSocDsiPanelCleanup(OS_GPU_INFO * pOsGpuInfo,void * dsiPanelInfo)397 osTegraSocDsiPanelCleanup
398 (
399 OS_GPU_INFO *pOsGpuInfo,
400 void *dsiPanelInfo
401 )
402 {
403 return;
404 }
405
406 NV_STATUS
osTegraSocHspSemaphoreAcquire(NvU32 ownerId,NvBool bAcquire,NvU64 timeout)407 osTegraSocHspSemaphoreAcquire
408 (
409 NvU32 ownerId,
410 NvBool bAcquire,
411 NvU64 timeout
412 )
413 {
414 return NV_ERR_NOT_SUPPORTED;
415 }
416
417 NvBool
osTegraSocGetHdcpEnabled(OS_GPU_INFO * pOsGpuInfo)418 osTegraSocGetHdcpEnabled(OS_GPU_INFO *pOsGpuInfo)
419 {
420 return NV_TRUE;
421 }
422
423 NvBool
osTegraSocIsSimNetlistNet07(OS_GPU_INFO * pOsGpuInfo)424 osTegraSocIsSimNetlistNet07
425 (
426 OS_GPU_INFO *pOsGpuInfo
427 )
428 {
429 return NV_FALSE;
430 }
431
432 void
osTegraGetDispSMMUStreamIds(OS_GPU_INFO * pOsGpuInfo,NvU32 * dispIsoStreamId,NvU32 * dispNisoStreamId)433 osTegraGetDispSMMUStreamIds
434 (
435 OS_GPU_INFO *pOsGpuInfo,
436 NvU32 *dispIsoStreamId,
437 NvU32 *dispNisoStreamId
438 )
439 {
440 /* NV_U32_MAX is used to indicate that the platform does not support SMMU */
441 *dispIsoStreamId = NV_U32_MAX;
442 *dispNisoStreamId = NV_U32_MAX;
443 }
444 #endif
445
446 NV_STATUS
osTegraSocParseFixedModeTimings(OS_GPU_INFO * pOsGpuInfo,NvU32 dcbIndex,NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS * pTimingsPerStream,NvU8 * pNumTimings)447 osTegraSocParseFixedModeTimings
448 (
449 OS_GPU_INFO *pOsGpuInfo,
450 NvU32 dcbIndex,
451 NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS *pTimingsPerStream,
452 NvU8 *pNumTimings
453 )
454 {
455 return NV_OK;
456 }
457
osLockPageableDataSection(RM_PAGEABLE_SECTION * pSection)458 NV_STATUS osLockPageableDataSection(RM_PAGEABLE_SECTION *pSection)
459 {
460 return NV_OK;
461 }
462
osUnlockPageableDataSection(RM_PAGEABLE_SECTION * pSection)463 NV_STATUS osUnlockPageableDataSection(RM_PAGEABLE_SECTION *pSection)
464 {
465 return NV_OK;
466 }
467
osIsKernelBuffer(void * pArg1,NvU32 arg2)468 NV_STATUS osIsKernelBuffer(void *pArg1, NvU32 arg2)
469 {
470 return NV_OK;
471 }
472
osMapViewToSection(OS_GPU_INFO * pArg1,void * pSectionHandle,void ** ppAddress,NvU64 actualSize,NvU64 sectionOffset,NvBool bIommuEnabled)473 NV_STATUS osMapViewToSection(OS_GPU_INFO *pArg1,
474 void *pSectionHandle,
475 void **ppAddress,
476 NvU64 actualSize,
477 NvU64 sectionOffset,
478 NvBool bIommuEnabled)
479 {
480 return NV_ERR_NOT_SUPPORTED;
481 }
482
osUnmapViewFromSection(OS_GPU_INFO * pArg1,void * pAddress,NvBool bIommuEnabled)483 NV_STATUS osUnmapViewFromSection(OS_GPU_INFO *pArg1,
484 void *pAddress,
485 NvBool bIommuEnabled)
486 {
487 return NV_ERR_NOT_SUPPORTED;
488 }
489
osSrPinSysmem(OS_GPU_INFO * pArg1,NvU64 commitSize,void * pMdl)490 NV_STATUS osSrPinSysmem(
491 OS_GPU_INFO *pArg1,
492 NvU64 commitSize,
493 void *pMdl
494 )
495 {
496 return NV_ERR_NOT_SUPPORTED;
497 }
498
osSrUnpinSysmem(OS_GPU_INFO * pArg1)499 NV_STATUS osSrUnpinSysmem(OS_GPU_INFO *pArg1)
500 {
501 return NV_ERR_NOT_SUPPORTED;
502 }
503
osCreateMemFromOsDescriptorInternal(OBJGPU * pGpu,void * pAddress,NvU32 flags,NvU64 size,MEMORY_DESCRIPTOR ** ppMemDesc,NvBool bCachedKernel,RS_PRIV_LEVEL privilegeLevel)504 NV_STATUS osCreateMemFromOsDescriptorInternal(
505 OBJGPU *pGpu,
506 void *pAddress,
507 NvU32 flags,
508 NvU64 size,
509 MEMORY_DESCRIPTOR **ppMemDesc,
510 NvBool bCachedKernel,
511 RS_PRIV_LEVEL privilegeLevel
512 )
513 {
514 return NV_ERR_NOT_SUPPORTED;
515 }
516
osReserveCpuAddressSpaceUpperBound(void ** ppSectionHandle,NvU64 maxSectionSize)517 NV_STATUS osReserveCpuAddressSpaceUpperBound(void **ppSectionHandle,
518 NvU64 maxSectionSize)
519 {
520 return NV_ERR_NOT_SUPPORTED;
521 }
522
osReleaseCpuAddressSpaceUpperBound(void * pSectionHandle)523 void osReleaseCpuAddressSpaceUpperBound(void *pSectionHandle)
524 {
525 }
526
osIoWriteDword(NvU32 port,NvU32 data)527 void osIoWriteDword(
528 NvU32 port,
529 NvU32 data
530 )
531 {
532 }
533
osIoReadDword(NvU32 port)534 NvU32 osIoReadDword(
535 NvU32 port
536 )
537 {
538 return 0;
539 }
540
osIsVga(OS_GPU_INFO * pArg1,NvBool bIsGpuPrimaryDevice)541 NvBool osIsVga(
542 OS_GPU_INFO *pArg1,
543 NvBool bIsGpuPrimaryDevice
544 )
545 {
546 return bIsGpuPrimaryDevice;
547 }
548
osInitOSHwInfo(OBJGPU * pGpu)549 void osInitOSHwInfo(
550 OBJGPU *pGpu
551 )
552 {
553 }
554
osDestroyOSHwInfo(OBJGPU * pGpu)555 void osDestroyOSHwInfo(
556 OBJGPU *pGpu
557 )
558 {
559 }
560
osDoFunctionLevelReset(OBJGPU * pGpu)561 NV_STATUS osDoFunctionLevelReset(
562 OBJGPU *pGpu
563 )
564 {
565 return NV_ERR_NOT_SUPPORTED;
566 }
567
osGrService(OS_GPU_INFO * pOsGpuInfo,NvU32 grIdx,NvU32 intr,NvU32 nstatus,NvU32 addr,NvU32 dataLo)568 NvBool osGrService(
569 OS_GPU_INFO *pOsGpuInfo,
570 NvU32 grIdx,
571 NvU32 intr,
572 NvU32 nstatus,
573 NvU32 addr,
574 NvU32 dataLo
575 )
576 {
577 return NV_FALSE;
578 }
579
osDispService(NvU32 Intr0,NvU32 Intr1)580 NvBool osDispService(
581 NvU32 Intr0,
582 NvU32 Intr1
583 )
584 {
585 return NV_FALSE;
586 }
587
osDeferredIsr(OBJGPU * pGpu)588 NV_STATUS osDeferredIsr(
589 OBJGPU *pGpu
590 )
591 {
592 return NV_OK;
593 }
594
osSetSurfaceName(void * pDescriptor,char * name)595 void osSetSurfaceName(
596 void *pDescriptor,
597 char *name
598 )
599 {
600 }
601
osGetAcpiTable(NvU32 tableSignature,void ** ppTable,NvU32 tableSize,NvU32 * retSize)602 NV_STATUS osGetAcpiTable(
603 NvU32 tableSignature,
604 void **ppTable,
605 NvU32 tableSize,
606 NvU32 *retSize
607 )
608 {
609 return NV_ERR_NOT_SUPPORTED;
610 }
611
osInitGetAcpiTable(void)612 NV_STATUS osInitGetAcpiTable(void)
613 {
614 return NV_ERR_NOT_SUPPORTED;
615 }
616
osDbgBugCheckOnAssert(void)617 void osDbgBugCheckOnAssert(void)
618 {
619 return;
620 }
621
osQueueDpc(OBJGPU * pGpu)622 NvBool osQueueDpc(OBJGPU *pGpu)
623 {
624 return NV_FALSE;
625 }
626
osBugCheckOnTimeoutEnabled(void)627 NvBool osBugCheckOnTimeoutEnabled(void)
628 {
629 return NV_FALSE;
630 }
631
osDbgBreakpointEnabled(void)632 NvBool osDbgBreakpointEnabled(void)
633 {
634 return NV_TRUE;
635 }
636
osNvifMethod(OBJGPU * pGpu,NvU32 func,NvU32 subFunc,void * pInParam,NvU16 inParamSize,NvU32 * pOutStatus,void * pOutData,NvU16 * pOutDataSize)637 NV_STATUS osNvifMethod(
638 OBJGPU *pGpu,
639 NvU32 func,
640 NvU32 subFunc,
641 void *pInParam,
642 NvU16 inParamSize,
643 NvU32 *pOutStatus,
644 void *pOutData,
645 NvU16 *pOutDataSize
646 )
647 {
648 return NV_ERR_NOT_SUPPORTED;
649 }
650
osNvifInitialize(OBJGPU * pGpu)651 NV_STATUS osNvifInitialize(
652 OBJGPU *pGpu
653 )
654 {
655 return NV_ERR_NOT_SUPPORTED;
656 }
657
658 NV_STATUS
osGetUefiVariable(const char * pName,LPGUID pGuid,NvU8 * pBuffer,NvU32 * pSize)659 osGetUefiVariable
660 (
661 const char *pName,
662 LPGUID pGuid,
663 NvU8 *pBuffer,
664 NvU32 *pSize
665 )
666 {
667 return NV_ERR_NOT_SUPPORTED;
668 }
669
670 NV_STATUS
osGetNvGlobalRegistryDword(OBJGPU * pGpu,const char * pRegParmStr,NvU32 * pData)671 osGetNvGlobalRegistryDword
672 (
673 OBJGPU *pGpu,
674 const char *pRegParmStr,
675 NvU32 *pData
676 )
677 {
678 return NV_ERR_NOT_SUPPORTED;
679 }
680
681 #if !RMCFG_FEATURE_PLATFORM_DCE /* dce_core_rm_clk_reset.c */ && \
682 (!RMCFG_FEATURE_PLATFORM_UNIX || !RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY || \
683 RMCFG_FEATURE_DCE_CLIENT_RM /* osSocNvDisp.c */ )
684 NV_STATUS
osTegraSocEnableClk(OS_GPU_INFO * pOsGpuInfo,NvU32 whichClkRM)685 osTegraSocEnableClk
686 (
687 OS_GPU_INFO *pOsGpuInfo,
688 NvU32 whichClkRM
689 )
690 {
691 return NV_ERR_NOT_SUPPORTED;
692 }
693
694 NV_STATUS
osTegraSocDisableClk(OS_GPU_INFO * pOsGpuInfo,NvU32 whichClkRM)695 osTegraSocDisableClk
696 (
697 OS_GPU_INFO *pOsGpuInfo,
698 NvU32 whichClkRM
699 )
700 {
701 return NV_ERR_NOT_SUPPORTED;
702 }
703
704 NV_STATUS
osTegraSocGetCurrFreqKHz(OS_GPU_INFO * pOsGpuInfo,NvU32 whichClkRM,NvU32 * pCurrFreqKHz)705 osTegraSocGetCurrFreqKHz
706 (
707 OS_GPU_INFO *pOsGpuInfo,
708 NvU32 whichClkRM,
709 NvU32 *pCurrFreqKHz
710 )
711 {
712 return NV_ERR_NOT_SUPPORTED;
713 }
714
715 NV_STATUS
osTegraSocGetMaxFreqKHz(OS_GPU_INFO * pOsGpuInfo,NvU32 whichClkRM,NvU32 * pMaxFreqKHz)716 osTegraSocGetMaxFreqKHz
717 (
718 OS_GPU_INFO *pOsGpuInfo,
719 NvU32 whichClkRM,
720 NvU32 *pMaxFreqKHz
721 )
722 {
723 return NV_ERR_NOT_SUPPORTED;
724 }
725
726 NV_STATUS
osTegraSocGetMinFreqKHz(OS_GPU_INFO * pOsGpuInfo,NvU32 whichClkRM,NvU32 * pMinFreqKHz)727 osTegraSocGetMinFreqKHz
728 (
729 OS_GPU_INFO *pOsGpuInfo,
730 NvU32 whichClkRM,
731 NvU32 *pMinFreqKHz
732 )
733 {
734 return NV_ERR_NOT_SUPPORTED;
735 }
736
737 NV_STATUS
osTegraSocSetFreqKHz(OS_GPU_INFO * pOsGpuInfo,NvU32 whichClkRM,NvU32 reqFreqKHz)738 osTegraSocSetFreqKHz
739 (
740 OS_GPU_INFO *pOsGpuInfo,
741 NvU32 whichClkRM,
742 NvU32 reqFreqKHz
743 )
744 {
745 return NV_ERR_NOT_SUPPORTED;
746 }
747
748 NV_STATUS
osTegraSocSetParent(OS_GPU_INFO * pOsGpuInfo,NvU32 whichClkRMsource,NvU32 whichClkRMparent)749 osTegraSocSetParent
750 (
751 OS_GPU_INFO *pOsGpuInfo,
752 NvU32 whichClkRMsource,
753 NvU32 whichClkRMparent
754 )
755 {
756 return NV_ERR_NOT_SUPPORTED;
757 }
758
759 NV_STATUS
osTegraSocGetParent(OS_GPU_INFO * pOsGpuInfo,NvU32 whichClkRMsource,NvU32 * pWhichClkRMparent)760 osTegraSocGetParent
761 (
762 OS_GPU_INFO *pOsGpuInfo,
763 NvU32 whichClkRMsource,
764 NvU32 *pWhichClkRMparent
765 )
766 {
767 return NV_ERR_NOT_SUPPORTED;
768 }
769
770 NV_STATUS
osTegraSocDeviceReset(OS_GPU_INFO * pOsGpuInfo)771 osTegraSocDeviceReset
772 (
773 OS_GPU_INFO *pOsGpuInfo
774 )
775 {
776 return NV_ERR_NOT_SUPPORTED;
777 }
778
779 NV_STATUS
osTegraSocPmPowergate(OS_GPU_INFO * pOsGpuInfo)780 osTegraSocPmPowergate
781 (
782 OS_GPU_INFO *pOsGpuInfo
783 )
784 {
785 return NV_ERR_NOT_SUPPORTED;
786 }
787
788 NV_STATUS
osTegraSocPmUnpowergate(OS_GPU_INFO * pOsGpuInfo)789 osTegraSocPmUnpowergate
790 (
791 OS_GPU_INFO *pOsGpuInfo
792 )
793 {
794 return NV_ERR_NOT_SUPPORTED;
795 }
796
797 NvU32
osTegraSocFuseRegRead(NvU32 addr)798 osTegraSocFuseRegRead(NvU32 addr)
799 {
800 return 0;
801 }
802 #endif
803
804 #if !(RMCFG_FEATURE_PLATFORM_UNIX) || \
805 (RMCFG_FEATURE_PLATFORM_UNIX && !RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY)
806 NV_STATUS
osTegraSocDpUphyPllInit(OS_GPU_INFO * pOsGpuInfo,NvU32 link_rate,NvU32 lanes)807 osTegraSocDpUphyPllInit(OS_GPU_INFO *pOsGpuInfo, NvU32 link_rate, NvU32 lanes)
808 {
809 return NV_ERR_NOT_SUPPORTED;
810 }
811
812 NV_STATUS
osTegraSocDpUphyPllDeInit(OS_GPU_INFO * pOsGpuInfo)813 osTegraSocDpUphyPllDeInit(OS_GPU_INFO *pOsGpuInfo)
814 {
815 return NV_ERR_NOT_SUPPORTED;
816 }
817
818 #endif
819
820
821