1 /*
2 * SPDX-FileCopyrightText: Copyright (c) 2008-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
3 * SPDX-License-Identifier: MIT
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23 /*
24 * WARNING: This is an autogenerated file. DO NOT EDIT.
25 * This file is generated using below files:
26 * template file: kernel/inc/vgpu/gt_rpc-structures.h
27 * definition file: kernel/inc/vgpu/rpc-structures.def
28 */
29
30
31 #ifdef RPC_STRUCTURES
32 // These structures will be used for the communication between the vmioplugin & guest RM.
33 #define SDK_STRUCTURES
34 #include "g_sdk-structures.h"
35 #undef SDK_STRUCTURES
36 typedef struct rpc_set_guest_system_info_v03_00
37 {
38 NvU32 vgxVersionMajorNum;
39 NvU32 vgxVersionMinorNum;
40 NvU32 guestDriverVersionBufferLength;
41 NvU32 guestVersionBufferLength;
42 NvU32 guestTitleBufferLength;
43 NvU32 guestClNum;
44 char guestDriverVersion[0x100];
45 char guestVersion[0x100];
46 char guestTitle[0x100];
47 } rpc_set_guest_system_info_v03_00;
48
49 typedef rpc_set_guest_system_info_v03_00 rpc_set_guest_system_info_v;
50
51 typedef struct rpc_set_guest_system_info_ext_v15_02
52 {
53 char guestDriverBranch[0x100];
54 NvU32 domain;
55 NvU16 bus;
56 NvU16 device;
57 } rpc_set_guest_system_info_ext_v15_02;
58
59 typedef struct rpc_set_guest_system_info_ext_v25_1B
60 {
61 char guestDriverBranch[0x100];
62 NvU32 domain;
63 NvU16 bus;
64 NvU16 device;
65 NvU32 gridBuildCsp;
66 } rpc_set_guest_system_info_ext_v25_1B;
67
68 typedef rpc_set_guest_system_info_ext_v25_1B rpc_set_guest_system_info_ext_v;
69
70 typedef struct rpc_alloc_root_v07_00
71 {
72 NvHandle hClient;
73 NvU32 processID;
74 char processName[0x64];
75 } rpc_alloc_root_v07_00;
76
77 typedef rpc_alloc_root_v07_00 rpc_alloc_root_v;
78
79 typedef struct rpc_alloc_memory_v13_01
80 {
81 NvHandle hClient;
82 NvHandle hDevice;
83 NvHandle hMemory;
84 NvU32 hClass;
85 NvU32 flags;
86 NvU32 pteAdjust;
87 NvU32 format;
88 NvU64 length NV_ALIGN_BYTES(8);
89 NvU32 pageCount;
90 struct pte_desc pteDesc;
91 } rpc_alloc_memory_v13_01;
92
93 typedef rpc_alloc_memory_v13_01 rpc_alloc_memory_v;
94
95 typedef struct rpc_alloc_channel_dma_v1F_04
96 {
97 NvHandle hClient;
98 NvHandle hDevice;
99 NvHandle hChannel;
100 NvU32 hClass;
101 NvU32 flags;
102 NV_CHANNEL_ALLOC_PARAMS_v1F_04 params;
103 NvU32 chid;
104 } rpc_alloc_channel_dma_v1F_04;
105
106 typedef rpc_alloc_channel_dma_v1F_04 rpc_alloc_channel_dma_v;
107
108 typedef struct rpc_alloc_object_v25_08
109 {
110 NvHandle hClient;
111 NvHandle hParent;
112 NvHandle hObject;
113 NvU32 hClass;
114 NvU32 param_len;
115 alloc_object_params_v25_08 params;
116 } rpc_alloc_object_v25_08;
117
118 typedef rpc_alloc_object_v25_08 rpc_alloc_object_v;
119
120 typedef struct rpc_free_v03_00
121 {
122 NVOS00_PARAMETERS_v03_00 params;
123 } rpc_free_v03_00;
124
125 typedef rpc_free_v03_00 rpc_free_v;
126
127 typedef struct rpc_log_v03_00
128 {
129 NvU32 level;
130 NvU32 log_len;
131 char log_msg[];
132 } rpc_log_v03_00;
133
134 typedef rpc_log_v03_00 rpc_log_v;
135
136 typedef struct rpc_map_memory_dma_v03_00
137 {
138 NVOS46_PARAMETERS_v03_00 params;
139 } rpc_map_memory_dma_v03_00;
140
141 typedef rpc_map_memory_dma_v03_00 rpc_map_memory_dma_v;
142
143 typedef struct rpc_unmap_memory_dma_v03_00
144 {
145 NVOS47_PARAMETERS_v03_00 params;
146 } rpc_unmap_memory_dma_v03_00;
147
148 typedef rpc_unmap_memory_dma_v03_00 rpc_unmap_memory_dma_v;
149
150 typedef struct rpc_alloc_subdevice_v08_01
151 {
152 NvU32 subDeviceInst;
153 NVOS21_PARAMETERS_v03_00 params;
154 } rpc_alloc_subdevice_v08_01;
155
156 typedef rpc_alloc_subdevice_v08_01 rpc_alloc_subdevice_v;
157
158 typedef struct rpc_dup_object_v03_00
159 {
160 NVOS55_PARAMETERS_v03_00 params;
161 } rpc_dup_object_v03_00;
162
163 typedef rpc_dup_object_v03_00 rpc_dup_object_v;
164
165 typedef struct rpc_idle_channels_v03_00
166 {
167 NvU32 flags;
168 NvU32 timeout;
169 NvU32 nchannels;
170 idle_channel_list_v03_00 channel_list[];
171 } rpc_idle_channels_v03_00;
172
173 typedef rpc_idle_channels_v03_00 rpc_idle_channels_v;
174
175 typedef struct rpc_alloc_event_v03_00
176 {
177 NvHandle hClient;
178 NvHandle hParentClient;
179 NvHandle hChannel;
180 NvHandle hObject;
181 NvHandle hEvent;
182 NvU32 hClass;
183 NvU32 notifyIndex;
184 } rpc_alloc_event_v03_00;
185
186 typedef rpc_alloc_event_v03_00 rpc_alloc_event_v;
187
188 typedef struct rpc_rm_api_control_v25_0D
189 {
190 NVOS54_PARAMETERS_v03_00 params;
191 NvP64 rm_api_params NV_ALIGN_BYTES(8);
192 } rpc_rm_api_control_v25_0D;
193
194 typedef struct rpc_rm_api_control_v25_0F
195 {
196 NVOS54_PARAMETERS_v03_00 params;
197 NvP64 rm_api_params NV_ALIGN_BYTES(8);
198 } rpc_rm_api_control_v25_0F;
199
200 typedef struct rpc_rm_api_control_v25_10
201 {
202 NVOS54_PARAMETERS_v03_00 params;
203 NvP64 rm_api_params NV_ALIGN_BYTES(8);
204 } rpc_rm_api_control_v25_10;
205
206 typedef struct rpc_rm_api_control_v25_14
207 {
208 NVOS54_PARAMETERS_v03_00 params;
209 NvP64 rm_api_params NV_ALIGN_BYTES(8);
210 } rpc_rm_api_control_v25_14;
211
212 typedef struct rpc_rm_api_control_v25_15
213 {
214 NVOS54_PARAMETERS_v03_00 params;
215 NvP64 rm_api_params NV_ALIGN_BYTES(8);
216 } rpc_rm_api_control_v25_15;
217
218 typedef struct rpc_rm_api_control_v25_16
219 {
220 NVOS54_PARAMETERS_v03_00 params;
221 NvP64 rm_api_params NV_ALIGN_BYTES(8);
222 } rpc_rm_api_control_v25_16;
223
224 typedef struct rpc_rm_api_control_v25_17
225 {
226 NVOS54_PARAMETERS_v03_00 params;
227 NvP64 rm_api_params NV_ALIGN_BYTES(8);
228 } rpc_rm_api_control_v25_17;
229
230 typedef struct rpc_rm_api_control_v25_18
231 {
232 NVOS54_PARAMETERS_v03_00 params;
233 NvP64 rm_api_params NV_ALIGN_BYTES(8);
234 } rpc_rm_api_control_v25_18;
235
236 typedef struct rpc_rm_api_control_v25_19
237 {
238 NVOS54_PARAMETERS_v03_00 params;
239 NvP64 rm_api_params NV_ALIGN_BYTES(8);
240 } rpc_rm_api_control_v25_19;
241
242 typedef struct rpc_rm_api_control_v25_1A
243 {
244 NVOS54_PARAMETERS_v03_00 params;
245 NvP64 rm_api_params NV_ALIGN_BYTES(8);
246 } rpc_rm_api_control_v25_1A;
247
248 typedef rpc_rm_api_control_v25_1A rpc_rm_api_control_v;
249
250 typedef struct rpc_alloc_share_device_v03_00
251 {
252 NvHandle hClient;
253 NvHandle hDevice;
254 NvU32 hClass;
255 NV_DEVICE_ALLOCATION_PARAMETERS_v03_00 params;
256 } rpc_alloc_share_device_v03_00;
257
258 typedef rpc_alloc_share_device_v03_00 rpc_alloc_share_device_v;
259
260 typedef struct rpc_get_engine_utilization_v1F_0E
261 {
262 NvHandle hClient;
263 NvHandle hObject;
264 NvU32 cmd;
265 vgpuGetEngineUtilization_data_v1F_0E params;
266 } rpc_get_engine_utilization_v1F_0E;
267
268 typedef rpc_get_engine_utilization_v1F_0E rpc_get_engine_utilization_v;
269
270 typedef struct rpc_perf_get_level_info_v03_00
271 {
272 NvHandle hClient;
273 NvHandle hObject;
274 NvU32 level;
275 NvU32 flags;
276 NvU32 perfGetClkInfoListSize;
277 NvU32 param_size;
278 NvU32 params[];
279 } rpc_perf_get_level_info_v03_00;
280
281 typedef rpc_perf_get_level_info_v03_00 rpc_perf_get_level_info_v;
282
283 typedef struct rpc_set_surface_properties_v07_07
284 {
285 NvHandle hClient;
286 NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_v07_07 params;
287 } rpc_set_surface_properties_v07_07;
288
289 typedef rpc_set_surface_properties_v07_07 rpc_set_surface_properties_v;
290
291 typedef struct rpc_cleanup_surface_v03_00
292 {
293 NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_v03_00 params;
294 } rpc_cleanup_surface_v03_00;
295
296 typedef rpc_cleanup_surface_v03_00 rpc_cleanup_surface_v;
297
298 typedef struct rpc_unloading_guest_driver_v1F_07
299 {
300 NvBool bInPMTransition;
301 NvBool bGc6Entering;
302 NvU32 newLevel;
303 } rpc_unloading_guest_driver_v1F_07;
304
305 typedef rpc_unloading_guest_driver_v1F_07 rpc_unloading_guest_driver_v;
306
307 typedef struct rpc_gpu_exec_reg_ops_v12_01
308 {
309 NvHandle hClient;
310 NvHandle hObject;
311 gpu_exec_reg_ops_v12_01 params;
312 } rpc_gpu_exec_reg_ops_v12_01;
313
314 typedef rpc_gpu_exec_reg_ops_v12_01 rpc_gpu_exec_reg_ops_v;
315
316 typedef struct rpc_get_static_data_v25_0E
317 {
318 NvU32 offset;
319 NvU32 size;
320 NvU8 payload[];
321 } rpc_get_static_data_v25_0E;
322
323 typedef rpc_get_static_data_v25_0E rpc_get_static_data_v;
324
325 typedef struct rpc_get_consolidated_gr_static_info_v1B_04
326 {
327 NvU32 offset;
328 NvU32 size;
329 NvU8 payload[];
330 } rpc_get_consolidated_gr_static_info_v1B_04;
331
332 typedef rpc_get_consolidated_gr_static_info_v1B_04 rpc_get_consolidated_gr_static_info_v;
333
334 typedef struct rpc_set_page_directory_v1E_05
335 {
336 NvHandle hClient;
337 NvHandle hDevice;
338 NvU32 pasid;
339 NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05 params;
340 } rpc_set_page_directory_v1E_05;
341
342 typedef rpc_set_page_directory_v1E_05 rpc_set_page_directory_v;
343
344 typedef struct rpc_unset_page_directory_v1E_05
345 {
346 NvHandle hClient;
347 NvHandle hDevice;
348 NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05 params;
349 } rpc_unset_page_directory_v1E_05;
350
351 typedef rpc_unset_page_directory_v1E_05 rpc_unset_page_directory_v;
352
353 typedef struct rpc_get_gsp_static_info_v14_00
354 {
355 NvU32 data;
356 } rpc_get_gsp_static_info_v14_00;
357
358 typedef rpc_get_gsp_static_info_v14_00 rpc_get_gsp_static_info_v;
359
360 typedef struct rpc_update_bar_pde_v15_00
361 {
362 UpdateBarPde_v15_00 info;
363 } rpc_update_bar_pde_v15_00;
364
365 typedef rpc_update_bar_pde_v15_00 rpc_update_bar_pde_v;
366
367 typedef struct rpc_get_encoder_capacity_v07_00
368 {
369 NvHandle hClient;
370 NvHandle hObject;
371 NvU32 encoderCapacity;
372 } rpc_get_encoder_capacity_v07_00;
373
374 typedef rpc_get_encoder_capacity_v07_00 rpc_get_encoder_capacity_v;
375
376 typedef struct rpc_vgpu_pf_reg_read32_v15_00
377 {
378 NvU64 address NV_ALIGN_BYTES(8);
379 NvU32 value;
380 NvU32 grEngId;
381 } rpc_vgpu_pf_reg_read32_v15_00;
382
383 typedef rpc_vgpu_pf_reg_read32_v15_00 rpc_vgpu_pf_reg_read32_v;
384
385 typedef struct rpc_ctrl_set_vgpu_fb_usage_v1A_08
386 {
387 NVA080_CTRL_SET_FB_USAGE_PARAMS_v07_02 setFbUsage;
388 } rpc_ctrl_set_vgpu_fb_usage_v1A_08;
389
390 typedef rpc_ctrl_set_vgpu_fb_usage_v1A_08 rpc_ctrl_set_vgpu_fb_usage_v;
391
392 typedef struct rpc_ctrl_nvenc_sw_session_update_info_v1A_09
393 {
394 NvHandle hClient;
395 NvHandle hObject;
396 NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01 nvencSessionUpdate;
397 } rpc_ctrl_nvenc_sw_session_update_info_v1A_09;
398
399 typedef rpc_ctrl_nvenc_sw_session_update_info_v1A_09 rpc_ctrl_nvenc_sw_session_update_info_v;
400
401 typedef struct rpc_ctrl_reset_channel_v1A_09
402 {
403 NvHandle hClient;
404 NvHandle hObject;
405 NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01 resetChannel;
406 } rpc_ctrl_reset_channel_v1A_09;
407
408 typedef rpc_ctrl_reset_channel_v1A_09 rpc_ctrl_reset_channel_v;
409
410 typedef struct rpc_ctrl_reset_isolated_channel_v1A_09
411 {
412 NvHandle hClient;
413 NvHandle hObject;
414 NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00 resetIsolatedChannel;
415 } rpc_ctrl_reset_isolated_channel_v1A_09;
416
417 typedef rpc_ctrl_reset_isolated_channel_v1A_09 rpc_ctrl_reset_isolated_channel_v;
418
419 typedef struct rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09
420 {
421 NvHandle hClient;
422 NvHandle hObject;
423 NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09 handleVfPriFault;
424 } rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09;
425
426 typedef rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09 rpc_ctrl_gpu_handle_vf_pri_fault_v;
427
428 typedef struct rpc_ctrl_perf_boost_v1A_09
429 {
430 NvHandle hClient;
431 NvHandle hObject;
432 NV2080_CTRL_PERF_BOOST_PARAMS_v03_00 perfBoost;
433 } rpc_ctrl_perf_boost_v1A_09;
434
435 typedef rpc_ctrl_perf_boost_v1A_09 rpc_ctrl_perf_boost_v;
436
437 typedef struct rpc_ctrl_get_zbc_clear_table_v1A_09
438 {
439 NvHandle hClient;
440 NvHandle hObject;
441 NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00 getZbcClearTable;
442 } rpc_ctrl_get_zbc_clear_table_v1A_09;
443
444 typedef rpc_ctrl_get_zbc_clear_table_v1A_09 rpc_ctrl_get_zbc_clear_table_v;
445
446 typedef struct rpc_ctrl_set_zbc_color_clear_v1A_09
447 {
448 NvHandle hClient;
449 NvHandle hObject;
450 NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00 setZbcColorClr;
451 } rpc_ctrl_set_zbc_color_clear_v1A_09;
452
453 typedef rpc_ctrl_set_zbc_color_clear_v1A_09 rpc_ctrl_set_zbc_color_clear_v;
454
455 typedef struct rpc_ctrl_set_zbc_depth_clear_v1A_09
456 {
457 NvHandle hClient;
458 NvHandle hObject;
459 NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00 setZbcDepthClr;
460 } rpc_ctrl_set_zbc_depth_clear_v1A_09;
461
462 typedef rpc_ctrl_set_zbc_depth_clear_v1A_09 rpc_ctrl_set_zbc_depth_clear_v;
463
464 typedef struct rpc_ctrl_gpfifo_schedule_v1A_0A
465 {
466 NvHandle hClient;
467 NvHandle hObject;
468 NvU32 cmd;
469 NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00 gpfifoSchedule;
470 } rpc_ctrl_gpfifo_schedule_v1A_0A;
471
472 typedef rpc_ctrl_gpfifo_schedule_v1A_0A rpc_ctrl_gpfifo_schedule_v;
473
474 typedef struct rpc_ctrl_set_timeslice_v1A_0A
475 {
476 NvHandle hClient;
477 NvHandle hObject;
478 NVA06C_CTRL_TIMESLICE_PARAMS_v06_00 setTimeSlice;
479 } rpc_ctrl_set_timeslice_v1A_0A;
480
481 typedef rpc_ctrl_set_timeslice_v1A_0A rpc_ctrl_set_timeslice_v;
482
483 typedef struct rpc_ctrl_fifo_disable_channels_v1A_0A
484 {
485 NvHandle hClient;
486 NvHandle hObject;
487 NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00 fifoDisableChannels;
488 } rpc_ctrl_fifo_disable_channels_v1A_0A;
489
490 typedef rpc_ctrl_fifo_disable_channels_v1A_0A rpc_ctrl_fifo_disable_channels_v;
491
492 typedef struct rpc_ctrl_preempt_v1A_0A
493 {
494 NvHandle hClient;
495 NvHandle hObject;
496 NVA06C_CTRL_PREEMPT_PARAMS_v09_0A cmdPreempt;
497 } rpc_ctrl_preempt_v1A_0A;
498
499 typedef rpc_ctrl_preempt_v1A_0A rpc_ctrl_preempt_v;
500
501 typedef struct rpc_ctrl_set_tsg_interleave_level_v1A_0A
502 {
503 NvHandle hClient;
504 NvHandle hObject;
505 NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02 interleaveLevelTSG;
506 } rpc_ctrl_set_tsg_interleave_level_v1A_0A;
507
508 typedef rpc_ctrl_set_tsg_interleave_level_v1A_0A rpc_ctrl_set_tsg_interleave_level_v;
509
510 typedef struct rpc_ctrl_set_channel_interleave_level_v1A_0A
511 {
512 NvHandle hClient;
513 NvHandle hObject;
514 NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02 interleaveLevelChannel;
515 } rpc_ctrl_set_channel_interleave_level_v1A_0A;
516
517 typedef rpc_ctrl_set_channel_interleave_level_v1A_0A rpc_ctrl_set_channel_interleave_level_v;
518
519 typedef struct rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E
520 {
521 NvHandle hClient;
522 NvHandle hObject;
523 NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01 ctrlParams;
524 } rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E;
525
526 typedef rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E rpc_ctrl_gr_ctxsw_preemption_bind_v;
527
528 typedef struct rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E
529 {
530 NvHandle hClient;
531 NvHandle hObject;
532 NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01 ctrlParams;
533 } rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E;
534
535 typedef rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E rpc_ctrl_gr_set_ctxsw_preemption_mode_v;
536
537 typedef struct rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E
538 {
539 NvHandle hClient;
540 NvHandle hObject;
541 NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00 ctrlParams;
542 } rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E;
543
544 typedef rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E rpc_ctrl_gr_ctxsw_zcull_bind_v;
545
546 typedef struct rpc_ctrl_gpu_initialize_ctx_v1A_0E
547 {
548 NvHandle hClient;
549 NvHandle hObject;
550 NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00 ctrlParams;
551 } rpc_ctrl_gpu_initialize_ctx_v1A_0E;
552
553 typedef rpc_ctrl_gpu_initialize_ctx_v1A_0E rpc_ctrl_gpu_initialize_ctx_v;
554
555 typedef struct rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04
556 {
557 NvHandle hClient;
558 NvHandle hObject;
559 NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04 ctrlParams;
560 } rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04;
561
562 typedef rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04 rpc_ctrl_vaspace_copy_server_reserved_pdes_v;
563
564 typedef struct rpc_ctrl_mc_service_interrupts_v1A_0E
565 {
566 NvHandle hClient;
567 NvHandle hObject;
568 NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01 ctrlParams;
569 } rpc_ctrl_mc_service_interrupts_v1A_0E;
570
571 typedef rpc_ctrl_mc_service_interrupts_v1A_0E rpc_ctrl_mc_service_interrupts_v;
572
573 typedef struct rpc_ctrl_get_p2p_caps_v2_v1F_0D
574 {
575 NvU8 iter;
576 NvU32 gpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS];
577 NvU32 gpuCount;
578 NvU32 p2pCaps;
579 NvU32 p2pOptimalReadCEs;
580 NvU32 p2pOptimalWriteCEs;
581 NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D];
582 NvU32 busPeerIds[VGPU_RPC_GET_P2P_CAPS_V2_MAX_GPUS_SQUARED_PER_RPC];
583 } rpc_ctrl_get_p2p_caps_v2_v1F_0D;
584
585 typedef rpc_ctrl_get_p2p_caps_v2_v1F_0D rpc_ctrl_get_p2p_caps_v2_v;
586
587 typedef struct rpc_ctrl_subdevice_get_p2p_caps_v21_02
588 {
589 NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02 ctrlParams;
590 } rpc_ctrl_subdevice_get_p2p_caps_v21_02;
591
592 typedef rpc_ctrl_subdevice_get_p2p_caps_v21_02 rpc_ctrl_subdevice_get_p2p_caps_v;
593
594 typedef struct rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C
595 {
596 NvHandle hClient;
597 NvHandle hObject;
598 NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00 ctrlParams;
599 } rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C;
600
601 typedef rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C rpc_ctrl_dbg_clear_all_sm_error_states_v;
602
603 typedef struct rpc_ctrl_dbg_read_all_sm_error_states_v21_06
604 {
605 NvHandle hClient;
606 NvHandle hObject;
607 NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06 ctrlParams;
608 } rpc_ctrl_dbg_read_all_sm_error_states_v21_06;
609
610 typedef rpc_ctrl_dbg_read_all_sm_error_states_v21_06 rpc_ctrl_dbg_read_all_sm_error_states_v;
611
612 typedef struct rpc_ctrl_dbg_set_exception_mask_v1A_0C
613 {
614 NvHandle hClient;
615 NvHandle hObject;
616 NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00 ctrlParams;
617 } rpc_ctrl_dbg_set_exception_mask_v1A_0C;
618
619 typedef rpc_ctrl_dbg_set_exception_mask_v1A_0C rpc_ctrl_dbg_set_exception_mask_v;
620
621 typedef struct rpc_ctrl_gpu_promote_ctx_v1A_20
622 {
623 NvHandle hClient;
624 NvHandle hObject;
625 NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20 promoteCtx;
626 } rpc_ctrl_gpu_promote_ctx_v1A_20;
627
628 typedef rpc_ctrl_gpu_promote_ctx_v1A_20 rpc_ctrl_gpu_promote_ctx_v;
629
630 typedef struct rpc_ctrl_dbg_suspend_context_v1A_10
631 {
632 NvHandle hClient;
633 NvHandle hObject;
634 NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06 ctrlParams;
635 } rpc_ctrl_dbg_suspend_context_v1A_10;
636
637 typedef rpc_ctrl_dbg_suspend_context_v1A_10 rpc_ctrl_dbg_suspend_context_v;
638
639 typedef struct rpc_ctrl_dbg_resume_context_v1A_10
640 {
641 NvHandle hClient;
642 NvHandle hObject;
643 } rpc_ctrl_dbg_resume_context_v1A_10;
644
645 typedef rpc_ctrl_dbg_resume_context_v1A_10 rpc_ctrl_dbg_resume_context_v;
646
647 typedef struct rpc_ctrl_dbg_exec_reg_ops_v1A_10
648 {
649 NvHandle hClient;
650 NvHandle hObject;
651 NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06 ctrlParams;
652 } rpc_ctrl_dbg_exec_reg_ops_v1A_10;
653
654 typedef rpc_ctrl_dbg_exec_reg_ops_v1A_10 rpc_ctrl_dbg_exec_reg_ops_v;
655
656 typedef struct rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10
657 {
658 NvHandle hClient;
659 NvHandle hObject;
660 NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06 ctrlParams;
661 } rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10;
662
663 typedef rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10 rpc_ctrl_dbg_set_mode_mmu_debug_v;
664
665 typedef struct rpc_ctrl_dbg_read_single_sm_error_state_v21_06
666 {
667 NvHandle hClient;
668 NvHandle hObject;
669 NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06 ctrlParams;
670 } rpc_ctrl_dbg_read_single_sm_error_state_v21_06;
671
672 typedef rpc_ctrl_dbg_read_single_sm_error_state_v21_06 rpc_ctrl_dbg_read_single_sm_error_state_v;
673
674 typedef struct rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10
675 {
676 NvHandle hClient;
677 NvHandle hObject;
678 NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06 ctrlParams;
679 } rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10;
680
681 typedef rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10 rpc_ctrl_dbg_clear_single_sm_error_state_v;
682
683 typedef struct rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10
684 {
685 NvHandle hClient;
686 NvHandle hObject;
687 NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06 ctrlParams;
688 } rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10;
689
690 typedef rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10 rpc_ctrl_dbg_set_mode_errbar_debug_v;
691
692 typedef struct rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10
693 {
694 NvHandle hClient;
695 NvHandle hObject;
696 NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06 ctrlParams;
697 } rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10;
698
699 typedef rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10 rpc_ctrl_dbg_set_next_stop_trigger_type_v;
700
701 typedef struct rpc_ctrl_dma_set_default_vaspace_v1A_0E
702 {
703 NvHandle hClient;
704 NvHandle hObject;
705 NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00 ctrlParams;
706 } rpc_ctrl_dma_set_default_vaspace_v1A_0E;
707
708 typedef rpc_ctrl_dma_set_default_vaspace_v1A_0E rpc_ctrl_dma_set_default_vaspace_v;
709
710 typedef struct rpc_ctrl_get_ce_pce_mask_v1A_0E
711 {
712 NvHandle hClient;
713 NvHandle hObject;
714 NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07 ctrlParams;
715 } rpc_ctrl_get_ce_pce_mask_v1A_0E;
716
717 typedef rpc_ctrl_get_ce_pce_mask_v1A_0E rpc_ctrl_get_ce_pce_mask_v;
718
719 typedef struct rpc_ctrl_get_zbc_clear_table_entry_v1A_0E
720 {
721 NvHandle hClient;
722 NvHandle hObject;
723 NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07 ctrlParams;
724 } rpc_ctrl_get_zbc_clear_table_entry_v1A_0E;
725
726 typedef rpc_ctrl_get_zbc_clear_table_entry_v1A_0E rpc_ctrl_get_zbc_clear_table_entry_v;
727
728 typedef struct rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E
729 {
730 NvHandle hClient;
731 NvHandle hObject;
732 NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_v14_00 ctrlParams;
733 } rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E;
734
735 typedef rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E rpc_ctrl_get_nvlink_peer_id_mask_v;
736
737 typedef struct rpc_ctrl_get_nvlink_status_v23_04
738 {
739 NvHandle hClient;
740 NvHandle hObject;
741 NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04 ctrlParams;
742 } rpc_ctrl_get_nvlink_status_v23_04;
743
744 typedef rpc_ctrl_get_nvlink_status_v23_04 rpc_ctrl_get_nvlink_status_v;
745
746 typedef struct rpc_ctrl_get_p2p_caps_v1F_0D
747 {
748 NvHandle hClient;
749 NvHandle hObject;
750 NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D ctrlParams;
751 } rpc_ctrl_get_p2p_caps_v1F_0D;
752
753 typedef rpc_ctrl_get_p2p_caps_v1F_0D rpc_ctrl_get_p2p_caps_v;
754
755 typedef struct rpc_ctrl_get_p2p_caps_matrix_v1A_0E
756 {
757 NvHandle hClient;
758 NvHandle hObject;
759 NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A ctrlParams;
760 } rpc_ctrl_get_p2p_caps_matrix_v1A_0E;
761
762 typedef rpc_ctrl_get_p2p_caps_matrix_v1A_0E rpc_ctrl_get_p2p_caps_matrix_v;
763
764 typedef struct rpc_ctrl_reserve_pm_area_smpc_v1A_0F
765 {
766 NvHandle hClient;
767 NvHandle hObject;
768 NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F params;
769 } rpc_ctrl_reserve_pm_area_smpc_v1A_0F;
770
771 typedef rpc_ctrl_reserve_pm_area_smpc_v1A_0F rpc_ctrl_reserve_pm_area_smpc_v;
772
773 typedef struct rpc_ctrl_reserve_hwpm_legacy_v1A_0F
774 {
775 NvHandle hClient;
776 NvHandle hObject;
777 NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F params;
778 } rpc_ctrl_reserve_hwpm_legacy_v1A_0F;
779
780 typedef rpc_ctrl_reserve_hwpm_legacy_v1A_0F rpc_ctrl_reserve_hwpm_legacy_v;
781
782 typedef struct rpc_ctrl_b0cc_exec_reg_ops_v1A_0F
783 {
784 NvHandle hClient;
785 NvHandle hObject;
786 NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F params;
787 } rpc_ctrl_b0cc_exec_reg_ops_v1A_0F;
788
789 typedef rpc_ctrl_b0cc_exec_reg_ops_v1A_0F rpc_ctrl_b0cc_exec_reg_ops_v;
790
791 typedef struct rpc_ctrl_bind_pm_resources_v1A_0F
792 {
793 NvHandle hClient;
794 NvHandle hObject;
795 } rpc_ctrl_bind_pm_resources_v1A_0F;
796
797 typedef rpc_ctrl_bind_pm_resources_v1A_0F rpc_ctrl_bind_pm_resources_v;
798
799 typedef struct rpc_ctrl_alloc_pma_stream_v1A_14
800 {
801 NvHandle hClient;
802 NvHandle hObject;
803 NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14 params;
804 } rpc_ctrl_alloc_pma_stream_v1A_14;
805
806 typedef rpc_ctrl_alloc_pma_stream_v1A_14 rpc_ctrl_alloc_pma_stream_v;
807
808 typedef struct rpc_ctrl_pma_stream_update_get_put_v1A_14
809 {
810 NvHandle hClient;
811 NvHandle hObject;
812 NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14 params;
813 } rpc_ctrl_pma_stream_update_get_put_v1A_14;
814
815 typedef rpc_ctrl_pma_stream_update_get_put_v1A_14 rpc_ctrl_pma_stream_update_get_put_v;
816
817 typedef struct rpc_ctrl_fb_get_info_v2_v25_0A
818 {
819 NvHandle hClient;
820 NvHandle hObject;
821 NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A ctrlParams;
822 } rpc_ctrl_fb_get_info_v2_v25_0A;
823
824 typedef rpc_ctrl_fb_get_info_v2_v25_0A rpc_ctrl_fb_get_info_v2_v;
825
826 typedef struct rpc_ctrl_fifo_set_channel_properties_v1A_16
827 {
828 NvHandle hClient;
829 NvHandle hObject;
830 NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00 ctrlParams;
831 } rpc_ctrl_fifo_set_channel_properties_v1A_16;
832
833 typedef rpc_ctrl_fifo_set_channel_properties_v1A_16 rpc_ctrl_fifo_set_channel_properties_v;
834
835 typedef struct rpc_ctrl_gpu_evict_ctx_v1A_1C
836 {
837 NvHandle hClient;
838 NvHandle hObject;
839 NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v03_00 params;
840 } rpc_ctrl_gpu_evict_ctx_v1A_1C;
841
842 typedef rpc_ctrl_gpu_evict_ctx_v1A_1C rpc_ctrl_gpu_evict_ctx_v;
843
844 typedef struct rpc_ctrl_fb_get_fs_info_v24_00
845 {
846 NvHandle hClient;
847 NvHandle hObject;
848 NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00 params;
849 } rpc_ctrl_fb_get_fs_info_v24_00;
850
851 typedef rpc_ctrl_fb_get_fs_info_v24_00 rpc_ctrl_fb_get_fs_info_v;
852
853 typedef struct rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D
854 {
855 NvHandle hClient;
856 NvHandle hObject;
857 NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D params;
858 } rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D;
859
860 typedef rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D rpc_ctrl_grmgr_get_gr_fs_info_v;
861
862 typedef struct rpc_ctrl_stop_channel_v1A_1E
863 {
864 NvHandle hClient;
865 NvHandle hObject;
866 NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E params;
867 } rpc_ctrl_stop_channel_v1A_1E;
868
869 typedef rpc_ctrl_stop_channel_v1A_1E rpc_ctrl_stop_channel_v;
870
871 typedef struct rpc_ctrl_gr_pc_sampling_mode_v1A_1F
872 {
873 NvHandle hClient;
874 NvHandle hObject;
875 NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F params;
876 } rpc_ctrl_gr_pc_sampling_mode_v1A_1F;
877
878 typedef rpc_ctrl_gr_pc_sampling_mode_v1A_1F rpc_ctrl_gr_pc_sampling_mode_v;
879
880 typedef struct rpc_ctrl_perf_rated_tdp_get_status_v1A_1F
881 {
882 NvHandle hClient;
883 NvHandle hObject;
884 NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F params;
885 } rpc_ctrl_perf_rated_tdp_get_status_v1A_1F;
886
887 typedef rpc_ctrl_perf_rated_tdp_get_status_v1A_1F rpc_ctrl_perf_rated_tdp_get_status_v;
888
889 typedef struct rpc_ctrl_perf_rated_tdp_set_control_v1A_1F
890 {
891 NvHandle hClient;
892 NvHandle hObject;
893 NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F params;
894 } rpc_ctrl_perf_rated_tdp_set_control_v1A_1F;
895
896 typedef rpc_ctrl_perf_rated_tdp_set_control_v1A_1F rpc_ctrl_perf_rated_tdp_set_control_v;
897
898 typedef struct rpc_ctrl_timer_set_gr_tick_freq_v1A_1F
899 {
900 NvHandle hClient;
901 NvHandle hObject;
902 NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F params;
903 } rpc_ctrl_timer_set_gr_tick_freq_v1A_1F;
904
905 typedef rpc_ctrl_timer_set_gr_tick_freq_v1A_1F rpc_ctrl_timer_set_gr_tick_freq_v;
906
907 typedef struct rpc_ctrl_free_pma_stream_v1A_1F
908 {
909 NvHandle hClient;
910 NvHandle hObject;
911 NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F params;
912 } rpc_ctrl_free_pma_stream_v1A_1F;
913
914 typedef rpc_ctrl_free_pma_stream_v1A_1F rpc_ctrl_free_pma_stream_v;
915
916 typedef struct rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23
917 {
918 NvHandle hClient;
919 NvHandle hObject;
920 NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23 params;
921 } rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23;
922
923 typedef rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23 rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v;
924
925 typedef struct rpc_ctrl_dbg_set_single_sm_single_step_v1C_02
926 {
927 NvHandle hClient;
928 NvHandle hObject;
929 NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02 params;
930 } rpc_ctrl_dbg_set_single_sm_single_step_v1C_02;
931
932 typedef rpc_ctrl_dbg_set_single_sm_single_step_v1C_02 rpc_ctrl_dbg_set_single_sm_single_step_v;
933
934 typedef struct rpc_ctrl_gr_get_tpc_partition_mode_v1C_04
935 {
936 NvHandle hClient;
937 NvHandle hObject;
938 NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04 params;
939 } rpc_ctrl_gr_get_tpc_partition_mode_v1C_04;
940
941 typedef rpc_ctrl_gr_get_tpc_partition_mode_v1C_04 rpc_ctrl_gr_get_tpc_partition_mode_v;
942
943 typedef struct rpc_ctrl_gr_set_tpc_partition_mode_v1C_04
944 {
945 NvHandle hClient;
946 NvHandle hObject;
947 NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04 params;
948 } rpc_ctrl_gr_set_tpc_partition_mode_v1C_04;
949
950 typedef rpc_ctrl_gr_set_tpc_partition_mode_v1C_04 rpc_ctrl_gr_set_tpc_partition_mode_v;
951
952 typedef struct rpc_ctrl_internal_promote_fault_method_buffers_v1E_07
953 {
954 NvHandle hClient;
955 NvHandle hObject;
956 NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07 params;
957 } rpc_ctrl_internal_promote_fault_method_buffers_v1E_07;
958
959 typedef rpc_ctrl_internal_promote_fault_method_buffers_v1E_07 rpc_ctrl_internal_promote_fault_method_buffers_v;
960
961 typedef struct rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05
962 {
963 NvHandle hClient;
964 NvHandle hObject;
965 NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_v1F_05 params;
966 } rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05;
967
968 typedef rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05 rpc_ctrl_internal_memsys_set_zbc_referenced_v;
969
970 typedef struct rpc_ctrl_fabric_memory_describe_v1E_0C
971 {
972 NvHandle hClient;
973 NvHandle hObject;
974 NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C params;
975 } rpc_ctrl_fabric_memory_describe_v1E_0C;
976
977 typedef rpc_ctrl_fabric_memory_describe_v1E_0C rpc_ctrl_fabric_memory_describe_v;
978
979 typedef struct rpc_ctrl_fabric_mem_stats_v1E_0C
980 {
981 NvHandle hClient;
982 NvHandle hObject;
983 NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C params;
984 } rpc_ctrl_fabric_mem_stats_v1E_0C;
985
986 typedef rpc_ctrl_fabric_mem_stats_v1E_0C rpc_ctrl_fabric_mem_stats_v;
987
988 typedef struct rpc_ctrl_bus_set_p2p_mapping_v21_03
989 {
990 NvHandle hClient;
991 NvHandle hObject;
992 NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03 params;
993 } rpc_ctrl_bus_set_p2p_mapping_v21_03;
994
995 typedef rpc_ctrl_bus_set_p2p_mapping_v21_03 rpc_ctrl_bus_set_p2p_mapping_v;
996
997 typedef struct rpc_ctrl_bus_unset_p2p_mapping_v21_03
998 {
999 NvHandle hClient;
1000 NvHandle hObject;
1001 NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03 params;
1002 } rpc_ctrl_bus_unset_p2p_mapping_v21_03;
1003
1004 typedef rpc_ctrl_bus_unset_p2p_mapping_v21_03 rpc_ctrl_bus_unset_p2p_mapping_v;
1005
1006 typedef struct rpc_ctrl_gpu_get_info_v2_v25_11
1007 {
1008 NvHandle hClient;
1009 NvHandle hObject;
1010 NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11 params;
1011 } rpc_ctrl_gpu_get_info_v2_v25_11;
1012
1013 typedef rpc_ctrl_gpu_get_info_v2_v25_11 rpc_ctrl_gpu_get_info_v2_v;
1014
1015 typedef struct rpc_ctrl_internal_quiesce_pma_channel_v1C_08
1016 {
1017 NvHandle hClient;
1018 NvHandle hObject;
1019 NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08 params;
1020 } rpc_ctrl_internal_quiesce_pma_channel_v1C_08;
1021
1022 typedef rpc_ctrl_internal_quiesce_pma_channel_v1C_08 rpc_ctrl_internal_quiesce_pma_channel_v;
1023
1024 typedef struct rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C
1025 {
1026 NvHandle hClient;
1027 NvHandle hObject;
1028 NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C params;
1029 } rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C;
1030
1031 typedef rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C rpc_ctrl_internal_sriov_promote_pma_stream_v;
1032
1033 typedef struct rpc_ctrl_exec_partitions_create_v24_05
1034 {
1035 NvHandle hClient;
1036 NvHandle hObject;
1037 NvU32 status;
1038 NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_v24_05 execPartitionsCreate;
1039 } rpc_ctrl_exec_partitions_create_v24_05;
1040
1041 typedef rpc_ctrl_exec_partitions_create_v24_05 rpc_ctrl_exec_partitions_create_v;
1042
1043 typedef struct rpc_ctrl_fla_setup_instance_mem_block_v21_05
1044 {
1045 NvHandle hClient;
1046 NvHandle hObject;
1047 NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_v13_04 params;
1048 } rpc_ctrl_fla_setup_instance_mem_block_v21_05;
1049
1050 typedef rpc_ctrl_fla_setup_instance_mem_block_v21_05 rpc_ctrl_fla_setup_instance_mem_block_v;
1051
1052 typedef struct rpc_ctrl_get_total_hs_credits_v21_08
1053 {
1054 NvHandle hClient;
1055 NvHandle hObject;
1056 NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08 params;
1057 } rpc_ctrl_get_total_hs_credits_v21_08;
1058
1059 typedef rpc_ctrl_get_total_hs_credits_v21_08 rpc_ctrl_get_total_hs_credits_v;
1060
1061 typedef struct rpc_ctrl_get_hs_credits_v21_08
1062 {
1063 NvHandle hClient;
1064 NvHandle hObject;
1065 NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08 params;
1066 } rpc_ctrl_get_hs_credits_v21_08;
1067
1068 typedef rpc_ctrl_get_hs_credits_v21_08 rpc_ctrl_get_hs_credits_v;
1069
1070 typedef struct rpc_ctrl_set_hs_credits_v21_08
1071 {
1072 NvHandle hClient;
1073 NvHandle hObject;
1074 NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08 params;
1075 } rpc_ctrl_set_hs_credits_v21_08;
1076
1077 typedef rpc_ctrl_set_hs_credits_v21_08 rpc_ctrl_set_hs_credits_v;
1078
1079 typedef struct rpc_ctrl_pm_area_pc_sampler_v21_0B
1080 {
1081 NvHandle hClient;
1082 NvHandle hObject;
1083 NvU32 cmd;
1084 } rpc_ctrl_pm_area_pc_sampler_v21_0B;
1085
1086 typedef rpc_ctrl_pm_area_pc_sampler_v21_0B rpc_ctrl_pm_area_pc_sampler_v;
1087
1088 typedef struct rpc_ctrl_exec_partitions_delete_v1F_0A
1089 {
1090 NvHandle hClient;
1091 NvHandle hObject;
1092 NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_v18_05 execPartitionsDelete;
1093 } rpc_ctrl_exec_partitions_delete_v1F_0A;
1094
1095 typedef rpc_ctrl_exec_partitions_delete_v1F_0A rpc_ctrl_exec_partitions_delete_v;
1096
1097 typedef struct rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A
1098 {
1099 NvHandle hClient;
1100 NvHandle hObject;
1101 NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_v08_00 workSubmitToken;
1102 } rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A;
1103
1104 typedef rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A rpc_ctrl_gpfifo_get_work_submit_token_v;
1105
1106 typedef struct rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A
1107 {
1108 NvHandle hClient;
1109 NvHandle hObject;
1110 NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_v16_04 setWorkSubmitTokenIndex;
1111 } rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A;
1112
1113 typedef rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v;
1114
1115 typedef struct rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D
1116 {
1117 NvHandle hClient;
1118 NvHandle hObject;
1119 NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B vfErrContIntrMask;
1120 } rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D;
1121
1122 typedef rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v;
1123
1124 typedef struct rpc_save_hibernation_data_v1E_0E
1125 {
1126 NvU32 remainedBytes;
1127 NvU8 payload[];
1128 } rpc_save_hibernation_data_v1E_0E;
1129
1130 typedef rpc_save_hibernation_data_v1E_0E rpc_save_hibernation_data_v;
1131
1132 typedef struct rpc_restore_hibernation_data_v1E_0E
1133 {
1134 NvU32 remainedBytes;
1135 NvU8 payload[];
1136 } rpc_restore_hibernation_data_v1E_0E;
1137
1138 typedef rpc_restore_hibernation_data_v1E_0E rpc_restore_hibernation_data_v;
1139
1140 typedef struct rpc_ctrl_get_mmu_debug_mode_v1E_06
1141 {
1142 NvHandle hClient;
1143 NvHandle hObject;
1144 NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06 params;
1145 } rpc_ctrl_get_mmu_debug_mode_v1E_06;
1146
1147 typedef rpc_ctrl_get_mmu_debug_mode_v1E_06 rpc_ctrl_get_mmu_debug_mode_v;
1148
1149 typedef struct rpc_disable_channels_v1E_0B
1150 {
1151 NvU32 bDisable;
1152 } rpc_disable_channels_v1E_0B;
1153
1154 typedef rpc_disable_channels_v1E_0B rpc_disable_channels_v;
1155
1156 typedef struct rpc_ctrl_gpu_migratable_ops_v21_07
1157 {
1158 NvHandle hClient;
1159 NvHandle hObject;
1160 NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07 ctrlParams;
1161 } rpc_ctrl_gpu_migratable_ops_v21_07;
1162
1163 typedef rpc_ctrl_gpu_migratable_ops_v21_07 rpc_ctrl_gpu_migratable_ops_v;
1164
1165 typedef struct rpc_invalidate_tlb_v23_03
1166 {
1167 NvU64 pdbAddress NV_ALIGN_BYTES(8);
1168 NvU32 regVal;
1169 } rpc_invalidate_tlb_v23_03;
1170
1171 typedef rpc_invalidate_tlb_v23_03 rpc_invalidate_tlb_v;
1172
1173 typedef struct rpc_get_brand_caps_v25_12
1174 {
1175 NvU32 brands;
1176 } rpc_get_brand_caps_v25_12;
1177
1178 typedef rpc_get_brand_caps_v25_12 rpc_get_brand_caps_v;
1179
1180 typedef struct rpc_gsp_set_system_info_v17_00
1181 {
1182 NvU32 data;
1183 } rpc_gsp_set_system_info_v17_00;
1184
1185 typedef rpc_gsp_set_system_info_v17_00 rpc_gsp_set_system_info_v;
1186
1187 typedef struct rpc_gsp_rm_alloc_v03_00
1188 {
1189 NvHandle hClient;
1190 NvHandle hParent;
1191 NvHandle hObject;
1192 NvU32 hClass;
1193 NvU32 status;
1194 NvU32 paramsSize;
1195 NvU32 flags;
1196 NvU8 reserved[4];
1197 NvU8 params[];
1198 } rpc_gsp_rm_alloc_v03_00;
1199
1200 typedef rpc_gsp_rm_alloc_v03_00 rpc_gsp_rm_alloc_v;
1201
1202 typedef struct rpc_gsp_rm_control_v03_00
1203 {
1204 NvHandle hClient;
1205 NvHandle hObject;
1206 NvU32 cmd;
1207 NvU32 status;
1208 NvU32 paramsSize;
1209 NvU32 flags;
1210 NvU8 params[];
1211 } rpc_gsp_rm_control_v03_00;
1212
1213 typedef rpc_gsp_rm_control_v03_00 rpc_gsp_rm_control_v;
1214
1215 typedef struct rpc_dump_protobuf_component_v18_12
1216 {
1217 NvU16 component;
1218 NvU8 nvDumpType;
1219 NvBool countOnly;
1220 NvU32 bugCheckCode;
1221 NvU32 internalCode;
1222 NvU32 bufferSize;
1223 NvU8 blob[];
1224 } rpc_dump_protobuf_component_v18_12;
1225
1226 typedef rpc_dump_protobuf_component_v18_12 rpc_dump_protobuf_component_v;
1227
1228 typedef struct rpc_run_cpu_sequencer_v17_00
1229 {
1230 NvU32 bufferSizeDWord;
1231 NvU32 cmdIndex;
1232 NvU32 regSaveArea[8];
1233 NvU32 commandBuffer[];
1234 } rpc_run_cpu_sequencer_v17_00;
1235
1236 typedef rpc_run_cpu_sequencer_v17_00 rpc_run_cpu_sequencer_v;
1237
1238 typedef struct rpc_post_event_v17_00
1239 {
1240 NvHandle hClient;
1241 NvHandle hEvent;
1242 NvU32 notifyIndex;
1243 NvU32 data;
1244 NvU16 info16;
1245 NvU32 status;
1246 NvU32 eventDataSize;
1247 NvBool bNotifyList;
1248 NvU8 eventData[];
1249 } rpc_post_event_v17_00;
1250
1251 typedef rpc_post_event_v17_00 rpc_post_event_v;
1252
1253 typedef struct rpc_rc_triggered_v17_02
1254 {
1255 NvU32 nv2080EngineType;
1256 NvU32 chid;
1257 NvU32 exceptType;
1258 NvU32 scope;
1259 NvU16 partitionAttributionId;
1260 NvU32 rcJournalBufferSize;
1261 NvU8 rcJournalBuffer[];
1262 } rpc_rc_triggered_v17_02;
1263
1264 typedef rpc_rc_triggered_v17_02 rpc_rc_triggered_v;
1265
1266 typedef struct rpc_os_error_log_v17_00
1267 {
1268 NvU32 exceptType;
1269 NvU32 runlistId;
1270 NvU32 chid;
1271 char errString[0x100];
1272 } rpc_os_error_log_v17_00;
1273
1274 typedef rpc_os_error_log_v17_00 rpc_os_error_log_v;
1275
1276 typedef struct rpc_rg_line_intr_v17_00
1277 {
1278 NvU32 head;
1279 NvU32 rgIntr;
1280 } rpc_rg_line_intr_v17_00;
1281
1282 typedef rpc_rg_line_intr_v17_00 rpc_rg_line_intr_v;
1283
1284 typedef struct rpc_display_modeset_v01_00
1285 {
1286 NvBool bModesetStart;
1287 NvU32 minRequiredIsoBandwidthKBPS;
1288 NvU32 minRequiredFloorBandwidthKBPS;
1289 } rpc_display_modeset_v01_00;
1290
1291 typedef rpc_display_modeset_v01_00 rpc_display_modeset_v;
1292
1293 typedef struct rpc_gpuacct_perfmon_util_samples_v1F_0E
1294 {
1295 NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E params;
1296 } rpc_gpuacct_perfmon_util_samples_v1F_0E;
1297
1298 typedef rpc_gpuacct_perfmon_util_samples_v1F_0E rpc_gpuacct_perfmon_util_samples_v;
1299
1300 typedef struct rpc_vgpu_gsp_plugin_triggered_v17_00
1301 {
1302 NvU32 gfid;
1303 NvU32 notifyIndex;
1304 } rpc_vgpu_gsp_plugin_triggered_v17_00;
1305
1306 typedef rpc_vgpu_gsp_plugin_triggered_v17_00 rpc_vgpu_gsp_plugin_triggered_v;
1307
1308 typedef struct rpc_vgpu_config_event_v17_00
1309 {
1310 NvU32 notifyIndex;
1311 } rpc_vgpu_config_event_v17_00;
1312
1313 typedef rpc_vgpu_config_event_v17_00 rpc_vgpu_config_event_v;
1314
1315 typedef struct rpc_dce_rm_init_v01_00
1316 {
1317 NvBool bInit;
1318 } rpc_dce_rm_init_v01_00;
1319
1320 typedef rpc_dce_rm_init_v01_00 rpc_dce_rm_init_v;
1321
1322 typedef struct rpc_sim_read_v1E_01
1323 {
1324 char path[0x100];
1325 NvU32 index;
1326 NvU32 count;
1327 } rpc_sim_read_v1E_01;
1328
1329 typedef rpc_sim_read_v1E_01 rpc_sim_read_v;
1330
1331 typedef struct rpc_sim_write_v1E_01
1332 {
1333 char path[0x100];
1334 NvU32 index;
1335 NvU32 count;
1336 NvU32 data;
1337 } rpc_sim_write_v1E_01;
1338
1339 typedef rpc_sim_write_v1E_01 rpc_sim_write_v;
1340
1341 typedef struct rpc_ucode_libos_print_v1E_08
1342 {
1343 NvU32 ucodeEngDesc;
1344 NvU32 libosPrintBufSize;
1345 NvU8 libosPrintBuf[];
1346 } rpc_ucode_libos_print_v1E_08;
1347
1348 typedef rpc_ucode_libos_print_v1E_08 rpc_ucode_libos_print_v;
1349
1350 typedef struct rpc_init_done_v17_00
1351 {
1352 NvU32 not_used;
1353 } rpc_init_done_v17_00;
1354
1355 typedef rpc_init_done_v17_00 rpc_init_done_v;
1356
1357 typedef struct rpc_semaphore_schedule_callback_v17_00
1358 {
1359 NvU64 GPUVA NV_ALIGN_BYTES(8);
1360 NvU32 hVASpace;
1361 NvU32 ReleaseValue;
1362 NvU32 Flags;
1363 NvU32 completionStatus;
1364 NvHandle hClient;
1365 NvHandle hEvent;
1366 } rpc_semaphore_schedule_callback_v17_00;
1367
1368 typedef rpc_semaphore_schedule_callback_v17_00 rpc_semaphore_schedule_callback_v;
1369
1370 typedef struct rpc_timed_semaphore_release_v01_00
1371 {
1372 NvU64 semaphoreVA NV_ALIGN_BYTES(8);
1373 NvU64 notifierVA NV_ALIGN_BYTES(8);
1374 NvU32 hVASpace;
1375 NvU32 releaseValue;
1376 NvU32 completionStatus;
1377 NvHandle hClient;
1378 NvHandle hDevice;
1379 } rpc_timed_semaphore_release_v01_00;
1380
1381 typedef rpc_timed_semaphore_release_v01_00 rpc_timed_semaphore_release_v;
1382
1383 typedef struct rpc_perf_gpu_boost_sync_limits_callback_v17_00
1384 {
1385 NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00 params;
1386 } rpc_perf_gpu_boost_sync_limits_callback_v17_00;
1387
1388 typedef rpc_perf_gpu_boost_sync_limits_callback_v17_00 rpc_perf_gpu_boost_sync_limits_callback_v;
1389
1390 typedef struct rpc_perf_bridgeless_info_update_v17_00
1391 {
1392 NvU64 bBridgeless NV_ALIGN_BYTES(8);
1393 } rpc_perf_bridgeless_info_update_v17_00;
1394
1395 typedef rpc_perf_bridgeless_info_update_v17_00 rpc_perf_bridgeless_info_update_v;
1396
1397 typedef struct rpc_nvlink_fault_up_v17_00
1398 {
1399 NvU32 linkId;
1400 } rpc_nvlink_fault_up_v17_00;
1401
1402 typedef rpc_nvlink_fault_up_v17_00 rpc_nvlink_fault_up_v;
1403
1404 typedef struct rpc_nvlink_inband_received_data_256_v17_00
1405 {
1406 NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00 params;
1407 } rpc_nvlink_inband_received_data_256_v17_00;
1408
1409 typedef rpc_nvlink_inband_received_data_256_v17_00 rpc_nvlink_inband_received_data_256_v;
1410
1411 typedef struct rpc_nvlink_inband_received_data_512_v17_00
1412 {
1413 NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00 params;
1414 } rpc_nvlink_inband_received_data_512_v17_00;
1415
1416 typedef rpc_nvlink_inband_received_data_512_v17_00 rpc_nvlink_inband_received_data_512_v;
1417
1418 typedef struct rpc_nvlink_inband_received_data_1024_v17_00
1419 {
1420 NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00 params;
1421 } rpc_nvlink_inband_received_data_1024_v17_00;
1422
1423 typedef rpc_nvlink_inband_received_data_1024_v17_00 rpc_nvlink_inband_received_data_1024_v;
1424
1425 typedef struct rpc_nvlink_inband_received_data_2048_v17_00
1426 {
1427 NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00 params;
1428 } rpc_nvlink_inband_received_data_2048_v17_00;
1429
1430 typedef rpc_nvlink_inband_received_data_2048_v17_00 rpc_nvlink_inband_received_data_2048_v;
1431
1432 typedef struct rpc_nvlink_inband_received_data_4096_v17_00
1433 {
1434 NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00 params;
1435 } rpc_nvlink_inband_received_data_4096_v17_00;
1436
1437 typedef rpc_nvlink_inband_received_data_4096_v17_00 rpc_nvlink_inband_received_data_4096_v;
1438
1439 typedef struct rpc_nvlink_is_gpu_degraded_v17_00
1440 {
1441 NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00 params;
1442 } rpc_nvlink_is_gpu_degraded_v17_00;
1443
1444 typedef rpc_nvlink_is_gpu_degraded_v17_00 rpc_nvlink_is_gpu_degraded_v;
1445
1446 typedef struct rpc_update_gsp_trace_v01_00
1447 {
1448 NvU32 records;
1449 NvU32 data;
1450 } rpc_update_gsp_trace_v01_00;
1451
1452 typedef rpc_update_gsp_trace_v01_00 rpc_update_gsp_trace_v;
1453
1454 typedef struct rpc_gsp_post_nocat_record_v01_00
1455 {
1456 NvU32 data;
1457 } rpc_gsp_post_nocat_record_v01_00;
1458
1459 typedef rpc_gsp_post_nocat_record_v01_00 rpc_gsp_post_nocat_record_v;
1460
1461 typedef struct rpc_extdev_intr_service_v17_00
1462 {
1463 NvU8 lossRegStatus;
1464 NvU8 gainRegStatus;
1465 NvU8 miscRegStatus;
1466 NvBool rmStatus;
1467 } rpc_extdev_intr_service_v17_00;
1468
1469 typedef rpc_extdev_intr_service_v17_00 rpc_extdev_intr_service_v;
1470
1471 typedef struct rpc_pfm_req_hndlr_state_sync_callback_v21_04
1472 {
1473 NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04 params;
1474 } rpc_pfm_req_hndlr_state_sync_callback_v21_04;
1475
1476 typedef rpc_pfm_req_hndlr_state_sync_callback_v21_04 rpc_pfm_req_hndlr_state_sync_callback_v;
1477
1478 typedef struct rpc_vgpu_gsp_mig_ci_config_v21_03
1479 {
1480 NvU32 execPartCount;
1481 NvU32 execPartId[NVC637_CTRL_MAX_EXEC_PARTITIONS];
1482 NvU32 gfid;
1483 NvBool bDelete;
1484 } rpc_vgpu_gsp_mig_ci_config_v21_03;
1485
1486 typedef rpc_vgpu_gsp_mig_ci_config_v21_03 rpc_vgpu_gsp_mig_ci_config_v;
1487
1488 typedef struct rpc_gsp_lockdown_notice_v17_00
1489 {
1490 NvBool bLockdownEngaging;
1491 } rpc_gsp_lockdown_notice_v17_00;
1492
1493 typedef rpc_gsp_lockdown_notice_v17_00 rpc_gsp_lockdown_notice_v;
1494
1495 typedef struct rpc_ctrl_gpu_query_ecc_status_v24_06
1496 {
1497 NvHandle hClient;
1498 NvHandle hObject;
1499 NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v24_06 params;
1500 } rpc_ctrl_gpu_query_ecc_status_v24_06;
1501
1502 typedef rpc_ctrl_gpu_query_ecc_status_v24_06 rpc_ctrl_gpu_query_ecc_status_v;
1503
1504 typedef struct rpc_ctrl_dbg_get_mode_mmu_debug_v25_04
1505 {
1506 NvHandle hClient;
1507 NvHandle hObject;
1508 NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04 ctrlParams;
1509 } rpc_ctrl_dbg_get_mode_mmu_debug_v25_04;
1510
1511 typedef rpc_ctrl_dbg_get_mode_mmu_debug_v25_04 rpc_ctrl_dbg_get_mode_mmu_debug_v;
1512
1513 typedef struct rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09
1514 {
1515 NvU8 bwMode;
1516 } rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09;
1517
1518 typedef rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09 rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v;
1519
1520 typedef struct rpc_ctrl_nvlink_get_inband_received_data_v25_0C
1521 {
1522 NvU16 message_type;
1523 NvBool more;
1524 NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_v25_0C payload;
1525 } rpc_ctrl_nvlink_get_inband_received_data_v25_0C;
1526
1527 typedef rpc_ctrl_nvlink_get_inband_received_data_v25_0C rpc_ctrl_nvlink_get_inband_received_data_v;
1528
1529
1530 #endif
1531
1532 #ifdef RPC_DEBUG_PRINT_STRUCTURES
1533 // These are printable definitions of above structures. These will be used for RPC logging in the vmioplugin.
1534 #define SDK_DEBUG_PRINT_STRUCTURES
1535 #include "g_sdk-structures.h"
1536 #undef SDK_DEBUG_PRINT_STRUCTURES
1537
1538 #ifndef SKIP_PRINT_rpc_nop_v03_00
1539 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nop_v03_00[] = {
1540 {
1541 .vtype = vt_end
1542 }
1543 };
1544
1545 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nop_v03_00 = {
1546 #if (defined(DEBUG) || defined(DEVELOP))
1547 .name = "rpc_nop",
1548 #endif
1549 .fdesc = vmiopd_fdesc_t_rpc_nop_v03_00
1550 };
1551 #endif
1552
1553 #ifndef SKIP_PRINT_rpc_set_guest_system_info_v03_00
1554 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_guest_system_info_v03_00[] = {
1555 {
1556 .vtype = vtype_NvU32,
1557 .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, vgxVersionMajorNum),
1558 #if (defined(DEBUG) || defined(DEVELOP))
1559 .name = "vgxVersionMajorNum"
1560 #endif
1561 },
1562 {
1563 .vtype = vtype_NvU32,
1564 .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, vgxVersionMinorNum),
1565 #if (defined(DEBUG) || defined(DEVELOP))
1566 .name = "vgxVersionMinorNum"
1567 #endif
1568 },
1569 {
1570 .vtype = vtype_NvU32,
1571 .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestDriverVersionBufferLength),
1572 #if (defined(DEBUG) || defined(DEVELOP))
1573 .name = "guestDriverVersionBufferLength"
1574 #endif
1575 },
1576 {
1577 .vtype = vtype_NvU32,
1578 .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestVersionBufferLength),
1579 #if (defined(DEBUG) || defined(DEVELOP))
1580 .name = "guestVersionBufferLength"
1581 #endif
1582 },
1583 {
1584 .vtype = vtype_NvU32,
1585 .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestTitleBufferLength),
1586 #if (defined(DEBUG) || defined(DEVELOP))
1587 .name = "guestTitleBufferLength"
1588 #endif
1589 },
1590 {
1591 .vtype = vtype_NvU32,
1592 .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestClNum),
1593 #if (defined(DEBUG) || defined(DEVELOP))
1594 .name = "guestClNum"
1595 #endif
1596 },
1597 {
1598 .vtype = vtype_char_array,
1599 .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestDriverVersion),
1600 .array_length = 0x100,
1601 #if (defined(DEBUG) || defined(DEVELOP))
1602 .name = "guestDriverVersion"
1603 #endif
1604 },
1605 {
1606 .vtype = vtype_char_array,
1607 .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestVersion),
1608 .array_length = 0x100,
1609 #if (defined(DEBUG) || defined(DEVELOP))
1610 .name = "guestVersion"
1611 #endif
1612 },
1613 {
1614 .vtype = vtype_char_array,
1615 .offset = NV_OFFSETOF(rpc_set_guest_system_info_v03_00, guestTitle),
1616 .array_length = 0x100,
1617 #if (defined(DEBUG) || defined(DEVELOP))
1618 .name = "guestTitle"
1619 #endif
1620 },
1621 {
1622 .vtype = vt_end
1623 }
1624 };
1625
1626 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_guest_system_info_v03_00 = {
1627 #if (defined(DEBUG) || defined(DEVELOP))
1628 .name = "rpc_set_guest_system_info",
1629 #endif
1630 .header_length = sizeof(rpc_set_guest_system_info_v03_00),
1631 .fdesc = vmiopd_fdesc_t_rpc_set_guest_system_info_v03_00
1632 };
1633 #endif
1634
1635 #ifndef SKIP_PRINT_rpc_set_guest_system_info_ext_v25_1B
1636 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_guest_system_info_ext_v25_1B[] = {
1637 {
1638 .vtype = vtype_char_array,
1639 .offset = NV_OFFSETOF(rpc_set_guest_system_info_ext_v25_1B, guestDriverBranch),
1640 .array_length = 0x100,
1641 #if (defined(DEBUG) || defined(DEVELOP))
1642 .name = "guestDriverBranch"
1643 #endif
1644 },
1645 {
1646 .vtype = vtype_NvU32,
1647 .offset = NV_OFFSETOF(rpc_set_guest_system_info_ext_v25_1B, domain),
1648 #if (defined(DEBUG) || defined(DEVELOP))
1649 .name = "domain"
1650 #endif
1651 },
1652 {
1653 .vtype = vtype_NvU16,
1654 .offset = NV_OFFSETOF(rpc_set_guest_system_info_ext_v25_1B, bus),
1655 #if (defined(DEBUG) || defined(DEVELOP))
1656 .name = "bus"
1657 #endif
1658 },
1659 {
1660 .vtype = vtype_NvU16,
1661 .offset = NV_OFFSETOF(rpc_set_guest_system_info_ext_v25_1B, device),
1662 #if (defined(DEBUG) || defined(DEVELOP))
1663 .name = "device"
1664 #endif
1665 },
1666 {
1667 .vtype = vtype_NvU32,
1668 .offset = NV_OFFSETOF(rpc_set_guest_system_info_ext_v25_1B, gridBuildCsp),
1669 #if (defined(DEBUG) || defined(DEVELOP))
1670 .name = "gridBuildCsp"
1671 #endif
1672 },
1673 {
1674 .vtype = vt_end
1675 }
1676 };
1677
1678 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_guest_system_info_ext_v25_1B = {
1679 #if (defined(DEBUG) || defined(DEVELOP))
1680 .name = "rpc_set_guest_system_info_ext",
1681 #endif
1682 .header_length = sizeof(rpc_set_guest_system_info_ext_v25_1B),
1683 .fdesc = vmiopd_fdesc_t_rpc_set_guest_system_info_ext_v25_1B
1684 };
1685 #endif
1686
1687 #ifndef SKIP_PRINT_rpc_set_guest_system_info_ext_v15_02
1688 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_guest_system_info_ext_v15_02[] = {
1689 {
1690 .vtype = vtype_char_array,
1691 .offset = NV_OFFSETOF(rpc_set_guest_system_info_ext_v15_02, guestDriverBranch),
1692 .array_length = 0x100,
1693 #if (defined(DEBUG) || defined(DEVELOP))
1694 .name = "guestDriverBranch"
1695 #endif
1696 },
1697 {
1698 .vtype = vtype_NvU32,
1699 .offset = NV_OFFSETOF(rpc_set_guest_system_info_ext_v15_02, domain),
1700 #if (defined(DEBUG) || defined(DEVELOP))
1701 .name = "domain"
1702 #endif
1703 },
1704 {
1705 .vtype = vtype_NvU16,
1706 .offset = NV_OFFSETOF(rpc_set_guest_system_info_ext_v15_02, bus),
1707 #if (defined(DEBUG) || defined(DEVELOP))
1708 .name = "bus"
1709 #endif
1710 },
1711 {
1712 .vtype = vtype_NvU16,
1713 .offset = NV_OFFSETOF(rpc_set_guest_system_info_ext_v15_02, device),
1714 #if (defined(DEBUG) || defined(DEVELOP))
1715 .name = "device"
1716 #endif
1717 },
1718 {
1719 .vtype = vt_end
1720 }
1721 };
1722
1723 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_guest_system_info_ext_v15_02 = {
1724 #if (defined(DEBUG) || defined(DEVELOP))
1725 .name = "rpc_set_guest_system_info_ext",
1726 #endif
1727 .header_length = sizeof(rpc_set_guest_system_info_ext_v15_02),
1728 .fdesc = vmiopd_fdesc_t_rpc_set_guest_system_info_ext_v15_02
1729 };
1730 #endif
1731
1732 #ifndef SKIP_PRINT_rpc_alloc_root_v07_00
1733 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_alloc_root_v07_00[] = {
1734 {
1735 .vtype = vtype_NvHandle,
1736 .offset = NV_OFFSETOF(rpc_alloc_root_v07_00, hClient),
1737 #if (defined(DEBUG) || defined(DEVELOP))
1738 .name = "hClient"
1739 #endif
1740 },
1741 {
1742 .vtype = vtype_NvU32,
1743 .offset = NV_OFFSETOF(rpc_alloc_root_v07_00, processID),
1744 #if (defined(DEBUG) || defined(DEVELOP))
1745 .name = "processID"
1746 #endif
1747 },
1748 {
1749 .vtype = vtype_char_array,
1750 .offset = NV_OFFSETOF(rpc_alloc_root_v07_00, processName),
1751 .array_length = 0x64,
1752 #if (defined(DEBUG) || defined(DEVELOP))
1753 .name = "processName"
1754 #endif
1755 },
1756 {
1757 .vtype = vt_end
1758 }
1759 };
1760
1761 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_alloc_root_v07_00 = {
1762 #if (defined(DEBUG) || defined(DEVELOP))
1763 .name = "rpc_alloc_root",
1764 #endif
1765 .header_length = sizeof(rpc_alloc_root_v07_00),
1766 .fdesc = vmiopd_fdesc_t_rpc_alloc_root_v07_00
1767 };
1768 #endif
1769
1770 #ifndef SKIP_PRINT_rpc_alloc_memory_v13_01
1771 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_alloc_memory_v13_01[] = {
1772 {
1773 .vtype = vtype_NvHandle,
1774 .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, hClient),
1775 #if (defined(DEBUG) || defined(DEVELOP))
1776 .name = "hClient"
1777 #endif
1778 },
1779 {
1780 .vtype = vtype_NvHandle,
1781 .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, hDevice),
1782 #if (defined(DEBUG) || defined(DEVELOP))
1783 .name = "hDevice"
1784 #endif
1785 },
1786 {
1787 .vtype = vtype_NvHandle,
1788 .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, hMemory),
1789 #if (defined(DEBUG) || defined(DEVELOP))
1790 .name = "hMemory"
1791 #endif
1792 },
1793 {
1794 .vtype = vtype_NvU32,
1795 .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, hClass),
1796 #if (defined(DEBUG) || defined(DEVELOP))
1797 .name = "hClass"
1798 #endif
1799 },
1800 {
1801 .vtype = vtype_NvU32,
1802 .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, flags),
1803 #if (defined(DEBUG) || defined(DEVELOP))
1804 .name = "flags"
1805 #endif
1806 },
1807 {
1808 .vtype = vtype_NvU32,
1809 .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, pteAdjust),
1810 #if (defined(DEBUG) || defined(DEVELOP))
1811 .name = "pteAdjust"
1812 #endif
1813 },
1814 {
1815 .vtype = vtype_NvU32,
1816 .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, format),
1817 #if (defined(DEBUG) || defined(DEVELOP))
1818 .name = "format"
1819 #endif
1820 },
1821 {
1822 .vtype = vtype_NvU64,
1823 .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, length),
1824 #if (defined(DEBUG) || defined(DEVELOP))
1825 .name = "length"
1826 #endif
1827 },
1828 {
1829 .vtype = vtype_NvU32,
1830 .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, pageCount),
1831 #if (defined(DEBUG) || defined(DEVELOP))
1832 .name = "pageCount"
1833 #endif
1834 },
1835 {
1836 .vtype = vtype_struct_pte_desc,
1837 .offset = NV_OFFSETOF(rpc_alloc_memory_v13_01, pteDesc),
1838 #if (defined(DEBUG) || defined(DEVELOP))
1839 .name = "pteDesc"
1840 #endif
1841 },
1842 {
1843 .vtype = vt_end
1844 }
1845 };
1846
1847 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_alloc_memory_v13_01 = {
1848 #if (defined(DEBUG) || defined(DEVELOP))
1849 .name = "rpc_alloc_memory",
1850 #endif
1851 .header_length = sizeof(rpc_alloc_memory_v13_01),
1852 .fdesc = vmiopd_fdesc_t_rpc_alloc_memory_v13_01
1853 };
1854 #endif
1855
1856 #ifndef SKIP_PRINT_rpc_alloc_channel_dma_v1F_04
1857 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_alloc_channel_dma_v1F_04[] = {
1858 {
1859 .vtype = vtype_NvHandle,
1860 .offset = NV_OFFSETOF(rpc_alloc_channel_dma_v1F_04, hClient),
1861 #if (defined(DEBUG) || defined(DEVELOP))
1862 .name = "hClient"
1863 #endif
1864 },
1865 {
1866 .vtype = vtype_NvHandle,
1867 .offset = NV_OFFSETOF(rpc_alloc_channel_dma_v1F_04, hDevice),
1868 #if (defined(DEBUG) || defined(DEVELOP))
1869 .name = "hDevice"
1870 #endif
1871 },
1872 {
1873 .vtype = vtype_NvHandle,
1874 .offset = NV_OFFSETOF(rpc_alloc_channel_dma_v1F_04, hChannel),
1875 #if (defined(DEBUG) || defined(DEVELOP))
1876 .name = "hChannel"
1877 #endif
1878 },
1879 {
1880 .vtype = vtype_NvU32,
1881 .offset = NV_OFFSETOF(rpc_alloc_channel_dma_v1F_04, hClass),
1882 #if (defined(DEBUG) || defined(DEVELOP))
1883 .name = "hClass"
1884 #endif
1885 },
1886 {
1887 .vtype = vtype_NvU32,
1888 .offset = NV_OFFSETOF(rpc_alloc_channel_dma_v1F_04, flags),
1889 #if (defined(DEBUG) || defined(DEVELOP))
1890 .name = "flags"
1891 #endif
1892 },
1893 {
1894 .vtype = vtype_NV_CHANNEL_ALLOC_PARAMS_v1F_04,
1895 .offset = NV_OFFSETOF(rpc_alloc_channel_dma_v1F_04, params),
1896 #if (defined(DEBUG) || defined(DEVELOP))
1897 .name = "params"
1898 #endif
1899 },
1900 {
1901 .vtype = vtype_NvU32,
1902 .offset = NV_OFFSETOF(rpc_alloc_channel_dma_v1F_04, chid),
1903 #if (defined(DEBUG) || defined(DEVELOP))
1904 .name = "chid"
1905 #endif
1906 },
1907 {
1908 .vtype = vt_end
1909 }
1910 };
1911
1912 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_alloc_channel_dma_v1F_04 = {
1913 #if (defined(DEBUG) || defined(DEVELOP))
1914 .name = "rpc_alloc_channel_dma",
1915 #endif
1916 .header_length = sizeof(rpc_alloc_channel_dma_v1F_04),
1917 .fdesc = vmiopd_fdesc_t_rpc_alloc_channel_dma_v1F_04
1918 };
1919 #endif
1920
1921 #ifndef SKIP_PRINT_rpc_alloc_object_v25_08
1922 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_alloc_object_v25_08[] = {
1923 {
1924 .vtype = vtype_NvHandle,
1925 .offset = NV_OFFSETOF(rpc_alloc_object_v25_08, hClient),
1926 #if (defined(DEBUG) || defined(DEVELOP))
1927 .name = "hClient"
1928 #endif
1929 },
1930 {
1931 .vtype = vtype_NvHandle,
1932 .offset = NV_OFFSETOF(rpc_alloc_object_v25_08, hParent),
1933 #if (defined(DEBUG) || defined(DEVELOP))
1934 .name = "hParent"
1935 #endif
1936 },
1937 {
1938 .vtype = vtype_NvHandle,
1939 .offset = NV_OFFSETOF(rpc_alloc_object_v25_08, hObject),
1940 #if (defined(DEBUG) || defined(DEVELOP))
1941 .name = "hObject"
1942 #endif
1943 },
1944 {
1945 .vtype = vtype_NvU32,
1946 .offset = NV_OFFSETOF(rpc_alloc_object_v25_08, hClass),
1947 #if (defined(DEBUG) || defined(DEVELOP))
1948 .name = "hClass"
1949 #endif
1950 },
1951 {
1952 .vtype = vtype_NvU32,
1953 .offset = NV_OFFSETOF(rpc_alloc_object_v25_08, param_len),
1954 #if (defined(DEBUG) || defined(DEVELOP))
1955 .name = "param_len"
1956 #endif
1957 },
1958 {
1959 .vtype = vtype_alloc_object_params_v25_08,
1960 .offset = NV_OFFSETOF(rpc_alloc_object_v25_08, params),
1961 .union_member_index_fn = get_union_member_index_rpc_alloc_object_v25_08_params,
1962 #if (defined(DEBUG) || defined(DEVELOP))
1963 .name = "params"
1964 #endif
1965 },
1966 {
1967 .vtype = vt_end
1968 }
1969 };
1970
1971 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_alloc_object_v25_08 = {
1972 #if (defined(DEBUG) || defined(DEVELOP))
1973 .name = "rpc_alloc_object",
1974 #endif
1975 .header_length = sizeof(rpc_alloc_object_v25_08),
1976 .fdesc = vmiopd_fdesc_t_rpc_alloc_object_v25_08
1977 };
1978 #endif
1979
1980 #ifndef SKIP_PRINT_rpc_free_v03_00
1981 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_free_v03_00[] = {
1982 {
1983 .vtype = vtype_NVOS00_PARAMETERS_v03_00,
1984 .offset = NV_OFFSETOF(rpc_free_v03_00, params),
1985 #if (defined(DEBUG) || defined(DEVELOP))
1986 .name = "params"
1987 #endif
1988 },
1989 {
1990 .vtype = vt_end
1991 }
1992 };
1993
1994 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_free_v03_00 = {
1995 #if (defined(DEBUG) || defined(DEVELOP))
1996 .name = "rpc_free",
1997 #endif
1998 .header_length = sizeof(rpc_free_v03_00),
1999 .fdesc = vmiopd_fdesc_t_rpc_free_v03_00
2000 };
2001 #endif
2002
2003 #ifndef SKIP_PRINT_rpc_log_v03_00
2004 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_log_v03_00[] = {
2005 {
2006 .vtype = vtype_NvU32,
2007 .offset = NV_OFFSETOF(rpc_log_v03_00, level),
2008 #if (defined(DEBUG) || defined(DEVELOP))
2009 .name = "level"
2010 #endif
2011 },
2012 {
2013 .vtype = vtype_NvU32,
2014 .offset = NV_OFFSETOF(rpc_log_v03_00, log_len),
2015 #if (defined(DEBUG) || defined(DEVELOP))
2016 .name = "log_len"
2017 #endif
2018 },
2019 {
2020 .vtype = vtype_char_array,
2021 .offset = NV_OFFSETOF(rpc_log_v03_00, log_msg),
2022 .array_length = 0,
2023 #if (defined(DEBUG) || defined(DEVELOP))
2024 .name = "log_msg"
2025 #endif
2026 },
2027 {
2028 .vtype = vt_end
2029 }
2030 };
2031
2032 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_log_v03_00 = {
2033 #if (defined(DEBUG) || defined(DEVELOP))
2034 .name = "rpc_log",
2035 #endif
2036 .header_length = sizeof(rpc_log_v03_00),
2037 .fdesc = vmiopd_fdesc_t_rpc_log_v03_00
2038 };
2039 #endif
2040
2041 #ifndef SKIP_PRINT_rpc_map_memory_dma_v03_00
2042 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_map_memory_dma_v03_00[] = {
2043 {
2044 .vtype = vtype_NVOS46_PARAMETERS_v03_00,
2045 .offset = NV_OFFSETOF(rpc_map_memory_dma_v03_00, params),
2046 #if (defined(DEBUG) || defined(DEVELOP))
2047 .name = "params"
2048 #endif
2049 },
2050 {
2051 .vtype = vt_end
2052 }
2053 };
2054
2055 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_map_memory_dma_v03_00 = {
2056 #if (defined(DEBUG) || defined(DEVELOP))
2057 .name = "rpc_map_memory_dma",
2058 #endif
2059 .header_length = sizeof(rpc_map_memory_dma_v03_00),
2060 .fdesc = vmiopd_fdesc_t_rpc_map_memory_dma_v03_00
2061 };
2062 #endif
2063
2064 #ifndef SKIP_PRINT_rpc_unmap_memory_dma_v03_00
2065 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unmap_memory_dma_v03_00[] = {
2066 {
2067 .vtype = vtype_NVOS47_PARAMETERS_v03_00,
2068 .offset = NV_OFFSETOF(rpc_unmap_memory_dma_v03_00, params),
2069 #if (defined(DEBUG) || defined(DEVELOP))
2070 .name = "params"
2071 #endif
2072 },
2073 {
2074 .vtype = vt_end
2075 }
2076 };
2077
2078 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_unmap_memory_dma_v03_00 = {
2079 #if (defined(DEBUG) || defined(DEVELOP))
2080 .name = "rpc_unmap_memory_dma",
2081 #endif
2082 .header_length = sizeof(rpc_unmap_memory_dma_v03_00),
2083 .fdesc = vmiopd_fdesc_t_rpc_unmap_memory_dma_v03_00
2084 };
2085 #endif
2086
2087 #ifndef SKIP_PRINT_rpc_alloc_subdevice_v08_01
2088 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_alloc_subdevice_v08_01[] = {
2089 {
2090 .vtype = vtype_NvU32,
2091 .offset = NV_OFFSETOF(rpc_alloc_subdevice_v08_01, subDeviceInst),
2092 #if (defined(DEBUG) || defined(DEVELOP))
2093 .name = "subDeviceInst"
2094 #endif
2095 },
2096 {
2097 .vtype = vtype_NVOS21_PARAMETERS_v03_00,
2098 .offset = NV_OFFSETOF(rpc_alloc_subdevice_v08_01, params),
2099 #if (defined(DEBUG) || defined(DEVELOP))
2100 .name = "params"
2101 #endif
2102 },
2103 {
2104 .vtype = vt_end
2105 }
2106 };
2107
2108 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_alloc_subdevice_v08_01 = {
2109 #if (defined(DEBUG) || defined(DEVELOP))
2110 .name = "rpc_alloc_subdevice",
2111 #endif
2112 .header_length = sizeof(rpc_alloc_subdevice_v08_01),
2113 .fdesc = vmiopd_fdesc_t_rpc_alloc_subdevice_v08_01
2114 };
2115 #endif
2116
2117 #ifndef SKIP_PRINT_rpc_dup_object_v03_00
2118 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_dup_object_v03_00[] = {
2119 {
2120 .vtype = vtype_NVOS55_PARAMETERS_v03_00,
2121 .offset = NV_OFFSETOF(rpc_dup_object_v03_00, params),
2122 #if (defined(DEBUG) || defined(DEVELOP))
2123 .name = "params"
2124 #endif
2125 },
2126 {
2127 .vtype = vt_end
2128 }
2129 };
2130
2131 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_dup_object_v03_00 = {
2132 #if (defined(DEBUG) || defined(DEVELOP))
2133 .name = "rpc_dup_object",
2134 #endif
2135 .header_length = sizeof(rpc_dup_object_v03_00),
2136 .fdesc = vmiopd_fdesc_t_rpc_dup_object_v03_00
2137 };
2138 #endif
2139
2140 #ifndef SKIP_PRINT_rpc_idle_channels_v03_00
2141 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_idle_channels_v03_00[] = {
2142 {
2143 .vtype = vtype_NvU32,
2144 .offset = NV_OFFSETOF(rpc_idle_channels_v03_00, flags),
2145 #if (defined(DEBUG) || defined(DEVELOP))
2146 .name = "flags"
2147 #endif
2148 },
2149 {
2150 .vtype = vtype_NvU32,
2151 .offset = NV_OFFSETOF(rpc_idle_channels_v03_00, timeout),
2152 #if (defined(DEBUG) || defined(DEVELOP))
2153 .name = "timeout"
2154 #endif
2155 },
2156 {
2157 .vtype = vtype_NvU32,
2158 .offset = NV_OFFSETOF(rpc_idle_channels_v03_00, nchannels),
2159 #if (defined(DEBUG) || defined(DEVELOP))
2160 .name = "nchannels"
2161 #endif
2162 },
2163 {
2164 .vtype = vtype_idle_channel_list_v03_00_array,
2165 .offset = NV_OFFSETOF(rpc_idle_channels_v03_00, channel_list),
2166 .array_length = 0,
2167 .array_length_fn = get_array_length_rpc_idle_channels_v03_00_channel_list,
2168 #if (defined(DEBUG) || defined(DEVELOP))
2169 .name = "channel_list"
2170 #endif
2171 },
2172 {
2173 .vtype = vt_end
2174 }
2175 };
2176
2177 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_idle_channels_v03_00 = {
2178 #if (defined(DEBUG) || defined(DEVELOP))
2179 .name = "rpc_idle_channels",
2180 #endif
2181 .header_length = sizeof(rpc_idle_channels_v03_00),
2182 .fdesc = vmiopd_fdesc_t_rpc_idle_channels_v03_00
2183 };
2184 #endif
2185
2186 #ifndef SKIP_PRINT_rpc_alloc_event_v03_00
2187 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_alloc_event_v03_00[] = {
2188 {
2189 .vtype = vtype_NvHandle,
2190 .offset = NV_OFFSETOF(rpc_alloc_event_v03_00, hClient),
2191 #if (defined(DEBUG) || defined(DEVELOP))
2192 .name = "hClient"
2193 #endif
2194 },
2195 {
2196 .vtype = vtype_NvHandle,
2197 .offset = NV_OFFSETOF(rpc_alloc_event_v03_00, hParentClient),
2198 #if (defined(DEBUG) || defined(DEVELOP))
2199 .name = "hParentClient"
2200 #endif
2201 },
2202 {
2203 .vtype = vtype_NvHandle,
2204 .offset = NV_OFFSETOF(rpc_alloc_event_v03_00, hChannel),
2205 #if (defined(DEBUG) || defined(DEVELOP))
2206 .name = "hChannel"
2207 #endif
2208 },
2209 {
2210 .vtype = vtype_NvHandle,
2211 .offset = NV_OFFSETOF(rpc_alloc_event_v03_00, hObject),
2212 #if (defined(DEBUG) || defined(DEVELOP))
2213 .name = "hObject"
2214 #endif
2215 },
2216 {
2217 .vtype = vtype_NvHandle,
2218 .offset = NV_OFFSETOF(rpc_alloc_event_v03_00, hEvent),
2219 #if (defined(DEBUG) || defined(DEVELOP))
2220 .name = "hEvent"
2221 #endif
2222 },
2223 {
2224 .vtype = vtype_NvU32,
2225 .offset = NV_OFFSETOF(rpc_alloc_event_v03_00, hClass),
2226 #if (defined(DEBUG) || defined(DEVELOP))
2227 .name = "hClass"
2228 #endif
2229 },
2230 {
2231 .vtype = vtype_NvU32,
2232 .offset = NV_OFFSETOF(rpc_alloc_event_v03_00, notifyIndex),
2233 #if (defined(DEBUG) || defined(DEVELOP))
2234 .name = "notifyIndex"
2235 #endif
2236 },
2237 {
2238 .vtype = vt_end
2239 }
2240 };
2241
2242 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_alloc_event_v03_00 = {
2243 #if (defined(DEBUG) || defined(DEVELOP))
2244 .name = "rpc_alloc_event",
2245 #endif
2246 .header_length = sizeof(rpc_alloc_event_v03_00),
2247 .fdesc = vmiopd_fdesc_t_rpc_alloc_event_v03_00
2248 };
2249 #endif
2250
2251 #ifndef SKIP_PRINT_rpc_rm_api_control_v25_19
2252 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rm_api_control_v25_19[] = {
2253 {
2254 .vtype = vtype_NVOS54_PARAMETERS_v03_00,
2255 .offset = NV_OFFSETOF(rpc_rm_api_control_v25_19, params),
2256 #if (defined(DEBUG) || defined(DEVELOP))
2257 .name = "params"
2258 #endif
2259 },
2260 {
2261 .vtype = vtype_NvP64,
2262 .offset = NV_OFFSETOF(rpc_rm_api_control_v25_19, rm_api_params),
2263 #if (defined(DEBUG) || defined(DEVELOP))
2264 .name = "rm_api_params"
2265 #endif
2266 },
2267 {
2268 .vtype = vt_end
2269 }
2270 };
2271
2272 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rm_api_control_v25_19 = {
2273 #if (defined(DEBUG) || defined(DEVELOP))
2274 .name = "rpc_rm_api_control",
2275 #endif
2276 .header_length = sizeof(rpc_rm_api_control_v25_19),
2277 .fdesc = vmiopd_fdesc_t_rpc_rm_api_control_v25_19
2278 };
2279 #endif
2280
2281 #ifndef SKIP_PRINT_rpc_rm_api_control_v25_0F
2282 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rm_api_control_v25_0F[] = {
2283 {
2284 .vtype = vtype_NVOS54_PARAMETERS_v03_00,
2285 .offset = NV_OFFSETOF(rpc_rm_api_control_v25_0F, params),
2286 #if (defined(DEBUG) || defined(DEVELOP))
2287 .name = "params"
2288 #endif
2289 },
2290 {
2291 .vtype = vtype_NvP64,
2292 .offset = NV_OFFSETOF(rpc_rm_api_control_v25_0F, rm_api_params),
2293 #if (defined(DEBUG) || defined(DEVELOP))
2294 .name = "rm_api_params"
2295 #endif
2296 },
2297 {
2298 .vtype = vt_end
2299 }
2300 };
2301
2302 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rm_api_control_v25_0F = {
2303 #if (defined(DEBUG) || defined(DEVELOP))
2304 .name = "rpc_rm_api_control",
2305 #endif
2306 .header_length = sizeof(rpc_rm_api_control_v25_0F),
2307 .fdesc = vmiopd_fdesc_t_rpc_rm_api_control_v25_0F
2308 };
2309 #endif
2310
2311 #ifndef SKIP_PRINT_rpc_rm_api_control_v25_16
2312 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rm_api_control_v25_16[] = {
2313 {
2314 .vtype = vtype_NVOS54_PARAMETERS_v03_00,
2315 .offset = NV_OFFSETOF(rpc_rm_api_control_v25_16, params),
2316 #if (defined(DEBUG) || defined(DEVELOP))
2317 .name = "params"
2318 #endif
2319 },
2320 {
2321 .vtype = vtype_NvP64,
2322 .offset = NV_OFFSETOF(rpc_rm_api_control_v25_16, rm_api_params),
2323 #if (defined(DEBUG) || defined(DEVELOP))
2324 .name = "rm_api_params"
2325 #endif
2326 },
2327 {
2328 .vtype = vt_end
2329 }
2330 };
2331
2332 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rm_api_control_v25_16 = {
2333 #if (defined(DEBUG) || defined(DEVELOP))
2334 .name = "rpc_rm_api_control",
2335 #endif
2336 .header_length = sizeof(rpc_rm_api_control_v25_16),
2337 .fdesc = vmiopd_fdesc_t_rpc_rm_api_control_v25_16
2338 };
2339 #endif
2340
2341 #ifndef SKIP_PRINT_rpc_rm_api_control_v25_10
2342 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rm_api_control_v25_10[] = {
2343 {
2344 .vtype = vtype_NVOS54_PARAMETERS_v03_00,
2345 .offset = NV_OFFSETOF(rpc_rm_api_control_v25_10, params),
2346 #if (defined(DEBUG) || defined(DEVELOP))
2347 .name = "params"
2348 #endif
2349 },
2350 {
2351 .vtype = vtype_NvP64,
2352 .offset = NV_OFFSETOF(rpc_rm_api_control_v25_10, rm_api_params),
2353 #if (defined(DEBUG) || defined(DEVELOP))
2354 .name = "rm_api_params"
2355 #endif
2356 },
2357 {
2358 .vtype = vt_end
2359 }
2360 };
2361
2362 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rm_api_control_v25_10 = {
2363 #if (defined(DEBUG) || defined(DEVELOP))
2364 .name = "rpc_rm_api_control",
2365 #endif
2366 .header_length = sizeof(rpc_rm_api_control_v25_10),
2367 .fdesc = vmiopd_fdesc_t_rpc_rm_api_control_v25_10
2368 };
2369 #endif
2370
2371 #ifndef SKIP_PRINT_rpc_rm_api_control_v25_15
2372 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rm_api_control_v25_15[] = {
2373 {
2374 .vtype = vtype_NVOS54_PARAMETERS_v03_00,
2375 .offset = NV_OFFSETOF(rpc_rm_api_control_v25_15, params),
2376 #if (defined(DEBUG) || defined(DEVELOP))
2377 .name = "params"
2378 #endif
2379 },
2380 {
2381 .vtype = vtype_NvP64,
2382 .offset = NV_OFFSETOF(rpc_rm_api_control_v25_15, rm_api_params),
2383 #if (defined(DEBUG) || defined(DEVELOP))
2384 .name = "rm_api_params"
2385 #endif
2386 },
2387 {
2388 .vtype = vt_end
2389 }
2390 };
2391
2392 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rm_api_control_v25_15 = {
2393 #if (defined(DEBUG) || defined(DEVELOP))
2394 .name = "rpc_rm_api_control",
2395 #endif
2396 .header_length = sizeof(rpc_rm_api_control_v25_15),
2397 .fdesc = vmiopd_fdesc_t_rpc_rm_api_control_v25_15
2398 };
2399 #endif
2400
2401 #ifndef SKIP_PRINT_rpc_rm_api_control_v25_0D
2402 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rm_api_control_v25_0D[] = {
2403 {
2404 .vtype = vtype_NVOS54_PARAMETERS_v03_00,
2405 .offset = NV_OFFSETOF(rpc_rm_api_control_v25_0D, params),
2406 #if (defined(DEBUG) || defined(DEVELOP))
2407 .name = "params"
2408 #endif
2409 },
2410 {
2411 .vtype = vtype_NvP64,
2412 .offset = NV_OFFSETOF(rpc_rm_api_control_v25_0D, rm_api_params),
2413 #if (defined(DEBUG) || defined(DEVELOP))
2414 .name = "rm_api_params"
2415 #endif
2416 },
2417 {
2418 .vtype = vt_end
2419 }
2420 };
2421
2422 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rm_api_control_v25_0D = {
2423 #if (defined(DEBUG) || defined(DEVELOP))
2424 .name = "rpc_rm_api_control",
2425 #endif
2426 .header_length = sizeof(rpc_rm_api_control_v25_0D),
2427 .fdesc = vmiopd_fdesc_t_rpc_rm_api_control_v25_0D
2428 };
2429 #endif
2430
2431 #ifndef SKIP_PRINT_rpc_rm_api_control_v25_17
2432 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rm_api_control_v25_17[] = {
2433 {
2434 .vtype = vtype_NVOS54_PARAMETERS_v03_00,
2435 .offset = NV_OFFSETOF(rpc_rm_api_control_v25_17, params),
2436 #if (defined(DEBUG) || defined(DEVELOP))
2437 .name = "params"
2438 #endif
2439 },
2440 {
2441 .vtype = vtype_NvP64,
2442 .offset = NV_OFFSETOF(rpc_rm_api_control_v25_17, rm_api_params),
2443 #if (defined(DEBUG) || defined(DEVELOP))
2444 .name = "rm_api_params"
2445 #endif
2446 },
2447 {
2448 .vtype = vt_end
2449 }
2450 };
2451
2452 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rm_api_control_v25_17 = {
2453 #if (defined(DEBUG) || defined(DEVELOP))
2454 .name = "rpc_rm_api_control",
2455 #endif
2456 .header_length = sizeof(rpc_rm_api_control_v25_17),
2457 .fdesc = vmiopd_fdesc_t_rpc_rm_api_control_v25_17
2458 };
2459 #endif
2460
2461 #ifndef SKIP_PRINT_rpc_rm_api_control_v25_18
2462 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rm_api_control_v25_18[] = {
2463 {
2464 .vtype = vtype_NVOS54_PARAMETERS_v03_00,
2465 .offset = NV_OFFSETOF(rpc_rm_api_control_v25_18, params),
2466 #if (defined(DEBUG) || defined(DEVELOP))
2467 .name = "params"
2468 #endif
2469 },
2470 {
2471 .vtype = vtype_NvP64,
2472 .offset = NV_OFFSETOF(rpc_rm_api_control_v25_18, rm_api_params),
2473 #if (defined(DEBUG) || defined(DEVELOP))
2474 .name = "rm_api_params"
2475 #endif
2476 },
2477 {
2478 .vtype = vt_end
2479 }
2480 };
2481
2482 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rm_api_control_v25_18 = {
2483 #if (defined(DEBUG) || defined(DEVELOP))
2484 .name = "rpc_rm_api_control",
2485 #endif
2486 .header_length = sizeof(rpc_rm_api_control_v25_18),
2487 .fdesc = vmiopd_fdesc_t_rpc_rm_api_control_v25_18
2488 };
2489 #endif
2490
2491 #ifndef SKIP_PRINT_rpc_rm_api_control_v25_1A
2492 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rm_api_control_v25_1A[] = {
2493 {
2494 .vtype = vtype_NVOS54_PARAMETERS_v03_00,
2495 .offset = NV_OFFSETOF(rpc_rm_api_control_v25_1A, params),
2496 #if (defined(DEBUG) || defined(DEVELOP))
2497 .name = "params"
2498 #endif
2499 },
2500 {
2501 .vtype = vtype_NvP64,
2502 .offset = NV_OFFSETOF(rpc_rm_api_control_v25_1A, rm_api_params),
2503 #if (defined(DEBUG) || defined(DEVELOP))
2504 .name = "rm_api_params"
2505 #endif
2506 },
2507 {
2508 .vtype = vt_end
2509 }
2510 };
2511
2512 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rm_api_control_v25_1A = {
2513 #if (defined(DEBUG) || defined(DEVELOP))
2514 .name = "rpc_rm_api_control",
2515 #endif
2516 .header_length = sizeof(rpc_rm_api_control_v25_1A),
2517 .fdesc = vmiopd_fdesc_t_rpc_rm_api_control_v25_1A
2518 };
2519 #endif
2520
2521 #ifndef SKIP_PRINT_rpc_rm_api_control_v25_14
2522 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rm_api_control_v25_14[] = {
2523 {
2524 .vtype = vtype_NVOS54_PARAMETERS_v03_00,
2525 .offset = NV_OFFSETOF(rpc_rm_api_control_v25_14, params),
2526 #if (defined(DEBUG) || defined(DEVELOP))
2527 .name = "params"
2528 #endif
2529 },
2530 {
2531 .vtype = vtype_NvP64,
2532 .offset = NV_OFFSETOF(rpc_rm_api_control_v25_14, rm_api_params),
2533 #if (defined(DEBUG) || defined(DEVELOP))
2534 .name = "rm_api_params"
2535 #endif
2536 },
2537 {
2538 .vtype = vt_end
2539 }
2540 };
2541
2542 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rm_api_control_v25_14 = {
2543 #if (defined(DEBUG) || defined(DEVELOP))
2544 .name = "rpc_rm_api_control",
2545 #endif
2546 .header_length = sizeof(rpc_rm_api_control_v25_14),
2547 .fdesc = vmiopd_fdesc_t_rpc_rm_api_control_v25_14
2548 };
2549 #endif
2550
2551 #ifndef SKIP_PRINT_rpc_alloc_share_device_v03_00
2552 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_alloc_share_device_v03_00[] = {
2553 {
2554 .vtype = vtype_NvHandle,
2555 .offset = NV_OFFSETOF(rpc_alloc_share_device_v03_00, hClient),
2556 #if (defined(DEBUG) || defined(DEVELOP))
2557 .name = "hClient"
2558 #endif
2559 },
2560 {
2561 .vtype = vtype_NvHandle,
2562 .offset = NV_OFFSETOF(rpc_alloc_share_device_v03_00, hDevice),
2563 #if (defined(DEBUG) || defined(DEVELOP))
2564 .name = "hDevice"
2565 #endif
2566 },
2567 {
2568 .vtype = vtype_NvU32,
2569 .offset = NV_OFFSETOF(rpc_alloc_share_device_v03_00, hClass),
2570 #if (defined(DEBUG) || defined(DEVELOP))
2571 .name = "hClass"
2572 #endif
2573 },
2574 {
2575 .vtype = vtype_NV_DEVICE_ALLOCATION_PARAMETERS_v03_00,
2576 .offset = NV_OFFSETOF(rpc_alloc_share_device_v03_00, params),
2577 #if (defined(DEBUG) || defined(DEVELOP))
2578 .name = "params"
2579 #endif
2580 },
2581 {
2582 .vtype = vt_end
2583 }
2584 };
2585
2586 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_alloc_share_device_v03_00 = {
2587 #if (defined(DEBUG) || defined(DEVELOP))
2588 .name = "rpc_alloc_share_device",
2589 #endif
2590 .header_length = sizeof(rpc_alloc_share_device_v03_00),
2591 .fdesc = vmiopd_fdesc_t_rpc_alloc_share_device_v03_00
2592 };
2593 #endif
2594
2595 #ifndef SKIP_PRINT_rpc_get_engine_utilization_v1F_0E
2596 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_get_engine_utilization_v1F_0E[] = {
2597 {
2598 .vtype = vtype_NvHandle,
2599 .offset = NV_OFFSETOF(rpc_get_engine_utilization_v1F_0E, hClient),
2600 #if (defined(DEBUG) || defined(DEVELOP))
2601 .name = "hClient"
2602 #endif
2603 },
2604 {
2605 .vtype = vtype_NvHandle,
2606 .offset = NV_OFFSETOF(rpc_get_engine_utilization_v1F_0E, hObject),
2607 #if (defined(DEBUG) || defined(DEVELOP))
2608 .name = "hObject"
2609 #endif
2610 },
2611 {
2612 .vtype = vtype_NvU32,
2613 .offset = NV_OFFSETOF(rpc_get_engine_utilization_v1F_0E, cmd),
2614 #if (defined(DEBUG) || defined(DEVELOP))
2615 .name = "cmd"
2616 #endif
2617 },
2618 {
2619 .vtype = vtype_vgpuGetEngineUtilization_data_v1F_0E,
2620 .offset = NV_OFFSETOF(rpc_get_engine_utilization_v1F_0E, params),
2621 .union_member_index_fn = get_union_member_index_rpc_get_engine_utilization_v1F_0E_params,
2622 #if (defined(DEBUG) || defined(DEVELOP))
2623 .name = "params"
2624 #endif
2625 },
2626 {
2627 .vtype = vt_end
2628 }
2629 };
2630
2631 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_get_engine_utilization_v1F_0E = {
2632 #if (defined(DEBUG) || defined(DEVELOP))
2633 .name = "rpc_get_engine_utilization",
2634 #endif
2635 .header_length = sizeof(rpc_get_engine_utilization_v1F_0E),
2636 .fdesc = vmiopd_fdesc_t_rpc_get_engine_utilization_v1F_0E
2637 };
2638 #endif
2639
2640 #ifndef SKIP_PRINT_rpc_perf_get_level_info_v03_00
2641 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_perf_get_level_info_v03_00[] = {
2642 {
2643 .vtype = vtype_NvHandle,
2644 .offset = NV_OFFSETOF(rpc_perf_get_level_info_v03_00, hClient),
2645 #if (defined(DEBUG) || defined(DEVELOP))
2646 .name = "hClient"
2647 #endif
2648 },
2649 {
2650 .vtype = vtype_NvHandle,
2651 .offset = NV_OFFSETOF(rpc_perf_get_level_info_v03_00, hObject),
2652 #if (defined(DEBUG) || defined(DEVELOP))
2653 .name = "hObject"
2654 #endif
2655 },
2656 {
2657 .vtype = vtype_NvU32,
2658 .offset = NV_OFFSETOF(rpc_perf_get_level_info_v03_00, level),
2659 #if (defined(DEBUG) || defined(DEVELOP))
2660 .name = "level"
2661 #endif
2662 },
2663 {
2664 .vtype = vtype_NvU32,
2665 .offset = NV_OFFSETOF(rpc_perf_get_level_info_v03_00, flags),
2666 #if (defined(DEBUG) || defined(DEVELOP))
2667 .name = "flags"
2668 #endif
2669 },
2670 {
2671 .vtype = vtype_NvU32,
2672 .offset = NV_OFFSETOF(rpc_perf_get_level_info_v03_00, perfGetClkInfoListSize),
2673 #if (defined(DEBUG) || defined(DEVELOP))
2674 .name = "perfGetClkInfoListSize"
2675 #endif
2676 },
2677 {
2678 .vtype = vtype_NvU32,
2679 .offset = NV_OFFSETOF(rpc_perf_get_level_info_v03_00, param_size),
2680 #if (defined(DEBUG) || defined(DEVELOP))
2681 .name = "param_size"
2682 #endif
2683 },
2684 {
2685 .vtype = vtype_NvU32_array,
2686 .offset = NV_OFFSETOF(rpc_perf_get_level_info_v03_00, params),
2687 .array_length = 0,
2688 #if (defined(DEBUG) || defined(DEVELOP))
2689 .name = "params"
2690 #endif
2691 },
2692 {
2693 .vtype = vt_end
2694 }
2695 };
2696
2697 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_perf_get_level_info_v03_00 = {
2698 #if (defined(DEBUG) || defined(DEVELOP))
2699 .name = "rpc_perf_get_level_info",
2700 #endif
2701 .header_length = sizeof(rpc_perf_get_level_info_v03_00),
2702 .fdesc = vmiopd_fdesc_t_rpc_perf_get_level_info_v03_00
2703 };
2704 #endif
2705
2706 #ifndef SKIP_PRINT_rpc_set_surface_properties_v07_07
2707 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_surface_properties_v07_07[] = {
2708 {
2709 .vtype = vtype_NvHandle,
2710 .offset = NV_OFFSETOF(rpc_set_surface_properties_v07_07, hClient),
2711 #if (defined(DEBUG) || defined(DEVELOP))
2712 .name = "hClient"
2713 #endif
2714 },
2715 {
2716 .vtype = vtype_NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES_v07_07,
2717 .offset = NV_OFFSETOF(rpc_set_surface_properties_v07_07, params),
2718 #if (defined(DEBUG) || defined(DEVELOP))
2719 .name = "params"
2720 #endif
2721 },
2722 {
2723 .vtype = vt_end
2724 }
2725 };
2726
2727 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_surface_properties_v07_07 = {
2728 #if (defined(DEBUG) || defined(DEVELOP))
2729 .name = "rpc_set_surface_properties",
2730 #endif
2731 .header_length = sizeof(rpc_set_surface_properties_v07_07),
2732 .fdesc = vmiopd_fdesc_t_rpc_set_surface_properties_v07_07
2733 };
2734 #endif
2735
2736 #ifndef SKIP_PRINT_rpc_cleanup_surface_v03_00
2737 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_cleanup_surface_v03_00[] = {
2738 {
2739 .vtype = vtype_NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS_v03_00,
2740 .offset = NV_OFFSETOF(rpc_cleanup_surface_v03_00, params),
2741 #if (defined(DEBUG) || defined(DEVELOP))
2742 .name = "params"
2743 #endif
2744 },
2745 {
2746 .vtype = vt_end
2747 }
2748 };
2749
2750 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_cleanup_surface_v03_00 = {
2751 #if (defined(DEBUG) || defined(DEVELOP))
2752 .name = "rpc_cleanup_surface",
2753 #endif
2754 .header_length = sizeof(rpc_cleanup_surface_v03_00),
2755 .fdesc = vmiopd_fdesc_t_rpc_cleanup_surface_v03_00
2756 };
2757 #endif
2758
2759 #ifndef SKIP_PRINT_rpc_unloading_guest_driver_v1F_07
2760 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unloading_guest_driver_v1F_07[] = {
2761 {
2762 .vtype = vtype_NvBool,
2763 .offset = NV_OFFSETOF(rpc_unloading_guest_driver_v1F_07, bInPMTransition),
2764 #if (defined(DEBUG) || defined(DEVELOP))
2765 .name = "bInPMTransition"
2766 #endif
2767 },
2768 {
2769 .vtype = vtype_NvBool,
2770 .offset = NV_OFFSETOF(rpc_unloading_guest_driver_v1F_07, bGc6Entering),
2771 #if (defined(DEBUG) || defined(DEVELOP))
2772 .name = "bGc6Entering"
2773 #endif
2774 },
2775 {
2776 .vtype = vtype_NvU32,
2777 .offset = NV_OFFSETOF(rpc_unloading_guest_driver_v1F_07, newLevel),
2778 #if (defined(DEBUG) || defined(DEVELOP))
2779 .name = "newLevel"
2780 #endif
2781 },
2782 {
2783 .vtype = vt_end
2784 }
2785 };
2786
2787 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_unloading_guest_driver_v1F_07 = {
2788 #if (defined(DEBUG) || defined(DEVELOP))
2789 .name = "rpc_unloading_guest_driver",
2790 #endif
2791 .header_length = sizeof(rpc_unloading_guest_driver_v1F_07),
2792 .fdesc = vmiopd_fdesc_t_rpc_unloading_guest_driver_v1F_07
2793 };
2794 #endif
2795
2796 #ifndef SKIP_PRINT_rpc_switch_to_vga_v03_00
2797 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_switch_to_vga_v03_00[] = {
2798 {
2799 .vtype = vt_end
2800 }
2801 };
2802
2803 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_switch_to_vga_v03_00 = {
2804 #if (defined(DEBUG) || defined(DEVELOP))
2805 .name = "rpc_switch_to_vga",
2806 #endif
2807 .fdesc = vmiopd_fdesc_t_rpc_switch_to_vga_v03_00
2808 };
2809 #endif
2810
2811 #ifndef SKIP_PRINT_rpc_gpu_exec_reg_ops_v12_01
2812 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gpu_exec_reg_ops_v12_01[] = {
2813 {
2814 .vtype = vtype_NvHandle,
2815 .offset = NV_OFFSETOF(rpc_gpu_exec_reg_ops_v12_01, hClient),
2816 #if (defined(DEBUG) || defined(DEVELOP))
2817 .name = "hClient"
2818 #endif
2819 },
2820 {
2821 .vtype = vtype_NvHandle,
2822 .offset = NV_OFFSETOF(rpc_gpu_exec_reg_ops_v12_01, hObject),
2823 #if (defined(DEBUG) || defined(DEVELOP))
2824 .name = "hObject"
2825 #endif
2826 },
2827 {
2828 .vtype = vtype_gpu_exec_reg_ops_v12_01,
2829 .offset = NV_OFFSETOF(rpc_gpu_exec_reg_ops_v12_01, params),
2830 #if (defined(DEBUG) || defined(DEVELOP))
2831 .name = "params"
2832 #endif
2833 },
2834 {
2835 .vtype = vt_end
2836 }
2837 };
2838
2839 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gpu_exec_reg_ops_v12_01 = {
2840 #if (defined(DEBUG) || defined(DEVELOP))
2841 .name = "rpc_gpu_exec_reg_ops",
2842 #endif
2843 .header_length = sizeof(rpc_gpu_exec_reg_ops_v12_01),
2844 .fdesc = vmiopd_fdesc_t_rpc_gpu_exec_reg_ops_v12_01
2845 };
2846 #endif
2847
2848 #ifndef SKIP_PRINT_rpc_get_static_data_v25_0E
2849 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_get_static_data_v25_0E[] = {
2850 {
2851 .vtype = vtype_NvU32,
2852 .offset = NV_OFFSETOF(rpc_get_static_data_v25_0E, offset),
2853 #if (defined(DEBUG) || defined(DEVELOP))
2854 .name = "offset"
2855 #endif
2856 },
2857 {
2858 .vtype = vtype_NvU32,
2859 .offset = NV_OFFSETOF(rpc_get_static_data_v25_0E, size),
2860 #if (defined(DEBUG) || defined(DEVELOP))
2861 .name = "size"
2862 #endif
2863 },
2864 {
2865 .vtype = vtype_NvU8_array,
2866 .offset = NV_OFFSETOF(rpc_get_static_data_v25_0E, payload),
2867 .array_length = 0,
2868 #if (defined(DEBUG) || defined(DEVELOP))
2869 .name = "payload"
2870 #endif
2871 },
2872 {
2873 .vtype = vt_end
2874 }
2875 };
2876
2877 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_get_static_data_v25_0E = {
2878 #if (defined(DEBUG) || defined(DEVELOP))
2879 .name = "rpc_get_static_data",
2880 #endif
2881 .header_length = sizeof(rpc_get_static_data_v25_0E),
2882 .fdesc = vmiopd_fdesc_t_rpc_get_static_data_v25_0E
2883 };
2884 #endif
2885
2886 #ifndef SKIP_PRINT_rpc_get_consolidated_gr_static_info_v1B_04
2887 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_get_consolidated_gr_static_info_v1B_04[] = {
2888 {
2889 .vtype = vtype_NvU32,
2890 .offset = NV_OFFSETOF(rpc_get_consolidated_gr_static_info_v1B_04, offset),
2891 #if (defined(DEBUG) || defined(DEVELOP))
2892 .name = "offset"
2893 #endif
2894 },
2895 {
2896 .vtype = vtype_NvU32,
2897 .offset = NV_OFFSETOF(rpc_get_consolidated_gr_static_info_v1B_04, size),
2898 #if (defined(DEBUG) || defined(DEVELOP))
2899 .name = "size"
2900 #endif
2901 },
2902 {
2903 .vtype = vtype_NvU8_array,
2904 .offset = NV_OFFSETOF(rpc_get_consolidated_gr_static_info_v1B_04, payload),
2905 .array_length = 0,
2906 #if (defined(DEBUG) || defined(DEVELOP))
2907 .name = "payload"
2908 #endif
2909 },
2910 {
2911 .vtype = vt_end
2912 }
2913 };
2914
2915 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_get_consolidated_gr_static_info_v1B_04 = {
2916 #if (defined(DEBUG) || defined(DEVELOP))
2917 .name = "rpc_get_consolidated_gr_static_info",
2918 #endif
2919 .header_length = sizeof(rpc_get_consolidated_gr_static_info_v1B_04),
2920 .fdesc = vmiopd_fdesc_t_rpc_get_consolidated_gr_static_info_v1B_04
2921 };
2922 #endif
2923
2924 #ifndef SKIP_PRINT_rpc_set_page_directory_v1E_05
2925 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_page_directory_v1E_05[] = {
2926 {
2927 .vtype = vtype_NvHandle,
2928 .offset = NV_OFFSETOF(rpc_set_page_directory_v1E_05, hClient),
2929 #if (defined(DEBUG) || defined(DEVELOP))
2930 .name = "hClient"
2931 #endif
2932 },
2933 {
2934 .vtype = vtype_NvHandle,
2935 .offset = NV_OFFSETOF(rpc_set_page_directory_v1E_05, hDevice),
2936 #if (defined(DEBUG) || defined(DEVELOP))
2937 .name = "hDevice"
2938 #endif
2939 },
2940 {
2941 .vtype = vtype_NvU32,
2942 .offset = NV_OFFSETOF(rpc_set_page_directory_v1E_05, pasid),
2943 #if (defined(DEBUG) || defined(DEVELOP))
2944 .name = "pasid"
2945 #endif
2946 },
2947 {
2948 .vtype = vtype_NV0080_CTRL_DMA_SET_PAGE_DIRECTORY_PARAMS_v1E_05,
2949 .offset = NV_OFFSETOF(rpc_set_page_directory_v1E_05, params),
2950 #if (defined(DEBUG) || defined(DEVELOP))
2951 .name = "params"
2952 #endif
2953 },
2954 {
2955 .vtype = vt_end
2956 }
2957 };
2958
2959 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_page_directory_v1E_05 = {
2960 #if (defined(DEBUG) || defined(DEVELOP))
2961 .name = "rpc_set_page_directory",
2962 #endif
2963 .header_length = sizeof(rpc_set_page_directory_v1E_05),
2964 .fdesc = vmiopd_fdesc_t_rpc_set_page_directory_v1E_05
2965 };
2966 #endif
2967
2968 #ifndef SKIP_PRINT_rpc_unset_page_directory_v1E_05
2969 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_unset_page_directory_v1E_05[] = {
2970 {
2971 .vtype = vtype_NvHandle,
2972 .offset = NV_OFFSETOF(rpc_unset_page_directory_v1E_05, hClient),
2973 #if (defined(DEBUG) || defined(DEVELOP))
2974 .name = "hClient"
2975 #endif
2976 },
2977 {
2978 .vtype = vtype_NvHandle,
2979 .offset = NV_OFFSETOF(rpc_unset_page_directory_v1E_05, hDevice),
2980 #if (defined(DEBUG) || defined(DEVELOP))
2981 .name = "hDevice"
2982 #endif
2983 },
2984 {
2985 .vtype = vtype_NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS_v1E_05,
2986 .offset = NV_OFFSETOF(rpc_unset_page_directory_v1E_05, params),
2987 #if (defined(DEBUG) || defined(DEVELOP))
2988 .name = "params"
2989 #endif
2990 },
2991 {
2992 .vtype = vt_end
2993 }
2994 };
2995
2996 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_unset_page_directory_v1E_05 = {
2997 #if (defined(DEBUG) || defined(DEVELOP))
2998 .name = "rpc_unset_page_directory",
2999 #endif
3000 .header_length = sizeof(rpc_unset_page_directory_v1E_05),
3001 .fdesc = vmiopd_fdesc_t_rpc_unset_page_directory_v1E_05
3002 };
3003 #endif
3004
3005 #ifndef SKIP_PRINT_rpc_get_gsp_static_info_v14_00
3006 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_get_gsp_static_info_v14_00[] = {
3007 {
3008 .vtype = vtype_NvU32,
3009 .offset = NV_OFFSETOF(rpc_get_gsp_static_info_v14_00, data),
3010 #if (defined(DEBUG) || defined(DEVELOP))
3011 .name = "data"
3012 #endif
3013 },
3014 {
3015 .vtype = vt_end
3016 }
3017 };
3018
3019 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_get_gsp_static_info_v14_00 = {
3020 #if (defined(DEBUG) || defined(DEVELOP))
3021 .name = "rpc_get_gsp_static_info",
3022 #endif
3023 .header_length = sizeof(rpc_get_gsp_static_info_v14_00),
3024 .fdesc = vmiopd_fdesc_t_rpc_get_gsp_static_info_v14_00
3025 };
3026 #endif
3027
3028 #ifndef SKIP_PRINT_rpc_update_bar_pde_v15_00
3029 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_update_bar_pde_v15_00[] = {
3030 {
3031 .vtype = vtype_UpdateBarPde_v15_00,
3032 .offset = NV_OFFSETOF(rpc_update_bar_pde_v15_00, info),
3033 #if (defined(DEBUG) || defined(DEVELOP))
3034 .name = "info"
3035 #endif
3036 },
3037 {
3038 .vtype = vt_end
3039 }
3040 };
3041
3042 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_update_bar_pde_v15_00 = {
3043 #if (defined(DEBUG) || defined(DEVELOP))
3044 .name = "rpc_update_bar_pde",
3045 #endif
3046 .header_length = sizeof(rpc_update_bar_pde_v15_00),
3047 .fdesc = vmiopd_fdesc_t_rpc_update_bar_pde_v15_00
3048 };
3049 #endif
3050
3051 #ifndef SKIP_PRINT_rpc_get_encoder_capacity_v07_00
3052 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_get_encoder_capacity_v07_00[] = {
3053 {
3054 .vtype = vtype_NvHandle,
3055 .offset = NV_OFFSETOF(rpc_get_encoder_capacity_v07_00, hClient),
3056 #if (defined(DEBUG) || defined(DEVELOP))
3057 .name = "hClient"
3058 #endif
3059 },
3060 {
3061 .vtype = vtype_NvHandle,
3062 .offset = NV_OFFSETOF(rpc_get_encoder_capacity_v07_00, hObject),
3063 #if (defined(DEBUG) || defined(DEVELOP))
3064 .name = "hObject"
3065 #endif
3066 },
3067 {
3068 .vtype = vtype_NvU32,
3069 .offset = NV_OFFSETOF(rpc_get_encoder_capacity_v07_00, encoderCapacity),
3070 #if (defined(DEBUG) || defined(DEVELOP))
3071 .name = "encoderCapacity"
3072 #endif
3073 },
3074 {
3075 .vtype = vt_end
3076 }
3077 };
3078
3079 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_get_encoder_capacity_v07_00 = {
3080 #if (defined(DEBUG) || defined(DEVELOP))
3081 .name = "rpc_get_encoder_capacity",
3082 #endif
3083 .header_length = sizeof(rpc_get_encoder_capacity_v07_00),
3084 .fdesc = vmiopd_fdesc_t_rpc_get_encoder_capacity_v07_00
3085 };
3086 #endif
3087
3088 #ifndef SKIP_PRINT_rpc_vgpu_pf_reg_read32_v15_00
3089 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_vgpu_pf_reg_read32_v15_00[] = {
3090 {
3091 .vtype = vtype_NvU64,
3092 .offset = NV_OFFSETOF(rpc_vgpu_pf_reg_read32_v15_00, address),
3093 #if (defined(DEBUG) || defined(DEVELOP))
3094 .name = "address"
3095 #endif
3096 },
3097 {
3098 .vtype = vtype_NvU32,
3099 .offset = NV_OFFSETOF(rpc_vgpu_pf_reg_read32_v15_00, value),
3100 #if (defined(DEBUG) || defined(DEVELOP))
3101 .name = "value"
3102 #endif
3103 },
3104 {
3105 .vtype = vtype_NvU32,
3106 .offset = NV_OFFSETOF(rpc_vgpu_pf_reg_read32_v15_00, grEngId),
3107 #if (defined(DEBUG) || defined(DEVELOP))
3108 .name = "grEngId"
3109 #endif
3110 },
3111 {
3112 .vtype = vt_end
3113 }
3114 };
3115
3116 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_vgpu_pf_reg_read32_v15_00 = {
3117 #if (defined(DEBUG) || defined(DEVELOP))
3118 .name = "rpc_vgpu_pf_reg_read32",
3119 #endif
3120 .header_length = sizeof(rpc_vgpu_pf_reg_read32_v15_00),
3121 .fdesc = vmiopd_fdesc_t_rpc_vgpu_pf_reg_read32_v15_00
3122 };
3123 #endif
3124
3125 #ifndef SKIP_PRINT_rpc_ctrl_set_vgpu_fb_usage_v1A_08
3126 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_set_vgpu_fb_usage_v1A_08[] = {
3127 {
3128 .vtype = vtype_NVA080_CTRL_SET_FB_USAGE_PARAMS_v07_02,
3129 .offset = NV_OFFSETOF(rpc_ctrl_set_vgpu_fb_usage_v1A_08, setFbUsage),
3130 #if (defined(DEBUG) || defined(DEVELOP))
3131 .name = "setFbUsage"
3132 #endif
3133 },
3134 {
3135 .vtype = vt_end
3136 }
3137 };
3138
3139 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_set_vgpu_fb_usage_v1A_08 = {
3140 #if (defined(DEBUG) || defined(DEVELOP))
3141 .name = "rpc_ctrl_set_vgpu_fb_usage",
3142 #endif
3143 .header_length = sizeof(rpc_ctrl_set_vgpu_fb_usage_v1A_08),
3144 .fdesc = vmiopd_fdesc_t_rpc_ctrl_set_vgpu_fb_usage_v1A_08
3145 };
3146 #endif
3147
3148 #ifndef SKIP_PRINT_rpc_ctrl_nvenc_sw_session_update_info_v1A_09
3149 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_nvenc_sw_session_update_info_v1A_09[] = {
3150 {
3151 .vtype = vtype_NvHandle,
3152 .offset = NV_OFFSETOF(rpc_ctrl_nvenc_sw_session_update_info_v1A_09, hClient),
3153 #if (defined(DEBUG) || defined(DEVELOP))
3154 .name = "hClient"
3155 #endif
3156 },
3157 {
3158 .vtype = vtype_NvHandle,
3159 .offset = NV_OFFSETOF(rpc_ctrl_nvenc_sw_session_update_info_v1A_09, hObject),
3160 #if (defined(DEBUG) || defined(DEVELOP))
3161 .name = "hObject"
3162 #endif
3163 },
3164 {
3165 .vtype = vtype_NVA0BC_CTRL_NVENC_SW_SESSION_UPDATE_INFO_PARAMS_v06_01,
3166 .offset = NV_OFFSETOF(rpc_ctrl_nvenc_sw_session_update_info_v1A_09, nvencSessionUpdate),
3167 #if (defined(DEBUG) || defined(DEVELOP))
3168 .name = "nvencSessionUpdate"
3169 #endif
3170 },
3171 {
3172 .vtype = vt_end
3173 }
3174 };
3175
3176 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_nvenc_sw_session_update_info_v1A_09 = {
3177 #if (defined(DEBUG) || defined(DEVELOP))
3178 .name = "rpc_ctrl_nvenc_sw_session_update_info",
3179 #endif
3180 .header_length = sizeof(rpc_ctrl_nvenc_sw_session_update_info_v1A_09),
3181 .fdesc = vmiopd_fdesc_t_rpc_ctrl_nvenc_sw_session_update_info_v1A_09
3182 };
3183 #endif
3184
3185 #ifndef SKIP_PRINT_rpc_ctrl_reset_channel_v1A_09
3186 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_reset_channel_v1A_09[] = {
3187 {
3188 .vtype = vtype_NvHandle,
3189 .offset = NV_OFFSETOF(rpc_ctrl_reset_channel_v1A_09, hClient),
3190 #if (defined(DEBUG) || defined(DEVELOP))
3191 .name = "hClient"
3192 #endif
3193 },
3194 {
3195 .vtype = vtype_NvHandle,
3196 .offset = NV_OFFSETOF(rpc_ctrl_reset_channel_v1A_09, hObject),
3197 #if (defined(DEBUG) || defined(DEVELOP))
3198 .name = "hObject"
3199 #endif
3200 },
3201 {
3202 .vtype = vtype_NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS_v10_01,
3203 .offset = NV_OFFSETOF(rpc_ctrl_reset_channel_v1A_09, resetChannel),
3204 #if (defined(DEBUG) || defined(DEVELOP))
3205 .name = "resetChannel"
3206 #endif
3207 },
3208 {
3209 .vtype = vt_end
3210 }
3211 };
3212
3213 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_reset_channel_v1A_09 = {
3214 #if (defined(DEBUG) || defined(DEVELOP))
3215 .name = "rpc_ctrl_reset_channel",
3216 #endif
3217 .header_length = sizeof(rpc_ctrl_reset_channel_v1A_09),
3218 .fdesc = vmiopd_fdesc_t_rpc_ctrl_reset_channel_v1A_09
3219 };
3220 #endif
3221
3222 #ifndef SKIP_PRINT_rpc_ctrl_reset_isolated_channel_v1A_09
3223 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_reset_isolated_channel_v1A_09[] = {
3224 {
3225 .vtype = vtype_NvHandle,
3226 .offset = NV_OFFSETOF(rpc_ctrl_reset_isolated_channel_v1A_09, hClient),
3227 #if (defined(DEBUG) || defined(DEVELOP))
3228 .name = "hClient"
3229 #endif
3230 },
3231 {
3232 .vtype = vtype_NvHandle,
3233 .offset = NV_OFFSETOF(rpc_ctrl_reset_isolated_channel_v1A_09, hObject),
3234 #if (defined(DEBUG) || defined(DEVELOP))
3235 .name = "hObject"
3236 #endif
3237 },
3238 {
3239 .vtype = vtype_NV506F_CTRL_CMD_RESET_ISOLATED_CHANNEL_PARAMS_v03_00,
3240 .offset = NV_OFFSETOF(rpc_ctrl_reset_isolated_channel_v1A_09, resetIsolatedChannel),
3241 #if (defined(DEBUG) || defined(DEVELOP))
3242 .name = "resetIsolatedChannel"
3243 #endif
3244 },
3245 {
3246 .vtype = vt_end
3247 }
3248 };
3249
3250 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_reset_isolated_channel_v1A_09 = {
3251 #if (defined(DEBUG) || defined(DEVELOP))
3252 .name = "rpc_ctrl_reset_isolated_channel",
3253 #endif
3254 .header_length = sizeof(rpc_ctrl_reset_isolated_channel_v1A_09),
3255 .fdesc = vmiopd_fdesc_t_rpc_ctrl_reset_isolated_channel_v1A_09
3256 };
3257 #endif
3258
3259 #ifndef SKIP_PRINT_rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09
3260 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09[] = {
3261 {
3262 .vtype = vtype_NvHandle,
3263 .offset = NV_OFFSETOF(rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09, hClient),
3264 #if (defined(DEBUG) || defined(DEVELOP))
3265 .name = "hClient"
3266 #endif
3267 },
3268 {
3269 .vtype = vtype_NvHandle,
3270 .offset = NV_OFFSETOF(rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09, hObject),
3271 #if (defined(DEBUG) || defined(DEVELOP))
3272 .name = "hObject"
3273 #endif
3274 },
3275 {
3276 .vtype = vtype_NV2080_CTRL_CMD_GPU_HANDLE_VF_PRI_FAULT_PARAMS_v18_09,
3277 .offset = NV_OFFSETOF(rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09, handleVfPriFault),
3278 #if (defined(DEBUG) || defined(DEVELOP))
3279 .name = "handleVfPriFault"
3280 #endif
3281 },
3282 {
3283 .vtype = vt_end
3284 }
3285 };
3286
3287 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09 = {
3288 #if (defined(DEBUG) || defined(DEVELOP))
3289 .name = "rpc_ctrl_gpu_handle_vf_pri_fault",
3290 #endif
3291 .header_length = sizeof(rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09),
3292 .fdesc = vmiopd_fdesc_t_rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09
3293 };
3294 #endif
3295
3296 #ifndef SKIP_PRINT_rpc_ctrl_perf_boost_v1A_09
3297 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_perf_boost_v1A_09[] = {
3298 {
3299 .vtype = vtype_NvHandle,
3300 .offset = NV_OFFSETOF(rpc_ctrl_perf_boost_v1A_09, hClient),
3301 #if (defined(DEBUG) || defined(DEVELOP))
3302 .name = "hClient"
3303 #endif
3304 },
3305 {
3306 .vtype = vtype_NvHandle,
3307 .offset = NV_OFFSETOF(rpc_ctrl_perf_boost_v1A_09, hObject),
3308 #if (defined(DEBUG) || defined(DEVELOP))
3309 .name = "hObject"
3310 #endif
3311 },
3312 {
3313 .vtype = vtype_NV2080_CTRL_PERF_BOOST_PARAMS_v03_00,
3314 .offset = NV_OFFSETOF(rpc_ctrl_perf_boost_v1A_09, perfBoost),
3315 #if (defined(DEBUG) || defined(DEVELOP))
3316 .name = "perfBoost"
3317 #endif
3318 },
3319 {
3320 .vtype = vt_end
3321 }
3322 };
3323
3324 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_perf_boost_v1A_09 = {
3325 #if (defined(DEBUG) || defined(DEVELOP))
3326 .name = "rpc_ctrl_perf_boost",
3327 #endif
3328 .header_length = sizeof(rpc_ctrl_perf_boost_v1A_09),
3329 .fdesc = vmiopd_fdesc_t_rpc_ctrl_perf_boost_v1A_09
3330 };
3331 #endif
3332
3333 #ifndef SKIP_PRINT_rpc_ctrl_get_zbc_clear_table_v1A_09
3334 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_get_zbc_clear_table_v1A_09[] = {
3335 {
3336 .vtype = vtype_NvHandle,
3337 .offset = NV_OFFSETOF(rpc_ctrl_get_zbc_clear_table_v1A_09, hClient),
3338 #if (defined(DEBUG) || defined(DEVELOP))
3339 .name = "hClient"
3340 #endif
3341 },
3342 {
3343 .vtype = vtype_NvHandle,
3344 .offset = NV_OFFSETOF(rpc_ctrl_get_zbc_clear_table_v1A_09, hObject),
3345 #if (defined(DEBUG) || defined(DEVELOP))
3346 .name = "hObject"
3347 #endif
3348 },
3349 {
3350 .vtype = vtype_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_PARAMS_v04_00,
3351 .offset = NV_OFFSETOF(rpc_ctrl_get_zbc_clear_table_v1A_09, getZbcClearTable),
3352 #if (defined(DEBUG) || defined(DEVELOP))
3353 .name = "getZbcClearTable"
3354 #endif
3355 },
3356 {
3357 .vtype = vt_end
3358 }
3359 };
3360
3361 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_get_zbc_clear_table_v1A_09 = {
3362 #if (defined(DEBUG) || defined(DEVELOP))
3363 .name = "rpc_ctrl_get_zbc_clear_table",
3364 #endif
3365 .header_length = sizeof(rpc_ctrl_get_zbc_clear_table_v1A_09),
3366 .fdesc = vmiopd_fdesc_t_rpc_ctrl_get_zbc_clear_table_v1A_09
3367 };
3368 #endif
3369
3370 #ifndef SKIP_PRINT_rpc_ctrl_set_zbc_color_clear_v1A_09
3371 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_set_zbc_color_clear_v1A_09[] = {
3372 {
3373 .vtype = vtype_NvHandle,
3374 .offset = NV_OFFSETOF(rpc_ctrl_set_zbc_color_clear_v1A_09, hClient),
3375 #if (defined(DEBUG) || defined(DEVELOP))
3376 .name = "hClient"
3377 #endif
3378 },
3379 {
3380 .vtype = vtype_NvHandle,
3381 .offset = NV_OFFSETOF(rpc_ctrl_set_zbc_color_clear_v1A_09, hObject),
3382 #if (defined(DEBUG) || defined(DEVELOP))
3383 .name = "hObject"
3384 #endif
3385 },
3386 {
3387 .vtype = vtype_NV9096_CTRL_SET_ZBC_COLOR_CLEAR_PARAMS_v03_00,
3388 .offset = NV_OFFSETOF(rpc_ctrl_set_zbc_color_clear_v1A_09, setZbcColorClr),
3389 #if (defined(DEBUG) || defined(DEVELOP))
3390 .name = "setZbcColorClr"
3391 #endif
3392 },
3393 {
3394 .vtype = vt_end
3395 }
3396 };
3397
3398 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_set_zbc_color_clear_v1A_09 = {
3399 #if (defined(DEBUG) || defined(DEVELOP))
3400 .name = "rpc_ctrl_set_zbc_color_clear",
3401 #endif
3402 .header_length = sizeof(rpc_ctrl_set_zbc_color_clear_v1A_09),
3403 .fdesc = vmiopd_fdesc_t_rpc_ctrl_set_zbc_color_clear_v1A_09
3404 };
3405 #endif
3406
3407 #ifndef SKIP_PRINT_rpc_ctrl_set_zbc_depth_clear_v1A_09
3408 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_set_zbc_depth_clear_v1A_09[] = {
3409 {
3410 .vtype = vtype_NvHandle,
3411 .offset = NV_OFFSETOF(rpc_ctrl_set_zbc_depth_clear_v1A_09, hClient),
3412 #if (defined(DEBUG) || defined(DEVELOP))
3413 .name = "hClient"
3414 #endif
3415 },
3416 {
3417 .vtype = vtype_NvHandle,
3418 .offset = NV_OFFSETOF(rpc_ctrl_set_zbc_depth_clear_v1A_09, hObject),
3419 #if (defined(DEBUG) || defined(DEVELOP))
3420 .name = "hObject"
3421 #endif
3422 },
3423 {
3424 .vtype = vtype_NV9096_CTRL_SET_ZBC_DEPTH_CLEAR_PARAMS_v03_00,
3425 .offset = NV_OFFSETOF(rpc_ctrl_set_zbc_depth_clear_v1A_09, setZbcDepthClr),
3426 #if (defined(DEBUG) || defined(DEVELOP))
3427 .name = "setZbcDepthClr"
3428 #endif
3429 },
3430 {
3431 .vtype = vt_end
3432 }
3433 };
3434
3435 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_set_zbc_depth_clear_v1A_09 = {
3436 #if (defined(DEBUG) || defined(DEVELOP))
3437 .name = "rpc_ctrl_set_zbc_depth_clear",
3438 #endif
3439 .header_length = sizeof(rpc_ctrl_set_zbc_depth_clear_v1A_09),
3440 .fdesc = vmiopd_fdesc_t_rpc_ctrl_set_zbc_depth_clear_v1A_09
3441 };
3442 #endif
3443
3444 #ifndef SKIP_PRINT_rpc_ctrl_gpfifo_schedule_v1A_0A
3445 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gpfifo_schedule_v1A_0A[] = {
3446 {
3447 .vtype = vtype_NvHandle,
3448 .offset = NV_OFFSETOF(rpc_ctrl_gpfifo_schedule_v1A_0A, hClient),
3449 #if (defined(DEBUG) || defined(DEVELOP))
3450 .name = "hClient"
3451 #endif
3452 },
3453 {
3454 .vtype = vtype_NvHandle,
3455 .offset = NV_OFFSETOF(rpc_ctrl_gpfifo_schedule_v1A_0A, hObject),
3456 #if (defined(DEBUG) || defined(DEVELOP))
3457 .name = "hObject"
3458 #endif
3459 },
3460 {
3461 .vtype = vtype_NvU32,
3462 .offset = NV_OFFSETOF(rpc_ctrl_gpfifo_schedule_v1A_0A, cmd),
3463 #if (defined(DEBUG) || defined(DEVELOP))
3464 .name = "cmd"
3465 #endif
3466 },
3467 {
3468 .vtype = vtype_NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_v03_00,
3469 .offset = NV_OFFSETOF(rpc_ctrl_gpfifo_schedule_v1A_0A, gpfifoSchedule),
3470 #if (defined(DEBUG) || defined(DEVELOP))
3471 .name = "gpfifoSchedule"
3472 #endif
3473 },
3474 {
3475 .vtype = vt_end
3476 }
3477 };
3478
3479 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gpfifo_schedule_v1A_0A = {
3480 #if (defined(DEBUG) || defined(DEVELOP))
3481 .name = "rpc_ctrl_gpfifo_schedule",
3482 #endif
3483 .header_length = sizeof(rpc_ctrl_gpfifo_schedule_v1A_0A),
3484 .fdesc = vmiopd_fdesc_t_rpc_ctrl_gpfifo_schedule_v1A_0A
3485 };
3486 #endif
3487
3488 #ifndef SKIP_PRINT_rpc_ctrl_set_timeslice_v1A_0A
3489 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_set_timeslice_v1A_0A[] = {
3490 {
3491 .vtype = vtype_NvHandle,
3492 .offset = NV_OFFSETOF(rpc_ctrl_set_timeslice_v1A_0A, hClient),
3493 #if (defined(DEBUG) || defined(DEVELOP))
3494 .name = "hClient"
3495 #endif
3496 },
3497 {
3498 .vtype = vtype_NvHandle,
3499 .offset = NV_OFFSETOF(rpc_ctrl_set_timeslice_v1A_0A, hObject),
3500 #if (defined(DEBUG) || defined(DEVELOP))
3501 .name = "hObject"
3502 #endif
3503 },
3504 {
3505 .vtype = vtype_NVA06C_CTRL_TIMESLICE_PARAMS_v06_00,
3506 .offset = NV_OFFSETOF(rpc_ctrl_set_timeslice_v1A_0A, setTimeSlice),
3507 #if (defined(DEBUG) || defined(DEVELOP))
3508 .name = "setTimeSlice"
3509 #endif
3510 },
3511 {
3512 .vtype = vt_end
3513 }
3514 };
3515
3516 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_set_timeslice_v1A_0A = {
3517 #if (defined(DEBUG) || defined(DEVELOP))
3518 .name = "rpc_ctrl_set_timeslice",
3519 #endif
3520 .header_length = sizeof(rpc_ctrl_set_timeslice_v1A_0A),
3521 .fdesc = vmiopd_fdesc_t_rpc_ctrl_set_timeslice_v1A_0A
3522 };
3523 #endif
3524
3525 #ifndef SKIP_PRINT_rpc_ctrl_fifo_disable_channels_v1A_0A
3526 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_fifo_disable_channels_v1A_0A[] = {
3527 {
3528 .vtype = vtype_NvHandle,
3529 .offset = NV_OFFSETOF(rpc_ctrl_fifo_disable_channels_v1A_0A, hClient),
3530 #if (defined(DEBUG) || defined(DEVELOP))
3531 .name = "hClient"
3532 #endif
3533 },
3534 {
3535 .vtype = vtype_NvHandle,
3536 .offset = NV_OFFSETOF(rpc_ctrl_fifo_disable_channels_v1A_0A, hObject),
3537 #if (defined(DEBUG) || defined(DEVELOP))
3538 .name = "hObject"
3539 #endif
3540 },
3541 {
3542 .vtype = vtype_NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS_v06_00,
3543 .offset = NV_OFFSETOF(rpc_ctrl_fifo_disable_channels_v1A_0A, fifoDisableChannels),
3544 #if (defined(DEBUG) || defined(DEVELOP))
3545 .name = "fifoDisableChannels"
3546 #endif
3547 },
3548 {
3549 .vtype = vt_end
3550 }
3551 };
3552
3553 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_fifo_disable_channels_v1A_0A = {
3554 #if (defined(DEBUG) || defined(DEVELOP))
3555 .name = "rpc_ctrl_fifo_disable_channels",
3556 #endif
3557 .header_length = sizeof(rpc_ctrl_fifo_disable_channels_v1A_0A),
3558 .fdesc = vmiopd_fdesc_t_rpc_ctrl_fifo_disable_channels_v1A_0A
3559 };
3560 #endif
3561
3562 #ifndef SKIP_PRINT_rpc_ctrl_preempt_v1A_0A
3563 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_preempt_v1A_0A[] = {
3564 {
3565 .vtype = vtype_NvHandle,
3566 .offset = NV_OFFSETOF(rpc_ctrl_preempt_v1A_0A, hClient),
3567 #if (defined(DEBUG) || defined(DEVELOP))
3568 .name = "hClient"
3569 #endif
3570 },
3571 {
3572 .vtype = vtype_NvHandle,
3573 .offset = NV_OFFSETOF(rpc_ctrl_preempt_v1A_0A, hObject),
3574 #if (defined(DEBUG) || defined(DEVELOP))
3575 .name = "hObject"
3576 #endif
3577 },
3578 {
3579 .vtype = vtype_NVA06C_CTRL_PREEMPT_PARAMS_v09_0A,
3580 .offset = NV_OFFSETOF(rpc_ctrl_preempt_v1A_0A, cmdPreempt),
3581 #if (defined(DEBUG) || defined(DEVELOP))
3582 .name = "cmdPreempt"
3583 #endif
3584 },
3585 {
3586 .vtype = vt_end
3587 }
3588 };
3589
3590 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_preempt_v1A_0A = {
3591 #if (defined(DEBUG) || defined(DEVELOP))
3592 .name = "rpc_ctrl_preempt",
3593 #endif
3594 .header_length = sizeof(rpc_ctrl_preempt_v1A_0A),
3595 .fdesc = vmiopd_fdesc_t_rpc_ctrl_preempt_v1A_0A
3596 };
3597 #endif
3598
3599 #ifndef SKIP_PRINT_rpc_ctrl_set_tsg_interleave_level_v1A_0A
3600 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_set_tsg_interleave_level_v1A_0A[] = {
3601 {
3602 .vtype = vtype_NvHandle,
3603 .offset = NV_OFFSETOF(rpc_ctrl_set_tsg_interleave_level_v1A_0A, hClient),
3604 #if (defined(DEBUG) || defined(DEVELOP))
3605 .name = "hClient"
3606 #endif
3607 },
3608 {
3609 .vtype = vtype_NvHandle,
3610 .offset = NV_OFFSETOF(rpc_ctrl_set_tsg_interleave_level_v1A_0A, hObject),
3611 #if (defined(DEBUG) || defined(DEVELOP))
3612 .name = "hObject"
3613 #endif
3614 },
3615 {
3616 .vtype = vtype_NVA06C_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02,
3617 .offset = NV_OFFSETOF(rpc_ctrl_set_tsg_interleave_level_v1A_0A, interleaveLevelTSG),
3618 #if (defined(DEBUG) || defined(DEVELOP))
3619 .name = "interleaveLevelTSG"
3620 #endif
3621 },
3622 {
3623 .vtype = vt_end
3624 }
3625 };
3626
3627 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_set_tsg_interleave_level_v1A_0A = {
3628 #if (defined(DEBUG) || defined(DEVELOP))
3629 .name = "rpc_ctrl_set_tsg_interleave_level",
3630 #endif
3631 .header_length = sizeof(rpc_ctrl_set_tsg_interleave_level_v1A_0A),
3632 .fdesc = vmiopd_fdesc_t_rpc_ctrl_set_tsg_interleave_level_v1A_0A
3633 };
3634 #endif
3635
3636 #ifndef SKIP_PRINT_rpc_ctrl_set_channel_interleave_level_v1A_0A
3637 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_set_channel_interleave_level_v1A_0A[] = {
3638 {
3639 .vtype = vtype_NvHandle,
3640 .offset = NV_OFFSETOF(rpc_ctrl_set_channel_interleave_level_v1A_0A, hClient),
3641 #if (defined(DEBUG) || defined(DEVELOP))
3642 .name = "hClient"
3643 #endif
3644 },
3645 {
3646 .vtype = vtype_NvHandle,
3647 .offset = NV_OFFSETOF(rpc_ctrl_set_channel_interleave_level_v1A_0A, hObject),
3648 #if (defined(DEBUG) || defined(DEVELOP))
3649 .name = "hObject"
3650 #endif
3651 },
3652 {
3653 .vtype = vtype_NVA06F_CTRL_INTERLEAVE_LEVEL_PARAMS_v17_02,
3654 .offset = NV_OFFSETOF(rpc_ctrl_set_channel_interleave_level_v1A_0A, interleaveLevelChannel),
3655 #if (defined(DEBUG) || defined(DEVELOP))
3656 .name = "interleaveLevelChannel"
3657 #endif
3658 },
3659 {
3660 .vtype = vt_end
3661 }
3662 };
3663
3664 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_set_channel_interleave_level_v1A_0A = {
3665 #if (defined(DEBUG) || defined(DEVELOP))
3666 .name = "rpc_ctrl_set_channel_interleave_level",
3667 #endif
3668 .header_length = sizeof(rpc_ctrl_set_channel_interleave_level_v1A_0A),
3669 .fdesc = vmiopd_fdesc_t_rpc_ctrl_set_channel_interleave_level_v1A_0A
3670 };
3671 #endif
3672
3673 #ifndef SKIP_PRINT_rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E
3674 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E[] = {
3675 {
3676 .vtype = vtype_NvHandle,
3677 .offset = NV_OFFSETOF(rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E, hClient),
3678 #if (defined(DEBUG) || defined(DEVELOP))
3679 .name = "hClient"
3680 #endif
3681 },
3682 {
3683 .vtype = vtype_NvHandle,
3684 .offset = NV_OFFSETOF(rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E, hObject),
3685 #if (defined(DEBUG) || defined(DEVELOP))
3686 .name = "hObject"
3687 #endif
3688 },
3689 {
3690 .vtype = vtype_NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_v12_01,
3691 .offset = NV_OFFSETOF(rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E, ctrlParams),
3692 #if (defined(DEBUG) || defined(DEVELOP))
3693 .name = "ctrlParams"
3694 #endif
3695 },
3696 {
3697 .vtype = vt_end
3698 }
3699 };
3700
3701 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E = {
3702 #if (defined(DEBUG) || defined(DEVELOP))
3703 .name = "rpc_ctrl_gr_ctxsw_preemption_bind",
3704 #endif
3705 .header_length = sizeof(rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E),
3706 .fdesc = vmiopd_fdesc_t_rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E
3707 };
3708 #endif
3709
3710 #ifndef SKIP_PRINT_rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E
3711 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E[] = {
3712 {
3713 .vtype = vtype_NvHandle,
3714 .offset = NV_OFFSETOF(rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E, hClient),
3715 #if (defined(DEBUG) || defined(DEVELOP))
3716 .name = "hClient"
3717 #endif
3718 },
3719 {
3720 .vtype = vtype_NvHandle,
3721 .offset = NV_OFFSETOF(rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E, hObject),
3722 #if (defined(DEBUG) || defined(DEVELOP))
3723 .name = "hObject"
3724 #endif
3725 },
3726 {
3727 .vtype = vtype_NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_v12_01,
3728 .offset = NV_OFFSETOF(rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E, ctrlParams),
3729 #if (defined(DEBUG) || defined(DEVELOP))
3730 .name = "ctrlParams"
3731 #endif
3732 },
3733 {
3734 .vtype = vt_end
3735 }
3736 };
3737
3738 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E = {
3739 #if (defined(DEBUG) || defined(DEVELOP))
3740 .name = "rpc_ctrl_gr_set_ctxsw_preemption_mode",
3741 #endif
3742 .header_length = sizeof(rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E),
3743 .fdesc = vmiopd_fdesc_t_rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E
3744 };
3745 #endif
3746
3747 #ifndef SKIP_PRINT_rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E
3748 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E[] = {
3749 {
3750 .vtype = vtype_NvHandle,
3751 .offset = NV_OFFSETOF(rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E, hClient),
3752 #if (defined(DEBUG) || defined(DEVELOP))
3753 .name = "hClient"
3754 #endif
3755 },
3756 {
3757 .vtype = vtype_NvHandle,
3758 .offset = NV_OFFSETOF(rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E, hObject),
3759 #if (defined(DEBUG) || defined(DEVELOP))
3760 .name = "hObject"
3761 #endif
3762 },
3763 {
3764 .vtype = vtype_NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_v03_00,
3765 .offset = NV_OFFSETOF(rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E, ctrlParams),
3766 #if (defined(DEBUG) || defined(DEVELOP))
3767 .name = "ctrlParams"
3768 #endif
3769 },
3770 {
3771 .vtype = vt_end
3772 }
3773 };
3774
3775 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E = {
3776 #if (defined(DEBUG) || defined(DEVELOP))
3777 .name = "rpc_ctrl_gr_ctxsw_zcull_bind",
3778 #endif
3779 .header_length = sizeof(rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E),
3780 .fdesc = vmiopd_fdesc_t_rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E
3781 };
3782 #endif
3783
3784 #ifndef SKIP_PRINT_rpc_ctrl_gpu_initialize_ctx_v1A_0E
3785 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gpu_initialize_ctx_v1A_0E[] = {
3786 {
3787 .vtype = vtype_NvHandle,
3788 .offset = NV_OFFSETOF(rpc_ctrl_gpu_initialize_ctx_v1A_0E, hClient),
3789 #if (defined(DEBUG) || defined(DEVELOP))
3790 .name = "hClient"
3791 #endif
3792 },
3793 {
3794 .vtype = vtype_NvHandle,
3795 .offset = NV_OFFSETOF(rpc_ctrl_gpu_initialize_ctx_v1A_0E, hObject),
3796 #if (defined(DEBUG) || defined(DEVELOP))
3797 .name = "hObject"
3798 #endif
3799 },
3800 {
3801 .vtype = vtype_NV2080_CTRL_GPU_INITIALIZE_CTX_PARAMS_v03_00,
3802 .offset = NV_OFFSETOF(rpc_ctrl_gpu_initialize_ctx_v1A_0E, ctrlParams),
3803 #if (defined(DEBUG) || defined(DEVELOP))
3804 .name = "ctrlParams"
3805 #endif
3806 },
3807 {
3808 .vtype = vt_end
3809 }
3810 };
3811
3812 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gpu_initialize_ctx_v1A_0E = {
3813 #if (defined(DEBUG) || defined(DEVELOP))
3814 .name = "rpc_ctrl_gpu_initialize_ctx",
3815 #endif
3816 .header_length = sizeof(rpc_ctrl_gpu_initialize_ctx_v1A_0E),
3817 .fdesc = vmiopd_fdesc_t_rpc_ctrl_gpu_initialize_ctx_v1A_0E
3818 };
3819 #endif
3820
3821 #ifndef SKIP_PRINT_rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04
3822 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04[] = {
3823 {
3824 .vtype = vtype_NvHandle,
3825 .offset = NV_OFFSETOF(rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04, hClient),
3826 #if (defined(DEBUG) || defined(DEVELOP))
3827 .name = "hClient"
3828 #endif
3829 },
3830 {
3831 .vtype = vtype_NvHandle,
3832 .offset = NV_OFFSETOF(rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04, hObject),
3833 #if (defined(DEBUG) || defined(DEVELOP))
3834 .name = "hObject"
3835 #endif
3836 },
3837 {
3838 .vtype = vtype_NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_v1E_04,
3839 .offset = NV_OFFSETOF(rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04, ctrlParams),
3840 #if (defined(DEBUG) || defined(DEVELOP))
3841 .name = "ctrlParams"
3842 #endif
3843 },
3844 {
3845 .vtype = vt_end
3846 }
3847 };
3848
3849 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04 = {
3850 #if (defined(DEBUG) || defined(DEVELOP))
3851 .name = "rpc_ctrl_vaspace_copy_server_reserved_pdes",
3852 #endif
3853 .header_length = sizeof(rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04),
3854 .fdesc = vmiopd_fdesc_t_rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04
3855 };
3856 #endif
3857
3858 #ifndef SKIP_PRINT_rpc_ctrl_mc_service_interrupts_v1A_0E
3859 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_mc_service_interrupts_v1A_0E[] = {
3860 {
3861 .vtype = vtype_NvHandle,
3862 .offset = NV_OFFSETOF(rpc_ctrl_mc_service_interrupts_v1A_0E, hClient),
3863 #if (defined(DEBUG) || defined(DEVELOP))
3864 .name = "hClient"
3865 #endif
3866 },
3867 {
3868 .vtype = vtype_NvHandle,
3869 .offset = NV_OFFSETOF(rpc_ctrl_mc_service_interrupts_v1A_0E, hObject),
3870 #if (defined(DEBUG) || defined(DEVELOP))
3871 .name = "hObject"
3872 #endif
3873 },
3874 {
3875 .vtype = vtype_NV2080_CTRL_MC_SERVICE_INTERRUPTS_PARAMS_v15_01,
3876 .offset = NV_OFFSETOF(rpc_ctrl_mc_service_interrupts_v1A_0E, ctrlParams),
3877 #if (defined(DEBUG) || defined(DEVELOP))
3878 .name = "ctrlParams"
3879 #endif
3880 },
3881 {
3882 .vtype = vt_end
3883 }
3884 };
3885
3886 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_mc_service_interrupts_v1A_0E = {
3887 #if (defined(DEBUG) || defined(DEVELOP))
3888 .name = "rpc_ctrl_mc_service_interrupts",
3889 #endif
3890 .header_length = sizeof(rpc_ctrl_mc_service_interrupts_v1A_0E),
3891 .fdesc = vmiopd_fdesc_t_rpc_ctrl_mc_service_interrupts_v1A_0E
3892 };
3893 #endif
3894
3895 #ifndef SKIP_PRINT_rpc_ctrl_get_p2p_caps_v2_v1F_0D
3896 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_get_p2p_caps_v2_v1F_0D[] = {
3897 {
3898 .vtype = vtype_NvU8,
3899 .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_v2_v1F_0D, iter),
3900 #if (defined(DEBUG) || defined(DEVELOP))
3901 .name = "iter"
3902 #endif
3903 },
3904 {
3905 .vtype = vtype_NvU32_array,
3906 .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_v2_v1F_0D, gpuIds),
3907 .array_length = NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS,
3908 #if (defined(DEBUG) || defined(DEVELOP))
3909 .name = "gpuIds"
3910 #endif
3911 },
3912 {
3913 .vtype = vtype_NvU32,
3914 .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_v2_v1F_0D, gpuCount),
3915 #if (defined(DEBUG) || defined(DEVELOP))
3916 .name = "gpuCount"
3917 #endif
3918 },
3919 {
3920 .vtype = vtype_NvU32,
3921 .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_v2_v1F_0D, p2pCaps),
3922 #if (defined(DEBUG) || defined(DEVELOP))
3923 .name = "p2pCaps"
3924 #endif
3925 },
3926 {
3927 .vtype = vtype_NvU32,
3928 .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_v2_v1F_0D, p2pOptimalReadCEs),
3929 #if (defined(DEBUG) || defined(DEVELOP))
3930 .name = "p2pOptimalReadCEs"
3931 #endif
3932 },
3933 {
3934 .vtype = vtype_NvU32,
3935 .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_v2_v1F_0D, p2pOptimalWriteCEs),
3936 #if (defined(DEBUG) || defined(DEVELOP))
3937 .name = "p2pOptimalWriteCEs"
3938 #endif
3939 },
3940 {
3941 .vtype = vtype_NvU8_array,
3942 .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_v2_v1F_0D, p2pCapsStatus),
3943 .array_length = NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE_v1F_0D,
3944 #if (defined(DEBUG) || defined(DEVELOP))
3945 .name = "p2pCapsStatus"
3946 #endif
3947 },
3948 {
3949 .vtype = vtype_NvU32_array,
3950 .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_v2_v1F_0D, busPeerIds),
3951 .array_length = VGPU_RPC_GET_P2P_CAPS_V2_MAX_GPUS_SQUARED_PER_RPC,
3952 #if (defined(DEBUG) || defined(DEVELOP))
3953 .name = "busPeerIds"
3954 #endif
3955 },
3956 {
3957 .vtype = vt_end
3958 }
3959 };
3960
3961 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_get_p2p_caps_v2_v1F_0D = {
3962 #if (defined(DEBUG) || defined(DEVELOP))
3963 .name = "rpc_ctrl_get_p2p_caps_v2",
3964 #endif
3965 .header_length = sizeof(rpc_ctrl_get_p2p_caps_v2_v1F_0D),
3966 .fdesc = vmiopd_fdesc_t_rpc_ctrl_get_p2p_caps_v2_v1F_0D
3967 };
3968 #endif
3969
3970 #ifndef SKIP_PRINT_rpc_ctrl_subdevice_get_p2p_caps_v21_02
3971 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_subdevice_get_p2p_caps_v21_02[] = {
3972 {
3973 .vtype = vtype_NV2080_CTRL_GET_P2P_CAPS_PARAMS_v21_02,
3974 .offset = NV_OFFSETOF(rpc_ctrl_subdevice_get_p2p_caps_v21_02, ctrlParams),
3975 #if (defined(DEBUG) || defined(DEVELOP))
3976 .name = "ctrlParams"
3977 #endif
3978 },
3979 {
3980 .vtype = vt_end
3981 }
3982 };
3983
3984 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_subdevice_get_p2p_caps_v21_02 = {
3985 #if (defined(DEBUG) || defined(DEVELOP))
3986 .name = "rpc_ctrl_subdevice_get_p2p_caps",
3987 #endif
3988 .header_length = sizeof(rpc_ctrl_subdevice_get_p2p_caps_v21_02),
3989 .fdesc = vmiopd_fdesc_t_rpc_ctrl_subdevice_get_p2p_caps_v21_02
3990 };
3991 #endif
3992
3993 #ifndef SKIP_PRINT_rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C
3994 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C[] = {
3995 {
3996 .vtype = vtype_NvHandle,
3997 .offset = NV_OFFSETOF(rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C, hClient),
3998 #if (defined(DEBUG) || defined(DEVELOP))
3999 .name = "hClient"
4000 #endif
4001 },
4002 {
4003 .vtype = vtype_NvHandle,
4004 .offset = NV_OFFSETOF(rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C, hObject),
4005 #if (defined(DEBUG) || defined(DEVELOP))
4006 .name = "hObject"
4007 #endif
4008 },
4009 {
4010 .vtype = vtype_NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS_v03_00,
4011 .offset = NV_OFFSETOF(rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C, ctrlParams),
4012 #if (defined(DEBUG) || defined(DEVELOP))
4013 .name = "ctrlParams"
4014 #endif
4015 },
4016 {
4017 .vtype = vt_end
4018 }
4019 };
4020
4021 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C = {
4022 #if (defined(DEBUG) || defined(DEVELOP))
4023 .name = "rpc_ctrl_dbg_clear_all_sm_error_states",
4024 #endif
4025 .header_length = sizeof(rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C),
4026 .fdesc = vmiopd_fdesc_t_rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C
4027 };
4028 #endif
4029
4030 #ifndef SKIP_PRINT_rpc_ctrl_dbg_read_all_sm_error_states_v21_06
4031 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dbg_read_all_sm_error_states_v21_06[] = {
4032 {
4033 .vtype = vtype_NvHandle,
4034 .offset = NV_OFFSETOF(rpc_ctrl_dbg_read_all_sm_error_states_v21_06, hClient),
4035 #if (defined(DEBUG) || defined(DEVELOP))
4036 .name = "hClient"
4037 #endif
4038 },
4039 {
4040 .vtype = vtype_NvHandle,
4041 .offset = NV_OFFSETOF(rpc_ctrl_dbg_read_all_sm_error_states_v21_06, hObject),
4042 #if (defined(DEBUG) || defined(DEVELOP))
4043 .name = "hObject"
4044 #endif
4045 },
4046 {
4047 .vtype = vtype_NV83DE_CTRL_DEBUG_READ_ALL_SM_ERROR_STATES_PARAMS_v21_06,
4048 .offset = NV_OFFSETOF(rpc_ctrl_dbg_read_all_sm_error_states_v21_06, ctrlParams),
4049 #if (defined(DEBUG) || defined(DEVELOP))
4050 .name = "ctrlParams"
4051 #endif
4052 },
4053 {
4054 .vtype = vt_end
4055 }
4056 };
4057
4058 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dbg_read_all_sm_error_states_v21_06 = {
4059 #if (defined(DEBUG) || defined(DEVELOP))
4060 .name = "rpc_ctrl_dbg_read_all_sm_error_states",
4061 #endif
4062 .header_length = sizeof(rpc_ctrl_dbg_read_all_sm_error_states_v21_06),
4063 .fdesc = vmiopd_fdesc_t_rpc_ctrl_dbg_read_all_sm_error_states_v21_06
4064 };
4065 #endif
4066
4067 #ifndef SKIP_PRINT_rpc_ctrl_dbg_set_exception_mask_v1A_0C
4068 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dbg_set_exception_mask_v1A_0C[] = {
4069 {
4070 .vtype = vtype_NvHandle,
4071 .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_exception_mask_v1A_0C, hClient),
4072 #if (defined(DEBUG) || defined(DEVELOP))
4073 .name = "hClient"
4074 #endif
4075 },
4076 {
4077 .vtype = vtype_NvHandle,
4078 .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_exception_mask_v1A_0C, hObject),
4079 #if (defined(DEBUG) || defined(DEVELOP))
4080 .name = "hObject"
4081 #endif
4082 },
4083 {
4084 .vtype = vtype_NV83DE_CTRL_DEBUG_SET_EXCEPTION_MASK_PARAMS_v03_00,
4085 .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_exception_mask_v1A_0C, ctrlParams),
4086 #if (defined(DEBUG) || defined(DEVELOP))
4087 .name = "ctrlParams"
4088 #endif
4089 },
4090 {
4091 .vtype = vt_end
4092 }
4093 };
4094
4095 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dbg_set_exception_mask_v1A_0C = {
4096 #if (defined(DEBUG) || defined(DEVELOP))
4097 .name = "rpc_ctrl_dbg_set_exception_mask",
4098 #endif
4099 .header_length = sizeof(rpc_ctrl_dbg_set_exception_mask_v1A_0C),
4100 .fdesc = vmiopd_fdesc_t_rpc_ctrl_dbg_set_exception_mask_v1A_0C
4101 };
4102 #endif
4103
4104 #ifndef SKIP_PRINT_rpc_ctrl_gpu_promote_ctx_v1A_20
4105 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gpu_promote_ctx_v1A_20[] = {
4106 {
4107 .vtype = vtype_NvHandle,
4108 .offset = NV_OFFSETOF(rpc_ctrl_gpu_promote_ctx_v1A_20, hClient),
4109 #if (defined(DEBUG) || defined(DEVELOP))
4110 .name = "hClient"
4111 #endif
4112 },
4113 {
4114 .vtype = vtype_NvHandle,
4115 .offset = NV_OFFSETOF(rpc_ctrl_gpu_promote_ctx_v1A_20, hObject),
4116 #if (defined(DEBUG) || defined(DEVELOP))
4117 .name = "hObject"
4118 #endif
4119 },
4120 {
4121 .vtype = vtype_NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_v1A_20,
4122 .offset = NV_OFFSETOF(rpc_ctrl_gpu_promote_ctx_v1A_20, promoteCtx),
4123 #if (defined(DEBUG) || defined(DEVELOP))
4124 .name = "promoteCtx"
4125 #endif
4126 },
4127 {
4128 .vtype = vt_end
4129 }
4130 };
4131
4132 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gpu_promote_ctx_v1A_20 = {
4133 #if (defined(DEBUG) || defined(DEVELOP))
4134 .name = "rpc_ctrl_gpu_promote_ctx",
4135 #endif
4136 .header_length = sizeof(rpc_ctrl_gpu_promote_ctx_v1A_20),
4137 .fdesc = vmiopd_fdesc_t_rpc_ctrl_gpu_promote_ctx_v1A_20
4138 };
4139 #endif
4140
4141 #ifndef SKIP_PRINT_rpc_ctrl_dbg_suspend_context_v1A_10
4142 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dbg_suspend_context_v1A_10[] = {
4143 {
4144 .vtype = vtype_NvHandle,
4145 .offset = NV_OFFSETOF(rpc_ctrl_dbg_suspend_context_v1A_10, hClient),
4146 #if (defined(DEBUG) || defined(DEVELOP))
4147 .name = "hClient"
4148 #endif
4149 },
4150 {
4151 .vtype = vtype_NvHandle,
4152 .offset = NV_OFFSETOF(rpc_ctrl_dbg_suspend_context_v1A_10, hObject),
4153 #if (defined(DEBUG) || defined(DEVELOP))
4154 .name = "hObject"
4155 #endif
4156 },
4157 {
4158 .vtype = vtype_NV83DE_CTRL_CMD_DEBUG_SUSPEND_CONTEXT_PARAMS_v1A_06,
4159 .offset = NV_OFFSETOF(rpc_ctrl_dbg_suspend_context_v1A_10, ctrlParams),
4160 #if (defined(DEBUG) || defined(DEVELOP))
4161 .name = "ctrlParams"
4162 #endif
4163 },
4164 {
4165 .vtype = vt_end
4166 }
4167 };
4168
4169 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dbg_suspend_context_v1A_10 = {
4170 #if (defined(DEBUG) || defined(DEVELOP))
4171 .name = "rpc_ctrl_dbg_suspend_context",
4172 #endif
4173 .header_length = sizeof(rpc_ctrl_dbg_suspend_context_v1A_10),
4174 .fdesc = vmiopd_fdesc_t_rpc_ctrl_dbg_suspend_context_v1A_10
4175 };
4176 #endif
4177
4178 #ifndef SKIP_PRINT_rpc_ctrl_dbg_resume_context_v1A_10
4179 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dbg_resume_context_v1A_10[] = {
4180 {
4181 .vtype = vtype_NvHandle,
4182 .offset = NV_OFFSETOF(rpc_ctrl_dbg_resume_context_v1A_10, hClient),
4183 #if (defined(DEBUG) || defined(DEVELOP))
4184 .name = "hClient"
4185 #endif
4186 },
4187 {
4188 .vtype = vtype_NvHandle,
4189 .offset = NV_OFFSETOF(rpc_ctrl_dbg_resume_context_v1A_10, hObject),
4190 #if (defined(DEBUG) || defined(DEVELOP))
4191 .name = "hObject"
4192 #endif
4193 },
4194 {
4195 .vtype = vt_end
4196 }
4197 };
4198
4199 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dbg_resume_context_v1A_10 = {
4200 #if (defined(DEBUG) || defined(DEVELOP))
4201 .name = "rpc_ctrl_dbg_resume_context",
4202 #endif
4203 .header_length = sizeof(rpc_ctrl_dbg_resume_context_v1A_10),
4204 .fdesc = vmiopd_fdesc_t_rpc_ctrl_dbg_resume_context_v1A_10
4205 };
4206 #endif
4207
4208 #ifndef SKIP_PRINT_rpc_ctrl_dbg_exec_reg_ops_v1A_10
4209 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dbg_exec_reg_ops_v1A_10[] = {
4210 {
4211 .vtype = vtype_NvHandle,
4212 .offset = NV_OFFSETOF(rpc_ctrl_dbg_exec_reg_ops_v1A_10, hClient),
4213 #if (defined(DEBUG) || defined(DEVELOP))
4214 .name = "hClient"
4215 #endif
4216 },
4217 {
4218 .vtype = vtype_NvHandle,
4219 .offset = NV_OFFSETOF(rpc_ctrl_dbg_exec_reg_ops_v1A_10, hObject),
4220 #if (defined(DEBUG) || defined(DEVELOP))
4221 .name = "hObject"
4222 #endif
4223 },
4224 {
4225 .vtype = vtype_NV83DE_CTRL_DEBUG_EXEC_REG_OPS_PARAMS_v1A_06,
4226 .offset = NV_OFFSETOF(rpc_ctrl_dbg_exec_reg_ops_v1A_10, ctrlParams),
4227 #if (defined(DEBUG) || defined(DEVELOP))
4228 .name = "ctrlParams"
4229 #endif
4230 },
4231 {
4232 .vtype = vt_end
4233 }
4234 };
4235
4236 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dbg_exec_reg_ops_v1A_10 = {
4237 #if (defined(DEBUG) || defined(DEVELOP))
4238 .name = "rpc_ctrl_dbg_exec_reg_ops",
4239 #endif
4240 .header_length = sizeof(rpc_ctrl_dbg_exec_reg_ops_v1A_10),
4241 .fdesc = vmiopd_fdesc_t_rpc_ctrl_dbg_exec_reg_ops_v1A_10
4242 };
4243 #endif
4244
4245 #ifndef SKIP_PRINT_rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10
4246 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10[] = {
4247 {
4248 .vtype = vtype_NvHandle,
4249 .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10, hClient),
4250 #if (defined(DEBUG) || defined(DEVELOP))
4251 .name = "hClient"
4252 #endif
4253 },
4254 {
4255 .vtype = vtype_NvHandle,
4256 .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10, hObject),
4257 #if (defined(DEBUG) || defined(DEVELOP))
4258 .name = "hObject"
4259 #endif
4260 },
4261 {
4262 .vtype = vtype_NV83DE_CTRL_DEBUG_SET_MODE_MMU_DEBUG_PARAMS_v1A_06,
4263 .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10, ctrlParams),
4264 #if (defined(DEBUG) || defined(DEVELOP))
4265 .name = "ctrlParams"
4266 #endif
4267 },
4268 {
4269 .vtype = vt_end
4270 }
4271 };
4272
4273 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10 = {
4274 #if (defined(DEBUG) || defined(DEVELOP))
4275 .name = "rpc_ctrl_dbg_set_mode_mmu_debug",
4276 #endif
4277 .header_length = sizeof(rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10),
4278 .fdesc = vmiopd_fdesc_t_rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10
4279 };
4280 #endif
4281
4282 #ifndef SKIP_PRINT_rpc_ctrl_dbg_read_single_sm_error_state_v21_06
4283 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dbg_read_single_sm_error_state_v21_06[] = {
4284 {
4285 .vtype = vtype_NvHandle,
4286 .offset = NV_OFFSETOF(rpc_ctrl_dbg_read_single_sm_error_state_v21_06, hClient),
4287 #if (defined(DEBUG) || defined(DEVELOP))
4288 .name = "hClient"
4289 #endif
4290 },
4291 {
4292 .vtype = vtype_NvHandle,
4293 .offset = NV_OFFSETOF(rpc_ctrl_dbg_read_single_sm_error_state_v21_06, hObject),
4294 #if (defined(DEBUG) || defined(DEVELOP))
4295 .name = "hObject"
4296 #endif
4297 },
4298 {
4299 .vtype = vtype_NV83DE_CTRL_DEBUG_READ_SINGLE_SM_ERROR_STATE_PARAMS_v21_06,
4300 .offset = NV_OFFSETOF(rpc_ctrl_dbg_read_single_sm_error_state_v21_06, ctrlParams),
4301 #if (defined(DEBUG) || defined(DEVELOP))
4302 .name = "ctrlParams"
4303 #endif
4304 },
4305 {
4306 .vtype = vt_end
4307 }
4308 };
4309
4310 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dbg_read_single_sm_error_state_v21_06 = {
4311 #if (defined(DEBUG) || defined(DEVELOP))
4312 .name = "rpc_ctrl_dbg_read_single_sm_error_state",
4313 #endif
4314 .header_length = sizeof(rpc_ctrl_dbg_read_single_sm_error_state_v21_06),
4315 .fdesc = vmiopd_fdesc_t_rpc_ctrl_dbg_read_single_sm_error_state_v21_06
4316 };
4317 #endif
4318
4319 #ifndef SKIP_PRINT_rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10
4320 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10[] = {
4321 {
4322 .vtype = vtype_NvHandle,
4323 .offset = NV_OFFSETOF(rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10, hClient),
4324 #if (defined(DEBUG) || defined(DEVELOP))
4325 .name = "hClient"
4326 #endif
4327 },
4328 {
4329 .vtype = vtype_NvHandle,
4330 .offset = NV_OFFSETOF(rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10, hObject),
4331 #if (defined(DEBUG) || defined(DEVELOP))
4332 .name = "hObject"
4333 #endif
4334 },
4335 {
4336 .vtype = vtype_NV83DE_CTRL_DEBUG_CLEAR_SINGLE_SM_ERROR_STATE_PARAMS_v1A_06,
4337 .offset = NV_OFFSETOF(rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10, ctrlParams),
4338 #if (defined(DEBUG) || defined(DEVELOP))
4339 .name = "ctrlParams"
4340 #endif
4341 },
4342 {
4343 .vtype = vt_end
4344 }
4345 };
4346
4347 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10 = {
4348 #if (defined(DEBUG) || defined(DEVELOP))
4349 .name = "rpc_ctrl_dbg_clear_single_sm_error_state",
4350 #endif
4351 .header_length = sizeof(rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10),
4352 .fdesc = vmiopd_fdesc_t_rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10
4353 };
4354 #endif
4355
4356 #ifndef SKIP_PRINT_rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10
4357 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10[] = {
4358 {
4359 .vtype = vtype_NvHandle,
4360 .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10, hClient),
4361 #if (defined(DEBUG) || defined(DEVELOP))
4362 .name = "hClient"
4363 #endif
4364 },
4365 {
4366 .vtype = vtype_NvHandle,
4367 .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10, hObject),
4368 #if (defined(DEBUG) || defined(DEVELOP))
4369 .name = "hObject"
4370 #endif
4371 },
4372 {
4373 .vtype = vtype_NV83DE_CTRL_DEBUG_SET_MODE_ERRBAR_DEBUG_PARAMS_v1A_06,
4374 .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10, ctrlParams),
4375 #if (defined(DEBUG) || defined(DEVELOP))
4376 .name = "ctrlParams"
4377 #endif
4378 },
4379 {
4380 .vtype = vt_end
4381 }
4382 };
4383
4384 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10 = {
4385 #if (defined(DEBUG) || defined(DEVELOP))
4386 .name = "rpc_ctrl_dbg_set_mode_errbar_debug",
4387 #endif
4388 .header_length = sizeof(rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10),
4389 .fdesc = vmiopd_fdesc_t_rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10
4390 };
4391 #endif
4392
4393 #ifndef SKIP_PRINT_rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10
4394 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10[] = {
4395 {
4396 .vtype = vtype_NvHandle,
4397 .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10, hClient),
4398 #if (defined(DEBUG) || defined(DEVELOP))
4399 .name = "hClient"
4400 #endif
4401 },
4402 {
4403 .vtype = vtype_NvHandle,
4404 .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10, hObject),
4405 #if (defined(DEBUG) || defined(DEVELOP))
4406 .name = "hObject"
4407 #endif
4408 },
4409 {
4410 .vtype = vtype_NV83DE_CTRL_DEBUG_SET_NEXT_STOP_TRIGGER_TYPE_PARAMS_v1A_06,
4411 .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10, ctrlParams),
4412 #if (defined(DEBUG) || defined(DEVELOP))
4413 .name = "ctrlParams"
4414 #endif
4415 },
4416 {
4417 .vtype = vt_end
4418 }
4419 };
4420
4421 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10 = {
4422 #if (defined(DEBUG) || defined(DEVELOP))
4423 .name = "rpc_ctrl_dbg_set_next_stop_trigger_type",
4424 #endif
4425 .header_length = sizeof(rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10),
4426 .fdesc = vmiopd_fdesc_t_rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10
4427 };
4428 #endif
4429
4430 #ifndef SKIP_PRINT_rpc_ctrl_dma_set_default_vaspace_v1A_0E
4431 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dma_set_default_vaspace_v1A_0E[] = {
4432 {
4433 .vtype = vtype_NvHandle,
4434 .offset = NV_OFFSETOF(rpc_ctrl_dma_set_default_vaspace_v1A_0E, hClient),
4435 #if (defined(DEBUG) || defined(DEVELOP))
4436 .name = "hClient"
4437 #endif
4438 },
4439 {
4440 .vtype = vtype_NvHandle,
4441 .offset = NV_OFFSETOF(rpc_ctrl_dma_set_default_vaspace_v1A_0E, hObject),
4442 #if (defined(DEBUG) || defined(DEVELOP))
4443 .name = "hObject"
4444 #endif
4445 },
4446 {
4447 .vtype = vtype_NV0080_CTRL_DMA_SET_DEFAULT_VASPACE_PARAMS_v03_00,
4448 .offset = NV_OFFSETOF(rpc_ctrl_dma_set_default_vaspace_v1A_0E, ctrlParams),
4449 #if (defined(DEBUG) || defined(DEVELOP))
4450 .name = "ctrlParams"
4451 #endif
4452 },
4453 {
4454 .vtype = vt_end
4455 }
4456 };
4457
4458 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dma_set_default_vaspace_v1A_0E = {
4459 #if (defined(DEBUG) || defined(DEVELOP))
4460 .name = "rpc_ctrl_dma_set_default_vaspace",
4461 #endif
4462 .header_length = sizeof(rpc_ctrl_dma_set_default_vaspace_v1A_0E),
4463 .fdesc = vmiopd_fdesc_t_rpc_ctrl_dma_set_default_vaspace_v1A_0E
4464 };
4465 #endif
4466
4467 #ifndef SKIP_PRINT_rpc_ctrl_get_ce_pce_mask_v1A_0E
4468 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_get_ce_pce_mask_v1A_0E[] = {
4469 {
4470 .vtype = vtype_NvHandle,
4471 .offset = NV_OFFSETOF(rpc_ctrl_get_ce_pce_mask_v1A_0E, hClient),
4472 #if (defined(DEBUG) || defined(DEVELOP))
4473 .name = "hClient"
4474 #endif
4475 },
4476 {
4477 .vtype = vtype_NvHandle,
4478 .offset = NV_OFFSETOF(rpc_ctrl_get_ce_pce_mask_v1A_0E, hObject),
4479 #if (defined(DEBUG) || defined(DEVELOP))
4480 .name = "hObject"
4481 #endif
4482 },
4483 {
4484 .vtype = vtype_NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_v1A_07,
4485 .offset = NV_OFFSETOF(rpc_ctrl_get_ce_pce_mask_v1A_0E, ctrlParams),
4486 #if (defined(DEBUG) || defined(DEVELOP))
4487 .name = "ctrlParams"
4488 #endif
4489 },
4490 {
4491 .vtype = vt_end
4492 }
4493 };
4494
4495 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_get_ce_pce_mask_v1A_0E = {
4496 #if (defined(DEBUG) || defined(DEVELOP))
4497 .name = "rpc_ctrl_get_ce_pce_mask",
4498 #endif
4499 .header_length = sizeof(rpc_ctrl_get_ce_pce_mask_v1A_0E),
4500 .fdesc = vmiopd_fdesc_t_rpc_ctrl_get_ce_pce_mask_v1A_0E
4501 };
4502 #endif
4503
4504 #ifndef SKIP_PRINT_rpc_ctrl_get_zbc_clear_table_entry_v1A_0E
4505 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_get_zbc_clear_table_entry_v1A_0E[] = {
4506 {
4507 .vtype = vtype_NvHandle,
4508 .offset = NV_OFFSETOF(rpc_ctrl_get_zbc_clear_table_entry_v1A_0E, hClient),
4509 #if (defined(DEBUG) || defined(DEVELOP))
4510 .name = "hClient"
4511 #endif
4512 },
4513 {
4514 .vtype = vtype_NvHandle,
4515 .offset = NV_OFFSETOF(rpc_ctrl_get_zbc_clear_table_entry_v1A_0E, hObject),
4516 #if (defined(DEBUG) || defined(DEVELOP))
4517 .name = "hObject"
4518 #endif
4519 },
4520 {
4521 .vtype = vtype_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS_v1A_07,
4522 .offset = NV_OFFSETOF(rpc_ctrl_get_zbc_clear_table_entry_v1A_0E, ctrlParams),
4523 #if (defined(DEBUG) || defined(DEVELOP))
4524 .name = "ctrlParams"
4525 #endif
4526 },
4527 {
4528 .vtype = vt_end
4529 }
4530 };
4531
4532 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_get_zbc_clear_table_entry_v1A_0E = {
4533 #if (defined(DEBUG) || defined(DEVELOP))
4534 .name = "rpc_ctrl_get_zbc_clear_table_entry",
4535 #endif
4536 .header_length = sizeof(rpc_ctrl_get_zbc_clear_table_entry_v1A_0E),
4537 .fdesc = vmiopd_fdesc_t_rpc_ctrl_get_zbc_clear_table_entry_v1A_0E
4538 };
4539 #endif
4540
4541 #ifndef SKIP_PRINT_rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E
4542 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E[] = {
4543 {
4544 .vtype = vtype_NvHandle,
4545 .offset = NV_OFFSETOF(rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E, hClient),
4546 #if (defined(DEBUG) || defined(DEVELOP))
4547 .name = "hClient"
4548 #endif
4549 },
4550 {
4551 .vtype = vtype_NvHandle,
4552 .offset = NV_OFFSETOF(rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E, hObject),
4553 #if (defined(DEBUG) || defined(DEVELOP))
4554 .name = "hObject"
4555 #endif
4556 },
4557 {
4558 .vtype = vtype_NV2080_CTRL_BUS_GET_NVLINK_PEER_ID_MASK_PARAMS_v14_00,
4559 .offset = NV_OFFSETOF(rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E, ctrlParams),
4560 #if (defined(DEBUG) || defined(DEVELOP))
4561 .name = "ctrlParams"
4562 #endif
4563 },
4564 {
4565 .vtype = vt_end
4566 }
4567 };
4568
4569 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E = {
4570 #if (defined(DEBUG) || defined(DEVELOP))
4571 .name = "rpc_ctrl_get_nvlink_peer_id_mask",
4572 #endif
4573 .header_length = sizeof(rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E),
4574 .fdesc = vmiopd_fdesc_t_rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E
4575 };
4576 #endif
4577
4578 #ifndef SKIP_PRINT_rpc_ctrl_get_nvlink_status_v23_04
4579 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_get_nvlink_status_v23_04[] = {
4580 {
4581 .vtype = vtype_NvHandle,
4582 .offset = NV_OFFSETOF(rpc_ctrl_get_nvlink_status_v23_04, hClient),
4583 #if (defined(DEBUG) || defined(DEVELOP))
4584 .name = "hClient"
4585 #endif
4586 },
4587 {
4588 .vtype = vtype_NvHandle,
4589 .offset = NV_OFFSETOF(rpc_ctrl_get_nvlink_status_v23_04, hObject),
4590 #if (defined(DEBUG) || defined(DEVELOP))
4591 .name = "hObject"
4592 #endif
4593 },
4594 {
4595 .vtype = vtype_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS_v23_04,
4596 .offset = NV_OFFSETOF(rpc_ctrl_get_nvlink_status_v23_04, ctrlParams),
4597 #if (defined(DEBUG) || defined(DEVELOP))
4598 .name = "ctrlParams"
4599 #endif
4600 },
4601 {
4602 .vtype = vt_end
4603 }
4604 };
4605
4606 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_get_nvlink_status_v23_04 = {
4607 #if (defined(DEBUG) || defined(DEVELOP))
4608 .name = "rpc_ctrl_get_nvlink_status",
4609 #endif
4610 .header_length = sizeof(rpc_ctrl_get_nvlink_status_v23_04),
4611 .fdesc = vmiopd_fdesc_t_rpc_ctrl_get_nvlink_status_v23_04
4612 };
4613 #endif
4614
4615 #ifndef SKIP_PRINT_rpc_ctrl_get_p2p_caps_v1F_0D
4616 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_get_p2p_caps_v1F_0D[] = {
4617 {
4618 .vtype = vtype_NvHandle,
4619 .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_v1F_0D, hClient),
4620 #if (defined(DEBUG) || defined(DEVELOP))
4621 .name = "hClient"
4622 #endif
4623 },
4624 {
4625 .vtype = vtype_NvHandle,
4626 .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_v1F_0D, hObject),
4627 #if (defined(DEBUG) || defined(DEVELOP))
4628 .name = "hObject"
4629 #endif
4630 },
4631 {
4632 .vtype = vtype_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_v1F_0D,
4633 .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_v1F_0D, ctrlParams),
4634 #if (defined(DEBUG) || defined(DEVELOP))
4635 .name = "ctrlParams"
4636 #endif
4637 },
4638 {
4639 .vtype = vt_end
4640 }
4641 };
4642
4643 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_get_p2p_caps_v1F_0D = {
4644 #if (defined(DEBUG) || defined(DEVELOP))
4645 .name = "rpc_ctrl_get_p2p_caps",
4646 #endif
4647 .header_length = sizeof(rpc_ctrl_get_p2p_caps_v1F_0D),
4648 .fdesc = vmiopd_fdesc_t_rpc_ctrl_get_p2p_caps_v1F_0D
4649 };
4650 #endif
4651
4652 #ifndef SKIP_PRINT_rpc_ctrl_get_p2p_caps_matrix_v1A_0E
4653 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_get_p2p_caps_matrix_v1A_0E[] = {
4654 {
4655 .vtype = vtype_NvHandle,
4656 .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_matrix_v1A_0E, hClient),
4657 #if (defined(DEBUG) || defined(DEVELOP))
4658 .name = "hClient"
4659 #endif
4660 },
4661 {
4662 .vtype = vtype_NvHandle,
4663 .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_matrix_v1A_0E, hObject),
4664 #if (defined(DEBUG) || defined(DEVELOP))
4665 .name = "hObject"
4666 #endif
4667 },
4668 {
4669 .vtype = vtype_NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_v18_0A,
4670 .offset = NV_OFFSETOF(rpc_ctrl_get_p2p_caps_matrix_v1A_0E, ctrlParams),
4671 #if (defined(DEBUG) || defined(DEVELOP))
4672 .name = "ctrlParams"
4673 #endif
4674 },
4675 {
4676 .vtype = vt_end
4677 }
4678 };
4679
4680 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_get_p2p_caps_matrix_v1A_0E = {
4681 #if (defined(DEBUG) || defined(DEVELOP))
4682 .name = "rpc_ctrl_get_p2p_caps_matrix",
4683 #endif
4684 .header_length = sizeof(rpc_ctrl_get_p2p_caps_matrix_v1A_0E),
4685 .fdesc = vmiopd_fdesc_t_rpc_ctrl_get_p2p_caps_matrix_v1A_0E
4686 };
4687 #endif
4688
4689 #ifndef SKIP_PRINT_rpc_ctrl_reserve_pm_area_smpc_v1A_0F
4690 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_reserve_pm_area_smpc_v1A_0F[] = {
4691 {
4692 .vtype = vtype_NvHandle,
4693 .offset = NV_OFFSETOF(rpc_ctrl_reserve_pm_area_smpc_v1A_0F, hClient),
4694 #if (defined(DEBUG) || defined(DEVELOP))
4695 .name = "hClient"
4696 #endif
4697 },
4698 {
4699 .vtype = vtype_NvHandle,
4700 .offset = NV_OFFSETOF(rpc_ctrl_reserve_pm_area_smpc_v1A_0F, hObject),
4701 #if (defined(DEBUG) || defined(DEVELOP))
4702 .name = "hObject"
4703 #endif
4704 },
4705 {
4706 .vtype = vtype_NVB0CC_CTRL_RESERVE_PM_AREA_SMPC_PARAMS_v1A_0F,
4707 .offset = NV_OFFSETOF(rpc_ctrl_reserve_pm_area_smpc_v1A_0F, params),
4708 #if (defined(DEBUG) || defined(DEVELOP))
4709 .name = "params"
4710 #endif
4711 },
4712 {
4713 .vtype = vt_end
4714 }
4715 };
4716
4717 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_reserve_pm_area_smpc_v1A_0F = {
4718 #if (defined(DEBUG) || defined(DEVELOP))
4719 .name = "rpc_ctrl_reserve_pm_area_smpc",
4720 #endif
4721 .header_length = sizeof(rpc_ctrl_reserve_pm_area_smpc_v1A_0F),
4722 .fdesc = vmiopd_fdesc_t_rpc_ctrl_reserve_pm_area_smpc_v1A_0F
4723 };
4724 #endif
4725
4726 #ifndef SKIP_PRINT_rpc_ctrl_reserve_hwpm_legacy_v1A_0F
4727 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_reserve_hwpm_legacy_v1A_0F[] = {
4728 {
4729 .vtype = vtype_NvHandle,
4730 .offset = NV_OFFSETOF(rpc_ctrl_reserve_hwpm_legacy_v1A_0F, hClient),
4731 #if (defined(DEBUG) || defined(DEVELOP))
4732 .name = "hClient"
4733 #endif
4734 },
4735 {
4736 .vtype = vtype_NvHandle,
4737 .offset = NV_OFFSETOF(rpc_ctrl_reserve_hwpm_legacy_v1A_0F, hObject),
4738 #if (defined(DEBUG) || defined(DEVELOP))
4739 .name = "hObject"
4740 #endif
4741 },
4742 {
4743 .vtype = vtype_NVB0CC_CTRL_RESERVE_HWPM_LEGACY_PARAMS_v1A_0F,
4744 .offset = NV_OFFSETOF(rpc_ctrl_reserve_hwpm_legacy_v1A_0F, params),
4745 #if (defined(DEBUG) || defined(DEVELOP))
4746 .name = "params"
4747 #endif
4748 },
4749 {
4750 .vtype = vt_end
4751 }
4752 };
4753
4754 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_reserve_hwpm_legacy_v1A_0F = {
4755 #if (defined(DEBUG) || defined(DEVELOP))
4756 .name = "rpc_ctrl_reserve_hwpm_legacy",
4757 #endif
4758 .header_length = sizeof(rpc_ctrl_reserve_hwpm_legacy_v1A_0F),
4759 .fdesc = vmiopd_fdesc_t_rpc_ctrl_reserve_hwpm_legacy_v1A_0F
4760 };
4761 #endif
4762
4763 #ifndef SKIP_PRINT_rpc_ctrl_b0cc_exec_reg_ops_v1A_0F
4764 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_b0cc_exec_reg_ops_v1A_0F[] = {
4765 {
4766 .vtype = vtype_NvHandle,
4767 .offset = NV_OFFSETOF(rpc_ctrl_b0cc_exec_reg_ops_v1A_0F, hClient),
4768 #if (defined(DEBUG) || defined(DEVELOP))
4769 .name = "hClient"
4770 #endif
4771 },
4772 {
4773 .vtype = vtype_NvHandle,
4774 .offset = NV_OFFSETOF(rpc_ctrl_b0cc_exec_reg_ops_v1A_0F, hObject),
4775 #if (defined(DEBUG) || defined(DEVELOP))
4776 .name = "hObject"
4777 #endif
4778 },
4779 {
4780 .vtype = vtype_NVB0CC_CTRL_EXEC_REG_OPS_PARAMS_v1A_0F,
4781 .offset = NV_OFFSETOF(rpc_ctrl_b0cc_exec_reg_ops_v1A_0F, params),
4782 #if (defined(DEBUG) || defined(DEVELOP))
4783 .name = "params"
4784 #endif
4785 },
4786 {
4787 .vtype = vt_end
4788 }
4789 };
4790
4791 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_b0cc_exec_reg_ops_v1A_0F = {
4792 #if (defined(DEBUG) || defined(DEVELOP))
4793 .name = "rpc_ctrl_b0cc_exec_reg_ops",
4794 #endif
4795 .header_length = sizeof(rpc_ctrl_b0cc_exec_reg_ops_v1A_0F),
4796 .fdesc = vmiopd_fdesc_t_rpc_ctrl_b0cc_exec_reg_ops_v1A_0F
4797 };
4798 #endif
4799
4800 #ifndef SKIP_PRINT_rpc_ctrl_bind_pm_resources_v1A_0F
4801 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_bind_pm_resources_v1A_0F[] = {
4802 {
4803 .vtype = vtype_NvHandle,
4804 .offset = NV_OFFSETOF(rpc_ctrl_bind_pm_resources_v1A_0F, hClient),
4805 #if (defined(DEBUG) || defined(DEVELOP))
4806 .name = "hClient"
4807 #endif
4808 },
4809 {
4810 .vtype = vtype_NvHandle,
4811 .offset = NV_OFFSETOF(rpc_ctrl_bind_pm_resources_v1A_0F, hObject),
4812 #if (defined(DEBUG) || defined(DEVELOP))
4813 .name = "hObject"
4814 #endif
4815 },
4816 {
4817 .vtype = vt_end
4818 }
4819 };
4820
4821 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_bind_pm_resources_v1A_0F = {
4822 #if (defined(DEBUG) || defined(DEVELOP))
4823 .name = "rpc_ctrl_bind_pm_resources",
4824 #endif
4825 .header_length = sizeof(rpc_ctrl_bind_pm_resources_v1A_0F),
4826 .fdesc = vmiopd_fdesc_t_rpc_ctrl_bind_pm_resources_v1A_0F
4827 };
4828 #endif
4829
4830 #ifndef SKIP_PRINT_rpc_ctrl_alloc_pma_stream_v1A_14
4831 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_alloc_pma_stream_v1A_14[] = {
4832 {
4833 .vtype = vtype_NvHandle,
4834 .offset = NV_OFFSETOF(rpc_ctrl_alloc_pma_stream_v1A_14, hClient),
4835 #if (defined(DEBUG) || defined(DEVELOP))
4836 .name = "hClient"
4837 #endif
4838 },
4839 {
4840 .vtype = vtype_NvHandle,
4841 .offset = NV_OFFSETOF(rpc_ctrl_alloc_pma_stream_v1A_14, hObject),
4842 #if (defined(DEBUG) || defined(DEVELOP))
4843 .name = "hObject"
4844 #endif
4845 },
4846 {
4847 .vtype = vtype_NVB0CC_CTRL_ALLOC_PMA_STREAM_PARAMS_v1A_14,
4848 .offset = NV_OFFSETOF(rpc_ctrl_alloc_pma_stream_v1A_14, params),
4849 #if (defined(DEBUG) || defined(DEVELOP))
4850 .name = "params"
4851 #endif
4852 },
4853 {
4854 .vtype = vt_end
4855 }
4856 };
4857
4858 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_alloc_pma_stream_v1A_14 = {
4859 #if (defined(DEBUG) || defined(DEVELOP))
4860 .name = "rpc_ctrl_alloc_pma_stream",
4861 #endif
4862 .header_length = sizeof(rpc_ctrl_alloc_pma_stream_v1A_14),
4863 .fdesc = vmiopd_fdesc_t_rpc_ctrl_alloc_pma_stream_v1A_14
4864 };
4865 #endif
4866
4867 #ifndef SKIP_PRINT_rpc_ctrl_pma_stream_update_get_put_v1A_14
4868 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_pma_stream_update_get_put_v1A_14[] = {
4869 {
4870 .vtype = vtype_NvHandle,
4871 .offset = NV_OFFSETOF(rpc_ctrl_pma_stream_update_get_put_v1A_14, hClient),
4872 #if (defined(DEBUG) || defined(DEVELOP))
4873 .name = "hClient"
4874 #endif
4875 },
4876 {
4877 .vtype = vtype_NvHandle,
4878 .offset = NV_OFFSETOF(rpc_ctrl_pma_stream_update_get_put_v1A_14, hObject),
4879 #if (defined(DEBUG) || defined(DEVELOP))
4880 .name = "hObject"
4881 #endif
4882 },
4883 {
4884 .vtype = vtype_NVB0CC_CTRL_PMA_STREAM_UPDATE_GET_PUT_PARAMS_v1A_14,
4885 .offset = NV_OFFSETOF(rpc_ctrl_pma_stream_update_get_put_v1A_14, params),
4886 #if (defined(DEBUG) || defined(DEVELOP))
4887 .name = "params"
4888 #endif
4889 },
4890 {
4891 .vtype = vt_end
4892 }
4893 };
4894
4895 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_pma_stream_update_get_put_v1A_14 = {
4896 #if (defined(DEBUG) || defined(DEVELOP))
4897 .name = "rpc_ctrl_pma_stream_update_get_put",
4898 #endif
4899 .header_length = sizeof(rpc_ctrl_pma_stream_update_get_put_v1A_14),
4900 .fdesc = vmiopd_fdesc_t_rpc_ctrl_pma_stream_update_get_put_v1A_14
4901 };
4902 #endif
4903
4904 #ifndef SKIP_PRINT_rpc_ctrl_fb_get_info_v2_v25_0A
4905 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_fb_get_info_v2_v25_0A[] = {
4906 {
4907 .vtype = vtype_NvHandle,
4908 .offset = NV_OFFSETOF(rpc_ctrl_fb_get_info_v2_v25_0A, hClient),
4909 #if (defined(DEBUG) || defined(DEVELOP))
4910 .name = "hClient"
4911 #endif
4912 },
4913 {
4914 .vtype = vtype_NvHandle,
4915 .offset = NV_OFFSETOF(rpc_ctrl_fb_get_info_v2_v25_0A, hObject),
4916 #if (defined(DEBUG) || defined(DEVELOP))
4917 .name = "hObject"
4918 #endif
4919 },
4920 {
4921 .vtype = vtype_NV2080_CTRL_FB_GET_INFO_V2_PARAMS_v25_0A,
4922 .offset = NV_OFFSETOF(rpc_ctrl_fb_get_info_v2_v25_0A, ctrlParams),
4923 #if (defined(DEBUG) || defined(DEVELOP))
4924 .name = "ctrlParams"
4925 #endif
4926 },
4927 {
4928 .vtype = vt_end
4929 }
4930 };
4931
4932 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_fb_get_info_v2_v25_0A = {
4933 #if (defined(DEBUG) || defined(DEVELOP))
4934 .name = "rpc_ctrl_fb_get_info_v2",
4935 #endif
4936 .header_length = sizeof(rpc_ctrl_fb_get_info_v2_v25_0A),
4937 .fdesc = vmiopd_fdesc_t_rpc_ctrl_fb_get_info_v2_v25_0A
4938 };
4939 #endif
4940
4941 #ifndef SKIP_PRINT_rpc_ctrl_fifo_set_channel_properties_v1A_16
4942 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_fifo_set_channel_properties_v1A_16[] = {
4943 {
4944 .vtype = vtype_NvHandle,
4945 .offset = NV_OFFSETOF(rpc_ctrl_fifo_set_channel_properties_v1A_16, hClient),
4946 #if (defined(DEBUG) || defined(DEVELOP))
4947 .name = "hClient"
4948 #endif
4949 },
4950 {
4951 .vtype = vtype_NvHandle,
4952 .offset = NV_OFFSETOF(rpc_ctrl_fifo_set_channel_properties_v1A_16, hObject),
4953 #if (defined(DEBUG) || defined(DEVELOP))
4954 .name = "hObject"
4955 #endif
4956 },
4957 {
4958 .vtype = vtype_NV0080_CTRL_FIFO_SET_CHANNEL_PROPERTIES_PARAMS_v03_00,
4959 .offset = NV_OFFSETOF(rpc_ctrl_fifo_set_channel_properties_v1A_16, ctrlParams),
4960 #if (defined(DEBUG) || defined(DEVELOP))
4961 .name = "ctrlParams"
4962 #endif
4963 },
4964 {
4965 .vtype = vt_end
4966 }
4967 };
4968
4969 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_fifo_set_channel_properties_v1A_16 = {
4970 #if (defined(DEBUG) || defined(DEVELOP))
4971 .name = "rpc_ctrl_fifo_set_channel_properties",
4972 #endif
4973 .header_length = sizeof(rpc_ctrl_fifo_set_channel_properties_v1A_16),
4974 .fdesc = vmiopd_fdesc_t_rpc_ctrl_fifo_set_channel_properties_v1A_16
4975 };
4976 #endif
4977
4978 #ifndef SKIP_PRINT_rpc_ctrl_gpu_evict_ctx_v1A_1C
4979 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gpu_evict_ctx_v1A_1C[] = {
4980 {
4981 .vtype = vtype_NvHandle,
4982 .offset = NV_OFFSETOF(rpc_ctrl_gpu_evict_ctx_v1A_1C, hClient),
4983 #if (defined(DEBUG) || defined(DEVELOP))
4984 .name = "hClient"
4985 #endif
4986 },
4987 {
4988 .vtype = vtype_NvHandle,
4989 .offset = NV_OFFSETOF(rpc_ctrl_gpu_evict_ctx_v1A_1C, hObject),
4990 #if (defined(DEBUG) || defined(DEVELOP))
4991 .name = "hObject"
4992 #endif
4993 },
4994 {
4995 .vtype = vtype_NV2080_CTRL_GPU_EVICT_CTX_PARAMS_v03_00,
4996 .offset = NV_OFFSETOF(rpc_ctrl_gpu_evict_ctx_v1A_1C, params),
4997 #if (defined(DEBUG) || defined(DEVELOP))
4998 .name = "params"
4999 #endif
5000 },
5001 {
5002 .vtype = vt_end
5003 }
5004 };
5005
5006 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gpu_evict_ctx_v1A_1C = {
5007 #if (defined(DEBUG) || defined(DEVELOP))
5008 .name = "rpc_ctrl_gpu_evict_ctx",
5009 #endif
5010 .header_length = sizeof(rpc_ctrl_gpu_evict_ctx_v1A_1C),
5011 .fdesc = vmiopd_fdesc_t_rpc_ctrl_gpu_evict_ctx_v1A_1C
5012 };
5013 #endif
5014
5015 #ifndef SKIP_PRINT_rpc_ctrl_fb_get_fs_info_v24_00
5016 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_fb_get_fs_info_v24_00[] = {
5017 {
5018 .vtype = vtype_NvHandle,
5019 .offset = NV_OFFSETOF(rpc_ctrl_fb_get_fs_info_v24_00, hClient),
5020 #if (defined(DEBUG) || defined(DEVELOP))
5021 .name = "hClient"
5022 #endif
5023 },
5024 {
5025 .vtype = vtype_NvHandle,
5026 .offset = NV_OFFSETOF(rpc_ctrl_fb_get_fs_info_v24_00, hObject),
5027 #if (defined(DEBUG) || defined(DEVELOP))
5028 .name = "hObject"
5029 #endif
5030 },
5031 {
5032 .vtype = vtype_NV2080_CTRL_FB_GET_FS_INFO_PARAMS_v24_00,
5033 .offset = NV_OFFSETOF(rpc_ctrl_fb_get_fs_info_v24_00, params),
5034 #if (defined(DEBUG) || defined(DEVELOP))
5035 .name = "params"
5036 #endif
5037 },
5038 {
5039 .vtype = vt_end
5040 }
5041 };
5042
5043 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_fb_get_fs_info_v24_00 = {
5044 #if (defined(DEBUG) || defined(DEVELOP))
5045 .name = "rpc_ctrl_fb_get_fs_info",
5046 #endif
5047 .header_length = sizeof(rpc_ctrl_fb_get_fs_info_v24_00),
5048 .fdesc = vmiopd_fdesc_t_rpc_ctrl_fb_get_fs_info_v24_00
5049 };
5050 #endif
5051
5052 #ifndef SKIP_PRINT_rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D
5053 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D[] = {
5054 {
5055 .vtype = vtype_NvHandle,
5056 .offset = NV_OFFSETOF(rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D, hClient),
5057 #if (defined(DEBUG) || defined(DEVELOP))
5058 .name = "hClient"
5059 #endif
5060 },
5061 {
5062 .vtype = vtype_NvHandle,
5063 .offset = NV_OFFSETOF(rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D, hObject),
5064 #if (defined(DEBUG) || defined(DEVELOP))
5065 .name = "hObject"
5066 #endif
5067 },
5068 {
5069 .vtype = vtype_NV2080_CTRL_GRMGR_GET_GR_FS_INFO_PARAMS_v1A_1D,
5070 .offset = NV_OFFSETOF(rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D, params),
5071 #if (defined(DEBUG) || defined(DEVELOP))
5072 .name = "params"
5073 #endif
5074 },
5075 {
5076 .vtype = vt_end
5077 }
5078 };
5079
5080 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D = {
5081 #if (defined(DEBUG) || defined(DEVELOP))
5082 .name = "rpc_ctrl_grmgr_get_gr_fs_info",
5083 #endif
5084 .header_length = sizeof(rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D),
5085 .fdesc = vmiopd_fdesc_t_rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D
5086 };
5087 #endif
5088
5089 #ifndef SKIP_PRINT_rpc_ctrl_stop_channel_v1A_1E
5090 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_stop_channel_v1A_1E[] = {
5091 {
5092 .vtype = vtype_NvHandle,
5093 .offset = NV_OFFSETOF(rpc_ctrl_stop_channel_v1A_1E, hClient),
5094 #if (defined(DEBUG) || defined(DEVELOP))
5095 .name = "hClient"
5096 #endif
5097 },
5098 {
5099 .vtype = vtype_NvHandle,
5100 .offset = NV_OFFSETOF(rpc_ctrl_stop_channel_v1A_1E, hObject),
5101 #if (defined(DEBUG) || defined(DEVELOP))
5102 .name = "hObject"
5103 #endif
5104 },
5105 {
5106 .vtype = vtype_NVA06F_CTRL_STOP_CHANNEL_PARAMS_v1A_1E,
5107 .offset = NV_OFFSETOF(rpc_ctrl_stop_channel_v1A_1E, params),
5108 #if (defined(DEBUG) || defined(DEVELOP))
5109 .name = "params"
5110 #endif
5111 },
5112 {
5113 .vtype = vt_end
5114 }
5115 };
5116
5117 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_stop_channel_v1A_1E = {
5118 #if (defined(DEBUG) || defined(DEVELOP))
5119 .name = "rpc_ctrl_stop_channel",
5120 #endif
5121 .header_length = sizeof(rpc_ctrl_stop_channel_v1A_1E),
5122 .fdesc = vmiopd_fdesc_t_rpc_ctrl_stop_channel_v1A_1E
5123 };
5124 #endif
5125
5126 #ifndef SKIP_PRINT_rpc_ctrl_gr_pc_sampling_mode_v1A_1F
5127 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gr_pc_sampling_mode_v1A_1F[] = {
5128 {
5129 .vtype = vtype_NvHandle,
5130 .offset = NV_OFFSETOF(rpc_ctrl_gr_pc_sampling_mode_v1A_1F, hClient),
5131 #if (defined(DEBUG) || defined(DEVELOP))
5132 .name = "hClient"
5133 #endif
5134 },
5135 {
5136 .vtype = vtype_NvHandle,
5137 .offset = NV_OFFSETOF(rpc_ctrl_gr_pc_sampling_mode_v1A_1F, hObject),
5138 #if (defined(DEBUG) || defined(DEVELOP))
5139 .name = "hObject"
5140 #endif
5141 },
5142 {
5143 .vtype = vtype_NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_v1A_1F,
5144 .offset = NV_OFFSETOF(rpc_ctrl_gr_pc_sampling_mode_v1A_1F, params),
5145 #if (defined(DEBUG) || defined(DEVELOP))
5146 .name = "params"
5147 #endif
5148 },
5149 {
5150 .vtype = vt_end
5151 }
5152 };
5153
5154 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gr_pc_sampling_mode_v1A_1F = {
5155 #if (defined(DEBUG) || defined(DEVELOP))
5156 .name = "rpc_ctrl_gr_pc_sampling_mode",
5157 #endif
5158 .header_length = sizeof(rpc_ctrl_gr_pc_sampling_mode_v1A_1F),
5159 .fdesc = vmiopd_fdesc_t_rpc_ctrl_gr_pc_sampling_mode_v1A_1F
5160 };
5161 #endif
5162
5163 #ifndef SKIP_PRINT_rpc_ctrl_perf_rated_tdp_get_status_v1A_1F
5164 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_perf_rated_tdp_get_status_v1A_1F[] = {
5165 {
5166 .vtype = vtype_NvHandle,
5167 .offset = NV_OFFSETOF(rpc_ctrl_perf_rated_tdp_get_status_v1A_1F, hClient),
5168 #if (defined(DEBUG) || defined(DEVELOP))
5169 .name = "hClient"
5170 #endif
5171 },
5172 {
5173 .vtype = vtype_NvHandle,
5174 .offset = NV_OFFSETOF(rpc_ctrl_perf_rated_tdp_get_status_v1A_1F, hObject),
5175 #if (defined(DEBUG) || defined(DEVELOP))
5176 .name = "hObject"
5177 #endif
5178 },
5179 {
5180 .vtype = vtype_NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS_v1A_1F,
5181 .offset = NV_OFFSETOF(rpc_ctrl_perf_rated_tdp_get_status_v1A_1F, params),
5182 #if (defined(DEBUG) || defined(DEVELOP))
5183 .name = "params"
5184 #endif
5185 },
5186 {
5187 .vtype = vt_end
5188 }
5189 };
5190
5191 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_perf_rated_tdp_get_status_v1A_1F = {
5192 #if (defined(DEBUG) || defined(DEVELOP))
5193 .name = "rpc_ctrl_perf_rated_tdp_get_status",
5194 #endif
5195 .header_length = sizeof(rpc_ctrl_perf_rated_tdp_get_status_v1A_1F),
5196 .fdesc = vmiopd_fdesc_t_rpc_ctrl_perf_rated_tdp_get_status_v1A_1F
5197 };
5198 #endif
5199
5200 #ifndef SKIP_PRINT_rpc_ctrl_perf_rated_tdp_set_control_v1A_1F
5201 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_perf_rated_tdp_set_control_v1A_1F[] = {
5202 {
5203 .vtype = vtype_NvHandle,
5204 .offset = NV_OFFSETOF(rpc_ctrl_perf_rated_tdp_set_control_v1A_1F, hClient),
5205 #if (defined(DEBUG) || defined(DEVELOP))
5206 .name = "hClient"
5207 #endif
5208 },
5209 {
5210 .vtype = vtype_NvHandle,
5211 .offset = NV_OFFSETOF(rpc_ctrl_perf_rated_tdp_set_control_v1A_1F, hObject),
5212 #if (defined(DEBUG) || defined(DEVELOP))
5213 .name = "hObject"
5214 #endif
5215 },
5216 {
5217 .vtype = vtype_NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS_v1A_1F,
5218 .offset = NV_OFFSETOF(rpc_ctrl_perf_rated_tdp_set_control_v1A_1F, params),
5219 #if (defined(DEBUG) || defined(DEVELOP))
5220 .name = "params"
5221 #endif
5222 },
5223 {
5224 .vtype = vt_end
5225 }
5226 };
5227
5228 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_perf_rated_tdp_set_control_v1A_1F = {
5229 #if (defined(DEBUG) || defined(DEVELOP))
5230 .name = "rpc_ctrl_perf_rated_tdp_set_control",
5231 #endif
5232 .header_length = sizeof(rpc_ctrl_perf_rated_tdp_set_control_v1A_1F),
5233 .fdesc = vmiopd_fdesc_t_rpc_ctrl_perf_rated_tdp_set_control_v1A_1F
5234 };
5235 #endif
5236
5237 #ifndef SKIP_PRINT_rpc_ctrl_timer_set_gr_tick_freq_v1A_1F
5238 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_timer_set_gr_tick_freq_v1A_1F[] = {
5239 {
5240 .vtype = vtype_NvHandle,
5241 .offset = NV_OFFSETOF(rpc_ctrl_timer_set_gr_tick_freq_v1A_1F, hClient),
5242 #if (defined(DEBUG) || defined(DEVELOP))
5243 .name = "hClient"
5244 #endif
5245 },
5246 {
5247 .vtype = vtype_NvHandle,
5248 .offset = NV_OFFSETOF(rpc_ctrl_timer_set_gr_tick_freq_v1A_1F, hObject),
5249 #if (defined(DEBUG) || defined(DEVELOP))
5250 .name = "hObject"
5251 #endif
5252 },
5253 {
5254 .vtype = vtype_NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS_v1A_1F,
5255 .offset = NV_OFFSETOF(rpc_ctrl_timer_set_gr_tick_freq_v1A_1F, params),
5256 #if (defined(DEBUG) || defined(DEVELOP))
5257 .name = "params"
5258 #endif
5259 },
5260 {
5261 .vtype = vt_end
5262 }
5263 };
5264
5265 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_timer_set_gr_tick_freq_v1A_1F = {
5266 #if (defined(DEBUG) || defined(DEVELOP))
5267 .name = "rpc_ctrl_timer_set_gr_tick_freq",
5268 #endif
5269 .header_length = sizeof(rpc_ctrl_timer_set_gr_tick_freq_v1A_1F),
5270 .fdesc = vmiopd_fdesc_t_rpc_ctrl_timer_set_gr_tick_freq_v1A_1F
5271 };
5272 #endif
5273
5274 #ifndef SKIP_PRINT_rpc_ctrl_free_pma_stream_v1A_1F
5275 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_free_pma_stream_v1A_1F[] = {
5276 {
5277 .vtype = vtype_NvHandle,
5278 .offset = NV_OFFSETOF(rpc_ctrl_free_pma_stream_v1A_1F, hClient),
5279 #if (defined(DEBUG) || defined(DEVELOP))
5280 .name = "hClient"
5281 #endif
5282 },
5283 {
5284 .vtype = vtype_NvHandle,
5285 .offset = NV_OFFSETOF(rpc_ctrl_free_pma_stream_v1A_1F, hObject),
5286 #if (defined(DEBUG) || defined(DEVELOP))
5287 .name = "hObject"
5288 #endif
5289 },
5290 {
5291 .vtype = vtype_NVB0CC_CTRL_FREE_PMA_STREAM_PARAMS_v1A_1F,
5292 .offset = NV_OFFSETOF(rpc_ctrl_free_pma_stream_v1A_1F, params),
5293 #if (defined(DEBUG) || defined(DEVELOP))
5294 .name = "params"
5295 #endif
5296 },
5297 {
5298 .vtype = vt_end
5299 }
5300 };
5301
5302 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_free_pma_stream_v1A_1F = {
5303 #if (defined(DEBUG) || defined(DEVELOP))
5304 .name = "rpc_ctrl_free_pma_stream",
5305 #endif
5306 .header_length = sizeof(rpc_ctrl_free_pma_stream_v1A_1F),
5307 .fdesc = vmiopd_fdesc_t_rpc_ctrl_free_pma_stream_v1A_1F
5308 };
5309 #endif
5310
5311 #ifndef SKIP_PRINT_rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23
5312 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23[] = {
5313 {
5314 .vtype = vtype_NvHandle,
5315 .offset = NV_OFFSETOF(rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23, hClient),
5316 #if (defined(DEBUG) || defined(DEVELOP))
5317 .name = "hClient"
5318 #endif
5319 },
5320 {
5321 .vtype = vtype_NvHandle,
5322 .offset = NV_OFFSETOF(rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23, hObject),
5323 #if (defined(DEBUG) || defined(DEVELOP))
5324 .name = "hObject"
5325 #endif
5326 },
5327 {
5328 .vtype = vtype_NV2080_CTRL_FIFO_SETUP_VF_ZOMBIE_SUBCTX_PDB_PARAMS_v1A_23,
5329 .offset = NV_OFFSETOF(rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23, params),
5330 #if (defined(DEBUG) || defined(DEVELOP))
5331 .name = "params"
5332 #endif
5333 },
5334 {
5335 .vtype = vt_end
5336 }
5337 };
5338
5339 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23 = {
5340 #if (defined(DEBUG) || defined(DEVELOP))
5341 .name = "rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb",
5342 #endif
5343 .header_length = sizeof(rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23),
5344 .fdesc = vmiopd_fdesc_t_rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23
5345 };
5346 #endif
5347
5348 #ifndef SKIP_PRINT_rpc_ctrl_dbg_set_single_sm_single_step_v1C_02
5349 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dbg_set_single_sm_single_step_v1C_02[] = {
5350 {
5351 .vtype = vtype_NvHandle,
5352 .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_single_sm_single_step_v1C_02, hClient),
5353 #if (defined(DEBUG) || defined(DEVELOP))
5354 .name = "hClient"
5355 #endif
5356 },
5357 {
5358 .vtype = vtype_NvHandle,
5359 .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_single_sm_single_step_v1C_02, hObject),
5360 #if (defined(DEBUG) || defined(DEVELOP))
5361 .name = "hObject"
5362 #endif
5363 },
5364 {
5365 .vtype = vtype_NV83DE_CTRL_DEBUG_SET_SINGLE_SM_SINGLE_STEP_PARAMS_v1C_02,
5366 .offset = NV_OFFSETOF(rpc_ctrl_dbg_set_single_sm_single_step_v1C_02, params),
5367 #if (defined(DEBUG) || defined(DEVELOP))
5368 .name = "params"
5369 #endif
5370 },
5371 {
5372 .vtype = vt_end
5373 }
5374 };
5375
5376 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dbg_set_single_sm_single_step_v1C_02 = {
5377 #if (defined(DEBUG) || defined(DEVELOP))
5378 .name = "rpc_ctrl_dbg_set_single_sm_single_step",
5379 #endif
5380 .header_length = sizeof(rpc_ctrl_dbg_set_single_sm_single_step_v1C_02),
5381 .fdesc = vmiopd_fdesc_t_rpc_ctrl_dbg_set_single_sm_single_step_v1C_02
5382 };
5383 #endif
5384
5385 #ifndef SKIP_PRINT_rpc_ctrl_gr_get_tpc_partition_mode_v1C_04
5386 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gr_get_tpc_partition_mode_v1C_04[] = {
5387 {
5388 .vtype = vtype_NvHandle,
5389 .offset = NV_OFFSETOF(rpc_ctrl_gr_get_tpc_partition_mode_v1C_04, hClient),
5390 #if (defined(DEBUG) || defined(DEVELOP))
5391 .name = "hClient"
5392 #endif
5393 },
5394 {
5395 .vtype = vtype_NvHandle,
5396 .offset = NV_OFFSETOF(rpc_ctrl_gr_get_tpc_partition_mode_v1C_04, hObject),
5397 #if (defined(DEBUG) || defined(DEVELOP))
5398 .name = "hObject"
5399 #endif
5400 },
5401 {
5402 .vtype = vtype_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04,
5403 .offset = NV_OFFSETOF(rpc_ctrl_gr_get_tpc_partition_mode_v1C_04, params),
5404 #if (defined(DEBUG) || defined(DEVELOP))
5405 .name = "params"
5406 #endif
5407 },
5408 {
5409 .vtype = vt_end
5410 }
5411 };
5412
5413 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gr_get_tpc_partition_mode_v1C_04 = {
5414 #if (defined(DEBUG) || defined(DEVELOP))
5415 .name = "rpc_ctrl_gr_get_tpc_partition_mode",
5416 #endif
5417 .header_length = sizeof(rpc_ctrl_gr_get_tpc_partition_mode_v1C_04),
5418 .fdesc = vmiopd_fdesc_t_rpc_ctrl_gr_get_tpc_partition_mode_v1C_04
5419 };
5420 #endif
5421
5422 #ifndef SKIP_PRINT_rpc_ctrl_gr_set_tpc_partition_mode_v1C_04
5423 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gr_set_tpc_partition_mode_v1C_04[] = {
5424 {
5425 .vtype = vtype_NvHandle,
5426 .offset = NV_OFFSETOF(rpc_ctrl_gr_set_tpc_partition_mode_v1C_04, hClient),
5427 #if (defined(DEBUG) || defined(DEVELOP))
5428 .name = "hClient"
5429 #endif
5430 },
5431 {
5432 .vtype = vtype_NvHandle,
5433 .offset = NV_OFFSETOF(rpc_ctrl_gr_set_tpc_partition_mode_v1C_04, hObject),
5434 #if (defined(DEBUG) || defined(DEVELOP))
5435 .name = "hObject"
5436 #endif
5437 },
5438 {
5439 .vtype = vtype_NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS_v1C_04,
5440 .offset = NV_OFFSETOF(rpc_ctrl_gr_set_tpc_partition_mode_v1C_04, params),
5441 #if (defined(DEBUG) || defined(DEVELOP))
5442 .name = "params"
5443 #endif
5444 },
5445 {
5446 .vtype = vt_end
5447 }
5448 };
5449
5450 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gr_set_tpc_partition_mode_v1C_04 = {
5451 #if (defined(DEBUG) || defined(DEVELOP))
5452 .name = "rpc_ctrl_gr_set_tpc_partition_mode",
5453 #endif
5454 .header_length = sizeof(rpc_ctrl_gr_set_tpc_partition_mode_v1C_04),
5455 .fdesc = vmiopd_fdesc_t_rpc_ctrl_gr_set_tpc_partition_mode_v1C_04
5456 };
5457 #endif
5458
5459 #ifndef SKIP_PRINT_rpc_ctrl_internal_promote_fault_method_buffers_v1E_07
5460 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_internal_promote_fault_method_buffers_v1E_07[] = {
5461 {
5462 .vtype = vtype_NvHandle,
5463 .offset = NV_OFFSETOF(rpc_ctrl_internal_promote_fault_method_buffers_v1E_07, hClient),
5464 #if (defined(DEBUG) || defined(DEVELOP))
5465 .name = "hClient"
5466 #endif
5467 },
5468 {
5469 .vtype = vtype_NvHandle,
5470 .offset = NV_OFFSETOF(rpc_ctrl_internal_promote_fault_method_buffers_v1E_07, hObject),
5471 #if (defined(DEBUG) || defined(DEVELOP))
5472 .name = "hObject"
5473 #endif
5474 },
5475 {
5476 .vtype = vtype_NVA06C_CTRL_INTERNAL_PROMOTE_FAULT_METHOD_BUFFERS_PARAMS_v1E_07,
5477 .offset = NV_OFFSETOF(rpc_ctrl_internal_promote_fault_method_buffers_v1E_07, params),
5478 #if (defined(DEBUG) || defined(DEVELOP))
5479 .name = "params"
5480 #endif
5481 },
5482 {
5483 .vtype = vt_end
5484 }
5485 };
5486
5487 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_internal_promote_fault_method_buffers_v1E_07 = {
5488 #if (defined(DEBUG) || defined(DEVELOP))
5489 .name = "rpc_ctrl_internal_promote_fault_method_buffers",
5490 #endif
5491 .header_length = sizeof(rpc_ctrl_internal_promote_fault_method_buffers_v1E_07),
5492 .fdesc = vmiopd_fdesc_t_rpc_ctrl_internal_promote_fault_method_buffers_v1E_07
5493 };
5494 #endif
5495
5496 #ifndef SKIP_PRINT_rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05
5497 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05[] = {
5498 {
5499 .vtype = vtype_NvHandle,
5500 .offset = NV_OFFSETOF(rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05, hClient),
5501 #if (defined(DEBUG) || defined(DEVELOP))
5502 .name = "hClient"
5503 #endif
5504 },
5505 {
5506 .vtype = vtype_NvHandle,
5507 .offset = NV_OFFSETOF(rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05, hObject),
5508 #if (defined(DEBUG) || defined(DEVELOP))
5509 .name = "hObject"
5510 #endif
5511 },
5512 {
5513 .vtype = vtype_NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_v1F_05,
5514 .offset = NV_OFFSETOF(rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05, params),
5515 #if (defined(DEBUG) || defined(DEVELOP))
5516 .name = "params"
5517 #endif
5518 },
5519 {
5520 .vtype = vt_end
5521 }
5522 };
5523
5524 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05 = {
5525 #if (defined(DEBUG) || defined(DEVELOP))
5526 .name = "rpc_ctrl_internal_memsys_set_zbc_referenced",
5527 #endif
5528 .header_length = sizeof(rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05),
5529 .fdesc = vmiopd_fdesc_t_rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05
5530 };
5531 #endif
5532
5533 #ifndef SKIP_PRINT_rpc_ctrl_fabric_memory_describe_v1E_0C
5534 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_fabric_memory_describe_v1E_0C[] = {
5535 {
5536 .vtype = vtype_NvHandle,
5537 .offset = NV_OFFSETOF(rpc_ctrl_fabric_memory_describe_v1E_0C, hClient),
5538 #if (defined(DEBUG) || defined(DEVELOP))
5539 .name = "hClient"
5540 #endif
5541 },
5542 {
5543 .vtype = vtype_NvHandle,
5544 .offset = NV_OFFSETOF(rpc_ctrl_fabric_memory_describe_v1E_0C, hObject),
5545 #if (defined(DEBUG) || defined(DEVELOP))
5546 .name = "hObject"
5547 #endif
5548 },
5549 {
5550 .vtype = vtype_NV00F8_CTRL_DESCRIBE_PARAMS_v1E_0C,
5551 .offset = NV_OFFSETOF(rpc_ctrl_fabric_memory_describe_v1E_0C, params),
5552 #if (defined(DEBUG) || defined(DEVELOP))
5553 .name = "params"
5554 #endif
5555 },
5556 {
5557 .vtype = vt_end
5558 }
5559 };
5560
5561 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_fabric_memory_describe_v1E_0C = {
5562 #if (defined(DEBUG) || defined(DEVELOP))
5563 .name = "rpc_ctrl_fabric_memory_describe",
5564 #endif
5565 .header_length = sizeof(rpc_ctrl_fabric_memory_describe_v1E_0C),
5566 .fdesc = vmiopd_fdesc_t_rpc_ctrl_fabric_memory_describe_v1E_0C
5567 };
5568 #endif
5569
5570 #ifndef SKIP_PRINT_rpc_ctrl_fabric_mem_stats_v1E_0C
5571 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_fabric_mem_stats_v1E_0C[] = {
5572 {
5573 .vtype = vtype_NvHandle,
5574 .offset = NV_OFFSETOF(rpc_ctrl_fabric_mem_stats_v1E_0C, hClient),
5575 #if (defined(DEBUG) || defined(DEVELOP))
5576 .name = "hClient"
5577 #endif
5578 },
5579 {
5580 .vtype = vtype_NvHandle,
5581 .offset = NV_OFFSETOF(rpc_ctrl_fabric_mem_stats_v1E_0C, hObject),
5582 #if (defined(DEBUG) || defined(DEVELOP))
5583 .name = "hObject"
5584 #endif
5585 },
5586 {
5587 .vtype = vtype_NV2080_CTRL_FLA_GET_FABRIC_MEM_STATS_PARAMS_v1E_0C,
5588 .offset = NV_OFFSETOF(rpc_ctrl_fabric_mem_stats_v1E_0C, params),
5589 #if (defined(DEBUG) || defined(DEVELOP))
5590 .name = "params"
5591 #endif
5592 },
5593 {
5594 .vtype = vt_end
5595 }
5596 };
5597
5598 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_fabric_mem_stats_v1E_0C = {
5599 #if (defined(DEBUG) || defined(DEVELOP))
5600 .name = "rpc_ctrl_fabric_mem_stats",
5601 #endif
5602 .header_length = sizeof(rpc_ctrl_fabric_mem_stats_v1E_0C),
5603 .fdesc = vmiopd_fdesc_t_rpc_ctrl_fabric_mem_stats_v1E_0C
5604 };
5605 #endif
5606
5607 #ifndef SKIP_PRINT_rpc_ctrl_bus_set_p2p_mapping_v21_03
5608 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_bus_set_p2p_mapping_v21_03[] = {
5609 {
5610 .vtype = vtype_NvHandle,
5611 .offset = NV_OFFSETOF(rpc_ctrl_bus_set_p2p_mapping_v21_03, hClient),
5612 #if (defined(DEBUG) || defined(DEVELOP))
5613 .name = "hClient"
5614 #endif
5615 },
5616 {
5617 .vtype = vtype_NvHandle,
5618 .offset = NV_OFFSETOF(rpc_ctrl_bus_set_p2p_mapping_v21_03, hObject),
5619 #if (defined(DEBUG) || defined(DEVELOP))
5620 .name = "hObject"
5621 #endif
5622 },
5623 {
5624 .vtype = vtype_NV2080_CTRL_BUS_SET_P2P_MAPPING_PARAMS_v21_03,
5625 .offset = NV_OFFSETOF(rpc_ctrl_bus_set_p2p_mapping_v21_03, params),
5626 #if (defined(DEBUG) || defined(DEVELOP))
5627 .name = "params"
5628 #endif
5629 },
5630 {
5631 .vtype = vt_end
5632 }
5633 };
5634
5635 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_bus_set_p2p_mapping_v21_03 = {
5636 #if (defined(DEBUG) || defined(DEVELOP))
5637 .name = "rpc_ctrl_bus_set_p2p_mapping",
5638 #endif
5639 .header_length = sizeof(rpc_ctrl_bus_set_p2p_mapping_v21_03),
5640 .fdesc = vmiopd_fdesc_t_rpc_ctrl_bus_set_p2p_mapping_v21_03
5641 };
5642 #endif
5643
5644 #ifndef SKIP_PRINT_rpc_ctrl_bus_unset_p2p_mapping_v21_03
5645 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_bus_unset_p2p_mapping_v21_03[] = {
5646 {
5647 .vtype = vtype_NvHandle,
5648 .offset = NV_OFFSETOF(rpc_ctrl_bus_unset_p2p_mapping_v21_03, hClient),
5649 #if (defined(DEBUG) || defined(DEVELOP))
5650 .name = "hClient"
5651 #endif
5652 },
5653 {
5654 .vtype = vtype_NvHandle,
5655 .offset = NV_OFFSETOF(rpc_ctrl_bus_unset_p2p_mapping_v21_03, hObject),
5656 #if (defined(DEBUG) || defined(DEVELOP))
5657 .name = "hObject"
5658 #endif
5659 },
5660 {
5661 .vtype = vtype_NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS_v21_03,
5662 .offset = NV_OFFSETOF(rpc_ctrl_bus_unset_p2p_mapping_v21_03, params),
5663 #if (defined(DEBUG) || defined(DEVELOP))
5664 .name = "params"
5665 #endif
5666 },
5667 {
5668 .vtype = vt_end
5669 }
5670 };
5671
5672 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_bus_unset_p2p_mapping_v21_03 = {
5673 #if (defined(DEBUG) || defined(DEVELOP))
5674 .name = "rpc_ctrl_bus_unset_p2p_mapping",
5675 #endif
5676 .header_length = sizeof(rpc_ctrl_bus_unset_p2p_mapping_v21_03),
5677 .fdesc = vmiopd_fdesc_t_rpc_ctrl_bus_unset_p2p_mapping_v21_03
5678 };
5679 #endif
5680
5681 #ifndef SKIP_PRINT_rpc_ctrl_gpu_get_info_v2_v25_11
5682 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gpu_get_info_v2_v25_11[] = {
5683 {
5684 .vtype = vtype_NvHandle,
5685 .offset = NV_OFFSETOF(rpc_ctrl_gpu_get_info_v2_v25_11, hClient),
5686 #if (defined(DEBUG) || defined(DEVELOP))
5687 .name = "hClient"
5688 #endif
5689 },
5690 {
5691 .vtype = vtype_NvHandle,
5692 .offset = NV_OFFSETOF(rpc_ctrl_gpu_get_info_v2_v25_11, hObject),
5693 #if (defined(DEBUG) || defined(DEVELOP))
5694 .name = "hObject"
5695 #endif
5696 },
5697 {
5698 .vtype = vtype_NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_v25_11,
5699 .offset = NV_OFFSETOF(rpc_ctrl_gpu_get_info_v2_v25_11, params),
5700 #if (defined(DEBUG) || defined(DEVELOP))
5701 .name = "params"
5702 #endif
5703 },
5704 {
5705 .vtype = vt_end
5706 }
5707 };
5708
5709 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gpu_get_info_v2_v25_11 = {
5710 #if (defined(DEBUG) || defined(DEVELOP))
5711 .name = "rpc_ctrl_gpu_get_info_v2",
5712 #endif
5713 .header_length = sizeof(rpc_ctrl_gpu_get_info_v2_v25_11),
5714 .fdesc = vmiopd_fdesc_t_rpc_ctrl_gpu_get_info_v2_v25_11
5715 };
5716 #endif
5717
5718 #ifndef SKIP_PRINT_rpc_ctrl_internal_quiesce_pma_channel_v1C_08
5719 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_internal_quiesce_pma_channel_v1C_08[] = {
5720 {
5721 .vtype = vtype_NvHandle,
5722 .offset = NV_OFFSETOF(rpc_ctrl_internal_quiesce_pma_channel_v1C_08, hClient),
5723 #if (defined(DEBUG) || defined(DEVELOP))
5724 .name = "hClient"
5725 #endif
5726 },
5727 {
5728 .vtype = vtype_NvHandle,
5729 .offset = NV_OFFSETOF(rpc_ctrl_internal_quiesce_pma_channel_v1C_08, hObject),
5730 #if (defined(DEBUG) || defined(DEVELOP))
5731 .name = "hObject"
5732 #endif
5733 },
5734 {
5735 .vtype = vtype_NVB0CC_CTRL_INTERNAL_QUIESCE_PMA_CHANNEL_PARAMS_v1C_08,
5736 .offset = NV_OFFSETOF(rpc_ctrl_internal_quiesce_pma_channel_v1C_08, params),
5737 #if (defined(DEBUG) || defined(DEVELOP))
5738 .name = "params"
5739 #endif
5740 },
5741 {
5742 .vtype = vt_end
5743 }
5744 };
5745
5746 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_internal_quiesce_pma_channel_v1C_08 = {
5747 #if (defined(DEBUG) || defined(DEVELOP))
5748 .name = "rpc_ctrl_internal_quiesce_pma_channel",
5749 #endif
5750 .header_length = sizeof(rpc_ctrl_internal_quiesce_pma_channel_v1C_08),
5751 .fdesc = vmiopd_fdesc_t_rpc_ctrl_internal_quiesce_pma_channel_v1C_08
5752 };
5753 #endif
5754
5755 #ifndef SKIP_PRINT_rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C
5756 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C[] = {
5757 {
5758 .vtype = vtype_NvHandle,
5759 .offset = NV_OFFSETOF(rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C, hClient),
5760 #if (defined(DEBUG) || defined(DEVELOP))
5761 .name = "hClient"
5762 #endif
5763 },
5764 {
5765 .vtype = vtype_NvHandle,
5766 .offset = NV_OFFSETOF(rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C, hObject),
5767 #if (defined(DEBUG) || defined(DEVELOP))
5768 .name = "hObject"
5769 #endif
5770 },
5771 {
5772 .vtype = vtype_NVB0CC_CTRL_INTERNAL_SRIOV_PROMOTE_PMA_STREAM_PARAMS_v1C_0C,
5773 .offset = NV_OFFSETOF(rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C, params),
5774 #if (defined(DEBUG) || defined(DEVELOP))
5775 .name = "params"
5776 #endif
5777 },
5778 {
5779 .vtype = vt_end
5780 }
5781 };
5782
5783 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C = {
5784 #if (defined(DEBUG) || defined(DEVELOP))
5785 .name = "rpc_ctrl_internal_sriov_promote_pma_stream",
5786 #endif
5787 .header_length = sizeof(rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C),
5788 .fdesc = vmiopd_fdesc_t_rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C
5789 };
5790 #endif
5791
5792 #ifndef SKIP_PRINT_rpc_ctrl_exec_partitions_create_v24_05
5793 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_exec_partitions_create_v24_05[] = {
5794 {
5795 .vtype = vtype_NvHandle,
5796 .offset = NV_OFFSETOF(rpc_ctrl_exec_partitions_create_v24_05, hClient),
5797 #if (defined(DEBUG) || defined(DEVELOP))
5798 .name = "hClient"
5799 #endif
5800 },
5801 {
5802 .vtype = vtype_NvHandle,
5803 .offset = NV_OFFSETOF(rpc_ctrl_exec_partitions_create_v24_05, hObject),
5804 #if (defined(DEBUG) || defined(DEVELOP))
5805 .name = "hObject"
5806 #endif
5807 },
5808 {
5809 .vtype = vtype_NvU32,
5810 .offset = NV_OFFSETOF(rpc_ctrl_exec_partitions_create_v24_05, status),
5811 #if (defined(DEBUG) || defined(DEVELOP))
5812 .name = "status"
5813 #endif
5814 },
5815 {
5816 .vtype = vtype_NVC637_CTRL_EXEC_PARTITIONS_CREATE_PARAMS_v24_05,
5817 .offset = NV_OFFSETOF(rpc_ctrl_exec_partitions_create_v24_05, execPartitionsCreate),
5818 #if (defined(DEBUG) || defined(DEVELOP))
5819 .name = "execPartitionsCreate"
5820 #endif
5821 },
5822 {
5823 .vtype = vt_end
5824 }
5825 };
5826
5827 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_exec_partitions_create_v24_05 = {
5828 #if (defined(DEBUG) || defined(DEVELOP))
5829 .name = "rpc_ctrl_exec_partitions_create",
5830 #endif
5831 .header_length = sizeof(rpc_ctrl_exec_partitions_create_v24_05),
5832 .fdesc = vmiopd_fdesc_t_rpc_ctrl_exec_partitions_create_v24_05
5833 };
5834 #endif
5835
5836 #ifndef SKIP_PRINT_rpc_ctrl_fla_setup_instance_mem_block_v21_05
5837 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_fla_setup_instance_mem_block_v21_05[] = {
5838 {
5839 .vtype = vtype_NvHandle,
5840 .offset = NV_OFFSETOF(rpc_ctrl_fla_setup_instance_mem_block_v21_05, hClient),
5841 #if (defined(DEBUG) || defined(DEVELOP))
5842 .name = "hClient"
5843 #endif
5844 },
5845 {
5846 .vtype = vtype_NvHandle,
5847 .offset = NV_OFFSETOF(rpc_ctrl_fla_setup_instance_mem_block_v21_05, hObject),
5848 #if (defined(DEBUG) || defined(DEVELOP))
5849 .name = "hObject"
5850 #endif
5851 },
5852 {
5853 .vtype = vtype_NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS_v13_04,
5854 .offset = NV_OFFSETOF(rpc_ctrl_fla_setup_instance_mem_block_v21_05, params),
5855 #if (defined(DEBUG) || defined(DEVELOP))
5856 .name = "params"
5857 #endif
5858 },
5859 {
5860 .vtype = vt_end
5861 }
5862 };
5863
5864 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_fla_setup_instance_mem_block_v21_05 = {
5865 #if (defined(DEBUG) || defined(DEVELOP))
5866 .name = "rpc_ctrl_fla_setup_instance_mem_block",
5867 #endif
5868 .header_length = sizeof(rpc_ctrl_fla_setup_instance_mem_block_v21_05),
5869 .fdesc = vmiopd_fdesc_t_rpc_ctrl_fla_setup_instance_mem_block_v21_05
5870 };
5871 #endif
5872
5873 #ifndef SKIP_PRINT_rpc_ctrl_get_total_hs_credits_v21_08
5874 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_get_total_hs_credits_v21_08[] = {
5875 {
5876 .vtype = vtype_NvHandle,
5877 .offset = NV_OFFSETOF(rpc_ctrl_get_total_hs_credits_v21_08, hClient),
5878 #if (defined(DEBUG) || defined(DEVELOP))
5879 .name = "hClient"
5880 #endif
5881 },
5882 {
5883 .vtype = vtype_NvHandle,
5884 .offset = NV_OFFSETOF(rpc_ctrl_get_total_hs_credits_v21_08, hObject),
5885 #if (defined(DEBUG) || defined(DEVELOP))
5886 .name = "hObject"
5887 #endif
5888 },
5889 {
5890 .vtype = vtype_NVB0CC_CTRL_GET_TOTAL_HS_CREDITS_PARAMS_v21_08,
5891 .offset = NV_OFFSETOF(rpc_ctrl_get_total_hs_credits_v21_08, params),
5892 #if (defined(DEBUG) || defined(DEVELOP))
5893 .name = "params"
5894 #endif
5895 },
5896 {
5897 .vtype = vt_end
5898 }
5899 };
5900
5901 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_get_total_hs_credits_v21_08 = {
5902 #if (defined(DEBUG) || defined(DEVELOP))
5903 .name = "rpc_ctrl_get_total_hs_credits",
5904 #endif
5905 .header_length = sizeof(rpc_ctrl_get_total_hs_credits_v21_08),
5906 .fdesc = vmiopd_fdesc_t_rpc_ctrl_get_total_hs_credits_v21_08
5907 };
5908 #endif
5909
5910 #ifndef SKIP_PRINT_rpc_ctrl_get_hs_credits_v21_08
5911 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_get_hs_credits_v21_08[] = {
5912 {
5913 .vtype = vtype_NvHandle,
5914 .offset = NV_OFFSETOF(rpc_ctrl_get_hs_credits_v21_08, hClient),
5915 #if (defined(DEBUG) || defined(DEVELOP))
5916 .name = "hClient"
5917 #endif
5918 },
5919 {
5920 .vtype = vtype_NvHandle,
5921 .offset = NV_OFFSETOF(rpc_ctrl_get_hs_credits_v21_08, hObject),
5922 #if (defined(DEBUG) || defined(DEVELOP))
5923 .name = "hObject"
5924 #endif
5925 },
5926 {
5927 .vtype = vtype_NVB0CC_CTRL_GET_HS_CREDITS_PARAMS_v21_08,
5928 .offset = NV_OFFSETOF(rpc_ctrl_get_hs_credits_v21_08, params),
5929 #if (defined(DEBUG) || defined(DEVELOP))
5930 .name = "params"
5931 #endif
5932 },
5933 {
5934 .vtype = vt_end
5935 }
5936 };
5937
5938 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_get_hs_credits_v21_08 = {
5939 #if (defined(DEBUG) || defined(DEVELOP))
5940 .name = "rpc_ctrl_get_hs_credits",
5941 #endif
5942 .header_length = sizeof(rpc_ctrl_get_hs_credits_v21_08),
5943 .fdesc = vmiopd_fdesc_t_rpc_ctrl_get_hs_credits_v21_08
5944 };
5945 #endif
5946
5947 #ifndef SKIP_PRINT_rpc_ctrl_set_hs_credits_v21_08
5948 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_set_hs_credits_v21_08[] = {
5949 {
5950 .vtype = vtype_NvHandle,
5951 .offset = NV_OFFSETOF(rpc_ctrl_set_hs_credits_v21_08, hClient),
5952 #if (defined(DEBUG) || defined(DEVELOP))
5953 .name = "hClient"
5954 #endif
5955 },
5956 {
5957 .vtype = vtype_NvHandle,
5958 .offset = NV_OFFSETOF(rpc_ctrl_set_hs_credits_v21_08, hObject),
5959 #if (defined(DEBUG) || defined(DEVELOP))
5960 .name = "hObject"
5961 #endif
5962 },
5963 {
5964 .vtype = vtype_NVB0CC_CTRL_SET_HS_CREDITS_PARAMS_v21_08,
5965 .offset = NV_OFFSETOF(rpc_ctrl_set_hs_credits_v21_08, params),
5966 #if (defined(DEBUG) || defined(DEVELOP))
5967 .name = "params"
5968 #endif
5969 },
5970 {
5971 .vtype = vt_end
5972 }
5973 };
5974
5975 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_set_hs_credits_v21_08 = {
5976 #if (defined(DEBUG) || defined(DEVELOP))
5977 .name = "rpc_ctrl_set_hs_credits",
5978 #endif
5979 .header_length = sizeof(rpc_ctrl_set_hs_credits_v21_08),
5980 .fdesc = vmiopd_fdesc_t_rpc_ctrl_set_hs_credits_v21_08
5981 };
5982 #endif
5983
5984 #ifndef SKIP_PRINT_rpc_ctrl_pm_area_pc_sampler_v21_0B
5985 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_pm_area_pc_sampler_v21_0B[] = {
5986 {
5987 .vtype = vtype_NvHandle,
5988 .offset = NV_OFFSETOF(rpc_ctrl_pm_area_pc_sampler_v21_0B, hClient),
5989 #if (defined(DEBUG) || defined(DEVELOP))
5990 .name = "hClient"
5991 #endif
5992 },
5993 {
5994 .vtype = vtype_NvHandle,
5995 .offset = NV_OFFSETOF(rpc_ctrl_pm_area_pc_sampler_v21_0B, hObject),
5996 #if (defined(DEBUG) || defined(DEVELOP))
5997 .name = "hObject"
5998 #endif
5999 },
6000 {
6001 .vtype = vtype_NvU32,
6002 .offset = NV_OFFSETOF(rpc_ctrl_pm_area_pc_sampler_v21_0B, cmd),
6003 #if (defined(DEBUG) || defined(DEVELOP))
6004 .name = "cmd"
6005 #endif
6006 },
6007 {
6008 .vtype = vt_end
6009 }
6010 };
6011
6012 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_pm_area_pc_sampler_v21_0B = {
6013 #if (defined(DEBUG) || defined(DEVELOP))
6014 .name = "rpc_ctrl_pm_area_pc_sampler",
6015 #endif
6016 .header_length = sizeof(rpc_ctrl_pm_area_pc_sampler_v21_0B),
6017 .fdesc = vmiopd_fdesc_t_rpc_ctrl_pm_area_pc_sampler_v21_0B
6018 };
6019 #endif
6020
6021 #ifndef SKIP_PRINT_rpc_ctrl_exec_partitions_delete_v1F_0A
6022 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_exec_partitions_delete_v1F_0A[] = {
6023 {
6024 .vtype = vtype_NvHandle,
6025 .offset = NV_OFFSETOF(rpc_ctrl_exec_partitions_delete_v1F_0A, hClient),
6026 #if (defined(DEBUG) || defined(DEVELOP))
6027 .name = "hClient"
6028 #endif
6029 },
6030 {
6031 .vtype = vtype_NvHandle,
6032 .offset = NV_OFFSETOF(rpc_ctrl_exec_partitions_delete_v1F_0A, hObject),
6033 #if (defined(DEBUG) || defined(DEVELOP))
6034 .name = "hObject"
6035 #endif
6036 },
6037 {
6038 .vtype = vtype_NVC637_CTRL_EXEC_PARTITIONS_DELETE_PARAMS_v18_05,
6039 .offset = NV_OFFSETOF(rpc_ctrl_exec_partitions_delete_v1F_0A, execPartitionsDelete),
6040 #if (defined(DEBUG) || defined(DEVELOP))
6041 .name = "execPartitionsDelete"
6042 #endif
6043 },
6044 {
6045 .vtype = vt_end
6046 }
6047 };
6048
6049 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_exec_partitions_delete_v1F_0A = {
6050 #if (defined(DEBUG) || defined(DEVELOP))
6051 .name = "rpc_ctrl_exec_partitions_delete",
6052 #endif
6053 .header_length = sizeof(rpc_ctrl_exec_partitions_delete_v1F_0A),
6054 .fdesc = vmiopd_fdesc_t_rpc_ctrl_exec_partitions_delete_v1F_0A
6055 };
6056 #endif
6057
6058 #ifndef SKIP_PRINT_rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A
6059 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A[] = {
6060 {
6061 .vtype = vtype_NvHandle,
6062 .offset = NV_OFFSETOF(rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A, hClient),
6063 #if (defined(DEBUG) || defined(DEVELOP))
6064 .name = "hClient"
6065 #endif
6066 },
6067 {
6068 .vtype = vtype_NvHandle,
6069 .offset = NV_OFFSETOF(rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A, hObject),
6070 #if (defined(DEBUG) || defined(DEVELOP))
6071 .name = "hObject"
6072 #endif
6073 },
6074 {
6075 .vtype = vtype_NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS_v08_00,
6076 .offset = NV_OFFSETOF(rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A, workSubmitToken),
6077 #if (defined(DEBUG) || defined(DEVELOP))
6078 .name = "workSubmitToken"
6079 #endif
6080 },
6081 {
6082 .vtype = vt_end
6083 }
6084 };
6085
6086 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A = {
6087 #if (defined(DEBUG) || defined(DEVELOP))
6088 .name = "rpc_ctrl_gpfifo_get_work_submit_token",
6089 #endif
6090 .header_length = sizeof(rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A),
6091 .fdesc = vmiopd_fdesc_t_rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A
6092 };
6093 #endif
6094
6095 #ifndef SKIP_PRINT_rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A
6096 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A[] = {
6097 {
6098 .vtype = vtype_NvHandle,
6099 .offset = NV_OFFSETOF(rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A, hClient),
6100 #if (defined(DEBUG) || defined(DEVELOP))
6101 .name = "hClient"
6102 #endif
6103 },
6104 {
6105 .vtype = vtype_NvHandle,
6106 .offset = NV_OFFSETOF(rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A, hObject),
6107 #if (defined(DEBUG) || defined(DEVELOP))
6108 .name = "hObject"
6109 #endif
6110 },
6111 {
6112 .vtype = vtype_NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS_v16_04,
6113 .offset = NV_OFFSETOF(rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A, setWorkSubmitTokenIndex),
6114 #if (defined(DEBUG) || defined(DEVELOP))
6115 .name = "setWorkSubmitTokenIndex"
6116 #endif
6117 },
6118 {
6119 .vtype = vt_end
6120 }
6121 };
6122
6123 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A = {
6124 #if (defined(DEBUG) || defined(DEVELOP))
6125 .name = "rpc_ctrl_gpfifo_set_work_submit_token_notif_index",
6126 #endif
6127 .header_length = sizeof(rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A),
6128 .fdesc = vmiopd_fdesc_t_rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A
6129 };
6130 #endif
6131
6132 #ifndef SKIP_PRINT_rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D
6133 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D[] = {
6134 {
6135 .vtype = vtype_NvHandle,
6136 .offset = NV_OFFSETOF(rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D, hClient),
6137 #if (defined(DEBUG) || defined(DEVELOP))
6138 .name = "hClient"
6139 #endif
6140 },
6141 {
6142 .vtype = vtype_NvHandle,
6143 .offset = NV_OFFSETOF(rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D, hObject),
6144 #if (defined(DEBUG) || defined(DEVELOP))
6145 .name = "hObject"
6146 #endif
6147 },
6148 {
6149 .vtype = vtype_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B,
6150 .offset = NV_OFFSETOF(rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D, vfErrContIntrMask),
6151 #if (defined(DEBUG) || defined(DEVELOP))
6152 .name = "vfErrContIntrMask"
6153 #endif
6154 },
6155 {
6156 .vtype = vt_end
6157 }
6158 };
6159
6160 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D = {
6161 #if (defined(DEBUG) || defined(DEVELOP))
6162 .name = "rpc_ctrl_master_get_virtual_function_error_cont_intr_mask",
6163 #endif
6164 .header_length = sizeof(rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D),
6165 .fdesc = vmiopd_fdesc_t_rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D
6166 };
6167 #endif
6168
6169 #ifndef SKIP_PRINT_rpc_save_hibernation_data_v1E_0E
6170 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_save_hibernation_data_v1E_0E[] = {
6171 {
6172 .vtype = vtype_NvU32,
6173 .offset = NV_OFFSETOF(rpc_save_hibernation_data_v1E_0E, remainedBytes),
6174 #if (defined(DEBUG) || defined(DEVELOP))
6175 .name = "remainedBytes"
6176 #endif
6177 },
6178 {
6179 .vtype = vtype_NvU8_array,
6180 .offset = NV_OFFSETOF(rpc_save_hibernation_data_v1E_0E, payload),
6181 .array_length = 0,
6182 #if (defined(DEBUG) || defined(DEVELOP))
6183 .name = "payload"
6184 #endif
6185 },
6186 {
6187 .vtype = vt_end
6188 }
6189 };
6190
6191 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_save_hibernation_data_v1E_0E = {
6192 #if (defined(DEBUG) || defined(DEVELOP))
6193 .name = "rpc_save_hibernation_data",
6194 #endif
6195 .header_length = sizeof(rpc_save_hibernation_data_v1E_0E),
6196 .fdesc = vmiopd_fdesc_t_rpc_save_hibernation_data_v1E_0E
6197 };
6198 #endif
6199
6200 #ifndef SKIP_PRINT_rpc_restore_hibernation_data_v1E_0E
6201 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_restore_hibernation_data_v1E_0E[] = {
6202 {
6203 .vtype = vtype_NvU32,
6204 .offset = NV_OFFSETOF(rpc_restore_hibernation_data_v1E_0E, remainedBytes),
6205 #if (defined(DEBUG) || defined(DEVELOP))
6206 .name = "remainedBytes"
6207 #endif
6208 },
6209 {
6210 .vtype = vtype_NvU8_array,
6211 .offset = NV_OFFSETOF(rpc_restore_hibernation_data_v1E_0E, payload),
6212 .array_length = 0,
6213 #if (defined(DEBUG) || defined(DEVELOP))
6214 .name = "payload"
6215 #endif
6216 },
6217 {
6218 .vtype = vt_end
6219 }
6220 };
6221
6222 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_restore_hibernation_data_v1E_0E = {
6223 #if (defined(DEBUG) || defined(DEVELOP))
6224 .name = "rpc_restore_hibernation_data",
6225 #endif
6226 .header_length = sizeof(rpc_restore_hibernation_data_v1E_0E),
6227 .fdesc = vmiopd_fdesc_t_rpc_restore_hibernation_data_v1E_0E
6228 };
6229 #endif
6230
6231 #ifndef SKIP_PRINT_rpc_ctrl_get_mmu_debug_mode_v1E_06
6232 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_get_mmu_debug_mode_v1E_06[] = {
6233 {
6234 .vtype = vtype_NvHandle,
6235 .offset = NV_OFFSETOF(rpc_ctrl_get_mmu_debug_mode_v1E_06, hClient),
6236 #if (defined(DEBUG) || defined(DEVELOP))
6237 .name = "hClient"
6238 #endif
6239 },
6240 {
6241 .vtype = vtype_NvHandle,
6242 .offset = NV_OFFSETOF(rpc_ctrl_get_mmu_debug_mode_v1E_06, hObject),
6243 #if (defined(DEBUG) || defined(DEVELOP))
6244 .name = "hObject"
6245 #endif
6246 },
6247 {
6248 .vtype = vtype_NV0090_CTRL_GET_MMU_DEBUG_MODE_PARAMS_v1E_06,
6249 .offset = NV_OFFSETOF(rpc_ctrl_get_mmu_debug_mode_v1E_06, params),
6250 #if (defined(DEBUG) || defined(DEVELOP))
6251 .name = "params"
6252 #endif
6253 },
6254 {
6255 .vtype = vt_end
6256 }
6257 };
6258
6259 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_get_mmu_debug_mode_v1E_06 = {
6260 #if (defined(DEBUG) || defined(DEVELOP))
6261 .name = "rpc_ctrl_get_mmu_debug_mode",
6262 #endif
6263 .header_length = sizeof(rpc_ctrl_get_mmu_debug_mode_v1E_06),
6264 .fdesc = vmiopd_fdesc_t_rpc_ctrl_get_mmu_debug_mode_v1E_06
6265 };
6266 #endif
6267
6268 #ifndef SKIP_PRINT_rpc_disable_channels_v1E_0B
6269 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_disable_channels_v1E_0B[] = {
6270 {
6271 .vtype = vtype_NvU32,
6272 .offset = NV_OFFSETOF(rpc_disable_channels_v1E_0B, bDisable),
6273 #if (defined(DEBUG) || defined(DEVELOP))
6274 .name = "bDisable"
6275 #endif
6276 },
6277 {
6278 .vtype = vt_end
6279 }
6280 };
6281
6282 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_disable_channels_v1E_0B = {
6283 #if (defined(DEBUG) || defined(DEVELOP))
6284 .name = "rpc_disable_channels",
6285 #endif
6286 .header_length = sizeof(rpc_disable_channels_v1E_0B),
6287 .fdesc = vmiopd_fdesc_t_rpc_disable_channels_v1E_0B
6288 };
6289 #endif
6290
6291 #ifndef SKIP_PRINT_rpc_ctrl_gpu_migratable_ops_v21_07
6292 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gpu_migratable_ops_v21_07[] = {
6293 {
6294 .vtype = vtype_NvHandle,
6295 .offset = NV_OFFSETOF(rpc_ctrl_gpu_migratable_ops_v21_07, hClient),
6296 #if (defined(DEBUG) || defined(DEVELOP))
6297 .name = "hClient"
6298 #endif
6299 },
6300 {
6301 .vtype = vtype_NvHandle,
6302 .offset = NV_OFFSETOF(rpc_ctrl_gpu_migratable_ops_v21_07, hObject),
6303 #if (defined(DEBUG) || defined(DEVELOP))
6304 .name = "hObject"
6305 #endif
6306 },
6307 {
6308 .vtype = vtype_NV2080_CTRL_GPU_MIGRATABLE_OPS_PARAMS_v21_07,
6309 .offset = NV_OFFSETOF(rpc_ctrl_gpu_migratable_ops_v21_07, ctrlParams),
6310 #if (defined(DEBUG) || defined(DEVELOP))
6311 .name = "ctrlParams"
6312 #endif
6313 },
6314 {
6315 .vtype = vt_end
6316 }
6317 };
6318
6319 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gpu_migratable_ops_v21_07 = {
6320 #if (defined(DEBUG) || defined(DEVELOP))
6321 .name = "rpc_ctrl_gpu_migratable_ops",
6322 #endif
6323 .header_length = sizeof(rpc_ctrl_gpu_migratable_ops_v21_07),
6324 .fdesc = vmiopd_fdesc_t_rpc_ctrl_gpu_migratable_ops_v21_07
6325 };
6326 #endif
6327
6328 #ifndef SKIP_PRINT_rpc_invalidate_tlb_v23_03
6329 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_invalidate_tlb_v23_03[] = {
6330 {
6331 .vtype = vtype_NvU64,
6332 .offset = NV_OFFSETOF(rpc_invalidate_tlb_v23_03, pdbAddress),
6333 #if (defined(DEBUG) || defined(DEVELOP))
6334 .name = "pdbAddress"
6335 #endif
6336 },
6337 {
6338 .vtype = vtype_NvU32,
6339 .offset = NV_OFFSETOF(rpc_invalidate_tlb_v23_03, regVal),
6340 #if (defined(DEBUG) || defined(DEVELOP))
6341 .name = "regVal"
6342 #endif
6343 },
6344 {
6345 .vtype = vt_end
6346 }
6347 };
6348
6349 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_invalidate_tlb_v23_03 = {
6350 #if (defined(DEBUG) || defined(DEVELOP))
6351 .name = "rpc_invalidate_tlb",
6352 #endif
6353 .header_length = sizeof(rpc_invalidate_tlb_v23_03),
6354 .fdesc = vmiopd_fdesc_t_rpc_invalidate_tlb_v23_03
6355 };
6356 #endif
6357
6358 #ifndef SKIP_PRINT_rpc_ecc_notifier_write_ack_v23_05
6359 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ecc_notifier_write_ack_v23_05[] = {
6360 {
6361 .vtype = vt_end
6362 }
6363 };
6364
6365 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ecc_notifier_write_ack_v23_05 = {
6366 #if (defined(DEBUG) || defined(DEVELOP))
6367 .name = "rpc_ecc_notifier_write_ack",
6368 #endif
6369 .fdesc = vmiopd_fdesc_t_rpc_ecc_notifier_write_ack_v23_05
6370 };
6371 #endif
6372
6373 #ifndef SKIP_PRINT_rpc_get_brand_caps_v25_12
6374 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_get_brand_caps_v25_12[] = {
6375 {
6376 .vtype = vtype_NvU32,
6377 .offset = NV_OFFSETOF(rpc_get_brand_caps_v25_12, brands),
6378 #if (defined(DEBUG) || defined(DEVELOP))
6379 .name = "brands"
6380 #endif
6381 },
6382 {
6383 .vtype = vt_end
6384 }
6385 };
6386
6387 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_get_brand_caps_v25_12 = {
6388 #if (defined(DEBUG) || defined(DEVELOP))
6389 .name = "rpc_get_brand_caps",
6390 #endif
6391 .header_length = sizeof(rpc_get_brand_caps_v25_12),
6392 .fdesc = vmiopd_fdesc_t_rpc_get_brand_caps_v25_12
6393 };
6394 #endif
6395
6396 #ifndef SKIP_PRINT_rpc_gsp_set_system_info_v17_00
6397 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_set_system_info_v17_00[] = {
6398 {
6399 .vtype = vtype_NvU32,
6400 .offset = NV_OFFSETOF(rpc_gsp_set_system_info_v17_00, data),
6401 #if (defined(DEBUG) || defined(DEVELOP))
6402 .name = "data"
6403 #endif
6404 },
6405 {
6406 .vtype = vt_end
6407 }
6408 };
6409
6410 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_set_system_info_v17_00 = {
6411 #if (defined(DEBUG) || defined(DEVELOP))
6412 .name = "rpc_gsp_set_system_info",
6413 #endif
6414 .header_length = sizeof(rpc_gsp_set_system_info_v17_00),
6415 .fdesc = vmiopd_fdesc_t_rpc_gsp_set_system_info_v17_00
6416 };
6417 #endif
6418
6419 #ifndef SKIP_PRINT_rpc_set_registry_v17_00
6420 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_set_registry_v17_00[] = {
6421 {
6422 .vtype = vt_end
6423 }
6424 };
6425
6426 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_set_registry_v17_00 = {
6427 #if (defined(DEBUG) || defined(DEVELOP))
6428 .name = "rpc_set_registry",
6429 #endif
6430 .fdesc = vmiopd_fdesc_t_rpc_set_registry_v17_00
6431 };
6432 #endif
6433
6434 #ifndef SKIP_PRINT_rpc_gsp_rm_alloc_v03_00
6435 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_rm_alloc_v03_00[] = {
6436 {
6437 .vtype = vtype_NvHandle,
6438 .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, hClient),
6439 #if (defined(DEBUG) || defined(DEVELOP))
6440 .name = "hClient"
6441 #endif
6442 },
6443 {
6444 .vtype = vtype_NvHandle,
6445 .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, hParent),
6446 #if (defined(DEBUG) || defined(DEVELOP))
6447 .name = "hParent"
6448 #endif
6449 },
6450 {
6451 .vtype = vtype_NvHandle,
6452 .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, hObject),
6453 #if (defined(DEBUG) || defined(DEVELOP))
6454 .name = "hObject"
6455 #endif
6456 },
6457 {
6458 .vtype = vtype_NvU32,
6459 .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, hClass),
6460 #if (defined(DEBUG) || defined(DEVELOP))
6461 .name = "hClass"
6462 #endif
6463 },
6464 {
6465 .vtype = vtype_NvU32,
6466 .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, status),
6467 #if (defined(DEBUG) || defined(DEVELOP))
6468 .name = "status"
6469 #endif
6470 },
6471 {
6472 .vtype = vtype_NvU32,
6473 .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, paramsSize),
6474 #if (defined(DEBUG) || defined(DEVELOP))
6475 .name = "paramsSize"
6476 #endif
6477 },
6478 {
6479 .vtype = vtype_NvU32,
6480 .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, flags),
6481 #if (defined(DEBUG) || defined(DEVELOP))
6482 .name = "flags"
6483 #endif
6484 },
6485 {
6486 .vtype = vtype_NvU8_array,
6487 .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, reserved),
6488 .array_length = 4,
6489 #if (defined(DEBUG) || defined(DEVELOP))
6490 .name = "reserved"
6491 #endif
6492 },
6493 {
6494 .vtype = vtype_NvU8_array,
6495 .offset = NV_OFFSETOF(rpc_gsp_rm_alloc_v03_00, params),
6496 .array_length = 0,
6497 #if (defined(DEBUG) || defined(DEVELOP))
6498 .name = "params"
6499 #endif
6500 },
6501 {
6502 .vtype = vt_end
6503 }
6504 };
6505
6506 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_rm_alloc_v03_00 = {
6507 #if (defined(DEBUG) || defined(DEVELOP))
6508 .name = "rpc_gsp_rm_alloc",
6509 #endif
6510 .header_length = sizeof(rpc_gsp_rm_alloc_v03_00),
6511 .fdesc = vmiopd_fdesc_t_rpc_gsp_rm_alloc_v03_00
6512 };
6513 #endif
6514
6515 #ifndef SKIP_PRINT_rpc_gsp_rm_control_v03_00
6516 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_rm_control_v03_00[] = {
6517 {
6518 .vtype = vtype_NvHandle,
6519 .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, hClient),
6520 #if (defined(DEBUG) || defined(DEVELOP))
6521 .name = "hClient"
6522 #endif
6523 },
6524 {
6525 .vtype = vtype_NvHandle,
6526 .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, hObject),
6527 #if (defined(DEBUG) || defined(DEVELOP))
6528 .name = "hObject"
6529 #endif
6530 },
6531 {
6532 .vtype = vtype_NvU32,
6533 .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, cmd),
6534 #if (defined(DEBUG) || defined(DEVELOP))
6535 .name = "cmd"
6536 #endif
6537 },
6538 {
6539 .vtype = vtype_NvU32,
6540 .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, status),
6541 #if (defined(DEBUG) || defined(DEVELOP))
6542 .name = "status"
6543 #endif
6544 },
6545 {
6546 .vtype = vtype_NvU32,
6547 .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, paramsSize),
6548 #if (defined(DEBUG) || defined(DEVELOP))
6549 .name = "paramsSize"
6550 #endif
6551 },
6552 {
6553 .vtype = vtype_NvU32,
6554 .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, flags),
6555 #if (defined(DEBUG) || defined(DEVELOP))
6556 .name = "flags"
6557 #endif
6558 },
6559 {
6560 .vtype = vtype_NvU8_array,
6561 .offset = NV_OFFSETOF(rpc_gsp_rm_control_v03_00, params),
6562 .array_length = 0,
6563 #if (defined(DEBUG) || defined(DEVELOP))
6564 .name = "params"
6565 #endif
6566 },
6567 {
6568 .vtype = vt_end
6569 }
6570 };
6571
6572 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_rm_control_v03_00 = {
6573 #if (defined(DEBUG) || defined(DEVELOP))
6574 .name = "rpc_gsp_rm_control",
6575 #endif
6576 .header_length = sizeof(rpc_gsp_rm_control_v03_00),
6577 .fdesc = vmiopd_fdesc_t_rpc_gsp_rm_control_v03_00
6578 };
6579 #endif
6580
6581 #ifndef SKIP_PRINT_rpc_dump_protobuf_component_v18_12
6582 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_dump_protobuf_component_v18_12[] = {
6583 {
6584 .vtype = vtype_NvU16,
6585 .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, component),
6586 #if (defined(DEBUG) || defined(DEVELOP))
6587 .name = "component"
6588 #endif
6589 },
6590 {
6591 .vtype = vtype_NvU8,
6592 .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, nvDumpType),
6593 #if (defined(DEBUG) || defined(DEVELOP))
6594 .name = "nvDumpType"
6595 #endif
6596 },
6597 {
6598 .vtype = vtype_NvBool,
6599 .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, countOnly),
6600 #if (defined(DEBUG) || defined(DEVELOP))
6601 .name = "countOnly"
6602 #endif
6603 },
6604 {
6605 .vtype = vtype_NvU32,
6606 .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, bugCheckCode),
6607 #if (defined(DEBUG) || defined(DEVELOP))
6608 .name = "bugCheckCode"
6609 #endif
6610 },
6611 {
6612 .vtype = vtype_NvU32,
6613 .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, internalCode),
6614 #if (defined(DEBUG) || defined(DEVELOP))
6615 .name = "internalCode"
6616 #endif
6617 },
6618 {
6619 .vtype = vtype_NvU32,
6620 .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, bufferSize),
6621 #if (defined(DEBUG) || defined(DEVELOP))
6622 .name = "bufferSize"
6623 #endif
6624 },
6625 {
6626 .vtype = vtype_NvU8_array,
6627 .offset = NV_OFFSETOF(rpc_dump_protobuf_component_v18_12, blob),
6628 .array_length = 0,
6629 #if (defined(DEBUG) || defined(DEVELOP))
6630 .name = "blob"
6631 #endif
6632 },
6633 {
6634 .vtype = vt_end
6635 }
6636 };
6637
6638 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_dump_protobuf_component_v18_12 = {
6639 #if (defined(DEBUG) || defined(DEVELOP))
6640 .name = "rpc_dump_protobuf_component",
6641 #endif
6642 .header_length = sizeof(rpc_dump_protobuf_component_v18_12),
6643 .fdesc = vmiopd_fdesc_t_rpc_dump_protobuf_component_v18_12
6644 };
6645 #endif
6646
6647 #ifndef SKIP_PRINT_rpc_run_cpu_sequencer_v17_00
6648 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_run_cpu_sequencer_v17_00[] = {
6649 {
6650 .vtype = vtype_NvU32,
6651 .offset = NV_OFFSETOF(rpc_run_cpu_sequencer_v17_00, bufferSizeDWord),
6652 #if (defined(DEBUG) || defined(DEVELOP))
6653 .name = "bufferSizeDWord"
6654 #endif
6655 },
6656 {
6657 .vtype = vtype_NvU32,
6658 .offset = NV_OFFSETOF(rpc_run_cpu_sequencer_v17_00, cmdIndex),
6659 #if (defined(DEBUG) || defined(DEVELOP))
6660 .name = "cmdIndex"
6661 #endif
6662 },
6663 {
6664 .vtype = vtype_NvU32_array,
6665 .offset = NV_OFFSETOF(rpc_run_cpu_sequencer_v17_00, regSaveArea),
6666 .array_length = 8,
6667 #if (defined(DEBUG) || defined(DEVELOP))
6668 .name = "regSaveArea"
6669 #endif
6670 },
6671 {
6672 .vtype = vtype_NvU32_array,
6673 .offset = NV_OFFSETOF(rpc_run_cpu_sequencer_v17_00, commandBuffer),
6674 .array_length = 0,
6675 #if (defined(DEBUG) || defined(DEVELOP))
6676 .name = "commandBuffer"
6677 #endif
6678 },
6679 {
6680 .vtype = vt_end
6681 }
6682 };
6683
6684 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_run_cpu_sequencer_v17_00 = {
6685 #if (defined(DEBUG) || defined(DEVELOP))
6686 .name = "rpc_run_cpu_sequencer",
6687 #endif
6688 .header_length = sizeof(rpc_run_cpu_sequencer_v17_00),
6689 .fdesc = vmiopd_fdesc_t_rpc_run_cpu_sequencer_v17_00
6690 };
6691 #endif
6692
6693 #ifndef SKIP_PRINT_rpc_post_event_v17_00
6694 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_post_event_v17_00[] = {
6695 {
6696 .vtype = vtype_NvHandle,
6697 .offset = NV_OFFSETOF(rpc_post_event_v17_00, hClient),
6698 #if (defined(DEBUG) || defined(DEVELOP))
6699 .name = "hClient"
6700 #endif
6701 },
6702 {
6703 .vtype = vtype_NvHandle,
6704 .offset = NV_OFFSETOF(rpc_post_event_v17_00, hEvent),
6705 #if (defined(DEBUG) || defined(DEVELOP))
6706 .name = "hEvent"
6707 #endif
6708 },
6709 {
6710 .vtype = vtype_NvU32,
6711 .offset = NV_OFFSETOF(rpc_post_event_v17_00, notifyIndex),
6712 #if (defined(DEBUG) || defined(DEVELOP))
6713 .name = "notifyIndex"
6714 #endif
6715 },
6716 {
6717 .vtype = vtype_NvU32,
6718 .offset = NV_OFFSETOF(rpc_post_event_v17_00, data),
6719 #if (defined(DEBUG) || defined(DEVELOP))
6720 .name = "data"
6721 #endif
6722 },
6723 {
6724 .vtype = vtype_NvU16,
6725 .offset = NV_OFFSETOF(rpc_post_event_v17_00, info16),
6726 #if (defined(DEBUG) || defined(DEVELOP))
6727 .name = "info16"
6728 #endif
6729 },
6730 {
6731 .vtype = vtype_NvU32,
6732 .offset = NV_OFFSETOF(rpc_post_event_v17_00, status),
6733 #if (defined(DEBUG) || defined(DEVELOP))
6734 .name = "status"
6735 #endif
6736 },
6737 {
6738 .vtype = vtype_NvU32,
6739 .offset = NV_OFFSETOF(rpc_post_event_v17_00, eventDataSize),
6740 #if (defined(DEBUG) || defined(DEVELOP))
6741 .name = "eventDataSize"
6742 #endif
6743 },
6744 {
6745 .vtype = vtype_NvBool,
6746 .offset = NV_OFFSETOF(rpc_post_event_v17_00, bNotifyList),
6747 #if (defined(DEBUG) || defined(DEVELOP))
6748 .name = "bNotifyList"
6749 #endif
6750 },
6751 {
6752 .vtype = vtype_NvU8_array,
6753 .offset = NV_OFFSETOF(rpc_post_event_v17_00, eventData),
6754 .array_length = 0,
6755 #if (defined(DEBUG) || defined(DEVELOP))
6756 .name = "eventData"
6757 #endif
6758 },
6759 {
6760 .vtype = vt_end
6761 }
6762 };
6763
6764 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_post_event_v17_00 = {
6765 #if (defined(DEBUG) || defined(DEVELOP))
6766 .name = "rpc_post_event",
6767 #endif
6768 .header_length = sizeof(rpc_post_event_v17_00),
6769 .fdesc = vmiopd_fdesc_t_rpc_post_event_v17_00
6770 };
6771 #endif
6772
6773 #ifndef SKIP_PRINT_rpc_rc_triggered_v17_02
6774 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rc_triggered_v17_02[] = {
6775 {
6776 .vtype = vtype_NvU32,
6777 .offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, nv2080EngineType),
6778 #if (defined(DEBUG) || defined(DEVELOP))
6779 .name = "nv2080EngineType"
6780 #endif
6781 },
6782 {
6783 .vtype = vtype_NvU32,
6784 .offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, chid),
6785 #if (defined(DEBUG) || defined(DEVELOP))
6786 .name = "chid"
6787 #endif
6788 },
6789 {
6790 .vtype = vtype_NvU32,
6791 .offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, exceptType),
6792 #if (defined(DEBUG) || defined(DEVELOP))
6793 .name = "exceptType"
6794 #endif
6795 },
6796 {
6797 .vtype = vtype_NvU32,
6798 .offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, scope),
6799 #if (defined(DEBUG) || defined(DEVELOP))
6800 .name = "scope"
6801 #endif
6802 },
6803 {
6804 .vtype = vtype_NvU16,
6805 .offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, partitionAttributionId),
6806 #if (defined(DEBUG) || defined(DEVELOP))
6807 .name = "partitionAttributionId"
6808 #endif
6809 },
6810 {
6811 .vtype = vtype_NvU32,
6812 .offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, rcJournalBufferSize),
6813 #if (defined(DEBUG) || defined(DEVELOP))
6814 .name = "rcJournalBufferSize"
6815 #endif
6816 },
6817 {
6818 .vtype = vtype_NvU8_array,
6819 .offset = NV_OFFSETOF(rpc_rc_triggered_v17_02, rcJournalBuffer),
6820 .array_length = 0,
6821 #if (defined(DEBUG) || defined(DEVELOP))
6822 .name = "rcJournalBuffer"
6823 #endif
6824 },
6825 {
6826 .vtype = vt_end
6827 }
6828 };
6829
6830 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rc_triggered_v17_02 = {
6831 #if (defined(DEBUG) || defined(DEVELOP))
6832 .name = "rpc_rc_triggered",
6833 #endif
6834 .header_length = sizeof(rpc_rc_triggered_v17_02),
6835 .fdesc = vmiopd_fdesc_t_rpc_rc_triggered_v17_02
6836 };
6837 #endif
6838
6839 #ifndef SKIP_PRINT_rpc_os_error_log_v17_00
6840 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_os_error_log_v17_00[] = {
6841 {
6842 .vtype = vtype_NvU32,
6843 .offset = NV_OFFSETOF(rpc_os_error_log_v17_00, exceptType),
6844 #if (defined(DEBUG) || defined(DEVELOP))
6845 .name = "exceptType"
6846 #endif
6847 },
6848 {
6849 .vtype = vtype_NvU32,
6850 .offset = NV_OFFSETOF(rpc_os_error_log_v17_00, runlistId),
6851 #if (defined(DEBUG) || defined(DEVELOP))
6852 .name = "runlistId"
6853 #endif
6854 },
6855 {
6856 .vtype = vtype_NvU32,
6857 .offset = NV_OFFSETOF(rpc_os_error_log_v17_00, chid),
6858 #if (defined(DEBUG) || defined(DEVELOP))
6859 .name = "chid"
6860 #endif
6861 },
6862 {
6863 .vtype = vtype_char_array,
6864 .offset = NV_OFFSETOF(rpc_os_error_log_v17_00, errString),
6865 .array_length = 0x100,
6866 #if (defined(DEBUG) || defined(DEVELOP))
6867 .name = "errString"
6868 #endif
6869 },
6870 {
6871 .vtype = vt_end
6872 }
6873 };
6874
6875 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_os_error_log_v17_00 = {
6876 #if (defined(DEBUG) || defined(DEVELOP))
6877 .name = "rpc_os_error_log",
6878 #endif
6879 .header_length = sizeof(rpc_os_error_log_v17_00),
6880 .fdesc = vmiopd_fdesc_t_rpc_os_error_log_v17_00
6881 };
6882 #endif
6883
6884 #ifndef SKIP_PRINT_rpc_rg_line_intr_v17_00
6885 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_rg_line_intr_v17_00[] = {
6886 {
6887 .vtype = vtype_NvU32,
6888 .offset = NV_OFFSETOF(rpc_rg_line_intr_v17_00, head),
6889 #if (defined(DEBUG) || defined(DEVELOP))
6890 .name = "head"
6891 #endif
6892 },
6893 {
6894 .vtype = vtype_NvU32,
6895 .offset = NV_OFFSETOF(rpc_rg_line_intr_v17_00, rgIntr),
6896 #if (defined(DEBUG) || defined(DEVELOP))
6897 .name = "rgIntr"
6898 #endif
6899 },
6900 {
6901 .vtype = vt_end
6902 }
6903 };
6904
6905 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_rg_line_intr_v17_00 = {
6906 #if (defined(DEBUG) || defined(DEVELOP))
6907 .name = "rpc_rg_line_intr",
6908 #endif
6909 .header_length = sizeof(rpc_rg_line_intr_v17_00),
6910 .fdesc = vmiopd_fdesc_t_rpc_rg_line_intr_v17_00
6911 };
6912 #endif
6913
6914 #ifndef SKIP_PRINT_rpc_display_modeset_v01_00
6915 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_display_modeset_v01_00[] = {
6916 {
6917 .vtype = vtype_NvBool,
6918 .offset = NV_OFFSETOF(rpc_display_modeset_v01_00, bModesetStart),
6919 #if (defined(DEBUG) || defined(DEVELOP))
6920 .name = "bModesetStart"
6921 #endif
6922 },
6923 {
6924 .vtype = vtype_NvU32,
6925 .offset = NV_OFFSETOF(rpc_display_modeset_v01_00, minRequiredIsoBandwidthKBPS),
6926 #if (defined(DEBUG) || defined(DEVELOP))
6927 .name = "minRequiredIsoBandwidthKBPS"
6928 #endif
6929 },
6930 {
6931 .vtype = vtype_NvU32,
6932 .offset = NV_OFFSETOF(rpc_display_modeset_v01_00, minRequiredFloorBandwidthKBPS),
6933 #if (defined(DEBUG) || defined(DEVELOP))
6934 .name = "minRequiredFloorBandwidthKBPS"
6935 #endif
6936 },
6937 {
6938 .vtype = vt_end
6939 }
6940 };
6941
6942 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_display_modeset_v01_00 = {
6943 #if (defined(DEBUG) || defined(DEVELOP))
6944 .name = "rpc_display_modeset",
6945 #endif
6946 .header_length = sizeof(rpc_display_modeset_v01_00),
6947 .fdesc = vmiopd_fdesc_t_rpc_display_modeset_v01_00
6948 };
6949 #endif
6950
6951 #ifndef SKIP_PRINT_rpc_gpuacct_perfmon_util_samples_v1F_0E
6952 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gpuacct_perfmon_util_samples_v1F_0E[] = {
6953 {
6954 .vtype = vtype_NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS_v1F_0E,
6955 .offset = NV_OFFSETOF(rpc_gpuacct_perfmon_util_samples_v1F_0E, params),
6956 #if (defined(DEBUG) || defined(DEVELOP))
6957 .name = "params"
6958 #endif
6959 },
6960 {
6961 .vtype = vt_end
6962 }
6963 };
6964
6965 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gpuacct_perfmon_util_samples_v1F_0E = {
6966 #if (defined(DEBUG) || defined(DEVELOP))
6967 .name = "rpc_gpuacct_perfmon_util_samples",
6968 #endif
6969 .header_length = sizeof(rpc_gpuacct_perfmon_util_samples_v1F_0E),
6970 .fdesc = vmiopd_fdesc_t_rpc_gpuacct_perfmon_util_samples_v1F_0E
6971 };
6972 #endif
6973
6974 #ifndef SKIP_PRINT_rpc_vgpu_gsp_plugin_triggered_v17_00
6975 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_vgpu_gsp_plugin_triggered_v17_00[] = {
6976 {
6977 .vtype = vtype_NvU32,
6978 .offset = NV_OFFSETOF(rpc_vgpu_gsp_plugin_triggered_v17_00, gfid),
6979 #if (defined(DEBUG) || defined(DEVELOP))
6980 .name = "gfid"
6981 #endif
6982 },
6983 {
6984 .vtype = vtype_NvU32,
6985 .offset = NV_OFFSETOF(rpc_vgpu_gsp_plugin_triggered_v17_00, notifyIndex),
6986 #if (defined(DEBUG) || defined(DEVELOP))
6987 .name = "notifyIndex"
6988 #endif
6989 },
6990 {
6991 .vtype = vt_end
6992 }
6993 };
6994
6995 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_vgpu_gsp_plugin_triggered_v17_00 = {
6996 #if (defined(DEBUG) || defined(DEVELOP))
6997 .name = "rpc_vgpu_gsp_plugin_triggered",
6998 #endif
6999 .header_length = sizeof(rpc_vgpu_gsp_plugin_triggered_v17_00),
7000 .fdesc = vmiopd_fdesc_t_rpc_vgpu_gsp_plugin_triggered_v17_00
7001 };
7002 #endif
7003
7004 #ifndef SKIP_PRINT_rpc_vgpu_config_event_v17_00
7005 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_vgpu_config_event_v17_00[] = {
7006 {
7007 .vtype = vtype_NvU32,
7008 .offset = NV_OFFSETOF(rpc_vgpu_config_event_v17_00, notifyIndex),
7009 #if (defined(DEBUG) || defined(DEVELOP))
7010 .name = "notifyIndex"
7011 #endif
7012 },
7013 {
7014 .vtype = vt_end
7015 }
7016 };
7017
7018 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_vgpu_config_event_v17_00 = {
7019 #if (defined(DEBUG) || defined(DEVELOP))
7020 .name = "rpc_vgpu_config_event",
7021 #endif
7022 .header_length = sizeof(rpc_vgpu_config_event_v17_00),
7023 .fdesc = vmiopd_fdesc_t_rpc_vgpu_config_event_v17_00
7024 };
7025 #endif
7026
7027 #ifndef SKIP_PRINT_rpc_dce_rm_init_v01_00
7028 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_dce_rm_init_v01_00[] = {
7029 {
7030 .vtype = vtype_NvBool,
7031 .offset = NV_OFFSETOF(rpc_dce_rm_init_v01_00, bInit),
7032 #if (defined(DEBUG) || defined(DEVELOP))
7033 .name = "bInit"
7034 #endif
7035 },
7036 {
7037 .vtype = vt_end
7038 }
7039 };
7040
7041 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_dce_rm_init_v01_00 = {
7042 #if (defined(DEBUG) || defined(DEVELOP))
7043 .name = "rpc_dce_rm_init",
7044 #endif
7045 .header_length = sizeof(rpc_dce_rm_init_v01_00),
7046 .fdesc = vmiopd_fdesc_t_rpc_dce_rm_init_v01_00
7047 };
7048 #endif
7049
7050 #ifndef SKIP_PRINT_rpc_sim_read_v1E_01
7051 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_sim_read_v1E_01[] = {
7052 {
7053 .vtype = vtype_char_array,
7054 .offset = NV_OFFSETOF(rpc_sim_read_v1E_01, path),
7055 .array_length = 0x100,
7056 #if (defined(DEBUG) || defined(DEVELOP))
7057 .name = "path"
7058 #endif
7059 },
7060 {
7061 .vtype = vtype_NvU32,
7062 .offset = NV_OFFSETOF(rpc_sim_read_v1E_01, index),
7063 #if (defined(DEBUG) || defined(DEVELOP))
7064 .name = "index"
7065 #endif
7066 },
7067 {
7068 .vtype = vtype_NvU32,
7069 .offset = NV_OFFSETOF(rpc_sim_read_v1E_01, count),
7070 #if (defined(DEBUG) || defined(DEVELOP))
7071 .name = "count"
7072 #endif
7073 },
7074 {
7075 .vtype = vt_end
7076 }
7077 };
7078
7079 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_sim_read_v1E_01 = {
7080 #if (defined(DEBUG) || defined(DEVELOP))
7081 .name = "rpc_sim_read",
7082 #endif
7083 .header_length = sizeof(rpc_sim_read_v1E_01),
7084 .fdesc = vmiopd_fdesc_t_rpc_sim_read_v1E_01
7085 };
7086 #endif
7087
7088 #ifndef SKIP_PRINT_rpc_sim_write_v1E_01
7089 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_sim_write_v1E_01[] = {
7090 {
7091 .vtype = vtype_char_array,
7092 .offset = NV_OFFSETOF(rpc_sim_write_v1E_01, path),
7093 .array_length = 0x100,
7094 #if (defined(DEBUG) || defined(DEVELOP))
7095 .name = "path"
7096 #endif
7097 },
7098 {
7099 .vtype = vtype_NvU32,
7100 .offset = NV_OFFSETOF(rpc_sim_write_v1E_01, index),
7101 #if (defined(DEBUG) || defined(DEVELOP))
7102 .name = "index"
7103 #endif
7104 },
7105 {
7106 .vtype = vtype_NvU32,
7107 .offset = NV_OFFSETOF(rpc_sim_write_v1E_01, count),
7108 #if (defined(DEBUG) || defined(DEVELOP))
7109 .name = "count"
7110 #endif
7111 },
7112 {
7113 .vtype = vtype_NvU32,
7114 .offset = NV_OFFSETOF(rpc_sim_write_v1E_01, data),
7115 #if (defined(DEBUG) || defined(DEVELOP))
7116 .name = "data"
7117 #endif
7118 },
7119 {
7120 .vtype = vt_end
7121 }
7122 };
7123
7124 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_sim_write_v1E_01 = {
7125 #if (defined(DEBUG) || defined(DEVELOP))
7126 .name = "rpc_sim_write",
7127 #endif
7128 .header_length = sizeof(rpc_sim_write_v1E_01),
7129 .fdesc = vmiopd_fdesc_t_rpc_sim_write_v1E_01
7130 };
7131 #endif
7132
7133 #ifndef SKIP_PRINT_rpc_ucode_libos_print_v1E_08
7134 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ucode_libos_print_v1E_08[] = {
7135 {
7136 .vtype = vtype_NvU32,
7137 .offset = NV_OFFSETOF(rpc_ucode_libos_print_v1E_08, ucodeEngDesc),
7138 #if (defined(DEBUG) || defined(DEVELOP))
7139 .name = "ucodeEngDesc"
7140 #endif
7141 },
7142 {
7143 .vtype = vtype_NvU32,
7144 .offset = NV_OFFSETOF(rpc_ucode_libos_print_v1E_08, libosPrintBufSize),
7145 #if (defined(DEBUG) || defined(DEVELOP))
7146 .name = "libosPrintBufSize"
7147 #endif
7148 },
7149 {
7150 .vtype = vtype_NvU8_array,
7151 .offset = NV_OFFSETOF(rpc_ucode_libos_print_v1E_08, libosPrintBuf),
7152 .array_length = 0,
7153 #if (defined(DEBUG) || defined(DEVELOP))
7154 .name = "libosPrintBuf"
7155 #endif
7156 },
7157 {
7158 .vtype = vt_end
7159 }
7160 };
7161
7162 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ucode_libos_print_v1E_08 = {
7163 #if (defined(DEBUG) || defined(DEVELOP))
7164 .name = "rpc_ucode_libos_print",
7165 #endif
7166 .header_length = sizeof(rpc_ucode_libos_print_v1E_08),
7167 .fdesc = vmiopd_fdesc_t_rpc_ucode_libos_print_v1E_08
7168 };
7169 #endif
7170
7171 #ifndef SKIP_PRINT_rpc_init_done_v17_00
7172 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_init_done_v17_00[] = {
7173 {
7174 .vtype = vtype_NvU32,
7175 .offset = NV_OFFSETOF(rpc_init_done_v17_00, not_used),
7176 #if (defined(DEBUG) || defined(DEVELOP))
7177 .name = "not_used"
7178 #endif
7179 },
7180 {
7181 .vtype = vt_end
7182 }
7183 };
7184
7185 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_init_done_v17_00 = {
7186 #if (defined(DEBUG) || defined(DEVELOP))
7187 .name = "rpc_init_done",
7188 #endif
7189 .header_length = sizeof(rpc_init_done_v17_00),
7190 .fdesc = vmiopd_fdesc_t_rpc_init_done_v17_00
7191 };
7192 #endif
7193
7194 #ifndef SKIP_PRINT_rpc_semaphore_schedule_callback_v17_00
7195 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_semaphore_schedule_callback_v17_00[] = {
7196 {
7197 .vtype = vtype_NvU64,
7198 .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, GPUVA),
7199 #if (defined(DEBUG) || defined(DEVELOP))
7200 .name = "GPUVA"
7201 #endif
7202 },
7203 {
7204 .vtype = vtype_NvU32,
7205 .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, hVASpace),
7206 #if (defined(DEBUG) || defined(DEVELOP))
7207 .name = "hVASpace"
7208 #endif
7209 },
7210 {
7211 .vtype = vtype_NvU32,
7212 .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, ReleaseValue),
7213 #if (defined(DEBUG) || defined(DEVELOP))
7214 .name = "ReleaseValue"
7215 #endif
7216 },
7217 {
7218 .vtype = vtype_NvU32,
7219 .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, Flags),
7220 #if (defined(DEBUG) || defined(DEVELOP))
7221 .name = "Flags"
7222 #endif
7223 },
7224 {
7225 .vtype = vtype_NvU32,
7226 .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, completionStatus),
7227 #if (defined(DEBUG) || defined(DEVELOP))
7228 .name = "completionStatus"
7229 #endif
7230 },
7231 {
7232 .vtype = vtype_NvHandle,
7233 .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, hClient),
7234 #if (defined(DEBUG) || defined(DEVELOP))
7235 .name = "hClient"
7236 #endif
7237 },
7238 {
7239 .vtype = vtype_NvHandle,
7240 .offset = NV_OFFSETOF(rpc_semaphore_schedule_callback_v17_00, hEvent),
7241 #if (defined(DEBUG) || defined(DEVELOP))
7242 .name = "hEvent"
7243 #endif
7244 },
7245 {
7246 .vtype = vt_end
7247 }
7248 };
7249
7250 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_semaphore_schedule_callback_v17_00 = {
7251 #if (defined(DEBUG) || defined(DEVELOP))
7252 .name = "rpc_semaphore_schedule_callback",
7253 #endif
7254 .header_length = sizeof(rpc_semaphore_schedule_callback_v17_00),
7255 .fdesc = vmiopd_fdesc_t_rpc_semaphore_schedule_callback_v17_00
7256 };
7257 #endif
7258
7259 #ifndef SKIP_PRINT_rpc_timed_semaphore_release_v01_00
7260 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_timed_semaphore_release_v01_00[] = {
7261 {
7262 .vtype = vtype_NvU64,
7263 .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, semaphoreVA),
7264 #if (defined(DEBUG) || defined(DEVELOP))
7265 .name = "semaphoreVA"
7266 #endif
7267 },
7268 {
7269 .vtype = vtype_NvU64,
7270 .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, notifierVA),
7271 #if (defined(DEBUG) || defined(DEVELOP))
7272 .name = "notifierVA"
7273 #endif
7274 },
7275 {
7276 .vtype = vtype_NvU32,
7277 .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, hVASpace),
7278 #if (defined(DEBUG) || defined(DEVELOP))
7279 .name = "hVASpace"
7280 #endif
7281 },
7282 {
7283 .vtype = vtype_NvU32,
7284 .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, releaseValue),
7285 #if (defined(DEBUG) || defined(DEVELOP))
7286 .name = "releaseValue"
7287 #endif
7288 },
7289 {
7290 .vtype = vtype_NvU32,
7291 .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, completionStatus),
7292 #if (defined(DEBUG) || defined(DEVELOP))
7293 .name = "completionStatus"
7294 #endif
7295 },
7296 {
7297 .vtype = vtype_NvHandle,
7298 .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, hClient),
7299 #if (defined(DEBUG) || defined(DEVELOP))
7300 .name = "hClient"
7301 #endif
7302 },
7303 {
7304 .vtype = vtype_NvHandle,
7305 .offset = NV_OFFSETOF(rpc_timed_semaphore_release_v01_00, hDevice),
7306 #if (defined(DEBUG) || defined(DEVELOP))
7307 .name = "hDevice"
7308 #endif
7309 },
7310 {
7311 .vtype = vt_end
7312 }
7313 };
7314
7315 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_timed_semaphore_release_v01_00 = {
7316 #if (defined(DEBUG) || defined(DEVELOP))
7317 .name = "rpc_timed_semaphore_release",
7318 #endif
7319 .header_length = sizeof(rpc_timed_semaphore_release_v01_00),
7320 .fdesc = vmiopd_fdesc_t_rpc_timed_semaphore_release_v01_00
7321 };
7322 #endif
7323
7324 #ifndef SKIP_PRINT_rpc_perf_gpu_boost_sync_limits_callback_v17_00
7325 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_perf_gpu_boost_sync_limits_callback_v17_00[] = {
7326 {
7327 .vtype = vtype_NV2080_CTRL_INTERNAL_PERF_GPU_BOOST_SYNC_SET_LIMITS_PARAMS_v17_00,
7328 .offset = NV_OFFSETOF(rpc_perf_gpu_boost_sync_limits_callback_v17_00, params),
7329 #if (defined(DEBUG) || defined(DEVELOP))
7330 .name = "params"
7331 #endif
7332 },
7333 {
7334 .vtype = vt_end
7335 }
7336 };
7337
7338 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_perf_gpu_boost_sync_limits_callback_v17_00 = {
7339 #if (defined(DEBUG) || defined(DEVELOP))
7340 .name = "rpc_perf_gpu_boost_sync_limits_callback",
7341 #endif
7342 .header_length = sizeof(rpc_perf_gpu_boost_sync_limits_callback_v17_00),
7343 .fdesc = vmiopd_fdesc_t_rpc_perf_gpu_boost_sync_limits_callback_v17_00
7344 };
7345 #endif
7346
7347 #ifndef SKIP_PRINT_rpc_perf_bridgeless_info_update_v17_00
7348 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_perf_bridgeless_info_update_v17_00[] = {
7349 {
7350 .vtype = vtype_NvU64,
7351 .offset = NV_OFFSETOF(rpc_perf_bridgeless_info_update_v17_00, bBridgeless),
7352 #if (defined(DEBUG) || defined(DEVELOP))
7353 .name = "bBridgeless"
7354 #endif
7355 },
7356 {
7357 .vtype = vt_end
7358 }
7359 };
7360
7361 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_perf_bridgeless_info_update_v17_00 = {
7362 #if (defined(DEBUG) || defined(DEVELOP))
7363 .name = "rpc_perf_bridgeless_info_update",
7364 #endif
7365 .header_length = sizeof(rpc_perf_bridgeless_info_update_v17_00),
7366 .fdesc = vmiopd_fdesc_t_rpc_perf_bridgeless_info_update_v17_00
7367 };
7368 #endif
7369
7370 #ifndef SKIP_PRINT_rpc_nvlink_fault_up_v17_00
7371 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_fault_up_v17_00[] = {
7372 {
7373 .vtype = vtype_NvU32,
7374 .offset = NV_OFFSETOF(rpc_nvlink_fault_up_v17_00, linkId),
7375 #if (defined(DEBUG) || defined(DEVELOP))
7376 .name = "linkId"
7377 #endif
7378 },
7379 {
7380 .vtype = vt_end
7381 }
7382 };
7383
7384 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_fault_up_v17_00 = {
7385 #if (defined(DEBUG) || defined(DEVELOP))
7386 .name = "rpc_nvlink_fault_up",
7387 #endif
7388 .header_length = sizeof(rpc_nvlink_fault_up_v17_00),
7389 .fdesc = vmiopd_fdesc_t_rpc_nvlink_fault_up_v17_00
7390 };
7391 #endif
7392
7393 #ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_256_v17_00
7394 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_256_v17_00[] = {
7395 {
7396 .vtype = vtype_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00,
7397 .offset = NV_OFFSETOF(rpc_nvlink_inband_received_data_256_v17_00, params),
7398 #if (defined(DEBUG) || defined(DEVELOP))
7399 .name = "params"
7400 #endif
7401 },
7402 {
7403 .vtype = vt_end
7404 }
7405 };
7406
7407 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_256_v17_00 = {
7408 #if (defined(DEBUG) || defined(DEVELOP))
7409 .name = "rpc_nvlink_inband_received_data_256",
7410 #endif
7411 .header_length = sizeof(rpc_nvlink_inband_received_data_256_v17_00),
7412 .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_256_v17_00
7413 };
7414 #endif
7415
7416 #ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_512_v17_00
7417 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_512_v17_00[] = {
7418 {
7419 .vtype = vtype_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_512_PARAMS_v17_00,
7420 .offset = NV_OFFSETOF(rpc_nvlink_inband_received_data_512_v17_00, params),
7421 #if (defined(DEBUG) || defined(DEVELOP))
7422 .name = "params"
7423 #endif
7424 },
7425 {
7426 .vtype = vt_end
7427 }
7428 };
7429
7430 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_512_v17_00 = {
7431 #if (defined(DEBUG) || defined(DEVELOP))
7432 .name = "rpc_nvlink_inband_received_data_512",
7433 #endif
7434 .header_length = sizeof(rpc_nvlink_inband_received_data_512_v17_00),
7435 .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_512_v17_00
7436 };
7437 #endif
7438
7439 #ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_1024_v17_00
7440 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_1024_v17_00[] = {
7441 {
7442 .vtype = vtype_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_1024_PARAMS_v17_00,
7443 .offset = NV_OFFSETOF(rpc_nvlink_inband_received_data_1024_v17_00, params),
7444 #if (defined(DEBUG) || defined(DEVELOP))
7445 .name = "params"
7446 #endif
7447 },
7448 {
7449 .vtype = vt_end
7450 }
7451 };
7452
7453 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_1024_v17_00 = {
7454 #if (defined(DEBUG) || defined(DEVELOP))
7455 .name = "rpc_nvlink_inband_received_data_1024",
7456 #endif
7457 .header_length = sizeof(rpc_nvlink_inband_received_data_1024_v17_00),
7458 .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_1024_v17_00
7459 };
7460 #endif
7461
7462 #ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_2048_v17_00
7463 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_2048_v17_00[] = {
7464 {
7465 .vtype = vtype_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_2048_PARAMS_v17_00,
7466 .offset = NV_OFFSETOF(rpc_nvlink_inband_received_data_2048_v17_00, params),
7467 #if (defined(DEBUG) || defined(DEVELOP))
7468 .name = "params"
7469 #endif
7470 },
7471 {
7472 .vtype = vt_end
7473 }
7474 };
7475
7476 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_2048_v17_00 = {
7477 #if (defined(DEBUG) || defined(DEVELOP))
7478 .name = "rpc_nvlink_inband_received_data_2048",
7479 #endif
7480 .header_length = sizeof(rpc_nvlink_inband_received_data_2048_v17_00),
7481 .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_2048_v17_00
7482 };
7483 #endif
7484
7485 #ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_4096_v17_00
7486 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_4096_v17_00[] = {
7487 {
7488 .vtype = vtype_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_4096_PARAMS_v17_00,
7489 .offset = NV_OFFSETOF(rpc_nvlink_inband_received_data_4096_v17_00, params),
7490 #if (defined(DEBUG) || defined(DEVELOP))
7491 .name = "params"
7492 #endif
7493 },
7494 {
7495 .vtype = vt_end
7496 }
7497 };
7498
7499 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_inband_received_data_4096_v17_00 = {
7500 #if (defined(DEBUG) || defined(DEVELOP))
7501 .name = "rpc_nvlink_inband_received_data_4096",
7502 #endif
7503 .header_length = sizeof(rpc_nvlink_inband_received_data_4096_v17_00),
7504 .fdesc = vmiopd_fdesc_t_rpc_nvlink_inband_received_data_4096_v17_00
7505 };
7506 #endif
7507
7508 #ifndef SKIP_PRINT_rpc_nvlink_is_gpu_degraded_v17_00
7509 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_is_gpu_degraded_v17_00[] = {
7510 {
7511 .vtype = vtype_NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00,
7512 .offset = NV_OFFSETOF(rpc_nvlink_is_gpu_degraded_v17_00, params),
7513 #if (defined(DEBUG) || defined(DEVELOP))
7514 .name = "params"
7515 #endif
7516 },
7517 {
7518 .vtype = vt_end
7519 }
7520 };
7521
7522 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_is_gpu_degraded_v17_00 = {
7523 #if (defined(DEBUG) || defined(DEVELOP))
7524 .name = "rpc_nvlink_is_gpu_degraded",
7525 #endif
7526 .header_length = sizeof(rpc_nvlink_is_gpu_degraded_v17_00),
7527 .fdesc = vmiopd_fdesc_t_rpc_nvlink_is_gpu_degraded_v17_00
7528 };
7529 #endif
7530
7531 #ifndef SKIP_PRINT_rpc_update_gsp_trace_v01_00
7532 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_update_gsp_trace_v01_00[] = {
7533 {
7534 .vtype = vtype_NvU32,
7535 .offset = NV_OFFSETOF(rpc_update_gsp_trace_v01_00, records),
7536 #if (defined(DEBUG) || defined(DEVELOP))
7537 .name = "records"
7538 #endif
7539 },
7540 {
7541 .vtype = vtype_NvU32,
7542 .offset = NV_OFFSETOF(rpc_update_gsp_trace_v01_00, data),
7543 #if (defined(DEBUG) || defined(DEVELOP))
7544 .name = "data"
7545 #endif
7546 },
7547 {
7548 .vtype = vt_end
7549 }
7550 };
7551
7552 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_update_gsp_trace_v01_00 = {
7553 #if (defined(DEBUG) || defined(DEVELOP))
7554 .name = "rpc_update_gsp_trace",
7555 #endif
7556 .header_length = sizeof(rpc_update_gsp_trace_v01_00),
7557 .fdesc = vmiopd_fdesc_t_rpc_update_gsp_trace_v01_00
7558 };
7559 #endif
7560
7561 #ifndef SKIP_PRINT_rpc_gsp_post_nocat_record_v01_00
7562 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_post_nocat_record_v01_00[] = {
7563 {
7564 .vtype = vtype_NvU32,
7565 .offset = NV_OFFSETOF(rpc_gsp_post_nocat_record_v01_00, data),
7566 #if (defined(DEBUG) || defined(DEVELOP))
7567 .name = "data"
7568 #endif
7569 },
7570 {
7571 .vtype = vt_end
7572 }
7573 };
7574
7575 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_post_nocat_record_v01_00 = {
7576 #if (defined(DEBUG) || defined(DEVELOP))
7577 .name = "rpc_gsp_post_nocat_record",
7578 #endif
7579 .header_length = sizeof(rpc_gsp_post_nocat_record_v01_00),
7580 .fdesc = vmiopd_fdesc_t_rpc_gsp_post_nocat_record_v01_00
7581 };
7582 #endif
7583
7584 #ifndef SKIP_PRINT_rpc_extdev_intr_service_v17_00
7585 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_extdev_intr_service_v17_00[] = {
7586 {
7587 .vtype = vtype_NvU8,
7588 .offset = NV_OFFSETOF(rpc_extdev_intr_service_v17_00, lossRegStatus),
7589 #if (defined(DEBUG) || defined(DEVELOP))
7590 .name = "lossRegStatus"
7591 #endif
7592 },
7593 {
7594 .vtype = vtype_NvU8,
7595 .offset = NV_OFFSETOF(rpc_extdev_intr_service_v17_00, gainRegStatus),
7596 #if (defined(DEBUG) || defined(DEVELOP))
7597 .name = "gainRegStatus"
7598 #endif
7599 },
7600 {
7601 .vtype = vtype_NvU8,
7602 .offset = NV_OFFSETOF(rpc_extdev_intr_service_v17_00, miscRegStatus),
7603 #if (defined(DEBUG) || defined(DEVELOP))
7604 .name = "miscRegStatus"
7605 #endif
7606 },
7607 {
7608 .vtype = vtype_NvBool,
7609 .offset = NV_OFFSETOF(rpc_extdev_intr_service_v17_00, rmStatus),
7610 #if (defined(DEBUG) || defined(DEVELOP))
7611 .name = "rmStatus"
7612 #endif
7613 },
7614 {
7615 .vtype = vt_end
7616 }
7617 };
7618
7619 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_extdev_intr_service_v17_00 = {
7620 #if (defined(DEBUG) || defined(DEVELOP))
7621 .name = "rpc_extdev_intr_service",
7622 #endif
7623 .header_length = sizeof(rpc_extdev_intr_service_v17_00),
7624 .fdesc = vmiopd_fdesc_t_rpc_extdev_intr_service_v17_00
7625 };
7626 #endif
7627
7628 #ifndef SKIP_PRINT_rpc_pfm_req_hndlr_state_sync_callback_v21_04
7629 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_pfm_req_hndlr_state_sync_callback_v21_04[] = {
7630 {
7631 .vtype = vtype_NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS_v21_04,
7632 .offset = NV_OFFSETOF(rpc_pfm_req_hndlr_state_sync_callback_v21_04, params),
7633 #if (defined(DEBUG) || defined(DEVELOP))
7634 .name = "params"
7635 #endif
7636 },
7637 {
7638 .vtype = vt_end
7639 }
7640 };
7641
7642 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_pfm_req_hndlr_state_sync_callback_v21_04 = {
7643 #if (defined(DEBUG) || defined(DEVELOP))
7644 .name = "rpc_pfm_req_hndlr_state_sync_callback",
7645 #endif
7646 .header_length = sizeof(rpc_pfm_req_hndlr_state_sync_callback_v21_04),
7647 .fdesc = vmiopd_fdesc_t_rpc_pfm_req_hndlr_state_sync_callback_v21_04
7648 };
7649 #endif
7650
7651 #ifndef SKIP_PRINT_rpc_vgpu_gsp_mig_ci_config_v21_03
7652 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_vgpu_gsp_mig_ci_config_v21_03[] = {
7653 {
7654 .vtype = vtype_NvU32,
7655 .offset = NV_OFFSETOF(rpc_vgpu_gsp_mig_ci_config_v21_03, execPartCount),
7656 #if (defined(DEBUG) || defined(DEVELOP))
7657 .name = "execPartCount"
7658 #endif
7659 },
7660 {
7661 .vtype = vtype_NvU32_array,
7662 .offset = NV_OFFSETOF(rpc_vgpu_gsp_mig_ci_config_v21_03, execPartId),
7663 .array_length = NVC637_CTRL_MAX_EXEC_PARTITIONS,
7664 #if (defined(DEBUG) || defined(DEVELOP))
7665 .name = "execPartId"
7666 #endif
7667 },
7668 {
7669 .vtype = vtype_NvU32,
7670 .offset = NV_OFFSETOF(rpc_vgpu_gsp_mig_ci_config_v21_03, gfid),
7671 #if (defined(DEBUG) || defined(DEVELOP))
7672 .name = "gfid"
7673 #endif
7674 },
7675 {
7676 .vtype = vtype_NvBool,
7677 .offset = NV_OFFSETOF(rpc_vgpu_gsp_mig_ci_config_v21_03, bDelete),
7678 #if (defined(DEBUG) || defined(DEVELOP))
7679 .name = "bDelete"
7680 #endif
7681 },
7682 {
7683 .vtype = vt_end
7684 }
7685 };
7686
7687 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_vgpu_gsp_mig_ci_config_v21_03 = {
7688 #if (defined(DEBUG) || defined(DEVELOP))
7689 .name = "rpc_vgpu_gsp_mig_ci_config",
7690 #endif
7691 .header_length = sizeof(rpc_vgpu_gsp_mig_ci_config_v21_03),
7692 .fdesc = vmiopd_fdesc_t_rpc_vgpu_gsp_mig_ci_config_v21_03
7693 };
7694 #endif
7695
7696 #ifndef SKIP_PRINT_rpc_gsp_lockdown_notice_v17_00
7697 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_gsp_lockdown_notice_v17_00[] = {
7698 {
7699 .vtype = vtype_NvBool,
7700 .offset = NV_OFFSETOF(rpc_gsp_lockdown_notice_v17_00, bLockdownEngaging),
7701 #if (defined(DEBUG) || defined(DEVELOP))
7702 .name = "bLockdownEngaging"
7703 #endif
7704 },
7705 {
7706 .vtype = vt_end
7707 }
7708 };
7709
7710 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_gsp_lockdown_notice_v17_00 = {
7711 #if (defined(DEBUG) || defined(DEVELOP))
7712 .name = "rpc_gsp_lockdown_notice",
7713 #endif
7714 .header_length = sizeof(rpc_gsp_lockdown_notice_v17_00),
7715 .fdesc = vmiopd_fdesc_t_rpc_gsp_lockdown_notice_v17_00
7716 };
7717 #endif
7718
7719 #ifndef SKIP_PRINT_rpc_ctrl_gpu_query_ecc_status_v24_06
7720 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_gpu_query_ecc_status_v24_06[] = {
7721 {
7722 .vtype = vtype_NvHandle,
7723 .offset = NV_OFFSETOF(rpc_ctrl_gpu_query_ecc_status_v24_06, hClient),
7724 #if (defined(DEBUG) || defined(DEVELOP))
7725 .name = "hClient"
7726 #endif
7727 },
7728 {
7729 .vtype = vtype_NvHandle,
7730 .offset = NV_OFFSETOF(rpc_ctrl_gpu_query_ecc_status_v24_06, hObject),
7731 #if (defined(DEBUG) || defined(DEVELOP))
7732 .name = "hObject"
7733 #endif
7734 },
7735 {
7736 .vtype = vtype_NV2080_CTRL_GPU_QUERY_ECC_STATUS_DEPRECATED_RPC_PARAMS_v24_06,
7737 .offset = NV_OFFSETOF(rpc_ctrl_gpu_query_ecc_status_v24_06, params),
7738 #if (defined(DEBUG) || defined(DEVELOP))
7739 .name = "params"
7740 #endif
7741 },
7742 {
7743 .vtype = vt_end
7744 }
7745 };
7746
7747 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_gpu_query_ecc_status_v24_06 = {
7748 #if (defined(DEBUG) || defined(DEVELOP))
7749 .name = "rpc_ctrl_gpu_query_ecc_status",
7750 #endif
7751 .header_length = sizeof(rpc_ctrl_gpu_query_ecc_status_v24_06),
7752 .fdesc = vmiopd_fdesc_t_rpc_ctrl_gpu_query_ecc_status_v24_06
7753 };
7754 #endif
7755
7756 #ifndef SKIP_PRINT_rpc_ctrl_dbg_get_mode_mmu_debug_v25_04
7757 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_dbg_get_mode_mmu_debug_v25_04[] = {
7758 {
7759 .vtype = vtype_NvHandle,
7760 .offset = NV_OFFSETOF(rpc_ctrl_dbg_get_mode_mmu_debug_v25_04, hClient),
7761 #if (defined(DEBUG) || defined(DEVELOP))
7762 .name = "hClient"
7763 #endif
7764 },
7765 {
7766 .vtype = vtype_NvHandle,
7767 .offset = NV_OFFSETOF(rpc_ctrl_dbg_get_mode_mmu_debug_v25_04, hObject),
7768 #if (defined(DEBUG) || defined(DEVELOP))
7769 .name = "hObject"
7770 #endif
7771 },
7772 {
7773 .vtype = vtype_NV83DE_CTRL_DEBUG_GET_MODE_MMU_DEBUG_PARAMS_v25_04,
7774 .offset = NV_OFFSETOF(rpc_ctrl_dbg_get_mode_mmu_debug_v25_04, ctrlParams),
7775 #if (defined(DEBUG) || defined(DEVELOP))
7776 .name = "ctrlParams"
7777 #endif
7778 },
7779 {
7780 .vtype = vt_end
7781 }
7782 };
7783
7784 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_dbg_get_mode_mmu_debug_v25_04 = {
7785 #if (defined(DEBUG) || defined(DEVELOP))
7786 .name = "rpc_ctrl_dbg_get_mode_mmu_debug",
7787 #endif
7788 .header_length = sizeof(rpc_ctrl_dbg_get_mode_mmu_debug_v25_04),
7789 .fdesc = vmiopd_fdesc_t_rpc_ctrl_dbg_get_mode_mmu_debug_v25_04
7790 };
7791 #endif
7792
7793 #ifndef SKIP_PRINT_rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09
7794 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09[] = {
7795 {
7796 .vtype = vtype_NvU8,
7797 .offset = NV_OFFSETOF(rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09, bwMode),
7798 #if (defined(DEBUG) || defined(DEVELOP))
7799 .name = "bwMode"
7800 #endif
7801 },
7802 {
7803 .vtype = vt_end
7804 }
7805 };
7806
7807 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09 = {
7808 #if (defined(DEBUG) || defined(DEVELOP))
7809 .name = "rpc_ctrl_cmd_internal_gpu_start_fabric_probe",
7810 #endif
7811 .header_length = sizeof(rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09),
7812 .fdesc = vmiopd_fdesc_t_rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09
7813 };
7814 #endif
7815
7816 #ifndef SKIP_PRINT_rpc_ctrl_nvlink_get_inband_received_data_v25_0C
7817 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_ctrl_nvlink_get_inband_received_data_v25_0C[] = {
7818 {
7819 .vtype = vtype_NvU16,
7820 .offset = NV_OFFSETOF(rpc_ctrl_nvlink_get_inband_received_data_v25_0C, message_type),
7821 #if (defined(DEBUG) || defined(DEVELOP))
7822 .name = "message_type"
7823 #endif
7824 },
7825 {
7826 .vtype = vtype_NvBool,
7827 .offset = NV_OFFSETOF(rpc_ctrl_nvlink_get_inband_received_data_v25_0C, more),
7828 #if (defined(DEBUG) || defined(DEVELOP))
7829 .name = "more"
7830 #endif
7831 },
7832 {
7833 .vtype = vtype_NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS_v25_0C,
7834 .offset = NV_OFFSETOF(rpc_ctrl_nvlink_get_inband_received_data_v25_0C, payload),
7835 #if (defined(DEBUG) || defined(DEVELOP))
7836 .name = "payload"
7837 #endif
7838 },
7839 {
7840 .vtype = vt_end
7841 }
7842 };
7843
7844 static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_ctrl_nvlink_get_inband_received_data_v25_0C = {
7845 #if (defined(DEBUG) || defined(DEVELOP))
7846 .name = "rpc_ctrl_nvlink_get_inband_received_data",
7847 #endif
7848 .header_length = sizeof(rpc_ctrl_nvlink_get_inband_received_data_v25_0C),
7849 .fdesc = vmiopd_fdesc_t_rpc_ctrl_nvlink_get_inband_received_data_v25_0C
7850 };
7851 #endif
7852
7853 #endif
7854
7855 #ifdef RPC_DEBUG_PRINT_FUNCTIONS
7856 // These are definitions for versioned functions. These will be used for RPC logging in the vmioplugin.
7857 #define SDK_DEBUG_PRINT_FUNCTIONS
7858 #include "g_sdk-structures.h"
7859 #undef SDK_DEBUG_PRINT_FUNCTIONS
7860 #ifndef SKIP_PRINT_rpc_nop_v03_00
rpcdebugNop_v03_00(void)7861 vmiopd_mdesc_t *rpcdebugNop_v03_00(void)
7862 {
7863 return &vmiopd_mdesc_t_rpc_nop_v03_00;
7864 }
7865 #endif
7866
7867 #ifndef SKIP_PRINT_rpc_set_guest_system_info_v03_00
rpcdebugSetGuestSystemInfo_v03_00(void)7868 vmiopd_mdesc_t *rpcdebugSetGuestSystemInfo_v03_00(void)
7869 {
7870 return &vmiopd_mdesc_t_rpc_set_guest_system_info_v03_00;
7871 }
7872 #endif
7873
7874 #ifndef SKIP_PRINT_rpc_set_guest_system_info_ext_v25_1B
rpcdebugSetGuestSystemInfoExt_v25_1B(void)7875 vmiopd_mdesc_t *rpcdebugSetGuestSystemInfoExt_v25_1B(void)
7876 {
7877 return &vmiopd_mdesc_t_rpc_set_guest_system_info_ext_v25_1B;
7878 }
7879 #endif
7880
7881 #ifndef SKIP_PRINT_rpc_set_guest_system_info_ext_v15_02
rpcdebugSetGuestSystemInfoExt_v15_02(void)7882 vmiopd_mdesc_t *rpcdebugSetGuestSystemInfoExt_v15_02(void)
7883 {
7884 return &vmiopd_mdesc_t_rpc_set_guest_system_info_ext_v15_02;
7885 }
7886 #endif
7887
7888 #ifndef SKIP_PRINT_rpc_alloc_root_v07_00
rpcdebugAllocRoot_v07_00(void)7889 vmiopd_mdesc_t *rpcdebugAllocRoot_v07_00(void)
7890 {
7891 return &vmiopd_mdesc_t_rpc_alloc_root_v07_00;
7892 }
7893 #endif
7894
7895 #ifndef SKIP_PRINT_rpc_alloc_memory_v13_01
rpcdebugAllocMemory_v13_01(void)7896 vmiopd_mdesc_t *rpcdebugAllocMemory_v13_01(void)
7897 {
7898 return &vmiopd_mdesc_t_rpc_alloc_memory_v13_01;
7899 }
7900 #endif
7901
7902 #ifndef SKIP_PRINT_rpc_alloc_channel_dma_v1F_04
rpcdebugAllocChannelDma_v1F_04(void)7903 vmiopd_mdesc_t *rpcdebugAllocChannelDma_v1F_04(void)
7904 {
7905 return &vmiopd_mdesc_t_rpc_alloc_channel_dma_v1F_04;
7906 }
7907 #endif
7908
7909 #ifndef SKIP_PRINT_rpc_alloc_object_v25_08
rpcdebugAllocObject_v25_08(void)7910 vmiopd_mdesc_t *rpcdebugAllocObject_v25_08(void)
7911 {
7912 return &vmiopd_mdesc_t_rpc_alloc_object_v25_08;
7913 }
7914 #endif
7915
7916 #ifndef SKIP_PRINT_rpc_free_v03_00
rpcdebugFree_v03_00(void)7917 vmiopd_mdesc_t *rpcdebugFree_v03_00(void)
7918 {
7919 return &vmiopd_mdesc_t_rpc_free_v03_00;
7920 }
7921 #endif
7922
7923 #ifndef SKIP_PRINT_rpc_log_v03_00
rpcdebugLog_v03_00(void)7924 vmiopd_mdesc_t *rpcdebugLog_v03_00(void)
7925 {
7926 return &vmiopd_mdesc_t_rpc_log_v03_00;
7927 }
7928 #endif
7929
7930 #ifndef SKIP_PRINT_rpc_map_memory_dma_v03_00
rpcdebugMapMemoryDma_v03_00(void)7931 vmiopd_mdesc_t *rpcdebugMapMemoryDma_v03_00(void)
7932 {
7933 return &vmiopd_mdesc_t_rpc_map_memory_dma_v03_00;
7934 }
7935 #endif
7936
7937 #ifndef SKIP_PRINT_rpc_unmap_memory_dma_v03_00
rpcdebugUnmapMemoryDma_v03_00(void)7938 vmiopd_mdesc_t *rpcdebugUnmapMemoryDma_v03_00(void)
7939 {
7940 return &vmiopd_mdesc_t_rpc_unmap_memory_dma_v03_00;
7941 }
7942 #endif
7943
7944 #ifndef SKIP_PRINT_rpc_alloc_subdevice_v08_01
rpcdebugAllocSubdevice_v08_01(void)7945 vmiopd_mdesc_t *rpcdebugAllocSubdevice_v08_01(void)
7946 {
7947 return &vmiopd_mdesc_t_rpc_alloc_subdevice_v08_01;
7948 }
7949 #endif
7950
7951 #ifndef SKIP_PRINT_rpc_dup_object_v03_00
rpcdebugDupObject_v03_00(void)7952 vmiopd_mdesc_t *rpcdebugDupObject_v03_00(void)
7953 {
7954 return &vmiopd_mdesc_t_rpc_dup_object_v03_00;
7955 }
7956 #endif
7957
7958 #ifndef SKIP_PRINT_rpc_idle_channels_v03_00
rpcdebugIdleChannels_v03_00(void)7959 vmiopd_mdesc_t *rpcdebugIdleChannels_v03_00(void)
7960 {
7961 return &vmiopd_mdesc_t_rpc_idle_channels_v03_00;
7962 }
7963 #endif
7964
7965 #ifndef SKIP_PRINT_rpc_alloc_event_v03_00
rpcdebugAllocEvent_v03_00(void)7966 vmiopd_mdesc_t *rpcdebugAllocEvent_v03_00(void)
7967 {
7968 return &vmiopd_mdesc_t_rpc_alloc_event_v03_00;
7969 }
7970 #endif
7971
7972 #ifndef SKIP_PRINT_rpc_rm_api_control_v25_19
rpcdebugRmApiControl_v25_19(void)7973 vmiopd_mdesc_t *rpcdebugRmApiControl_v25_19(void)
7974 {
7975 return &vmiopd_mdesc_t_rpc_rm_api_control_v25_19;
7976 }
7977 #endif
7978
7979 #ifndef SKIP_PRINT_rpc_rm_api_control_v25_0F
rpcdebugRmApiControl_v25_0F(void)7980 vmiopd_mdesc_t *rpcdebugRmApiControl_v25_0F(void)
7981 {
7982 return &vmiopd_mdesc_t_rpc_rm_api_control_v25_0F;
7983 }
7984 #endif
7985
7986 #ifndef SKIP_PRINT_rpc_rm_api_control_v25_16
rpcdebugRmApiControl_v25_16(void)7987 vmiopd_mdesc_t *rpcdebugRmApiControl_v25_16(void)
7988 {
7989 return &vmiopd_mdesc_t_rpc_rm_api_control_v25_16;
7990 }
7991 #endif
7992
7993 #ifndef SKIP_PRINT_rpc_rm_api_control_v25_10
rpcdebugRmApiControl_v25_10(void)7994 vmiopd_mdesc_t *rpcdebugRmApiControl_v25_10(void)
7995 {
7996 return &vmiopd_mdesc_t_rpc_rm_api_control_v25_10;
7997 }
7998 #endif
7999
8000 #ifndef SKIP_PRINT_rpc_rm_api_control_v25_15
rpcdebugRmApiControl_v25_15(void)8001 vmiopd_mdesc_t *rpcdebugRmApiControl_v25_15(void)
8002 {
8003 return &vmiopd_mdesc_t_rpc_rm_api_control_v25_15;
8004 }
8005 #endif
8006
8007 #ifndef SKIP_PRINT_rpc_rm_api_control_v25_0D
rpcdebugRmApiControl_v25_0D(void)8008 vmiopd_mdesc_t *rpcdebugRmApiControl_v25_0D(void)
8009 {
8010 return &vmiopd_mdesc_t_rpc_rm_api_control_v25_0D;
8011 }
8012 #endif
8013
8014 #ifndef SKIP_PRINT_rpc_rm_api_control_v25_17
rpcdebugRmApiControl_v25_17(void)8015 vmiopd_mdesc_t *rpcdebugRmApiControl_v25_17(void)
8016 {
8017 return &vmiopd_mdesc_t_rpc_rm_api_control_v25_17;
8018 }
8019 #endif
8020
8021 #ifndef SKIP_PRINT_rpc_rm_api_control_v25_18
rpcdebugRmApiControl_v25_18(void)8022 vmiopd_mdesc_t *rpcdebugRmApiControl_v25_18(void)
8023 {
8024 return &vmiopd_mdesc_t_rpc_rm_api_control_v25_18;
8025 }
8026 #endif
8027
8028 #ifndef SKIP_PRINT_rpc_rm_api_control_v25_1A
rpcdebugRmApiControl_v25_1A(void)8029 vmiopd_mdesc_t *rpcdebugRmApiControl_v25_1A(void)
8030 {
8031 return &vmiopd_mdesc_t_rpc_rm_api_control_v25_1A;
8032 }
8033 #endif
8034
8035 #ifndef SKIP_PRINT_rpc_rm_api_control_v25_14
rpcdebugRmApiControl_v25_14(void)8036 vmiopd_mdesc_t *rpcdebugRmApiControl_v25_14(void)
8037 {
8038 return &vmiopd_mdesc_t_rpc_rm_api_control_v25_14;
8039 }
8040 #endif
8041
8042 #ifndef SKIP_PRINT_rpc_alloc_share_device_v03_00
rpcdebugAllocShareDevice_v03_00(void)8043 vmiopd_mdesc_t *rpcdebugAllocShareDevice_v03_00(void)
8044 {
8045 return &vmiopd_mdesc_t_rpc_alloc_share_device_v03_00;
8046 }
8047 #endif
8048
8049 #ifndef SKIP_PRINT_rpc_get_engine_utilization_v1F_0E
rpcdebugGetEngineUtilization_v1F_0E(void)8050 vmiopd_mdesc_t *rpcdebugGetEngineUtilization_v1F_0E(void)
8051 {
8052 return &vmiopd_mdesc_t_rpc_get_engine_utilization_v1F_0E;
8053 }
8054 #endif
8055
8056 #ifndef SKIP_PRINT_rpc_perf_get_level_info_v03_00
rpcdebugPerfGetLevelInfo_v03_00(void)8057 vmiopd_mdesc_t *rpcdebugPerfGetLevelInfo_v03_00(void)
8058 {
8059 return &vmiopd_mdesc_t_rpc_perf_get_level_info_v03_00;
8060 }
8061 #endif
8062
8063 #ifndef SKIP_PRINT_rpc_set_surface_properties_v07_07
rpcdebugSetSurfaceProperties_v07_07(void)8064 vmiopd_mdesc_t *rpcdebugSetSurfaceProperties_v07_07(void)
8065 {
8066 return &vmiopd_mdesc_t_rpc_set_surface_properties_v07_07;
8067 }
8068 #endif
8069
8070 #ifndef SKIP_PRINT_rpc_cleanup_surface_v03_00
rpcdebugCleanupSurface_v03_00(void)8071 vmiopd_mdesc_t *rpcdebugCleanupSurface_v03_00(void)
8072 {
8073 return &vmiopd_mdesc_t_rpc_cleanup_surface_v03_00;
8074 }
8075 #endif
8076
8077 #ifndef SKIP_PRINT_rpc_unloading_guest_driver_v1F_07
rpcdebugUnloadingGuestDriver_v1F_07(void)8078 vmiopd_mdesc_t *rpcdebugUnloadingGuestDriver_v1F_07(void)
8079 {
8080 return &vmiopd_mdesc_t_rpc_unloading_guest_driver_v1F_07;
8081 }
8082 #endif
8083
8084 #ifndef SKIP_PRINT_rpc_switch_to_vga_v03_00
rpcdebugSwitchToVga_v03_00(void)8085 vmiopd_mdesc_t *rpcdebugSwitchToVga_v03_00(void)
8086 {
8087 return &vmiopd_mdesc_t_rpc_switch_to_vga_v03_00;
8088 }
8089 #endif
8090
8091 #ifndef SKIP_PRINT_rpc_gpu_exec_reg_ops_v12_01
rpcdebugGpuExecRegOps_v12_01(void)8092 vmiopd_mdesc_t *rpcdebugGpuExecRegOps_v12_01(void)
8093 {
8094 return &vmiopd_mdesc_t_rpc_gpu_exec_reg_ops_v12_01;
8095 }
8096 #endif
8097
8098 #ifndef SKIP_PRINT_rpc_get_static_data_v25_0E
rpcdebugGetStaticData_v25_0E(void)8099 vmiopd_mdesc_t *rpcdebugGetStaticData_v25_0E(void)
8100 {
8101 return &vmiopd_mdesc_t_rpc_get_static_data_v25_0E;
8102 }
8103 #endif
8104
8105 #ifndef SKIP_PRINT_rpc_get_consolidated_gr_static_info_v1B_04
rpcdebugGetConsolidatedGrStaticInfo_v1B_04(void)8106 vmiopd_mdesc_t *rpcdebugGetConsolidatedGrStaticInfo_v1B_04(void)
8107 {
8108 return &vmiopd_mdesc_t_rpc_get_consolidated_gr_static_info_v1B_04;
8109 }
8110 #endif
8111
8112 #ifndef SKIP_PRINT_rpc_set_page_directory_v1E_05
rpcdebugSetPageDirectory_v1E_05(void)8113 vmiopd_mdesc_t *rpcdebugSetPageDirectory_v1E_05(void)
8114 {
8115 return &vmiopd_mdesc_t_rpc_set_page_directory_v1E_05;
8116 }
8117 #endif
8118
8119 #ifndef SKIP_PRINT_rpc_unset_page_directory_v1E_05
rpcdebugUnsetPageDirectory_v1E_05(void)8120 vmiopd_mdesc_t *rpcdebugUnsetPageDirectory_v1E_05(void)
8121 {
8122 return &vmiopd_mdesc_t_rpc_unset_page_directory_v1E_05;
8123 }
8124 #endif
8125
8126 #ifndef SKIP_PRINT_rpc_get_gsp_static_info_v14_00
rpcdebugGetGspStaticInfo_v14_00(void)8127 vmiopd_mdesc_t *rpcdebugGetGspStaticInfo_v14_00(void)
8128 {
8129 return &vmiopd_mdesc_t_rpc_get_gsp_static_info_v14_00;
8130 }
8131 #endif
8132
8133 #ifndef SKIP_PRINT_rpc_update_bar_pde_v15_00
rpcdebugUpdateBarPde_v15_00(void)8134 vmiopd_mdesc_t *rpcdebugUpdateBarPde_v15_00(void)
8135 {
8136 return &vmiopd_mdesc_t_rpc_update_bar_pde_v15_00;
8137 }
8138 #endif
8139
8140 #ifndef SKIP_PRINT_rpc_get_encoder_capacity_v07_00
rpcdebugGetEncoderCapacity_v07_00(void)8141 vmiopd_mdesc_t *rpcdebugGetEncoderCapacity_v07_00(void)
8142 {
8143 return &vmiopd_mdesc_t_rpc_get_encoder_capacity_v07_00;
8144 }
8145 #endif
8146
8147 #ifndef SKIP_PRINT_rpc_vgpu_pf_reg_read32_v15_00
rpcdebugVgpuPfRegRead32_v15_00(void)8148 vmiopd_mdesc_t *rpcdebugVgpuPfRegRead32_v15_00(void)
8149 {
8150 return &vmiopd_mdesc_t_rpc_vgpu_pf_reg_read32_v15_00;
8151 }
8152 #endif
8153
8154 #ifndef SKIP_PRINT_rpc_ctrl_set_vgpu_fb_usage_v1A_08
rpcdebugCtrlSetVgpuFbUsage_v1A_08(void)8155 vmiopd_mdesc_t *rpcdebugCtrlSetVgpuFbUsage_v1A_08(void)
8156 {
8157 return &vmiopd_mdesc_t_rpc_ctrl_set_vgpu_fb_usage_v1A_08;
8158 }
8159 #endif
8160
8161 #ifndef SKIP_PRINT_rpc_ctrl_nvenc_sw_session_update_info_v1A_09
rpcdebugCtrlNvencSwSessionUpdateInfo_v1A_09(void)8162 vmiopd_mdesc_t *rpcdebugCtrlNvencSwSessionUpdateInfo_v1A_09(void)
8163 {
8164 return &vmiopd_mdesc_t_rpc_ctrl_nvenc_sw_session_update_info_v1A_09;
8165 }
8166 #endif
8167
8168 #ifndef SKIP_PRINT_rpc_ctrl_reset_channel_v1A_09
rpcdebugCtrlResetChannel_v1A_09(void)8169 vmiopd_mdesc_t *rpcdebugCtrlResetChannel_v1A_09(void)
8170 {
8171 return &vmiopd_mdesc_t_rpc_ctrl_reset_channel_v1A_09;
8172 }
8173 #endif
8174
8175 #ifndef SKIP_PRINT_rpc_ctrl_reset_isolated_channel_v1A_09
rpcdebugCtrlResetIsolatedChannel_v1A_09(void)8176 vmiopd_mdesc_t *rpcdebugCtrlResetIsolatedChannel_v1A_09(void)
8177 {
8178 return &vmiopd_mdesc_t_rpc_ctrl_reset_isolated_channel_v1A_09;
8179 }
8180 #endif
8181
8182 #ifndef SKIP_PRINT_rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09
rpcdebugCtrlGpuHandleVfPriFault_v1A_09(void)8183 vmiopd_mdesc_t *rpcdebugCtrlGpuHandleVfPriFault_v1A_09(void)
8184 {
8185 return &vmiopd_mdesc_t_rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09;
8186 }
8187 #endif
8188
8189 #ifndef SKIP_PRINT_rpc_ctrl_perf_boost_v1A_09
rpcdebugCtrlPerfBoost_v1A_09(void)8190 vmiopd_mdesc_t *rpcdebugCtrlPerfBoost_v1A_09(void)
8191 {
8192 return &vmiopd_mdesc_t_rpc_ctrl_perf_boost_v1A_09;
8193 }
8194 #endif
8195
8196 #ifndef SKIP_PRINT_rpc_ctrl_get_zbc_clear_table_v1A_09
rpcdebugCtrlGetZbcClearTable_v1A_09(void)8197 vmiopd_mdesc_t *rpcdebugCtrlGetZbcClearTable_v1A_09(void)
8198 {
8199 return &vmiopd_mdesc_t_rpc_ctrl_get_zbc_clear_table_v1A_09;
8200 }
8201 #endif
8202
8203 #ifndef SKIP_PRINT_rpc_ctrl_set_zbc_color_clear_v1A_09
rpcdebugCtrlSetZbcColorClear_v1A_09(void)8204 vmiopd_mdesc_t *rpcdebugCtrlSetZbcColorClear_v1A_09(void)
8205 {
8206 return &vmiopd_mdesc_t_rpc_ctrl_set_zbc_color_clear_v1A_09;
8207 }
8208 #endif
8209
8210 #ifndef SKIP_PRINT_rpc_ctrl_set_zbc_depth_clear_v1A_09
rpcdebugCtrlSetZbcDepthClear_v1A_09(void)8211 vmiopd_mdesc_t *rpcdebugCtrlSetZbcDepthClear_v1A_09(void)
8212 {
8213 return &vmiopd_mdesc_t_rpc_ctrl_set_zbc_depth_clear_v1A_09;
8214 }
8215 #endif
8216
8217 #ifndef SKIP_PRINT_rpc_ctrl_gpfifo_schedule_v1A_0A
rpcdebugCtrlGpfifoSchedule_v1A_0A(void)8218 vmiopd_mdesc_t *rpcdebugCtrlGpfifoSchedule_v1A_0A(void)
8219 {
8220 return &vmiopd_mdesc_t_rpc_ctrl_gpfifo_schedule_v1A_0A;
8221 }
8222 #endif
8223
8224 #ifndef SKIP_PRINT_rpc_ctrl_set_timeslice_v1A_0A
rpcdebugCtrlSetTimeslice_v1A_0A(void)8225 vmiopd_mdesc_t *rpcdebugCtrlSetTimeslice_v1A_0A(void)
8226 {
8227 return &vmiopd_mdesc_t_rpc_ctrl_set_timeslice_v1A_0A;
8228 }
8229 #endif
8230
8231 #ifndef SKIP_PRINT_rpc_ctrl_fifo_disable_channels_v1A_0A
rpcdebugCtrlFifoDisableChannels_v1A_0A(void)8232 vmiopd_mdesc_t *rpcdebugCtrlFifoDisableChannels_v1A_0A(void)
8233 {
8234 return &vmiopd_mdesc_t_rpc_ctrl_fifo_disable_channels_v1A_0A;
8235 }
8236 #endif
8237
8238 #ifndef SKIP_PRINT_rpc_ctrl_preempt_v1A_0A
rpcdebugCtrlPreempt_v1A_0A(void)8239 vmiopd_mdesc_t *rpcdebugCtrlPreempt_v1A_0A(void)
8240 {
8241 return &vmiopd_mdesc_t_rpc_ctrl_preempt_v1A_0A;
8242 }
8243 #endif
8244
8245 #ifndef SKIP_PRINT_rpc_ctrl_set_tsg_interleave_level_v1A_0A
rpcdebugCtrlSetTsgInterleaveLevel_v1A_0A(void)8246 vmiopd_mdesc_t *rpcdebugCtrlSetTsgInterleaveLevel_v1A_0A(void)
8247 {
8248 return &vmiopd_mdesc_t_rpc_ctrl_set_tsg_interleave_level_v1A_0A;
8249 }
8250 #endif
8251
8252 #ifndef SKIP_PRINT_rpc_ctrl_set_channel_interleave_level_v1A_0A
rpcdebugCtrlSetChannelInterleaveLevel_v1A_0A(void)8253 vmiopd_mdesc_t *rpcdebugCtrlSetChannelInterleaveLevel_v1A_0A(void)
8254 {
8255 return &vmiopd_mdesc_t_rpc_ctrl_set_channel_interleave_level_v1A_0A;
8256 }
8257 #endif
8258
8259 #ifndef SKIP_PRINT_rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E
rpcdebugCtrlGrCtxswPreemptionBind_v1A_0E(void)8260 vmiopd_mdesc_t *rpcdebugCtrlGrCtxswPreemptionBind_v1A_0E(void)
8261 {
8262 return &vmiopd_mdesc_t_rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E;
8263 }
8264 #endif
8265
8266 #ifndef SKIP_PRINT_rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E
rpcdebugCtrlGrSetCtxswPreemptionMode_v1A_0E(void)8267 vmiopd_mdesc_t *rpcdebugCtrlGrSetCtxswPreemptionMode_v1A_0E(void)
8268 {
8269 return &vmiopd_mdesc_t_rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E;
8270 }
8271 #endif
8272
8273 #ifndef SKIP_PRINT_rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E
rpcdebugCtrlGrCtxswZcullBind_v1A_0E(void)8274 vmiopd_mdesc_t *rpcdebugCtrlGrCtxswZcullBind_v1A_0E(void)
8275 {
8276 return &vmiopd_mdesc_t_rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E;
8277 }
8278 #endif
8279
8280 #ifndef SKIP_PRINT_rpc_ctrl_gpu_initialize_ctx_v1A_0E
rpcdebugCtrlGpuInitializeCtx_v1A_0E(void)8281 vmiopd_mdesc_t *rpcdebugCtrlGpuInitializeCtx_v1A_0E(void)
8282 {
8283 return &vmiopd_mdesc_t_rpc_ctrl_gpu_initialize_ctx_v1A_0E;
8284 }
8285 #endif
8286
8287 #ifndef SKIP_PRINT_rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04
rpcdebugCtrlVaspaceCopyServerReservedPdes_v1E_04(void)8288 vmiopd_mdesc_t *rpcdebugCtrlVaspaceCopyServerReservedPdes_v1E_04(void)
8289 {
8290 return &vmiopd_mdesc_t_rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04;
8291 }
8292 #endif
8293
8294 #ifndef SKIP_PRINT_rpc_ctrl_mc_service_interrupts_v1A_0E
rpcdebugCtrlMcServiceInterrupts_v1A_0E(void)8295 vmiopd_mdesc_t *rpcdebugCtrlMcServiceInterrupts_v1A_0E(void)
8296 {
8297 return &vmiopd_mdesc_t_rpc_ctrl_mc_service_interrupts_v1A_0E;
8298 }
8299 #endif
8300
8301 #ifndef SKIP_PRINT_rpc_ctrl_get_p2p_caps_v2_v1F_0D
rpcdebugCtrlGetP2pCapsV2_v1F_0D(void)8302 vmiopd_mdesc_t *rpcdebugCtrlGetP2pCapsV2_v1F_0D(void)
8303 {
8304 return &vmiopd_mdesc_t_rpc_ctrl_get_p2p_caps_v2_v1F_0D;
8305 }
8306 #endif
8307
8308 #ifndef SKIP_PRINT_rpc_ctrl_subdevice_get_p2p_caps_v21_02
rpcdebugCtrlSubdeviceGetP2pCaps_v21_02(void)8309 vmiopd_mdesc_t *rpcdebugCtrlSubdeviceGetP2pCaps_v21_02(void)
8310 {
8311 return &vmiopd_mdesc_t_rpc_ctrl_subdevice_get_p2p_caps_v21_02;
8312 }
8313 #endif
8314
8315 #ifndef SKIP_PRINT_rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C
rpcdebugCtrlDbgClearAllSmErrorStates_v1A_0C(void)8316 vmiopd_mdesc_t *rpcdebugCtrlDbgClearAllSmErrorStates_v1A_0C(void)
8317 {
8318 return &vmiopd_mdesc_t_rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C;
8319 }
8320 #endif
8321
8322 #ifndef SKIP_PRINT_rpc_ctrl_dbg_read_all_sm_error_states_v21_06
rpcdebugCtrlDbgReadAllSmErrorStates_v21_06(void)8323 vmiopd_mdesc_t *rpcdebugCtrlDbgReadAllSmErrorStates_v21_06(void)
8324 {
8325 return &vmiopd_mdesc_t_rpc_ctrl_dbg_read_all_sm_error_states_v21_06;
8326 }
8327 #endif
8328
8329 #ifndef SKIP_PRINT_rpc_ctrl_dbg_set_exception_mask_v1A_0C
rpcdebugCtrlDbgSetExceptionMask_v1A_0C(void)8330 vmiopd_mdesc_t *rpcdebugCtrlDbgSetExceptionMask_v1A_0C(void)
8331 {
8332 return &vmiopd_mdesc_t_rpc_ctrl_dbg_set_exception_mask_v1A_0C;
8333 }
8334 #endif
8335
8336 #ifndef SKIP_PRINT_rpc_ctrl_gpu_promote_ctx_v1A_20
rpcdebugCtrlGpuPromoteCtx_v1A_20(void)8337 vmiopd_mdesc_t *rpcdebugCtrlGpuPromoteCtx_v1A_20(void)
8338 {
8339 return &vmiopd_mdesc_t_rpc_ctrl_gpu_promote_ctx_v1A_20;
8340 }
8341 #endif
8342
8343 #ifndef SKIP_PRINT_rpc_ctrl_dbg_suspend_context_v1A_10
rpcdebugCtrlDbgSuspendContext_v1A_10(void)8344 vmiopd_mdesc_t *rpcdebugCtrlDbgSuspendContext_v1A_10(void)
8345 {
8346 return &vmiopd_mdesc_t_rpc_ctrl_dbg_suspend_context_v1A_10;
8347 }
8348 #endif
8349
8350 #ifndef SKIP_PRINT_rpc_ctrl_dbg_resume_context_v1A_10
rpcdebugCtrlDbgResumeContext_v1A_10(void)8351 vmiopd_mdesc_t *rpcdebugCtrlDbgResumeContext_v1A_10(void)
8352 {
8353 return &vmiopd_mdesc_t_rpc_ctrl_dbg_resume_context_v1A_10;
8354 }
8355 #endif
8356
8357 #ifndef SKIP_PRINT_rpc_ctrl_dbg_exec_reg_ops_v1A_10
rpcdebugCtrlDbgExecRegOps_v1A_10(void)8358 vmiopd_mdesc_t *rpcdebugCtrlDbgExecRegOps_v1A_10(void)
8359 {
8360 return &vmiopd_mdesc_t_rpc_ctrl_dbg_exec_reg_ops_v1A_10;
8361 }
8362 #endif
8363
8364 #ifndef SKIP_PRINT_rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10
rpcdebugCtrlDbgSetModeMmuDebug_v1A_10(void)8365 vmiopd_mdesc_t *rpcdebugCtrlDbgSetModeMmuDebug_v1A_10(void)
8366 {
8367 return &vmiopd_mdesc_t_rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10;
8368 }
8369 #endif
8370
8371 #ifndef SKIP_PRINT_rpc_ctrl_dbg_read_single_sm_error_state_v21_06
rpcdebugCtrlDbgReadSingleSmErrorState_v21_06(void)8372 vmiopd_mdesc_t *rpcdebugCtrlDbgReadSingleSmErrorState_v21_06(void)
8373 {
8374 return &vmiopd_mdesc_t_rpc_ctrl_dbg_read_single_sm_error_state_v21_06;
8375 }
8376 #endif
8377
8378 #ifndef SKIP_PRINT_rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10
rpcdebugCtrlDbgClearSingleSmErrorState_v1A_10(void)8379 vmiopd_mdesc_t *rpcdebugCtrlDbgClearSingleSmErrorState_v1A_10(void)
8380 {
8381 return &vmiopd_mdesc_t_rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10;
8382 }
8383 #endif
8384
8385 #ifndef SKIP_PRINT_rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10
rpcdebugCtrlDbgSetModeErrbarDebug_v1A_10(void)8386 vmiopd_mdesc_t *rpcdebugCtrlDbgSetModeErrbarDebug_v1A_10(void)
8387 {
8388 return &vmiopd_mdesc_t_rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10;
8389 }
8390 #endif
8391
8392 #ifndef SKIP_PRINT_rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10
rpcdebugCtrlDbgSetNextStopTriggerType_v1A_10(void)8393 vmiopd_mdesc_t *rpcdebugCtrlDbgSetNextStopTriggerType_v1A_10(void)
8394 {
8395 return &vmiopd_mdesc_t_rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10;
8396 }
8397 #endif
8398
8399 #ifndef SKIP_PRINT_rpc_ctrl_dma_set_default_vaspace_v1A_0E
rpcdebugCtrlDmaSetDefaultVaspace_v1A_0E(void)8400 vmiopd_mdesc_t *rpcdebugCtrlDmaSetDefaultVaspace_v1A_0E(void)
8401 {
8402 return &vmiopd_mdesc_t_rpc_ctrl_dma_set_default_vaspace_v1A_0E;
8403 }
8404 #endif
8405
8406 #ifndef SKIP_PRINT_rpc_ctrl_get_ce_pce_mask_v1A_0E
rpcdebugCtrlGetCePceMask_v1A_0E(void)8407 vmiopd_mdesc_t *rpcdebugCtrlGetCePceMask_v1A_0E(void)
8408 {
8409 return &vmiopd_mdesc_t_rpc_ctrl_get_ce_pce_mask_v1A_0E;
8410 }
8411 #endif
8412
8413 #ifndef SKIP_PRINT_rpc_ctrl_get_zbc_clear_table_entry_v1A_0E
rpcdebugCtrlGetZbcClearTableEntry_v1A_0E(void)8414 vmiopd_mdesc_t *rpcdebugCtrlGetZbcClearTableEntry_v1A_0E(void)
8415 {
8416 return &vmiopd_mdesc_t_rpc_ctrl_get_zbc_clear_table_entry_v1A_0E;
8417 }
8418 #endif
8419
8420 #ifndef SKIP_PRINT_rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E
rpcdebugCtrlGetNvlinkPeerIdMask_v1A_0E(void)8421 vmiopd_mdesc_t *rpcdebugCtrlGetNvlinkPeerIdMask_v1A_0E(void)
8422 {
8423 return &vmiopd_mdesc_t_rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E;
8424 }
8425 #endif
8426
8427 #ifndef SKIP_PRINT_rpc_ctrl_get_nvlink_status_v23_04
rpcdebugCtrlGetNvlinkStatus_v23_04(void)8428 vmiopd_mdesc_t *rpcdebugCtrlGetNvlinkStatus_v23_04(void)
8429 {
8430 return &vmiopd_mdesc_t_rpc_ctrl_get_nvlink_status_v23_04;
8431 }
8432 #endif
8433
8434 #ifndef SKIP_PRINT_rpc_ctrl_get_p2p_caps_v1F_0D
rpcdebugCtrlGetP2pCaps_v1F_0D(void)8435 vmiopd_mdesc_t *rpcdebugCtrlGetP2pCaps_v1F_0D(void)
8436 {
8437 return &vmiopd_mdesc_t_rpc_ctrl_get_p2p_caps_v1F_0D;
8438 }
8439 #endif
8440
8441 #ifndef SKIP_PRINT_rpc_ctrl_get_p2p_caps_matrix_v1A_0E
rpcdebugCtrlGetP2pCapsMatrix_v1A_0E(void)8442 vmiopd_mdesc_t *rpcdebugCtrlGetP2pCapsMatrix_v1A_0E(void)
8443 {
8444 return &vmiopd_mdesc_t_rpc_ctrl_get_p2p_caps_matrix_v1A_0E;
8445 }
8446 #endif
8447
8448 #ifndef SKIP_PRINT_rpc_ctrl_reserve_pm_area_smpc_v1A_0F
rpcdebugCtrlReservePmAreaSmpc_v1A_0F(void)8449 vmiopd_mdesc_t *rpcdebugCtrlReservePmAreaSmpc_v1A_0F(void)
8450 {
8451 return &vmiopd_mdesc_t_rpc_ctrl_reserve_pm_area_smpc_v1A_0F;
8452 }
8453 #endif
8454
8455 #ifndef SKIP_PRINT_rpc_ctrl_reserve_hwpm_legacy_v1A_0F
rpcdebugCtrlReserveHwpmLegacy_v1A_0F(void)8456 vmiopd_mdesc_t *rpcdebugCtrlReserveHwpmLegacy_v1A_0F(void)
8457 {
8458 return &vmiopd_mdesc_t_rpc_ctrl_reserve_hwpm_legacy_v1A_0F;
8459 }
8460 #endif
8461
8462 #ifndef SKIP_PRINT_rpc_ctrl_b0cc_exec_reg_ops_v1A_0F
rpcdebugCtrlB0ccExecRegOps_v1A_0F(void)8463 vmiopd_mdesc_t *rpcdebugCtrlB0ccExecRegOps_v1A_0F(void)
8464 {
8465 return &vmiopd_mdesc_t_rpc_ctrl_b0cc_exec_reg_ops_v1A_0F;
8466 }
8467 #endif
8468
8469 #ifndef SKIP_PRINT_rpc_ctrl_bind_pm_resources_v1A_0F
rpcdebugCtrlBindPmResources_v1A_0F(void)8470 vmiopd_mdesc_t *rpcdebugCtrlBindPmResources_v1A_0F(void)
8471 {
8472 return &vmiopd_mdesc_t_rpc_ctrl_bind_pm_resources_v1A_0F;
8473 }
8474 #endif
8475
8476 #ifndef SKIP_PRINT_rpc_ctrl_alloc_pma_stream_v1A_14
rpcdebugCtrlAllocPmaStream_v1A_14(void)8477 vmiopd_mdesc_t *rpcdebugCtrlAllocPmaStream_v1A_14(void)
8478 {
8479 return &vmiopd_mdesc_t_rpc_ctrl_alloc_pma_stream_v1A_14;
8480 }
8481 #endif
8482
8483 #ifndef SKIP_PRINT_rpc_ctrl_pma_stream_update_get_put_v1A_14
rpcdebugCtrlPmaStreamUpdateGetPut_v1A_14(void)8484 vmiopd_mdesc_t *rpcdebugCtrlPmaStreamUpdateGetPut_v1A_14(void)
8485 {
8486 return &vmiopd_mdesc_t_rpc_ctrl_pma_stream_update_get_put_v1A_14;
8487 }
8488 #endif
8489
8490 #ifndef SKIP_PRINT_rpc_ctrl_fb_get_info_v2_v25_0A
rpcdebugCtrlFbGetInfoV2_v25_0A(void)8491 vmiopd_mdesc_t *rpcdebugCtrlFbGetInfoV2_v25_0A(void)
8492 {
8493 return &vmiopd_mdesc_t_rpc_ctrl_fb_get_info_v2_v25_0A;
8494 }
8495 #endif
8496
8497 #ifndef SKIP_PRINT_rpc_ctrl_fifo_set_channel_properties_v1A_16
rpcdebugCtrlFifoSetChannelProperties_v1A_16(void)8498 vmiopd_mdesc_t *rpcdebugCtrlFifoSetChannelProperties_v1A_16(void)
8499 {
8500 return &vmiopd_mdesc_t_rpc_ctrl_fifo_set_channel_properties_v1A_16;
8501 }
8502 #endif
8503
8504 #ifndef SKIP_PRINT_rpc_ctrl_gpu_evict_ctx_v1A_1C
rpcdebugCtrlGpuEvictCtx_v1A_1C(void)8505 vmiopd_mdesc_t *rpcdebugCtrlGpuEvictCtx_v1A_1C(void)
8506 {
8507 return &vmiopd_mdesc_t_rpc_ctrl_gpu_evict_ctx_v1A_1C;
8508 }
8509 #endif
8510
8511 #ifndef SKIP_PRINT_rpc_ctrl_fb_get_fs_info_v24_00
rpcdebugCtrlFbGetFsInfo_v24_00(void)8512 vmiopd_mdesc_t *rpcdebugCtrlFbGetFsInfo_v24_00(void)
8513 {
8514 return &vmiopd_mdesc_t_rpc_ctrl_fb_get_fs_info_v24_00;
8515 }
8516 #endif
8517
8518 #ifndef SKIP_PRINT_rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D
rpcdebugCtrlGrmgrGetGrFsInfo_v1A_1D(void)8519 vmiopd_mdesc_t *rpcdebugCtrlGrmgrGetGrFsInfo_v1A_1D(void)
8520 {
8521 return &vmiopd_mdesc_t_rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D;
8522 }
8523 #endif
8524
8525 #ifndef SKIP_PRINT_rpc_ctrl_stop_channel_v1A_1E
rpcdebugCtrlStopChannel_v1A_1E(void)8526 vmiopd_mdesc_t *rpcdebugCtrlStopChannel_v1A_1E(void)
8527 {
8528 return &vmiopd_mdesc_t_rpc_ctrl_stop_channel_v1A_1E;
8529 }
8530 #endif
8531
8532 #ifndef SKIP_PRINT_rpc_ctrl_gr_pc_sampling_mode_v1A_1F
rpcdebugCtrlGrPcSamplingMode_v1A_1F(void)8533 vmiopd_mdesc_t *rpcdebugCtrlGrPcSamplingMode_v1A_1F(void)
8534 {
8535 return &vmiopd_mdesc_t_rpc_ctrl_gr_pc_sampling_mode_v1A_1F;
8536 }
8537 #endif
8538
8539 #ifndef SKIP_PRINT_rpc_ctrl_perf_rated_tdp_get_status_v1A_1F
rpcdebugCtrlPerfRatedTdpGetStatus_v1A_1F(void)8540 vmiopd_mdesc_t *rpcdebugCtrlPerfRatedTdpGetStatus_v1A_1F(void)
8541 {
8542 return &vmiopd_mdesc_t_rpc_ctrl_perf_rated_tdp_get_status_v1A_1F;
8543 }
8544 #endif
8545
8546 #ifndef SKIP_PRINT_rpc_ctrl_perf_rated_tdp_set_control_v1A_1F
rpcdebugCtrlPerfRatedTdpSetControl_v1A_1F(void)8547 vmiopd_mdesc_t *rpcdebugCtrlPerfRatedTdpSetControl_v1A_1F(void)
8548 {
8549 return &vmiopd_mdesc_t_rpc_ctrl_perf_rated_tdp_set_control_v1A_1F;
8550 }
8551 #endif
8552
8553 #ifndef SKIP_PRINT_rpc_ctrl_timer_set_gr_tick_freq_v1A_1F
rpcdebugCtrlTimerSetGrTickFreq_v1A_1F(void)8554 vmiopd_mdesc_t *rpcdebugCtrlTimerSetGrTickFreq_v1A_1F(void)
8555 {
8556 return &vmiopd_mdesc_t_rpc_ctrl_timer_set_gr_tick_freq_v1A_1F;
8557 }
8558 #endif
8559
8560 #ifndef SKIP_PRINT_rpc_ctrl_free_pma_stream_v1A_1F
rpcdebugCtrlFreePmaStream_v1A_1F(void)8561 vmiopd_mdesc_t *rpcdebugCtrlFreePmaStream_v1A_1F(void)
8562 {
8563 return &vmiopd_mdesc_t_rpc_ctrl_free_pma_stream_v1A_1F;
8564 }
8565 #endif
8566
8567 #ifndef SKIP_PRINT_rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23
rpcdebugCtrlFifoSetupVfZombieSubctxPdb_v1A_23(void)8568 vmiopd_mdesc_t *rpcdebugCtrlFifoSetupVfZombieSubctxPdb_v1A_23(void)
8569 {
8570 return &vmiopd_mdesc_t_rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23;
8571 }
8572 #endif
8573
8574 #ifndef SKIP_PRINT_rpc_ctrl_dbg_set_single_sm_single_step_v1C_02
rpcdebugCtrlDbgSetSingleSmSingleStep_v1C_02(void)8575 vmiopd_mdesc_t *rpcdebugCtrlDbgSetSingleSmSingleStep_v1C_02(void)
8576 {
8577 return &vmiopd_mdesc_t_rpc_ctrl_dbg_set_single_sm_single_step_v1C_02;
8578 }
8579 #endif
8580
8581 #ifndef SKIP_PRINT_rpc_ctrl_gr_get_tpc_partition_mode_v1C_04
rpcdebugCtrlGrGetTpcPartitionMode_v1C_04(void)8582 vmiopd_mdesc_t *rpcdebugCtrlGrGetTpcPartitionMode_v1C_04(void)
8583 {
8584 return &vmiopd_mdesc_t_rpc_ctrl_gr_get_tpc_partition_mode_v1C_04;
8585 }
8586 #endif
8587
8588 #ifndef SKIP_PRINT_rpc_ctrl_gr_set_tpc_partition_mode_v1C_04
rpcdebugCtrlGrSetTpcPartitionMode_v1C_04(void)8589 vmiopd_mdesc_t *rpcdebugCtrlGrSetTpcPartitionMode_v1C_04(void)
8590 {
8591 return &vmiopd_mdesc_t_rpc_ctrl_gr_set_tpc_partition_mode_v1C_04;
8592 }
8593 #endif
8594
8595 #ifndef SKIP_PRINT_rpc_ctrl_internal_promote_fault_method_buffers_v1E_07
rpcdebugCtrlInternalPromoteFaultMethodBuffers_v1E_07(void)8596 vmiopd_mdesc_t *rpcdebugCtrlInternalPromoteFaultMethodBuffers_v1E_07(void)
8597 {
8598 return &vmiopd_mdesc_t_rpc_ctrl_internal_promote_fault_method_buffers_v1E_07;
8599 }
8600 #endif
8601
8602 #ifndef SKIP_PRINT_rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05
rpcdebugCtrlInternalMemsysSetZbcReferenced_v1F_05(void)8603 vmiopd_mdesc_t *rpcdebugCtrlInternalMemsysSetZbcReferenced_v1F_05(void)
8604 {
8605 return &vmiopd_mdesc_t_rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05;
8606 }
8607 #endif
8608
8609 #ifndef SKIP_PRINT_rpc_ctrl_fabric_memory_describe_v1E_0C
rpcdebugCtrlFabricMemoryDescribe_v1E_0C(void)8610 vmiopd_mdesc_t *rpcdebugCtrlFabricMemoryDescribe_v1E_0C(void)
8611 {
8612 return &vmiopd_mdesc_t_rpc_ctrl_fabric_memory_describe_v1E_0C;
8613 }
8614 #endif
8615
8616 #ifndef SKIP_PRINT_rpc_ctrl_fabric_mem_stats_v1E_0C
rpcdebugCtrlFabricMemStats_v1E_0C(void)8617 vmiopd_mdesc_t *rpcdebugCtrlFabricMemStats_v1E_0C(void)
8618 {
8619 return &vmiopd_mdesc_t_rpc_ctrl_fabric_mem_stats_v1E_0C;
8620 }
8621 #endif
8622
8623 #ifndef SKIP_PRINT_rpc_ctrl_bus_set_p2p_mapping_v21_03
rpcdebugCtrlBusSetP2pMapping_v21_03(void)8624 vmiopd_mdesc_t *rpcdebugCtrlBusSetP2pMapping_v21_03(void)
8625 {
8626 return &vmiopd_mdesc_t_rpc_ctrl_bus_set_p2p_mapping_v21_03;
8627 }
8628 #endif
8629
8630 #ifndef SKIP_PRINT_rpc_ctrl_bus_unset_p2p_mapping_v21_03
rpcdebugCtrlBusUnsetP2pMapping_v21_03(void)8631 vmiopd_mdesc_t *rpcdebugCtrlBusUnsetP2pMapping_v21_03(void)
8632 {
8633 return &vmiopd_mdesc_t_rpc_ctrl_bus_unset_p2p_mapping_v21_03;
8634 }
8635 #endif
8636
8637 #ifndef SKIP_PRINT_rpc_ctrl_gpu_get_info_v2_v25_11
rpcdebugCtrlGpuGetInfoV2_v25_11(void)8638 vmiopd_mdesc_t *rpcdebugCtrlGpuGetInfoV2_v25_11(void)
8639 {
8640 return &vmiopd_mdesc_t_rpc_ctrl_gpu_get_info_v2_v25_11;
8641 }
8642 #endif
8643
8644 #ifndef SKIP_PRINT_rpc_ctrl_internal_quiesce_pma_channel_v1C_08
rpcdebugCtrlInternalQuiescePmaChannel_v1C_08(void)8645 vmiopd_mdesc_t *rpcdebugCtrlInternalQuiescePmaChannel_v1C_08(void)
8646 {
8647 return &vmiopd_mdesc_t_rpc_ctrl_internal_quiesce_pma_channel_v1C_08;
8648 }
8649 #endif
8650
8651 #ifndef SKIP_PRINT_rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C
rpcdebugCtrlInternalSriovPromotePmaStream_v1C_0C(void)8652 vmiopd_mdesc_t *rpcdebugCtrlInternalSriovPromotePmaStream_v1C_0C(void)
8653 {
8654 return &vmiopd_mdesc_t_rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C;
8655 }
8656 #endif
8657
8658 #ifndef SKIP_PRINT_rpc_ctrl_exec_partitions_create_v24_05
rpcdebugCtrlExecPartitionsCreate_v24_05(void)8659 vmiopd_mdesc_t *rpcdebugCtrlExecPartitionsCreate_v24_05(void)
8660 {
8661 return &vmiopd_mdesc_t_rpc_ctrl_exec_partitions_create_v24_05;
8662 }
8663 #endif
8664
8665 #ifndef SKIP_PRINT_rpc_ctrl_fla_setup_instance_mem_block_v21_05
rpcdebugCtrlFlaSetupInstanceMemBlock_v21_05(void)8666 vmiopd_mdesc_t *rpcdebugCtrlFlaSetupInstanceMemBlock_v21_05(void)
8667 {
8668 return &vmiopd_mdesc_t_rpc_ctrl_fla_setup_instance_mem_block_v21_05;
8669 }
8670 #endif
8671
8672 #ifndef SKIP_PRINT_rpc_ctrl_get_total_hs_credits_v21_08
rpcdebugCtrlGetTotalHsCredits_v21_08(void)8673 vmiopd_mdesc_t *rpcdebugCtrlGetTotalHsCredits_v21_08(void)
8674 {
8675 return &vmiopd_mdesc_t_rpc_ctrl_get_total_hs_credits_v21_08;
8676 }
8677 #endif
8678
8679 #ifndef SKIP_PRINT_rpc_ctrl_get_hs_credits_v21_08
rpcdebugCtrlGetHsCredits_v21_08(void)8680 vmiopd_mdesc_t *rpcdebugCtrlGetHsCredits_v21_08(void)
8681 {
8682 return &vmiopd_mdesc_t_rpc_ctrl_get_hs_credits_v21_08;
8683 }
8684 #endif
8685
8686 #ifndef SKIP_PRINT_rpc_ctrl_set_hs_credits_v21_08
rpcdebugCtrlSetHsCredits_v21_08(void)8687 vmiopd_mdesc_t *rpcdebugCtrlSetHsCredits_v21_08(void)
8688 {
8689 return &vmiopd_mdesc_t_rpc_ctrl_set_hs_credits_v21_08;
8690 }
8691 #endif
8692
8693 #ifndef SKIP_PRINT_rpc_ctrl_pm_area_pc_sampler_v21_0B
rpcdebugCtrlPmAreaPcSampler_v21_0B(void)8694 vmiopd_mdesc_t *rpcdebugCtrlPmAreaPcSampler_v21_0B(void)
8695 {
8696 return &vmiopd_mdesc_t_rpc_ctrl_pm_area_pc_sampler_v21_0B;
8697 }
8698 #endif
8699
8700 #ifndef SKIP_PRINT_rpc_ctrl_exec_partitions_delete_v1F_0A
rpcdebugCtrlExecPartitionsDelete_v1F_0A(void)8701 vmiopd_mdesc_t *rpcdebugCtrlExecPartitionsDelete_v1F_0A(void)
8702 {
8703 return &vmiopd_mdesc_t_rpc_ctrl_exec_partitions_delete_v1F_0A;
8704 }
8705 #endif
8706
8707 #ifndef SKIP_PRINT_rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A
rpcdebugCtrlGpfifoGetWorkSubmitToken_v1F_0A(void)8708 vmiopd_mdesc_t *rpcdebugCtrlGpfifoGetWorkSubmitToken_v1F_0A(void)
8709 {
8710 return &vmiopd_mdesc_t_rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A;
8711 }
8712 #endif
8713
8714 #ifndef SKIP_PRINT_rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A
rpcdebugCtrlGpfifoSetWorkSubmitTokenNotifIndex_v1F_0A(void)8715 vmiopd_mdesc_t *rpcdebugCtrlGpfifoSetWorkSubmitTokenNotifIndex_v1F_0A(void)
8716 {
8717 return &vmiopd_mdesc_t_rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A;
8718 }
8719 #endif
8720
8721 #ifndef SKIP_PRINT_rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D
rpcdebugCtrlMasterGetVirtualFunctionErrorContIntrMask_v1F_0D(void)8722 vmiopd_mdesc_t *rpcdebugCtrlMasterGetVirtualFunctionErrorContIntrMask_v1F_0D(void)
8723 {
8724 return &vmiopd_mdesc_t_rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D;
8725 }
8726 #endif
8727
8728 #ifndef SKIP_PRINT_rpc_save_hibernation_data_v1E_0E
rpcdebugSaveHibernationData_v1E_0E(void)8729 vmiopd_mdesc_t *rpcdebugSaveHibernationData_v1E_0E(void)
8730 {
8731 return &vmiopd_mdesc_t_rpc_save_hibernation_data_v1E_0E;
8732 }
8733 #endif
8734
8735 #ifndef SKIP_PRINT_rpc_restore_hibernation_data_v1E_0E
rpcdebugRestoreHibernationData_v1E_0E(void)8736 vmiopd_mdesc_t *rpcdebugRestoreHibernationData_v1E_0E(void)
8737 {
8738 return &vmiopd_mdesc_t_rpc_restore_hibernation_data_v1E_0E;
8739 }
8740 #endif
8741
8742 #ifndef SKIP_PRINT_rpc_ctrl_get_mmu_debug_mode_v1E_06
rpcdebugCtrlGetMmuDebugMode_v1E_06(void)8743 vmiopd_mdesc_t *rpcdebugCtrlGetMmuDebugMode_v1E_06(void)
8744 {
8745 return &vmiopd_mdesc_t_rpc_ctrl_get_mmu_debug_mode_v1E_06;
8746 }
8747 #endif
8748
8749 #ifndef SKIP_PRINT_rpc_disable_channels_v1E_0B
rpcdebugDisableChannels_v1E_0B(void)8750 vmiopd_mdesc_t *rpcdebugDisableChannels_v1E_0B(void)
8751 {
8752 return &vmiopd_mdesc_t_rpc_disable_channels_v1E_0B;
8753 }
8754 #endif
8755
8756 #ifndef SKIP_PRINT_rpc_ctrl_gpu_migratable_ops_v21_07
rpcdebugCtrlGpuMigratableOps_v21_07(void)8757 vmiopd_mdesc_t *rpcdebugCtrlGpuMigratableOps_v21_07(void)
8758 {
8759 return &vmiopd_mdesc_t_rpc_ctrl_gpu_migratable_ops_v21_07;
8760 }
8761 #endif
8762
8763 #ifndef SKIP_PRINT_rpc_invalidate_tlb_v23_03
rpcdebugInvalidateTlb_v23_03(void)8764 vmiopd_mdesc_t *rpcdebugInvalidateTlb_v23_03(void)
8765 {
8766 return &vmiopd_mdesc_t_rpc_invalidate_tlb_v23_03;
8767 }
8768 #endif
8769
8770 #ifndef SKIP_PRINT_rpc_ecc_notifier_write_ack_v23_05
rpcdebugEccNotifierWriteAck_v23_05(void)8771 vmiopd_mdesc_t *rpcdebugEccNotifierWriteAck_v23_05(void)
8772 {
8773 return &vmiopd_mdesc_t_rpc_ecc_notifier_write_ack_v23_05;
8774 }
8775 #endif
8776
8777 #ifndef SKIP_PRINT_rpc_get_brand_caps_v25_12
rpcdebugGetBrandCaps_v25_12(void)8778 vmiopd_mdesc_t *rpcdebugGetBrandCaps_v25_12(void)
8779 {
8780 return &vmiopd_mdesc_t_rpc_get_brand_caps_v25_12;
8781 }
8782 #endif
8783
8784 #ifndef SKIP_PRINT_rpc_gsp_set_system_info_v17_00
rpcdebugGspSetSystemInfo_v17_00(void)8785 vmiopd_mdesc_t *rpcdebugGspSetSystemInfo_v17_00(void)
8786 {
8787 return &vmiopd_mdesc_t_rpc_gsp_set_system_info_v17_00;
8788 }
8789 #endif
8790
8791 #ifndef SKIP_PRINT_rpc_set_registry_v17_00
rpcdebugSetRegistry_v17_00(void)8792 vmiopd_mdesc_t *rpcdebugSetRegistry_v17_00(void)
8793 {
8794 return &vmiopd_mdesc_t_rpc_set_registry_v17_00;
8795 }
8796 #endif
8797
8798 #ifndef SKIP_PRINT_rpc_gsp_rm_alloc_v03_00
rpcdebugGspRmAlloc_v03_00(void)8799 vmiopd_mdesc_t *rpcdebugGspRmAlloc_v03_00(void)
8800 {
8801 return &vmiopd_mdesc_t_rpc_gsp_rm_alloc_v03_00;
8802 }
8803 #endif
8804
8805 #ifndef SKIP_PRINT_rpc_gsp_rm_control_v03_00
rpcdebugGspRmControl_v03_00(void)8806 vmiopd_mdesc_t *rpcdebugGspRmControl_v03_00(void)
8807 {
8808 return &vmiopd_mdesc_t_rpc_gsp_rm_control_v03_00;
8809 }
8810 #endif
8811
8812 #ifndef SKIP_PRINT_rpc_dump_protobuf_component_v18_12
rpcdebugDumpProtobufComponent_v18_12(void)8813 vmiopd_mdesc_t *rpcdebugDumpProtobufComponent_v18_12(void)
8814 {
8815 return &vmiopd_mdesc_t_rpc_dump_protobuf_component_v18_12;
8816 }
8817 #endif
8818
8819 #ifndef SKIP_PRINT_rpc_run_cpu_sequencer_v17_00
rpcdebugRunCpuSequencer_v17_00(void)8820 vmiopd_mdesc_t *rpcdebugRunCpuSequencer_v17_00(void)
8821 {
8822 return &vmiopd_mdesc_t_rpc_run_cpu_sequencer_v17_00;
8823 }
8824 #endif
8825
8826 #ifndef SKIP_PRINT_rpc_post_event_v17_00
rpcdebugPostEvent_v17_00(void)8827 vmiopd_mdesc_t *rpcdebugPostEvent_v17_00(void)
8828 {
8829 return &vmiopd_mdesc_t_rpc_post_event_v17_00;
8830 }
8831 #endif
8832
8833 #ifndef SKIP_PRINT_rpc_rc_triggered_v17_02
rpcdebugRcTriggered_v17_02(void)8834 vmiopd_mdesc_t *rpcdebugRcTriggered_v17_02(void)
8835 {
8836 return &vmiopd_mdesc_t_rpc_rc_triggered_v17_02;
8837 }
8838 #endif
8839
8840 #ifndef SKIP_PRINT_rpc_os_error_log_v17_00
rpcdebugOsErrorLog_v17_00(void)8841 vmiopd_mdesc_t *rpcdebugOsErrorLog_v17_00(void)
8842 {
8843 return &vmiopd_mdesc_t_rpc_os_error_log_v17_00;
8844 }
8845 #endif
8846
8847 #ifndef SKIP_PRINT_rpc_rg_line_intr_v17_00
rpcdebugRgLineIntr_v17_00(void)8848 vmiopd_mdesc_t *rpcdebugRgLineIntr_v17_00(void)
8849 {
8850 return &vmiopd_mdesc_t_rpc_rg_line_intr_v17_00;
8851 }
8852 #endif
8853
8854 #ifndef SKIP_PRINT_rpc_display_modeset_v01_00
rpcdebugDisplayModeset_v01_00(void)8855 vmiopd_mdesc_t *rpcdebugDisplayModeset_v01_00(void)
8856 {
8857 return &vmiopd_mdesc_t_rpc_display_modeset_v01_00;
8858 }
8859 #endif
8860
8861 #ifndef SKIP_PRINT_rpc_gpuacct_perfmon_util_samples_v1F_0E
rpcdebugGpuacctPerfmonUtilSamples_v1F_0E(void)8862 vmiopd_mdesc_t *rpcdebugGpuacctPerfmonUtilSamples_v1F_0E(void)
8863 {
8864 return &vmiopd_mdesc_t_rpc_gpuacct_perfmon_util_samples_v1F_0E;
8865 }
8866 #endif
8867
8868 #ifndef SKIP_PRINT_rpc_vgpu_gsp_plugin_triggered_v17_00
rpcdebugVgpuGspPluginTriggered_v17_00(void)8869 vmiopd_mdesc_t *rpcdebugVgpuGspPluginTriggered_v17_00(void)
8870 {
8871 return &vmiopd_mdesc_t_rpc_vgpu_gsp_plugin_triggered_v17_00;
8872 }
8873 #endif
8874
8875 #ifndef SKIP_PRINT_rpc_vgpu_config_event_v17_00
rpcdebugVgpuConfigEvent_v17_00(void)8876 vmiopd_mdesc_t *rpcdebugVgpuConfigEvent_v17_00(void)
8877 {
8878 return &vmiopd_mdesc_t_rpc_vgpu_config_event_v17_00;
8879 }
8880 #endif
8881
8882 #ifndef SKIP_PRINT_rpc_dce_rm_init_v01_00
rpcdebugDceRmInit_v01_00(void)8883 vmiopd_mdesc_t *rpcdebugDceRmInit_v01_00(void)
8884 {
8885 return &vmiopd_mdesc_t_rpc_dce_rm_init_v01_00;
8886 }
8887 #endif
8888
8889 #ifndef SKIP_PRINT_rpc_sim_read_v1E_01
rpcdebugSimRead_v1E_01(void)8890 vmiopd_mdesc_t *rpcdebugSimRead_v1E_01(void)
8891 {
8892 return &vmiopd_mdesc_t_rpc_sim_read_v1E_01;
8893 }
8894 #endif
8895
8896 #ifndef SKIP_PRINT_rpc_sim_write_v1E_01
rpcdebugSimWrite_v1E_01(void)8897 vmiopd_mdesc_t *rpcdebugSimWrite_v1E_01(void)
8898 {
8899 return &vmiopd_mdesc_t_rpc_sim_write_v1E_01;
8900 }
8901 #endif
8902
8903 #ifndef SKIP_PRINT_rpc_ucode_libos_print_v1E_08
rpcdebugUcodeLibosPrint_v1E_08(void)8904 vmiopd_mdesc_t *rpcdebugUcodeLibosPrint_v1E_08(void)
8905 {
8906 return &vmiopd_mdesc_t_rpc_ucode_libos_print_v1E_08;
8907 }
8908 #endif
8909
8910 #ifndef SKIP_PRINT_rpc_init_done_v17_00
rpcdebugInitDone_v17_00(void)8911 vmiopd_mdesc_t *rpcdebugInitDone_v17_00(void)
8912 {
8913 return &vmiopd_mdesc_t_rpc_init_done_v17_00;
8914 }
8915 #endif
8916
8917 #ifndef SKIP_PRINT_rpc_semaphore_schedule_callback_v17_00
rpcdebugSemaphoreScheduleCallback_v17_00(void)8918 vmiopd_mdesc_t *rpcdebugSemaphoreScheduleCallback_v17_00(void)
8919 {
8920 return &vmiopd_mdesc_t_rpc_semaphore_schedule_callback_v17_00;
8921 }
8922 #endif
8923
8924 #ifndef SKIP_PRINT_rpc_timed_semaphore_release_v01_00
rpcdebugTimedSemaphoreRelease_v01_00(void)8925 vmiopd_mdesc_t *rpcdebugTimedSemaphoreRelease_v01_00(void)
8926 {
8927 return &vmiopd_mdesc_t_rpc_timed_semaphore_release_v01_00;
8928 }
8929 #endif
8930
8931 #ifndef SKIP_PRINT_rpc_perf_gpu_boost_sync_limits_callback_v17_00
rpcdebugPerfGpuBoostSyncLimitsCallback_v17_00(void)8932 vmiopd_mdesc_t *rpcdebugPerfGpuBoostSyncLimitsCallback_v17_00(void)
8933 {
8934 return &vmiopd_mdesc_t_rpc_perf_gpu_boost_sync_limits_callback_v17_00;
8935 }
8936 #endif
8937
8938 #ifndef SKIP_PRINT_rpc_perf_bridgeless_info_update_v17_00
rpcdebugPerfBridgelessInfoUpdate_v17_00(void)8939 vmiopd_mdesc_t *rpcdebugPerfBridgelessInfoUpdate_v17_00(void)
8940 {
8941 return &vmiopd_mdesc_t_rpc_perf_bridgeless_info_update_v17_00;
8942 }
8943 #endif
8944
8945 #ifndef SKIP_PRINT_rpc_nvlink_fault_up_v17_00
rpcdebugNvlinkFaultUp_v17_00(void)8946 vmiopd_mdesc_t *rpcdebugNvlinkFaultUp_v17_00(void)
8947 {
8948 return &vmiopd_mdesc_t_rpc_nvlink_fault_up_v17_00;
8949 }
8950 #endif
8951
8952 #ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_256_v17_00
rpcdebugNvlinkInbandReceivedData256_v17_00(void)8953 vmiopd_mdesc_t *rpcdebugNvlinkInbandReceivedData256_v17_00(void)
8954 {
8955 return &vmiopd_mdesc_t_rpc_nvlink_inband_received_data_256_v17_00;
8956 }
8957 #endif
8958
8959 #ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_512_v17_00
rpcdebugNvlinkInbandReceivedData512_v17_00(void)8960 vmiopd_mdesc_t *rpcdebugNvlinkInbandReceivedData512_v17_00(void)
8961 {
8962 return &vmiopd_mdesc_t_rpc_nvlink_inband_received_data_512_v17_00;
8963 }
8964 #endif
8965
8966 #ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_1024_v17_00
rpcdebugNvlinkInbandReceivedData1024_v17_00(void)8967 vmiopd_mdesc_t *rpcdebugNvlinkInbandReceivedData1024_v17_00(void)
8968 {
8969 return &vmiopd_mdesc_t_rpc_nvlink_inband_received_data_1024_v17_00;
8970 }
8971 #endif
8972
8973 #ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_2048_v17_00
rpcdebugNvlinkInbandReceivedData2048_v17_00(void)8974 vmiopd_mdesc_t *rpcdebugNvlinkInbandReceivedData2048_v17_00(void)
8975 {
8976 return &vmiopd_mdesc_t_rpc_nvlink_inband_received_data_2048_v17_00;
8977 }
8978 #endif
8979
8980 #ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_4096_v17_00
rpcdebugNvlinkInbandReceivedData4096_v17_00(void)8981 vmiopd_mdesc_t *rpcdebugNvlinkInbandReceivedData4096_v17_00(void)
8982 {
8983 return &vmiopd_mdesc_t_rpc_nvlink_inband_received_data_4096_v17_00;
8984 }
8985 #endif
8986
8987 #ifndef SKIP_PRINT_rpc_nvlink_is_gpu_degraded_v17_00
rpcdebugNvlinkIsGpuDegraded_v17_00(void)8988 vmiopd_mdesc_t *rpcdebugNvlinkIsGpuDegraded_v17_00(void)
8989 {
8990 return &vmiopd_mdesc_t_rpc_nvlink_is_gpu_degraded_v17_00;
8991 }
8992 #endif
8993
8994 #ifndef SKIP_PRINT_rpc_update_gsp_trace_v01_00
rpcdebugUpdateGspTrace_v01_00(void)8995 vmiopd_mdesc_t *rpcdebugUpdateGspTrace_v01_00(void)
8996 {
8997 return &vmiopd_mdesc_t_rpc_update_gsp_trace_v01_00;
8998 }
8999 #endif
9000
9001 #ifndef SKIP_PRINT_rpc_gsp_post_nocat_record_v01_00
rpcdebugGspPostNocatRecord_v01_00(void)9002 vmiopd_mdesc_t *rpcdebugGspPostNocatRecord_v01_00(void)
9003 {
9004 return &vmiopd_mdesc_t_rpc_gsp_post_nocat_record_v01_00;
9005 }
9006 #endif
9007
9008 #ifndef SKIP_PRINT_rpc_extdev_intr_service_v17_00
rpcdebugExtdevIntrService_v17_00(void)9009 vmiopd_mdesc_t *rpcdebugExtdevIntrService_v17_00(void)
9010 {
9011 return &vmiopd_mdesc_t_rpc_extdev_intr_service_v17_00;
9012 }
9013 #endif
9014
9015 #ifndef SKIP_PRINT_rpc_pfm_req_hndlr_state_sync_callback_v21_04
rpcdebugPfmReqHndlrStateSyncCallback_v21_04(void)9016 vmiopd_mdesc_t *rpcdebugPfmReqHndlrStateSyncCallback_v21_04(void)
9017 {
9018 return &vmiopd_mdesc_t_rpc_pfm_req_hndlr_state_sync_callback_v21_04;
9019 }
9020 #endif
9021
9022 #ifndef SKIP_PRINT_rpc_vgpu_gsp_mig_ci_config_v21_03
rpcdebugVgpuGspMigCiConfig_v21_03(void)9023 vmiopd_mdesc_t *rpcdebugVgpuGspMigCiConfig_v21_03(void)
9024 {
9025 return &vmiopd_mdesc_t_rpc_vgpu_gsp_mig_ci_config_v21_03;
9026 }
9027 #endif
9028
9029 #ifndef SKIP_PRINT_rpc_gsp_lockdown_notice_v17_00
rpcdebugGspLockdownNotice_v17_00(void)9030 vmiopd_mdesc_t *rpcdebugGspLockdownNotice_v17_00(void)
9031 {
9032 return &vmiopd_mdesc_t_rpc_gsp_lockdown_notice_v17_00;
9033 }
9034 #endif
9035
9036 #ifndef SKIP_PRINT_rpc_ctrl_gpu_query_ecc_status_v24_06
rpcdebugCtrlGpuQueryEccStatus_v24_06(void)9037 vmiopd_mdesc_t *rpcdebugCtrlGpuQueryEccStatus_v24_06(void)
9038 {
9039 return &vmiopd_mdesc_t_rpc_ctrl_gpu_query_ecc_status_v24_06;
9040 }
9041 #endif
9042
9043 #ifndef SKIP_PRINT_rpc_ctrl_dbg_get_mode_mmu_debug_v25_04
rpcdebugCtrlDbgGetModeMmuDebug_v25_04(void)9044 vmiopd_mdesc_t *rpcdebugCtrlDbgGetModeMmuDebug_v25_04(void)
9045 {
9046 return &vmiopd_mdesc_t_rpc_ctrl_dbg_get_mode_mmu_debug_v25_04;
9047 }
9048 #endif
9049
9050 #ifndef SKIP_PRINT_rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09
rpcdebugCtrlCmdInternalGpuStartFabricProbe_v25_09(void)9051 vmiopd_mdesc_t *rpcdebugCtrlCmdInternalGpuStartFabricProbe_v25_09(void)
9052 {
9053 return &vmiopd_mdesc_t_rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09;
9054 }
9055 #endif
9056
9057 #ifndef SKIP_PRINT_rpc_ctrl_nvlink_get_inband_received_data_v25_0C
rpcdebugCtrlNvlinkGetInbandReceivedData_v25_0C(void)9058 vmiopd_mdesc_t *rpcdebugCtrlNvlinkGetInbandReceivedData_v25_0C(void)
9059 {
9060 return &vmiopd_mdesc_t_rpc_ctrl_nvlink_get_inband_received_data_v25_0C;
9061 }
9062 #endif
9063
9064
9065 #endif
9066
9067 #ifdef RPC_GENERIC_UNION
9068 // This is a generic union, that will be used for the communication between the vmioplugin & guest RM.
9069 typedef union rpc_generic_union {
9070 rpc_set_guest_system_info_v03_00 set_guest_system_info_v03_00;
9071 rpc_set_guest_system_info_v set_guest_system_info_v;
9072 rpc_set_guest_system_info_ext_v25_1B set_guest_system_info_ext_v25_1B;
9073 rpc_set_guest_system_info_ext_v15_02 set_guest_system_info_ext_v15_02;
9074 rpc_set_guest_system_info_ext_v set_guest_system_info_ext_v;
9075 rpc_alloc_root_v07_00 alloc_root_v07_00;
9076 rpc_alloc_root_v alloc_root_v;
9077 rpc_alloc_memory_v13_01 alloc_memory_v13_01;
9078 rpc_alloc_memory_v alloc_memory_v;
9079 rpc_alloc_channel_dma_v1F_04 alloc_channel_dma_v1F_04;
9080 rpc_alloc_channel_dma_v alloc_channel_dma_v;
9081 rpc_alloc_object_v25_08 alloc_object_v25_08;
9082 rpc_alloc_object_v alloc_object_v;
9083 rpc_free_v03_00 free_v03_00;
9084 rpc_free_v free_v;
9085 rpc_log_v03_00 log_v03_00;
9086 rpc_log_v log_v;
9087 rpc_map_memory_dma_v03_00 map_memory_dma_v03_00;
9088 rpc_map_memory_dma_v map_memory_dma_v;
9089 rpc_unmap_memory_dma_v03_00 unmap_memory_dma_v03_00;
9090 rpc_unmap_memory_dma_v unmap_memory_dma_v;
9091 rpc_alloc_subdevice_v08_01 alloc_subdevice_v08_01;
9092 rpc_alloc_subdevice_v alloc_subdevice_v;
9093 rpc_dup_object_v03_00 dup_object_v03_00;
9094 rpc_dup_object_v dup_object_v;
9095 rpc_idle_channels_v03_00 idle_channels_v03_00;
9096 rpc_idle_channels_v idle_channels_v;
9097 rpc_alloc_event_v03_00 alloc_event_v03_00;
9098 rpc_alloc_event_v alloc_event_v;
9099 rpc_rm_api_control_v25_19 rm_api_control_v25_19;
9100 rpc_rm_api_control_v25_0F rm_api_control_v25_0F;
9101 rpc_rm_api_control_v25_16 rm_api_control_v25_16;
9102 rpc_rm_api_control_v25_10 rm_api_control_v25_10;
9103 rpc_rm_api_control_v25_15 rm_api_control_v25_15;
9104 rpc_rm_api_control_v25_0D rm_api_control_v25_0D;
9105 rpc_rm_api_control_v25_17 rm_api_control_v25_17;
9106 rpc_rm_api_control_v25_18 rm_api_control_v25_18;
9107 rpc_rm_api_control_v25_1A rm_api_control_v25_1A;
9108 rpc_rm_api_control_v25_14 rm_api_control_v25_14;
9109 rpc_rm_api_control_v rm_api_control_v;
9110 rpc_alloc_share_device_v03_00 alloc_share_device_v03_00;
9111 rpc_alloc_share_device_v alloc_share_device_v;
9112 rpc_get_engine_utilization_v1F_0E get_engine_utilization_v1F_0E;
9113 rpc_get_engine_utilization_v get_engine_utilization_v;
9114 rpc_perf_get_level_info_v03_00 perf_get_level_info_v03_00;
9115 rpc_perf_get_level_info_v perf_get_level_info_v;
9116 rpc_set_surface_properties_v07_07 set_surface_properties_v07_07;
9117 rpc_set_surface_properties_v set_surface_properties_v;
9118 rpc_cleanup_surface_v03_00 cleanup_surface_v03_00;
9119 rpc_cleanup_surface_v cleanup_surface_v;
9120 rpc_unloading_guest_driver_v1F_07 unloading_guest_driver_v1F_07;
9121 rpc_unloading_guest_driver_v unloading_guest_driver_v;
9122 rpc_gpu_exec_reg_ops_v12_01 gpu_exec_reg_ops_v12_01;
9123 rpc_gpu_exec_reg_ops_v gpu_exec_reg_ops_v;
9124 rpc_get_static_data_v25_0E get_static_data_v25_0E;
9125 rpc_get_static_data_v get_static_data_v;
9126 rpc_get_consolidated_gr_static_info_v1B_04 get_consolidated_gr_static_info_v1B_04;
9127 rpc_get_consolidated_gr_static_info_v get_consolidated_gr_static_info_v;
9128 rpc_set_page_directory_v1E_05 set_page_directory_v1E_05;
9129 rpc_set_page_directory_v set_page_directory_v;
9130 rpc_unset_page_directory_v1E_05 unset_page_directory_v1E_05;
9131 rpc_unset_page_directory_v unset_page_directory_v;
9132 rpc_get_gsp_static_info_v14_00 get_gsp_static_info_v14_00;
9133 rpc_get_gsp_static_info_v get_gsp_static_info_v;
9134 rpc_update_bar_pde_v15_00 update_bar_pde_v15_00;
9135 rpc_update_bar_pde_v update_bar_pde_v;
9136 rpc_get_encoder_capacity_v07_00 get_encoder_capacity_v07_00;
9137 rpc_get_encoder_capacity_v get_encoder_capacity_v;
9138 rpc_vgpu_pf_reg_read32_v15_00 vgpu_pf_reg_read32_v15_00;
9139 rpc_vgpu_pf_reg_read32_v vgpu_pf_reg_read32_v;
9140 rpc_ctrl_set_vgpu_fb_usage_v1A_08 ctrl_set_vgpu_fb_usage_v1A_08;
9141 rpc_ctrl_set_vgpu_fb_usage_v ctrl_set_vgpu_fb_usage_v;
9142 rpc_ctrl_nvenc_sw_session_update_info_v1A_09 ctrl_nvenc_sw_session_update_info_v1A_09;
9143 rpc_ctrl_nvenc_sw_session_update_info_v ctrl_nvenc_sw_session_update_info_v;
9144 rpc_ctrl_reset_channel_v1A_09 ctrl_reset_channel_v1A_09;
9145 rpc_ctrl_reset_channel_v ctrl_reset_channel_v;
9146 rpc_ctrl_reset_isolated_channel_v1A_09 ctrl_reset_isolated_channel_v1A_09;
9147 rpc_ctrl_reset_isolated_channel_v ctrl_reset_isolated_channel_v;
9148 rpc_ctrl_gpu_handle_vf_pri_fault_v1A_09 ctrl_gpu_handle_vf_pri_fault_v1A_09;
9149 rpc_ctrl_gpu_handle_vf_pri_fault_v ctrl_gpu_handle_vf_pri_fault_v;
9150 rpc_ctrl_perf_boost_v1A_09 ctrl_perf_boost_v1A_09;
9151 rpc_ctrl_perf_boost_v ctrl_perf_boost_v;
9152 rpc_ctrl_get_zbc_clear_table_v1A_09 ctrl_get_zbc_clear_table_v1A_09;
9153 rpc_ctrl_get_zbc_clear_table_v ctrl_get_zbc_clear_table_v;
9154 rpc_ctrl_set_zbc_color_clear_v1A_09 ctrl_set_zbc_color_clear_v1A_09;
9155 rpc_ctrl_set_zbc_color_clear_v ctrl_set_zbc_color_clear_v;
9156 rpc_ctrl_set_zbc_depth_clear_v1A_09 ctrl_set_zbc_depth_clear_v1A_09;
9157 rpc_ctrl_set_zbc_depth_clear_v ctrl_set_zbc_depth_clear_v;
9158 rpc_ctrl_gpfifo_schedule_v1A_0A ctrl_gpfifo_schedule_v1A_0A;
9159 rpc_ctrl_gpfifo_schedule_v ctrl_gpfifo_schedule_v;
9160 rpc_ctrl_set_timeslice_v1A_0A ctrl_set_timeslice_v1A_0A;
9161 rpc_ctrl_set_timeslice_v ctrl_set_timeslice_v;
9162 rpc_ctrl_fifo_disable_channels_v1A_0A ctrl_fifo_disable_channels_v1A_0A;
9163 rpc_ctrl_fifo_disable_channels_v ctrl_fifo_disable_channels_v;
9164 rpc_ctrl_preempt_v1A_0A ctrl_preempt_v1A_0A;
9165 rpc_ctrl_preempt_v ctrl_preempt_v;
9166 rpc_ctrl_set_tsg_interleave_level_v1A_0A ctrl_set_tsg_interleave_level_v1A_0A;
9167 rpc_ctrl_set_tsg_interleave_level_v ctrl_set_tsg_interleave_level_v;
9168 rpc_ctrl_set_channel_interleave_level_v1A_0A ctrl_set_channel_interleave_level_v1A_0A;
9169 rpc_ctrl_set_channel_interleave_level_v ctrl_set_channel_interleave_level_v;
9170 rpc_ctrl_gr_ctxsw_preemption_bind_v1A_0E ctrl_gr_ctxsw_preemption_bind_v1A_0E;
9171 rpc_ctrl_gr_ctxsw_preemption_bind_v ctrl_gr_ctxsw_preemption_bind_v;
9172 rpc_ctrl_gr_set_ctxsw_preemption_mode_v1A_0E ctrl_gr_set_ctxsw_preemption_mode_v1A_0E;
9173 rpc_ctrl_gr_set_ctxsw_preemption_mode_v ctrl_gr_set_ctxsw_preemption_mode_v;
9174 rpc_ctrl_gr_ctxsw_zcull_bind_v1A_0E ctrl_gr_ctxsw_zcull_bind_v1A_0E;
9175 rpc_ctrl_gr_ctxsw_zcull_bind_v ctrl_gr_ctxsw_zcull_bind_v;
9176 rpc_ctrl_gpu_initialize_ctx_v1A_0E ctrl_gpu_initialize_ctx_v1A_0E;
9177 rpc_ctrl_gpu_initialize_ctx_v ctrl_gpu_initialize_ctx_v;
9178 rpc_ctrl_vaspace_copy_server_reserved_pdes_v1E_04 ctrl_vaspace_copy_server_reserved_pdes_v1E_04;
9179 rpc_ctrl_vaspace_copy_server_reserved_pdes_v ctrl_vaspace_copy_server_reserved_pdes_v;
9180 rpc_ctrl_mc_service_interrupts_v1A_0E ctrl_mc_service_interrupts_v1A_0E;
9181 rpc_ctrl_mc_service_interrupts_v ctrl_mc_service_interrupts_v;
9182 rpc_ctrl_get_p2p_caps_v2_v1F_0D ctrl_get_p2p_caps_v2_v1F_0D;
9183 rpc_ctrl_get_p2p_caps_v2_v ctrl_get_p2p_caps_v2_v;
9184 rpc_ctrl_subdevice_get_p2p_caps_v21_02 ctrl_subdevice_get_p2p_caps_v21_02;
9185 rpc_ctrl_subdevice_get_p2p_caps_v ctrl_subdevice_get_p2p_caps_v;
9186 rpc_ctrl_dbg_clear_all_sm_error_states_v1A_0C ctrl_dbg_clear_all_sm_error_states_v1A_0C;
9187 rpc_ctrl_dbg_clear_all_sm_error_states_v ctrl_dbg_clear_all_sm_error_states_v;
9188 rpc_ctrl_dbg_read_all_sm_error_states_v21_06 ctrl_dbg_read_all_sm_error_states_v21_06;
9189 rpc_ctrl_dbg_read_all_sm_error_states_v ctrl_dbg_read_all_sm_error_states_v;
9190 rpc_ctrl_dbg_set_exception_mask_v1A_0C ctrl_dbg_set_exception_mask_v1A_0C;
9191 rpc_ctrl_dbg_set_exception_mask_v ctrl_dbg_set_exception_mask_v;
9192 rpc_ctrl_gpu_promote_ctx_v1A_20 ctrl_gpu_promote_ctx_v1A_20;
9193 rpc_ctrl_gpu_promote_ctx_v ctrl_gpu_promote_ctx_v;
9194 rpc_ctrl_dbg_suspend_context_v1A_10 ctrl_dbg_suspend_context_v1A_10;
9195 rpc_ctrl_dbg_suspend_context_v ctrl_dbg_suspend_context_v;
9196 rpc_ctrl_dbg_resume_context_v1A_10 ctrl_dbg_resume_context_v1A_10;
9197 rpc_ctrl_dbg_resume_context_v ctrl_dbg_resume_context_v;
9198 rpc_ctrl_dbg_exec_reg_ops_v1A_10 ctrl_dbg_exec_reg_ops_v1A_10;
9199 rpc_ctrl_dbg_exec_reg_ops_v ctrl_dbg_exec_reg_ops_v;
9200 rpc_ctrl_dbg_set_mode_mmu_debug_v1A_10 ctrl_dbg_set_mode_mmu_debug_v1A_10;
9201 rpc_ctrl_dbg_set_mode_mmu_debug_v ctrl_dbg_set_mode_mmu_debug_v;
9202 rpc_ctrl_dbg_read_single_sm_error_state_v21_06 ctrl_dbg_read_single_sm_error_state_v21_06;
9203 rpc_ctrl_dbg_read_single_sm_error_state_v ctrl_dbg_read_single_sm_error_state_v;
9204 rpc_ctrl_dbg_clear_single_sm_error_state_v1A_10 ctrl_dbg_clear_single_sm_error_state_v1A_10;
9205 rpc_ctrl_dbg_clear_single_sm_error_state_v ctrl_dbg_clear_single_sm_error_state_v;
9206 rpc_ctrl_dbg_set_mode_errbar_debug_v1A_10 ctrl_dbg_set_mode_errbar_debug_v1A_10;
9207 rpc_ctrl_dbg_set_mode_errbar_debug_v ctrl_dbg_set_mode_errbar_debug_v;
9208 rpc_ctrl_dbg_set_next_stop_trigger_type_v1A_10 ctrl_dbg_set_next_stop_trigger_type_v1A_10;
9209 rpc_ctrl_dbg_set_next_stop_trigger_type_v ctrl_dbg_set_next_stop_trigger_type_v;
9210 rpc_ctrl_dma_set_default_vaspace_v1A_0E ctrl_dma_set_default_vaspace_v1A_0E;
9211 rpc_ctrl_dma_set_default_vaspace_v ctrl_dma_set_default_vaspace_v;
9212 rpc_ctrl_get_ce_pce_mask_v1A_0E ctrl_get_ce_pce_mask_v1A_0E;
9213 rpc_ctrl_get_ce_pce_mask_v ctrl_get_ce_pce_mask_v;
9214 rpc_ctrl_get_zbc_clear_table_entry_v1A_0E ctrl_get_zbc_clear_table_entry_v1A_0E;
9215 rpc_ctrl_get_zbc_clear_table_entry_v ctrl_get_zbc_clear_table_entry_v;
9216 rpc_ctrl_get_nvlink_peer_id_mask_v1A_0E ctrl_get_nvlink_peer_id_mask_v1A_0E;
9217 rpc_ctrl_get_nvlink_peer_id_mask_v ctrl_get_nvlink_peer_id_mask_v;
9218 rpc_ctrl_get_nvlink_status_v23_04 ctrl_get_nvlink_status_v23_04;
9219 rpc_ctrl_get_nvlink_status_v ctrl_get_nvlink_status_v;
9220 rpc_ctrl_get_p2p_caps_v1F_0D ctrl_get_p2p_caps_v1F_0D;
9221 rpc_ctrl_get_p2p_caps_v ctrl_get_p2p_caps_v;
9222 rpc_ctrl_get_p2p_caps_matrix_v1A_0E ctrl_get_p2p_caps_matrix_v1A_0E;
9223 rpc_ctrl_get_p2p_caps_matrix_v ctrl_get_p2p_caps_matrix_v;
9224 rpc_ctrl_reserve_pm_area_smpc_v1A_0F ctrl_reserve_pm_area_smpc_v1A_0F;
9225 rpc_ctrl_reserve_pm_area_smpc_v ctrl_reserve_pm_area_smpc_v;
9226 rpc_ctrl_reserve_hwpm_legacy_v1A_0F ctrl_reserve_hwpm_legacy_v1A_0F;
9227 rpc_ctrl_reserve_hwpm_legacy_v ctrl_reserve_hwpm_legacy_v;
9228 rpc_ctrl_b0cc_exec_reg_ops_v1A_0F ctrl_b0cc_exec_reg_ops_v1A_0F;
9229 rpc_ctrl_b0cc_exec_reg_ops_v ctrl_b0cc_exec_reg_ops_v;
9230 rpc_ctrl_bind_pm_resources_v1A_0F ctrl_bind_pm_resources_v1A_0F;
9231 rpc_ctrl_bind_pm_resources_v ctrl_bind_pm_resources_v;
9232 rpc_ctrl_alloc_pma_stream_v1A_14 ctrl_alloc_pma_stream_v1A_14;
9233 rpc_ctrl_alloc_pma_stream_v ctrl_alloc_pma_stream_v;
9234 rpc_ctrl_pma_stream_update_get_put_v1A_14 ctrl_pma_stream_update_get_put_v1A_14;
9235 rpc_ctrl_pma_stream_update_get_put_v ctrl_pma_stream_update_get_put_v;
9236 rpc_ctrl_fb_get_info_v2_v25_0A ctrl_fb_get_info_v2_v25_0A;
9237 rpc_ctrl_fb_get_info_v2_v ctrl_fb_get_info_v2_v;
9238 rpc_ctrl_fifo_set_channel_properties_v1A_16 ctrl_fifo_set_channel_properties_v1A_16;
9239 rpc_ctrl_fifo_set_channel_properties_v ctrl_fifo_set_channel_properties_v;
9240 rpc_ctrl_gpu_evict_ctx_v1A_1C ctrl_gpu_evict_ctx_v1A_1C;
9241 rpc_ctrl_gpu_evict_ctx_v ctrl_gpu_evict_ctx_v;
9242 rpc_ctrl_fb_get_fs_info_v24_00 ctrl_fb_get_fs_info_v24_00;
9243 rpc_ctrl_fb_get_fs_info_v ctrl_fb_get_fs_info_v;
9244 rpc_ctrl_grmgr_get_gr_fs_info_v1A_1D ctrl_grmgr_get_gr_fs_info_v1A_1D;
9245 rpc_ctrl_grmgr_get_gr_fs_info_v ctrl_grmgr_get_gr_fs_info_v;
9246 rpc_ctrl_stop_channel_v1A_1E ctrl_stop_channel_v1A_1E;
9247 rpc_ctrl_stop_channel_v ctrl_stop_channel_v;
9248 rpc_ctrl_gr_pc_sampling_mode_v1A_1F ctrl_gr_pc_sampling_mode_v1A_1F;
9249 rpc_ctrl_gr_pc_sampling_mode_v ctrl_gr_pc_sampling_mode_v;
9250 rpc_ctrl_perf_rated_tdp_get_status_v1A_1F ctrl_perf_rated_tdp_get_status_v1A_1F;
9251 rpc_ctrl_perf_rated_tdp_get_status_v ctrl_perf_rated_tdp_get_status_v;
9252 rpc_ctrl_perf_rated_tdp_set_control_v1A_1F ctrl_perf_rated_tdp_set_control_v1A_1F;
9253 rpc_ctrl_perf_rated_tdp_set_control_v ctrl_perf_rated_tdp_set_control_v;
9254 rpc_ctrl_timer_set_gr_tick_freq_v1A_1F ctrl_timer_set_gr_tick_freq_v1A_1F;
9255 rpc_ctrl_timer_set_gr_tick_freq_v ctrl_timer_set_gr_tick_freq_v;
9256 rpc_ctrl_free_pma_stream_v1A_1F ctrl_free_pma_stream_v1A_1F;
9257 rpc_ctrl_free_pma_stream_v ctrl_free_pma_stream_v;
9258 rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23 ctrl_fifo_setup_vf_zombie_subctx_pdb_v1A_23;
9259 rpc_ctrl_fifo_setup_vf_zombie_subctx_pdb_v ctrl_fifo_setup_vf_zombie_subctx_pdb_v;
9260 rpc_ctrl_dbg_set_single_sm_single_step_v1C_02 ctrl_dbg_set_single_sm_single_step_v1C_02;
9261 rpc_ctrl_dbg_set_single_sm_single_step_v ctrl_dbg_set_single_sm_single_step_v;
9262 rpc_ctrl_gr_get_tpc_partition_mode_v1C_04 ctrl_gr_get_tpc_partition_mode_v1C_04;
9263 rpc_ctrl_gr_get_tpc_partition_mode_v ctrl_gr_get_tpc_partition_mode_v;
9264 rpc_ctrl_gr_set_tpc_partition_mode_v1C_04 ctrl_gr_set_tpc_partition_mode_v1C_04;
9265 rpc_ctrl_gr_set_tpc_partition_mode_v ctrl_gr_set_tpc_partition_mode_v;
9266 rpc_ctrl_internal_promote_fault_method_buffers_v1E_07 ctrl_internal_promote_fault_method_buffers_v1E_07;
9267 rpc_ctrl_internal_promote_fault_method_buffers_v ctrl_internal_promote_fault_method_buffers_v;
9268 rpc_ctrl_internal_memsys_set_zbc_referenced_v1F_05 ctrl_internal_memsys_set_zbc_referenced_v1F_05;
9269 rpc_ctrl_internal_memsys_set_zbc_referenced_v ctrl_internal_memsys_set_zbc_referenced_v;
9270 rpc_ctrl_fabric_memory_describe_v1E_0C ctrl_fabric_memory_describe_v1E_0C;
9271 rpc_ctrl_fabric_memory_describe_v ctrl_fabric_memory_describe_v;
9272 rpc_ctrl_fabric_mem_stats_v1E_0C ctrl_fabric_mem_stats_v1E_0C;
9273 rpc_ctrl_fabric_mem_stats_v ctrl_fabric_mem_stats_v;
9274 rpc_ctrl_bus_set_p2p_mapping_v21_03 ctrl_bus_set_p2p_mapping_v21_03;
9275 rpc_ctrl_bus_set_p2p_mapping_v ctrl_bus_set_p2p_mapping_v;
9276 rpc_ctrl_bus_unset_p2p_mapping_v21_03 ctrl_bus_unset_p2p_mapping_v21_03;
9277 rpc_ctrl_bus_unset_p2p_mapping_v ctrl_bus_unset_p2p_mapping_v;
9278 rpc_ctrl_gpu_get_info_v2_v25_11 ctrl_gpu_get_info_v2_v25_11;
9279 rpc_ctrl_gpu_get_info_v2_v ctrl_gpu_get_info_v2_v;
9280 rpc_ctrl_internal_quiesce_pma_channel_v1C_08 ctrl_internal_quiesce_pma_channel_v1C_08;
9281 rpc_ctrl_internal_quiesce_pma_channel_v ctrl_internal_quiesce_pma_channel_v;
9282 rpc_ctrl_internal_sriov_promote_pma_stream_v1C_0C ctrl_internal_sriov_promote_pma_stream_v1C_0C;
9283 rpc_ctrl_internal_sriov_promote_pma_stream_v ctrl_internal_sriov_promote_pma_stream_v;
9284 rpc_ctrl_exec_partitions_create_v24_05 ctrl_exec_partitions_create_v24_05;
9285 rpc_ctrl_exec_partitions_create_v ctrl_exec_partitions_create_v;
9286 rpc_ctrl_fla_setup_instance_mem_block_v21_05 ctrl_fla_setup_instance_mem_block_v21_05;
9287 rpc_ctrl_fla_setup_instance_mem_block_v ctrl_fla_setup_instance_mem_block_v;
9288 rpc_ctrl_get_total_hs_credits_v21_08 ctrl_get_total_hs_credits_v21_08;
9289 rpc_ctrl_get_total_hs_credits_v ctrl_get_total_hs_credits_v;
9290 rpc_ctrl_get_hs_credits_v21_08 ctrl_get_hs_credits_v21_08;
9291 rpc_ctrl_get_hs_credits_v ctrl_get_hs_credits_v;
9292 rpc_ctrl_set_hs_credits_v21_08 ctrl_set_hs_credits_v21_08;
9293 rpc_ctrl_set_hs_credits_v ctrl_set_hs_credits_v;
9294 rpc_ctrl_pm_area_pc_sampler_v21_0B ctrl_pm_area_pc_sampler_v21_0B;
9295 rpc_ctrl_pm_area_pc_sampler_v ctrl_pm_area_pc_sampler_v;
9296 rpc_ctrl_exec_partitions_delete_v1F_0A ctrl_exec_partitions_delete_v1F_0A;
9297 rpc_ctrl_exec_partitions_delete_v ctrl_exec_partitions_delete_v;
9298 rpc_ctrl_gpfifo_get_work_submit_token_v1F_0A ctrl_gpfifo_get_work_submit_token_v1F_0A;
9299 rpc_ctrl_gpfifo_get_work_submit_token_v ctrl_gpfifo_get_work_submit_token_v;
9300 rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A ctrl_gpfifo_set_work_submit_token_notif_index_v1F_0A;
9301 rpc_ctrl_gpfifo_set_work_submit_token_notif_index_v ctrl_gpfifo_set_work_submit_token_notif_index_v;
9302 rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D ctrl_master_get_virtual_function_error_cont_intr_mask_v1F_0D;
9303 rpc_ctrl_master_get_virtual_function_error_cont_intr_mask_v ctrl_master_get_virtual_function_error_cont_intr_mask_v;
9304 rpc_save_hibernation_data_v1E_0E save_hibernation_data_v1E_0E;
9305 rpc_save_hibernation_data_v save_hibernation_data_v;
9306 rpc_restore_hibernation_data_v1E_0E restore_hibernation_data_v1E_0E;
9307 rpc_restore_hibernation_data_v restore_hibernation_data_v;
9308 rpc_ctrl_get_mmu_debug_mode_v1E_06 ctrl_get_mmu_debug_mode_v1E_06;
9309 rpc_ctrl_get_mmu_debug_mode_v ctrl_get_mmu_debug_mode_v;
9310 rpc_disable_channels_v1E_0B disable_channels_v1E_0B;
9311 rpc_disable_channels_v disable_channels_v;
9312 rpc_ctrl_gpu_migratable_ops_v21_07 ctrl_gpu_migratable_ops_v21_07;
9313 rpc_ctrl_gpu_migratable_ops_v ctrl_gpu_migratable_ops_v;
9314 rpc_invalidate_tlb_v23_03 invalidate_tlb_v23_03;
9315 rpc_invalidate_tlb_v invalidate_tlb_v;
9316 rpc_get_brand_caps_v25_12 get_brand_caps_v25_12;
9317 rpc_get_brand_caps_v get_brand_caps_v;
9318 rpc_gsp_set_system_info_v17_00 gsp_set_system_info_v17_00;
9319 rpc_gsp_set_system_info_v gsp_set_system_info_v;
9320 rpc_gsp_rm_alloc_v03_00 gsp_rm_alloc_v03_00;
9321 rpc_gsp_rm_alloc_v gsp_rm_alloc_v;
9322 rpc_gsp_rm_control_v03_00 gsp_rm_control_v03_00;
9323 rpc_gsp_rm_control_v gsp_rm_control_v;
9324 rpc_dump_protobuf_component_v18_12 dump_protobuf_component_v18_12;
9325 rpc_dump_protobuf_component_v dump_protobuf_component_v;
9326 rpc_run_cpu_sequencer_v17_00 run_cpu_sequencer_v17_00;
9327 rpc_run_cpu_sequencer_v run_cpu_sequencer_v;
9328 rpc_post_event_v17_00 post_event_v17_00;
9329 rpc_post_event_v post_event_v;
9330 rpc_rc_triggered_v17_02 rc_triggered_v17_02;
9331 rpc_rc_triggered_v rc_triggered_v;
9332 rpc_os_error_log_v17_00 os_error_log_v17_00;
9333 rpc_os_error_log_v os_error_log_v;
9334 rpc_rg_line_intr_v17_00 rg_line_intr_v17_00;
9335 rpc_rg_line_intr_v rg_line_intr_v;
9336 rpc_display_modeset_v01_00 display_modeset_v01_00;
9337 rpc_display_modeset_v display_modeset_v;
9338 rpc_gpuacct_perfmon_util_samples_v1F_0E gpuacct_perfmon_util_samples_v1F_0E;
9339 rpc_gpuacct_perfmon_util_samples_v gpuacct_perfmon_util_samples_v;
9340 rpc_vgpu_gsp_plugin_triggered_v17_00 vgpu_gsp_plugin_triggered_v17_00;
9341 rpc_vgpu_gsp_plugin_triggered_v vgpu_gsp_plugin_triggered_v;
9342 rpc_vgpu_config_event_v17_00 vgpu_config_event_v17_00;
9343 rpc_vgpu_config_event_v vgpu_config_event_v;
9344 rpc_dce_rm_init_v01_00 dce_rm_init_v01_00;
9345 rpc_dce_rm_init_v dce_rm_init_v;
9346 rpc_sim_read_v1E_01 sim_read_v1E_01;
9347 rpc_sim_read_v sim_read_v;
9348 rpc_sim_write_v1E_01 sim_write_v1E_01;
9349 rpc_sim_write_v sim_write_v;
9350 rpc_ucode_libos_print_v1E_08 ucode_libos_print_v1E_08;
9351 rpc_ucode_libos_print_v ucode_libos_print_v;
9352 rpc_init_done_v17_00 init_done_v17_00;
9353 rpc_init_done_v init_done_v;
9354 rpc_semaphore_schedule_callback_v17_00 semaphore_schedule_callback_v17_00;
9355 rpc_semaphore_schedule_callback_v semaphore_schedule_callback_v;
9356 rpc_timed_semaphore_release_v01_00 timed_semaphore_release_v01_00;
9357 rpc_timed_semaphore_release_v timed_semaphore_release_v;
9358 rpc_perf_gpu_boost_sync_limits_callback_v17_00 perf_gpu_boost_sync_limits_callback_v17_00;
9359 rpc_perf_gpu_boost_sync_limits_callback_v perf_gpu_boost_sync_limits_callback_v;
9360 rpc_perf_bridgeless_info_update_v17_00 perf_bridgeless_info_update_v17_00;
9361 rpc_perf_bridgeless_info_update_v perf_bridgeless_info_update_v;
9362 rpc_nvlink_fault_up_v17_00 nvlink_fault_up_v17_00;
9363 rpc_nvlink_fault_up_v nvlink_fault_up_v;
9364 rpc_nvlink_inband_received_data_256_v17_00 nvlink_inband_received_data_256_v17_00;
9365 rpc_nvlink_inband_received_data_256_v nvlink_inband_received_data_256_v;
9366 rpc_nvlink_inband_received_data_512_v17_00 nvlink_inband_received_data_512_v17_00;
9367 rpc_nvlink_inband_received_data_512_v nvlink_inband_received_data_512_v;
9368 rpc_nvlink_inband_received_data_1024_v17_00 nvlink_inband_received_data_1024_v17_00;
9369 rpc_nvlink_inband_received_data_1024_v nvlink_inband_received_data_1024_v;
9370 rpc_nvlink_inband_received_data_2048_v17_00 nvlink_inband_received_data_2048_v17_00;
9371 rpc_nvlink_inband_received_data_2048_v nvlink_inband_received_data_2048_v;
9372 rpc_nvlink_inband_received_data_4096_v17_00 nvlink_inband_received_data_4096_v17_00;
9373 rpc_nvlink_inband_received_data_4096_v nvlink_inband_received_data_4096_v;
9374 rpc_nvlink_is_gpu_degraded_v17_00 nvlink_is_gpu_degraded_v17_00;
9375 rpc_nvlink_is_gpu_degraded_v nvlink_is_gpu_degraded_v;
9376 rpc_update_gsp_trace_v01_00 update_gsp_trace_v01_00;
9377 rpc_update_gsp_trace_v update_gsp_trace_v;
9378 rpc_gsp_post_nocat_record_v01_00 gsp_post_nocat_record_v01_00;
9379 rpc_gsp_post_nocat_record_v gsp_post_nocat_record_v;
9380 rpc_extdev_intr_service_v17_00 extdev_intr_service_v17_00;
9381 rpc_extdev_intr_service_v extdev_intr_service_v;
9382 rpc_pfm_req_hndlr_state_sync_callback_v21_04 pfm_req_hndlr_state_sync_callback_v21_04;
9383 rpc_pfm_req_hndlr_state_sync_callback_v pfm_req_hndlr_state_sync_callback_v;
9384 rpc_vgpu_gsp_mig_ci_config_v21_03 vgpu_gsp_mig_ci_config_v21_03;
9385 rpc_vgpu_gsp_mig_ci_config_v vgpu_gsp_mig_ci_config_v;
9386 rpc_gsp_lockdown_notice_v17_00 gsp_lockdown_notice_v17_00;
9387 rpc_gsp_lockdown_notice_v gsp_lockdown_notice_v;
9388 rpc_ctrl_gpu_query_ecc_status_v24_06 ctrl_gpu_query_ecc_status_v24_06;
9389 rpc_ctrl_gpu_query_ecc_status_v ctrl_gpu_query_ecc_status_v;
9390 rpc_ctrl_dbg_get_mode_mmu_debug_v25_04 ctrl_dbg_get_mode_mmu_debug_v25_04;
9391 rpc_ctrl_dbg_get_mode_mmu_debug_v ctrl_dbg_get_mode_mmu_debug_v;
9392 rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v25_09 ctrl_cmd_internal_gpu_start_fabric_probe_v25_09;
9393 rpc_ctrl_cmd_internal_gpu_start_fabric_probe_v ctrl_cmd_internal_gpu_start_fabric_probe_v;
9394 rpc_ctrl_nvlink_get_inband_received_data_v25_0C ctrl_nvlink_get_inband_received_data_v25_0C;
9395 rpc_ctrl_nvlink_get_inband_received_data_v ctrl_nvlink_get_inband_received_data_v;
9396 } rpc_generic_union;
9397
9398 #endif
9399
9400 #ifdef RPC_UNION_MEMBER_NAME_FUNCTIONS_CMD
9401 #define SDK_UNION_MEMBER_NAME_FUNCTIONS_CMD
9402 #include "g_sdk-structures.h"
9403 #undef SDK_UNION_MEMBER_NAME_FUNCTIONS_CMD
get_union_member_index_rpc_alloc_object_v25_08_params(void * msg,NvS32 bytes_remaining,uint32_t * index)9404 static NV_STATUS get_union_member_index_rpc_alloc_object_v25_08_params(void *msg, NvS32 bytes_remaining, uint32_t* index)
9405 {
9406 rpc_alloc_object_v25_08 *param = msg;
9407
9408 if ((NvS32)(NV_OFFSETOF(rpc_alloc_object_v25_08, hClass) + sizeof(param->hClass)) > bytes_remaining)
9409 return NV_ERR_BUFFER_TOO_SMALL;
9410 *index = _get_union_member_index_alloc_object_params_v25_08(param->hClass);
9411 return NV_OK;
9412 }
get_union_member_index_rpc_get_engine_utilization_v1F_0E_params(void * msg,NvS32 bytes_remaining,uint32_t * index)9413 static NV_STATUS get_union_member_index_rpc_get_engine_utilization_v1F_0E_params(void *msg, NvS32 bytes_remaining, uint32_t* index)
9414 {
9415 rpc_get_engine_utilization_v1F_0E *param = msg;
9416
9417 if ((NvS32)(NV_OFFSETOF(rpc_get_engine_utilization_v1F_0E, cmd) + sizeof(param->cmd)) > bytes_remaining)
9418 return NV_ERR_BUFFER_TOO_SMALL;
9419 *index = _get_union_member_index_vgpuGetEngineUtilization_data_v1F_0E(param->cmd);
9420 return NV_OK;
9421 }
9422
9423 #endif
9424
9425
9426 #ifdef RPC_ARRAY_LENGTH_FUNCTIONS
9427 #define SDK_ARRAY_LENGTH_FUNCTIONS
9428 #include "g_sdk-structures.h"
9429 #undef SDK_ARRAY_LENGTH_FUNCTIONS
9430
9431 // Array length functions for IDLE_CHANNELS:
get_array_length_rpc_idle_channels_v03_00_channel_list(void * msg,NvS32 bytes_remaining,uint32_t * length)9432 static NV_STATUS get_array_length_rpc_idle_channels_v03_00_channel_list(void *msg, NvS32 bytes_remaining, uint32_t* length)
9433 {
9434 rpc_idle_channels_v03_00 *param = msg;
9435
9436 if ((NvS32)(NV_OFFSETOF(rpc_idle_channels_v03_00, nchannels) + sizeof(param->nchannels)) > bytes_remaining)
9437 return NV_ERR_BUFFER_TOO_SMALL;
9438 *length = param->nchannels;
9439 return NV_OK;
9440 }
9441
9442 #endif
9443
9444 #ifdef AUTOGENERATE_RPC_MIN_SUPPORTED_VERSION_INFORMATION
9445 #define NV_VGPU_GRIDSW_VERSION_MIN_SUPPORTED_INTERNAL_MAJOR 0x25
9446 #define NV_VGPU_GRIDSW_VERSION_MIN_SUPPORTED_INTERNAL_MINOR 0x0E
9447 #endif
9448