1 /* $OpenBSD: rccosb4.c,v 1.7 2023/01/30 10:49:05 jsg Exp $ */
2
3 /*
4 * Copyright (c) 2004,2005 Michael Shalayeff
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 /*
30 * Support for RCC South Bridge interrupt controller
31 */
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/malloc.h>
36
37 #include <machine/intr.h>
38 #include <machine/bus.h>
39
40 #include <dev/pci/pcivar.h>
41
42 #include <i386/pci/pcibiosvar.h>
43 #include <i386/pci/piixvar.h>
44 #include <i386/pci/rccosb4reg.h>
45
46 struct osb4_handle {
47 struct piix_handle piix;
48
49 #define osb4_iot piix.ph_iot
50 bus_space_handle_t osb4_ioh;
51 };
52
53 int osb4_getclink(pciintr_icu_handle_t, int, int *);
54 int osb4_get_intr(pciintr_icu_handle_t, int, int *);
55 int osb4_set_intr(pciintr_icu_handle_t, int, int);
56
57 const struct pciintr_icu osb4_pci_icu = {
58 osb4_getclink,
59 osb4_get_intr,
60 osb4_set_intr,
61 piix_get_trigger,
62 piix_set_trigger,
63 };
64
65 int
osb4_init(pci_chipset_tag_t pc,bus_space_tag_t iot,pcitag_t tag,pciintr_icu_tag_t * ptagp,pciintr_icu_handle_t * phandp)66 osb4_init(pci_chipset_tag_t pc, bus_space_tag_t iot, pcitag_t tag,
67 pciintr_icu_tag_t *ptagp, pciintr_icu_handle_t *phandp)
68 {
69 struct osb4_handle *ph;
70
71 ph = malloc(sizeof(*ph), M_DEVBUF, M_NOWAIT);
72 if (ph == NULL)
73 return (1);
74
75 ph->piix.ph_iot = iot;
76 ph->piix.ph_pc = pc;
77 ph->piix.ph_tag = tag;
78
79 if (bus_space_map(iot, OSB4_PIAIR, 2, 0, &ph->osb4_ioh)) {
80 free(ph, M_DEVBUF, sizeof *ph);
81 return (1);
82 }
83
84 if (bus_space_map(iot, OSB4_REG_ELCR, 2, 0, &ph->piix.ph_elcr_ioh)) {
85 free(ph, M_DEVBUF, sizeof *ph);
86 return (1);
87 }
88
89 *ptagp = &osb4_pci_icu;
90 *phandp = ph;
91 return (0);
92 }
93
94 int
osb4_getclink(pciintr_icu_handle_t v,int link,int * clinkp)95 osb4_getclink(pciintr_icu_handle_t v, int link, int *clinkp)
96 {
97 if (OSB4_LEGAL_LINK(link - 1)) {
98 *clinkp = link;
99 if (link <= OSB4_PISP)
100 *clinkp |= PCI_INT_VIA_ISA;
101 return (0);
102 }
103
104 return (1);
105 }
106
107 int
osb4_get_intr(pciintr_icu_handle_t v,int clink,int * irqp)108 osb4_get_intr(pciintr_icu_handle_t v, int clink, int *irqp)
109 {
110 struct osb4_handle *ph = v;
111 int link = clink & 0xff;
112
113 if (!OSB4_LEGAL_LINK(link))
114 return (1);
115
116 bus_space_write_1(ph->osb4_iot, ph->osb4_ioh, 0, link);
117 *irqp = bus_space_read_1(ph->osb4_iot, ph->osb4_ioh, 1) & 0xf;
118 if (*irqp == 0)
119 *irqp = I386_PCI_INTERRUPT_LINE_NO_CONNECTION;
120
121 return (0);
122 }
123
124 int
osb4_set_intr(pciintr_icu_handle_t v,int clink,int irq)125 osb4_set_intr(pciintr_icu_handle_t v, int clink, int irq)
126 {
127 struct osb4_handle *ph = v;
128 int link = clink & 0xff;
129
130 if (!OSB4_LEGAL_LINK(link) || !OSB4_LEGAL_IRQ(irq & 0xf))
131 return (1);
132
133 bus_space_write_1(ph->osb4_iot, ph->osb4_ioh, 0, link);
134 bus_space_write_1(ph->osb4_iot, ph->osb4_ioh, 1, irq & 0xf);
135
136 return (0);
137 }
138