| /dports/cad/abc/abc-a4518e6f833885c905964f1233d11e5b941ec24c/src/aig/miniaig/ |
| H A D | ndr.h | 531 static inline int Ndr_AddModule( void * pDesign, int Name ) in Ndr_AddModule()
547 static inline void Ndr_AddObject( void * pDesign, int ModuleId, in Ndr_AddObject()
573 static inline void Ndr_Delete( void * pDesign ) in Ndr_Delete()
648 void * pDesign = Ndr_Create( 1 ); in Ndr_ModuleTest() local
719 void * pDesign = Ndr_Create( 14 ); in Ndr_ModuleTestAdder() local
802 void * pDesign = Ndr_Create( 2 ); in Ndr_ModuleTestHierarchy() local
952 void * pDesign = Ndr_Create( 1 ); in Ndr_ModuleTestFlop() local
1009 void * pDesign = Ndr_Create( 1 ); in Ndr_ModuleTestSelSel() local
1050 void * pDesign = Ndr_Create( 1 ); in Ndr_ModuleTestDec() local
1083 void * pDesign = Ndr_Create( 1 ); in Ndr_ModuleTestAddSub() local
[all …]
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| /dports/cad/abc/abc-a4518e6f833885c905964f1233d11e5b941ec24c/src/base/io/ |
| H A D | ioReadVerilog.c | 51 Abc_Des_t * pDesign; in Io_ReadVerilog() local
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| H A D | ioReadBlifMv.c | 81 Abc_Des_t * pDesign; // the design under construction member
147 Abc_Des_t * pDesign = NULL; in Io_ReadBlifMv() local
905 Abc_Des_t * pDesign; in Io_MvParse() local
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| /dports/cad/abc/abc-a4518e6f833885c905964f1233d11e5b941ec24c/src/base/wln/ |
| H A D | wlnNdr.c | 50 void * pDesign = Ndr_Create( 1 ); in Wln_NtkToNdr() local
83 void * pDesign = Wln_NtkToNdr( p ); in Wln_WriteNdr() local
91 void * pDesign = Wln_NtkToNdr( p ); in Wln_NtkToNdrTest() local
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| /dports/cad/abc/abc-a4518e6f833885c905964f1233d11e5b941ec24c/src/base/wlc/ |
| H A D | wlcNdr.c | 195 void * pDesign = Ndr_Create( 1 ); in Wlc_NtkToNdr() local
249 void * pDesign = Wlc_NtkToNdr( pNtk ); in Wlc_WriteNdr() local
257 void * pDesign = Wlc_NtkToNdr( pNtk ); in Wlc_NtkToNdrTest() local
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| /dports/cad/abc/abc-a4518e6f833885c905964f1233d11e5b941ec24c/src/base/ver/ |
| H A D | ver.h | 60 Abc_Des_t * pDesign; member
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| H A D | verCore.c | 168 Abc_Des_t * pDesign; in Ver_ParseFile() local
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| /dports/cad/abc/abc-a4518e6f833885c905964f1233d11e5b941ec24c/src/base/abc/ |
| H A D | abcHie.c | 693 Abc_Des_t * pDesign; in Abc_NtkInsertNewLogic() local
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| H A D | abc.h | 180 Abc_Des_t * pDesign; // design (hierarchical networks only) member
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| /dports/editors/libreoffice/libreoffice-7.2.6.2/sd/source/filter/html/ |
| H A D | pubdlg.cxx | 1279 void SdPublishingDlg::SetDesign( SdPublishingDesign const * pDesign ) in SetDesign()
1360 void SdPublishingDlg::GetDesign( SdPublishingDesign* pDesign ) in GetDesign()
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| /dports/editors/libreoffice6/libreoffice-6.4.7.2/sd/source/filter/html/ |
| H A D | pubdlg.cxx | 1251 void SdPublishingDlg::SetDesign( SdPublishingDesign const * pDesign ) in SetDesign()
1331 void SdPublishingDlg::GetDesign( SdPublishingDesign* pDesign ) in GetDesign()
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| /dports/cad/abc/abc-a4518e6f833885c905964f1233d11e5b941ec24c/src/base/acb/ |
| H A D | acbFunc.c | 225 Ndr_Data_t * pDesign = NULL; in Acb_VerilogSimpleParse() local
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| H A D | acb.h | 53 Acb_Man_t * pDesign; // design member
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| /dports/cad/abc/abc-a4518e6f833885c905964f1233d11e5b941ec24c/src/base/bac/ |
| H A D | bac.h | 147 Bac_Man_t * pDesign; // design member
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| /dports/cad/abc/abc-a4518e6f833885c905964f1233d11e5b941ec24c/src/base/cba/ |
| H A D | cba.h | 51 Cba_Man_t * pDesign; // design member
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