xref: /original-bsd/sys/pmax/dev/siireg.h (revision dbaf26eb)
1 /*
2  * Copyright (c) 1992, 1993
3  *	The Regents of the University of California.  All rights reserved.
4  *
5  * This code is derived from software contributed to Berkeley by
6  * Ralph Campbell.
7  *
8  * %sccs.include.redist.c%
9  *
10  *	@(#)siireg.h	8.1 (Berkeley) 06/10/93
11  *
12  * sii.h --
13  *
14  * 	SII registers.
15  *
16  *	Copyright (C) 1989 Digital Equipment Corporation.
17  *	Permission to use, copy, modify, and distribute this software and
18  *	its documentation for any purpose and without fee is hereby granted,
19  *	provided that the above copyright notice appears in all copies.
20  *	Digital Equipment Corporation makes no representations about the
21  *	suitability of this software for any purpose.  It is provided "as is"
22  *	without express or implied warranty.
23  *
24  * from: $Header: /sprite/src/kernel/dev/ds3100.md/RCS/sii.h,
25  *	v 1.2 89/08/15 19:53:04 rab Exp $ SPRITE (DECWRL)
26  */
27 
28 #ifndef _SII
29 #define _SII
30 
31 /*
32  * SII hardware registers
33  */
34 typedef volatile struct {
35 	u_short	sdb;		/* SCSI Data Bus and Parity */
36 	u_short	pad0;
37 	u_short	sc1;		/* SCSI Control Signals One */
38 	u_short	pad1;
39 	u_short	sc2;		/* SCSI Control Signals Two */
40 	u_short	pad2;
41 	u_short	csr;		/* Control/Status register */
42 	u_short	pad3;
43 	u_short	id;		/* Bus ID register */
44 	u_short	pad4;
45 	u_short	slcsr;		/* Select Control and Status Register */
46 	u_short	pad5;
47 	u_short	destat;		/* Selection Detector Status Register */
48 	u_short	pad6;
49 	u_short	dstmo;		/* DSSI Timeout Register */
50 	u_short	pad7;
51 	u_short	data;		/* Data Register */
52 	u_short	pad8;
53 	u_short	dmctrl;		/* DMA Control Register */
54 	u_short	pad9;
55 	u_short	dmlotc;		/* DMA Length of Transfer Counter */
56 	u_short	pad10;
57 	u_short	dmaddrl;	/* DMA Address Register Low */
58 	u_short	pad11;
59 	u_short	dmaddrh;	/* DMA Address Register High */
60 	u_short	pad12;
61 	u_short	dmabyte;	/* DMA Initial Byte Register */
62 	u_short	pad13;
63 	u_short	stlp;		/* DSSI Short Target List Pointer */
64 	u_short	pad14;
65 	u_short	ltlp;		/* DSSI Long Target List Pointer */
66 	u_short	pad15;
67 	u_short	ilp;		/* DSSI Initiator List Pointer */
68 	u_short	pad16;
69 	u_short	dsctrl;		/* DSSI Control Register */
70 	u_short	pad17;
71 	u_short	cstat;		/* Connection Status Register */
72 	u_short	pad18;
73 	u_short	dstat;		/* Data Transfer Status Register */
74 	u_short	pad19;
75 	u_short	comm;		/* Command Register */
76 	u_short	pad20;
77 	u_short	dictrl;		/* Diagnostic Control Register */
78 	u_short	pad21;
79 	u_short	clock;		/* Diagnostic Clock Register */
80 	u_short	pad22;
81 	u_short	bhdiag;		/* Bus Handler Diagnostic Register */
82 	u_short	pad23;
83 	u_short	sidiag;		/* SCSI IO Diagnostic Register */
84 	u_short	pad24;
85 	u_short	dmdiag;		/* Data Mover Diagnostic Register */
86 	u_short	pad25;
87 	u_short	mcdiag;		/* Main Control Diagnostic Register */
88 	u_short	pad26;
89 } SIIRegs;
90 
91 /*
92  * SC1 - SCSI Control Signals One
93  */
94 #define SII_SC1_MSK	0x1ff		/* All possible signals on the bus */
95 #define SII_SC1_SEL	0x80		/* SCSI SEL signal active on bus */
96 #define SII_SC1_ATN	0x08		/* SCSI ATN signal active on bus */
97 
98 /*
99  * SC2 - SCSI Control Signals Two
100  */
101 #define SII_SC2_IGS	0x8		/* SCSI drivers for initiator mode */
102 
103 /*
104  * CSR - Control/Status Register
105  */
106 #define SII_HPM	0x10			/* SII in on an arbitrated SCSI bus */
107 #define	SII_RSE	0x08			/* 1 = respond to reselections */
108 #define SII_SLE	0x04			/* 1 = respond to selections */
109 #define SII_PCE	0x02			/* 1 = report parity errors */
110 #define SII_IE	0x01			/* 1 = enable interrupts */
111 
112 /*
113  * ID - Bus ID Register
114  */
115 #define SII_ID_IO	0x8000		/* I/O */
116 
117 /*
118  * DESTAT - Selection Detector Status Register
119  */
120 #define SII_IDMSK	0x7		/* ID of target reselected the SII */
121 
122 /*
123  * DMCTRL - DMA Control Register
124  */
125 #define SII_ASYNC	0x00		/* REQ/ACK Offset for async mode */
126 #define SII_SYNC	0x03		/* REQ/ACK Offset for sync mode */
127 
128 /*
129  * DMLOTC - DMA Length Of Transfer Counter
130  */
131 #define SII_TCMSK	0x1fff		/* transfer count mask */
132 
133 /*
134  * CSTAT - Connection Status Register
135  */
136 #define	SII_CI		0x8000	/* composite interrupt bit for CSTAT */
137 #define SII_DI		0x4000	/* composite interrupt bit for DSTAT */
138 #define SII_RST		0x2000	/* 1 if reset is asserted on SCSI bus */
139 #define	SII_BER		0x1000	/* Bus error */
140 #define	SII_OBC		0x0800	/* Out_en Bit Cleared (DSSI mode) */
141 #define SII_TZ		0x0400	/* Target pointer Zero (STLP or LTLP is zero) */
142 #define	SII_BUF		0x0200	/* Buffer service - outbound pkt to non-DSSI */
143 #define SII_LDN		0x0100	/* List element Done */
144 #define SII_SCH		0x0080	/* State Change */
145 #define SII_CON		0x0040	/* SII is Connected to another device */
146 #define SII_DST		0x0020	/* SII was Destination of current transfer */
147 #define SII_TGT		0x0010	/* SII is operating as a Target */
148 #define SII_STATE_MSK	0x0070	/* State Mask */
149 #define SII_SWA		0x0008	/* Selected With Attention */
150 #define SII_SIP		0x0004	/* Selection In Progress */
151 #define SII_LST		0x0002	/* Lost arbitration */
152 
153 /*
154  * DSTAT - Data Transfer Status Register
155  */
156 #define SII_DNE		0x2000	/* DMA transfer Done */
157 #define SII_TCZ		0x1000	/* Transfer Count register is Zero */
158 #define SII_TBE		0x0800	/* Transmit Buffer Empty */
159 #define SII_IBF		0x0400	/* Input Buffer Full */
160 #define SII_IPE		0x0200	/* Incoming Parity Error */
161 #define SII_OBB		0x0100	/* Odd Byte Boundry */
162 #define SII_MIS		0x0010	/* Phase Mismatch */
163 #define SII_ATN		0x0008	/* ATN set by initiator if in Target mode */
164 #define SII_MSG		0x0004	/* current bus state of MSG */
165 #define SII_CD		0x0002	/* current bus state of C/D */
166 #define SII_IO		0x0001	/* current bus state of I/O */
167 #define SII_PHASE_MSK	0x0007	/* Phase Mask */
168 
169 /*
170  * The different phases.
171  */
172 #define SII_MSG_IN_PHASE	0x7
173 #define SII_MSG_OUT_PHASE	0x6
174 #define SII_STATUS_PHASE	0x3
175 #define SII_CMD_PHASE		0x2
176 #define SII_DATA_IN_PHASE	0x1
177 #define SII_DATA_OUT_PHASE	0x0
178 
179 /*
180  * COMM - Command Register
181  */
182 #define	SII_DMA		0x8000	/* DMA mode */
183 #define SII_DO_RST	0x4000	/* Assert reset on SCSI bus for 25 usecs */
184 #define SII_RSL		0x1000	/* 0 = select, 1 = reselect desired device */
185 
186 /* Commands: I - Initiator, T - Target, D - Disconnected */
187 #define SII_INXFER	0x0800	/* Information Transfer command	(I,T) */
188 #define SII_SELECT	0x0400	/* Select command		(D) */
189 #define SII_REQDATA	0x0200	/* Request Data command		(T) */
190 #define	SII_DISCON	0x0100	/* Disconnect command		(I,T,D) */
191 #define SII_CHRESET	0x0080	/* Chip Reset command		(I,T,D) */
192 
193 /* Command state bits same as connection status register */
194 /* Command phase bits same as data transfer status register */
195 
196 /*
197  * DICTRL - Diagnostic Control Register
198  */
199 #define SII_PRE		0x4	/* Enable the SII to drive the SCSI bus */
200 
201 #define SII_WAIT_COUNT		10000	/* Delay count used for the SII chip */
202 /*
203  * Max DMA transfer length for SII
204  * The SII chip only has a 13 bit counter. If 8192 is used as the max count,
205  * you can't tell the difference between a count of zero and 8192.
206  * 8190 is used instead of 8191 so the count is even.
207  */
208 #define SII_MAX_DMA_XFER_LENGTH	8192
209 
210 #endif /* _SII */
211