xref: /openbsd/sys/arch/arm/arm/vectors.S (revision 81621933)
1/*	$OpenBSD: vectors.S,v 1.4 2022/12/08 01:25:44 guenther Exp $	*/
2/*	$NetBSD: vectors.S,v 1.4 2002/08/17 16:36:32 thorpej Exp $	*/
3
4/*
5 * Copyright (C) 1994-1997 Mark Brinicombe
6 * Copyright (C) 1994 Brini
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 *    must display the following acknowledgement:
19 *	This product includes software developed by Brini.
20 * 4. The name of Brini may not be used to endorse or promote products
21 *    derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include "assym.h"
36
37#include <machine/asm.h>
38
39/*
40 * These are the exception vectors copied down to page 0.
41 *
42 * Note that FIQs are special; rather than using a level of
43 * indirection, we actually copy the FIQ code down into the
44 * vector page.
45 */
46
47	.text
48	.align	2
49	.global	page0, page0_data, page0_end
50	.global fiqvector
51
52page0:
53	ldr	pc, .Lreset_target
54	ldr	pc, .Lundefined_target
55	ldr	pc, .Lswi_target
56	ldr	pc, .Lprefetch_abort_target
57	ldr	pc, .Ldata_abort_target
58	ldr	pc, .Laddress_exception_target
59	ldr	pc, .Lirq_target
60#ifdef __ARM_FIQ_INDIRECT
61	ldr	pc, .Lfiq_target
62#else
63.Lfiqvector:
64	.set	fiqvector, . - page0
65	subs	pc, lr, #4
66	.org	.Lfiqvector + 0x100
67#endif
68
69page0_data:
70.Lreset_target:
71	.word	reset_entry
72
73.Lundefined_target:
74	.word	undefined_entry
75
76.Lswi_target:
77	.word	swi_entry
78
79.Lprefetch_abort_target:
80	.word	prefetch_abort_entry
81
82.Ldata_abort_target:
83	.word	data_abort_entry
84
85.Laddress_exception_target:
86	.word	address_exception_entry
87
88.Lirq_target:
89	.word	irq_entry
90
91#ifdef __ARM_FIQ_INDIRECT
92.Lfiq_target:
93	.word	fiqvector
94#else
95	.word	0	/* pad it out */
96#endif
97page0_end:
98
99#ifdef __ARM_FIQ_INDIRECT
100	.data
101	.align	2
102fiqvector:
103	subs	pc, lr, #4
104	.org	fiqvector + 0x100
105#endif
106