1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \ 3; RUN: -relocation-model=pic -ppc-asm-full-reg-names -verify-machineinstrs \ 4; RUN: -enable-ppc-quad-precision < %s | FileCheck %s 5; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown -ppc-vsr-nums-as-vr \ 6; RUN: -ppc-asm-full-reg-names -verify-machineinstrs \ 7; RUN: -enable-ppc-quad-precision < %s | FileCheck %s -check-prefix=CHECK-BE 8 9; Vector extract DWord and convert to quad precision. 10 11@sdwVecMem = global <2 x i64> <i64 88, i64 99>, align 16 12@udwVecMem = global <2 x i64> <i64 88, i64 99>, align 16 13 14; Function Attrs: norecurse nounwind 15define void @sdwVecConv2qp(fp128* nocapture %a, <2 x i64> %b) { 16; CHECK-LABEL: sdwVecConv2qp: 17; CHECK: # %bb.0: # %entry 18; CHECK-NEXT: xxspltd v2, v2, 1 19; CHECK-NEXT: xscvsdqp v2, v2 20; CHECK-NEXT: stxv v2, 0(r3) 21; CHECK-NEXT: blr 22 23; CHECK-BE-LABEL: sdwVecConv2qp: 24; CHECK-BE: xscvsdqp v2, v2 25; CHECK-BE-NEXT: stxv v2, 0(r3) 26; CHECK-BE-NEXT: blr 27entry: 28 %vecext = extractelement <2 x i64> %b, i32 0 29 %conv = sitofp i64 %vecext to fp128 30 store fp128 %conv, fp128* %a, align 16 31 ret void 32} 33 34; Function Attrs: norecurse nounwind 35define void @sdwVecConv2qp1(fp128* nocapture %a, <2 x i64> %b) { 36; CHECK-LABEL: sdwVecConv2qp1: 37; CHECK: # %bb.0: # %entry 38; CHECK-NEXT: xscvsdqp v2, v2 39; CHECK-NEXT: stxv v2, 0(r3) 40; CHECK-NEXT: blr 41 42; CHECK-BE-LABEL: sdwVecConv2qp1: 43; CHECK-BE: # %bb.0: # %entry 44; CHECK-BE-NEXT: xxspltd v2, v2, 1 45; CHECK-BE-NEXT: xscvsdqp v2, v2 46; CHECK-BE-NEXT: stxv v2, 0(r3) 47; CHECK-BE-NEXT: blr 48entry: 49 %vecext = extractelement <2 x i64> %b, i32 1 50 %conv = sitofp i64 %vecext to fp128 51 store fp128 %conv, fp128* %a, align 16 52 ret void 53} 54 55; Function Attrs: norecurse nounwind 56define void @sdwVecConv2qp_02(fp128* nocapture %a) { 57; CHECK-LABEL: sdwVecConv2qp_02: 58; CHECK: # %bb.0: # %entry 59; CHECK-NEXT: addis r4, r2, .LC0@toc@ha 60; CHECK-NEXT: ld r4, .LC0@toc@l(r4) 61; CHECK-NEXT: lxsd v2, 0(r4) 62; CHECK-NEXT: xscvsdqp v2, v2 63; CHECK-NEXT: stxv v2, 0(r3) 64; CHECK-NEXT: blr 65entry: 66 %0 = load <2 x i64>, <2 x i64>* @sdwVecMem, align 16 67 %vecext = extractelement <2 x i64> %0, i32 0 68 %conv = sitofp i64 %vecext to fp128 69 store fp128 %conv, fp128* %a, align 16 70 ret void 71} 72 73; Function Attrs: norecurse nounwind 74define void @sdwVecConv2qp1_03(fp128* nocapture %a, <2 x i64>* nocapture readonly %b) { 75; CHECK-LABEL: sdwVecConv2qp1_03: 76; CHECK: # %bb.0: # %entry 77; CHECK-NEXT: lxsd v2, 8(r4) 78; CHECK-NEXT: xscvsdqp v2, v2 79; CHECK-NEXT: stxv v2, 0(r3) 80; CHECK-NEXT: blr 81entry: 82 %0 = load <2 x i64>, <2 x i64>* %b, align 16 83 %vecext = extractelement <2 x i64> %0, i32 1 84 %conv = sitofp i64 %vecext to fp128 85 store fp128 %conv, fp128* %a, align 16 86 ret void 87} 88 89; Function Attrs: norecurse nounwind 90define void @udwVecConv2qp(fp128* nocapture %a, <2 x i64> %b) { 91; CHECK-LABEL: udwVecConv2qp: 92; CHECK: # %bb.0: # %entry 93; CHECK-NEXT: xxspltd v2, v2, 1 94; CHECK-NEXT: xscvudqp v2, v2 95; CHECK-NEXT: stxv v2, 0(r3) 96; CHECK-NEXT: blr 97 98; CHECK-BE-LABEL: udwVecConv2qp: 99; CHECK-BE: # %bb.0: # %entry 100; CHECK-BE-NEXT: xscvudqp v2, v2 101; CHECK-BE-NEXT: stxv v2, 0(r3) 102; CHECK-BE-NEXT: blr 103entry: 104 %vecext = extractelement <2 x i64> %b, i32 0 105 %conv = uitofp i64 %vecext to fp128 106 store fp128 %conv, fp128* %a, align 16 107 ret void 108} 109 110; Function Attrs: norecurse nounwind 111define void @udwVecConv2qp1(fp128* nocapture %a, <2 x i64> %b) { 112; CHECK-LABEL: udwVecConv2qp1: 113; CHECK: # %bb.0: # %entry 114; CHECK-NEXT: xscvudqp v2, v2 115; CHECK-NEXT: stxv v2, 0(r3) 116; CHECK-NEXT: blr 117 118; CHECK-BE-LABEL: udwVecConv2qp1: 119; CHECK-BE: # %bb.0: # %entry 120; CHECK-BE-NEXT: xxspltd v2, v2, 1 121; CHECK-BE-NEXT: xscvudqp v2, v2 122; CHECK-BE-NEXT: stxv v2, 0(r3) 123; CHECK-BE-NEXT: blr 124entry: 125 %vecext = extractelement <2 x i64> %b, i32 1 126 %conv = uitofp i64 %vecext to fp128 127 store fp128 %conv, fp128* %a, align 16 128 ret void 129} 130 131; Function Attrs: norecurse nounwind 132define void @udwVecConv2qp1_02(fp128* nocapture %a) { 133; CHECK-LABEL: udwVecConv2qp1_02: 134; CHECK: # %bb.0: # %entry 135; CHECK-NEXT: addis r4, r2, .LC1@toc@ha 136; CHECK-NEXT: ld r4, .LC1@toc@l(r4) 137; CHECK-NEXT: lxsd v2, 8(r4) 138; CHECK-NEXT: xscvudqp v2, v2 139; CHECK-NEXT: stxv v2, 0(r3) 140; CHECK-NEXT: blr 141entry: 142 %0 = load <2 x i64>, <2 x i64>* @udwVecMem, align 16 143 %vecext = extractelement <2 x i64> %0, i32 1 144 %conv = uitofp i64 %vecext to fp128 145 store fp128 %conv, fp128* %a, align 16 146 ret void 147} 148 149; Function Attrs: norecurse nounwind 150define void @udwVecConv2qp_03(fp128* nocapture %a, <2 x i64>* nocapture readonly %b) { 151; CHECK-LABEL: udwVecConv2qp_03: 152; CHECK: # %bb.0: # %entry 153; CHECK-NEXT: lxsd v2, 0(r4) 154; CHECK-NEXT: xscvudqp v2, v2 155; CHECK-NEXT: stxv v2, 0(r3) 156; CHECK-NEXT: blr 157entry: 158 %0 = load <2 x i64>, <2 x i64>* %b, align 16 159 %vecext = extractelement <2 x i64> %0, i32 0 160 %conv = uitofp i64 %vecext to fp128 161 store fp128 %conv, fp128* %a, align 16 162 ret void 163} 164 165; Vector extract Word and convert to quad precision. 166 167; Function Attrs: norecurse nounwind 168define void @swVecConv2qp(fp128* nocapture %a, <4 x i32> %b) { 169; CHECK-LABEL: swVecConv2qp: 170; CHECK: # %bb.0: # %entry 171; CHECK-NEXT: vspltw v2, v2, 3 172; CHECK-NEXT: vextsw2d v2, v2 173; CHECK-NEXT: xscvsdqp v2, v2 174; CHECK-NEXT: stxv v2, 0(r3) 175; CHECK-NEXT: blr 176 177; CHECK-BE-LABEL: swVecConv2qp: 178; CHECK-BE: vspltw v2, v2, 0 179; CHECK-BE-NEXT: vextsw2d v2, v2 180; CHECK-BE-NEXT: xscvsdqp v2, v2 181; CHECK-BE-NEXT: stxv v2, 0(r3) 182; CHECK-BE-NEXT: blr 183entry: 184 %vecext = extractelement <4 x i32> %b, i32 0 185 %conv = sitofp i32 %vecext to fp128 186 store fp128 %conv, fp128* %a, align 16 187 ret void 188} 189 190; Function Attrs: norecurse nounwind 191define void @swVecConv2qp1(fp128* nocapture %a, <4 x i32> %b) { 192; CHECK-LABEL: swVecConv2qp1: 193; CHECK: # %bb.0: # %entry 194; CHECK-NEXT: vspltw v2, v2, 2 195; CHECK-NEXT: vextsw2d v2, v2 196; CHECK-NEXT: xscvsdqp v2, v2 197; CHECK-NEXT: stxv v2, 0(r3) 198; CHECK-NEXT: blr 199 200; CHECK-BE-LABEL: swVecConv2qp1: 201; CHECK-BE: vextsw2d v2, v2 202; CHECK-BE-NEXT: xscvsdqp v2, v2 203; CHECK-BE-NEXT: stxv v2, 0(r3) 204; CHECK-BE-NEXT: blr 205entry: 206 %vecext = extractelement <4 x i32> %b, i32 1 207 %conv = sitofp i32 %vecext to fp128 208 store fp128 %conv, fp128* %a, align 16 209 ret void 210} 211 212; Function Attrs: norecurse nounwind 213define void @swVecConv2qp2(fp128* nocapture %a, <4 x i32> %b) { 214; CHECK-LABEL: swVecConv2qp2: 215; CHECK: # %bb.0: # %entry 216; CHECK-NEXT: vextsw2d v2, v2 217; CHECK-NEXT: xscvsdqp v2, v2 218; CHECK-NEXT: stxv v2, 0(r3) 219; CHECK-NEXT: blr 220 221; CHECK-BE-LABEL: swVecConv2qp2: 222; CHECK-BE: vspltw v2, v2, 2 223; CHECK-BE-NEXT: vextsw2d v2, v2 224; CHECK-BE-NEXT: xscvsdqp v2, v2 225; CHECK-BE-NEXT: stxv v2, 0(r3) 226; CHECK-BE-NEXT: blr 227entry: 228 %vecext = extractelement <4 x i32> %b, i32 2 229 %conv = sitofp i32 %vecext to fp128 230 store fp128 %conv, fp128* %a, align 16 231 ret void 232} 233 234; Function Attrs: norecurse nounwind 235define void @swVecConv2qp3(fp128* nocapture %a, <4 x i32> %b) { 236; CHECK-LABEL: swVecConv2qp3: 237; CHECK: # %bb.0: # %entry 238; CHECK-NEXT: vspltw v2, v2, 0 239; CHECK-NEXT: vextsw2d v2, v2 240; CHECK-NEXT: xscvsdqp v2, v2 241; CHECK-NEXT: stxv v2, 0(r3) 242; CHECK-NEXT: blr 243 244; CHECK-BE-LABEL: swVecConv2qp3: 245; CHECK-BE: vspltw v2, v2, 3 246; CHECK-BE-NEXT: vextsw2d v2, v2 247; CHECK-BE-NEXT: xscvsdqp v2, v2 248; CHECK-BE-NEXT: stxv v2, 0(r3) 249; CHECK-BE-NEXT: blr 250entry: 251 %vecext = extractelement <4 x i32> %b, i32 3 252 %conv = sitofp i32 %vecext to fp128 253 store fp128 %conv, fp128* %a, align 16 254 ret void 255} 256 257; Function Attrs: norecurse nounwind 258define void @uwVecConv2qp(fp128* nocapture %a, <4 x i32> %b) { 259; CHECK-LABEL: uwVecConv2qp: 260; CHECK: # %bb.0: # %entry 261; CHECK-NEXT: xxextractuw v2, v2, 12 262; CHECK-NEXT: xscvudqp v2, v2 263; CHECK-NEXT: stxv v2, 0(r3) 264; CHECK-NEXT: blr 265 266; CHECK-BE-LABEL: uwVecConv2qp: 267; CHECK-BE: xxextractuw v2, v2, 0 268; CHECK-BE-NEXT: xscvudqp v2, v2 269; CHECK-BE-NEXT: stxv v2, 0(r3) 270; CHECK-BE-NEXT: blr 271entry: 272 %vecext = extractelement <4 x i32> %b, i32 0 273 %conv = uitofp i32 %vecext to fp128 274 store fp128 %conv, fp128* %a, align 16 275 ret void 276} 277 278; Function Attrs: norecurse nounwind 279define void @uwVecConv2qp1(fp128* nocapture %a, <4 x i32> %b) { 280; CHECK-LABEL: uwVecConv2qp1: 281; CHECK: # %bb.0: # %entry 282; CHECK-NEXT: xxextractuw v2, v2, 8 283; CHECK-NEXT: xscvudqp v2, v2 284; CHECK-NEXT: stxv v2, 0(r3) 285; CHECK-NEXT: blr 286 287; CHECK-BE-LABEL: uwVecConv2qp1: 288; CHECK-BE: xxextractuw v2, v2, 4 289; CHECK-BE-NEXT: xscvudqp v2, v2 290; CHECK-BE-NEXT: stxv v2, 0(r3) 291; CHECK-BE-NEXT: blr 292entry: 293 %vecext = extractelement <4 x i32> %b, i32 1 294 %conv = uitofp i32 %vecext to fp128 295 store fp128 %conv, fp128* %a, align 16 296 ret void 297} 298 299; Function Attrs: norecurse nounwind 300define void @uwVecConv2qp2(fp128* nocapture %a, <4 x i32> %b) { 301; CHECK-LABEL: uwVecConv2qp2: 302; CHECK: # %bb.0: # %entry 303; CHECK-NEXT: xxextractuw v2, v2, 4 304; CHECK-NEXT: xscvudqp v2, v2 305; CHECK-NEXT: stxv v2, 0(r3) 306; CHECK-NEXT: blr 307 308; CHECK-BE-LABEL: uwVecConv2qp2: 309; CHECK-BE: xxextractuw v2, v2, 8 310; CHECK-BE-NEXT: xscvudqp v2, v2 311; CHECK-BE-NEXT: stxv v2, 0(r3) 312; CHECK-BE-NEXT: blr 313entry: 314 %vecext = extractelement <4 x i32> %b, i32 2 315 %conv = uitofp i32 %vecext to fp128 316 store fp128 %conv, fp128* %a, align 16 317 ret void 318} 319 320; Function Attrs: norecurse nounwind 321define void @uwVecConv2qp3(fp128* nocapture %a, <4 x i32> %b) { 322; CHECK-LABEL: uwVecConv2qp3: 323; CHECK: # %bb.0: # %entry 324; CHECK-NEXT: xxextractuw v2, v2, 0 325; CHECK-NEXT: xscvudqp v2, v2 326; CHECK-NEXT: stxv v2, 0(r3) 327; CHECK-NEXT: blr 328 329; CHECK-BE-LABEL: uwVecConv2qp3: 330; CHECK-BE: xxextractuw v2, v2, 12 331; CHECK-BE-NEXT: xscvudqp v2, v2 332; CHECK-BE-NEXT: stxv v2, 0(r3) 333; CHECK-BE-NEXT: blr 334entry: 335 %vecext = extractelement <4 x i32> %b, i32 3 336 %conv = uitofp i32 %vecext to fp128 337 store fp128 %conv, fp128* %a, align 16 338 ret void 339} 340 341; Vector extract HWord and convert to quad precision. 342 343; Function Attrs: norecurse nounwind 344define void @shwVecConv2qp(fp128* nocapture %a, <8 x i16> %b) { 345; CHECK-LABEL: shwVecConv2qp: 346; CHECK: # %bb.0: # %entry 347; CHECK-NEXT: vextractuh v2, v2, 14 348; CHECK-NEXT: vextsh2d v2, v2 349; CHECK-NEXT: xscvsdqp v2, v2 350; CHECK-NEXT: stxv v2, 0(r3) 351; CHECK-NEXT: blr 352; 353; CHECK-BE-LABEL: shwVecConv2qp: 354; CHECK-BE: # %bb.0: # %entry 355; CHECK-BE-NEXT: vextractuh v2, v2, 0 356; CHECK-BE-NEXT: vextsh2d v2, v2 357; CHECK-BE-NEXT: xscvsdqp v2, v2 358; CHECK-BE-NEXT: stxv v2, 0(r3) 359; CHECK-BE-NEXT: blr 360entry: 361 %vecext = extractelement <8 x i16> %b, i32 0 362 %conv = sitofp i16 %vecext to fp128 363 store fp128 %conv, fp128* %a, align 16 364 ret void 365} 366 367; Function Attrs: norecurse nounwind 368define void @shwVecConv2qp1(fp128* nocapture %a, <8 x i16> %b) { 369; CHECK-LABEL: shwVecConv2qp1: 370; CHECK: # %bb.0: # %entry 371; CHECK-NEXT: vextractuh v2, v2, 12 372; CHECK-NEXT: vextsh2d v2, v2 373; CHECK-NEXT: xscvsdqp v2, v2 374; CHECK-NEXT: stxv v2, 0(r3) 375; CHECK-NEXT: blr 376; 377; CHECK-BE-LABEL: shwVecConv2qp1: 378; CHECK-BE: # %bb.0: # %entry 379; CHECK-BE-NEXT: vextractuh v2, v2, 2 380; CHECK-BE-NEXT: vextsh2d v2, v2 381; CHECK-BE-NEXT: xscvsdqp v2, v2 382; CHECK-BE-NEXT: stxv v2, 0(r3) 383; CHECK-BE-NEXT: blr 384entry: 385 %vecext = extractelement <8 x i16> %b, i32 1 386 %conv = sitofp i16 %vecext to fp128 387 store fp128 %conv, fp128* %a, align 16 388 ret void 389} 390 391; Function Attrs: norecurse nounwind 392define void @shwVecConv2qp2(fp128* nocapture %a, <8 x i16> %b) { 393; CHECK-LABEL: shwVecConv2qp2: 394; CHECK: # %bb.0: # %entry 395; CHECK-NEXT: vextractuh v2, v2, 10 396; CHECK-NEXT: vextsh2d v2, v2 397; CHECK-NEXT: xscvsdqp v2, v2 398; CHECK-NEXT: stxv v2, 0(r3) 399; CHECK-NEXT: blr 400; 401; CHECK-BE-LABEL: shwVecConv2qp2: 402; CHECK-BE: # %bb.0: # %entry 403; CHECK-BE-NEXT: vextractuh v2, v2, 4 404; CHECK-BE-NEXT: vextsh2d v2, v2 405; CHECK-BE-NEXT: xscvsdqp v2, v2 406; CHECK-BE-NEXT: stxv v2, 0(r3) 407; CHECK-BE-NEXT: blr 408entry: 409 %vecext = extractelement <8 x i16> %b, i32 2 410 %conv = sitofp i16 %vecext to fp128 411 store fp128 %conv, fp128* %a, align 16 412 ret void 413} 414 415; Function Attrs: norecurse nounwind 416define void @shwVecConv2qp3(fp128* nocapture %a, <8 x i16> %b) { 417; CHECK-LABEL: shwVecConv2qp3: 418; CHECK: # %bb.0: # %entry 419; CHECK-NEXT: vextractuh v2, v2, 8 420; CHECK-NEXT: vextsh2d v2, v2 421; CHECK-NEXT: xscvsdqp v2, v2 422; CHECK-NEXT: stxv v2, 0(r3) 423; CHECK-NEXT: blr 424; 425; CHECK-BE-LABEL: shwVecConv2qp3: 426; CHECK-BE: # %bb.0: # %entry 427; CHECK-BE-NEXT: vextractuh v2, v2, 6 428; CHECK-BE-NEXT: vextsh2d v2, v2 429; CHECK-BE-NEXT: xscvsdqp v2, v2 430; CHECK-BE-NEXT: stxv v2, 0(r3) 431; CHECK-BE-NEXT: blr 432entry: 433 %vecext = extractelement <8 x i16> %b, i32 3 434 %conv = sitofp i16 %vecext to fp128 435 store fp128 %conv, fp128* %a, align 16 436 ret void 437} 438 439; Function Attrs: norecurse nounwind 440define void @shwVecConv2qp4(fp128* nocapture %a, <8 x i16> %b) { 441; CHECK-LABEL: shwVecConv2qp4: 442; CHECK: # %bb.0: # %entry 443; CHECK-NEXT: vextractuh v2, v2, 6 444; CHECK-NEXT: vextsh2d v2, v2 445; CHECK-NEXT: xscvsdqp v2, v2 446; CHECK-NEXT: stxv v2, 0(r3) 447; CHECK-NEXT: blr 448; 449; CHECK-BE-LABEL: shwVecConv2qp4: 450; CHECK-BE: # %bb.0: # %entry 451; CHECK-BE-NEXT: vextractuh v2, v2, 8 452; CHECK-BE-NEXT: vextsh2d v2, v2 453; CHECK-BE-NEXT: xscvsdqp v2, v2 454; CHECK-BE-NEXT: stxv v2, 0(r3) 455; CHECK-BE-NEXT: blr 456entry: 457 %vecext = extractelement <8 x i16> %b, i32 4 458 %conv = sitofp i16 %vecext to fp128 459 store fp128 %conv, fp128* %a, align 16 460 ret void 461} 462 463; Function Attrs: norecurse nounwind 464define void @shwVecConv2qp5(fp128* nocapture %a, <8 x i16> %b) { 465; CHECK-LABEL: shwVecConv2qp5: 466; CHECK: # %bb.0: # %entry 467; CHECK-NEXT: vextractuh v2, v2, 4 468; CHECK-NEXT: vextsh2d v2, v2 469; CHECK-NEXT: xscvsdqp v2, v2 470; CHECK-NEXT: stxv v2, 0(r3) 471; CHECK-NEXT: blr 472; 473; CHECK-BE-LABEL: shwVecConv2qp5: 474; CHECK-BE: # %bb.0: # %entry 475; CHECK-BE-NEXT: vextractuh v2, v2, 10 476; CHECK-BE-NEXT: vextsh2d v2, v2 477; CHECK-BE-NEXT: xscvsdqp v2, v2 478; CHECK-BE-NEXT: stxv v2, 0(r3) 479; CHECK-BE-NEXT: blr 480entry: 481 %vecext = extractelement <8 x i16> %b, i32 5 482 %conv = sitofp i16 %vecext to fp128 483 store fp128 %conv, fp128* %a, align 16 484 ret void 485} 486 487; Function Attrs: norecurse nounwind 488define void @shwVecConv2qp6(fp128* nocapture %a, <8 x i16> %b) { 489; CHECK-LABEL: shwVecConv2qp6: 490; CHECK: # %bb.0: # %entry 491; CHECK-NEXT: vextractuh v2, v2, 2 492; CHECK-NEXT: vextsh2d v2, v2 493; CHECK-NEXT: xscvsdqp v2, v2 494; CHECK-NEXT: stxv v2, 0(r3) 495; CHECK-NEXT: blr 496; 497; CHECK-BE-LABEL: shwVecConv2qp6: 498; CHECK-BE: # %bb.0: # %entry 499; CHECK-BE-NEXT: vextractuh v2, v2, 12 500; CHECK-BE-NEXT: vextsh2d v2, v2 501; CHECK-BE-NEXT: xscvsdqp v2, v2 502; CHECK-BE-NEXT: stxv v2, 0(r3) 503; CHECK-BE-NEXT: blr 504entry: 505 %vecext = extractelement <8 x i16> %b, i32 6 506 %conv = sitofp i16 %vecext to fp128 507 store fp128 %conv, fp128* %a, align 16 508 ret void 509} 510 511; Function Attrs: norecurse nounwind 512define void @shwVecConv2qp7(fp128* nocapture %a, <8 x i16> %b) { 513; CHECK-LABEL: shwVecConv2qp7: 514; CHECK: # %bb.0: # %entry 515; CHECK-NEXT: vextractuh v2, v2, 0 516; CHECK-NEXT: vextsh2d v2, v2 517; CHECK-NEXT: xscvsdqp v2, v2 518; CHECK-NEXT: stxv v2, 0(r3) 519; CHECK-NEXT: blr 520; 521; CHECK-BE-LABEL: shwVecConv2qp7: 522; CHECK-BE: # %bb.0: # %entry 523; CHECK-BE-NEXT: vextractuh v2, v2, 14 524; CHECK-BE-NEXT: vextsh2d v2, v2 525; CHECK-BE-NEXT: xscvsdqp v2, v2 526; CHECK-BE-NEXT: stxv v2, 0(r3) 527; CHECK-BE-NEXT: blr 528entry: 529 %vecext = extractelement <8 x i16> %b, i32 7 530 %conv = sitofp i16 %vecext to fp128 531 store fp128 %conv, fp128* %a, align 16 532 ret void 533} 534 535; Function Attrs: norecurse nounwind 536define void @uhwVecConv2qp(fp128* nocapture %a, <8 x i16> %b) { 537; CHECK-LABEL: uhwVecConv2qp: 538; CHECK: # %bb.0: # %entry 539; CHECK-NEXT: vextractuh v2, v2, 14 540; CHECK-NEXT: xscvudqp v2, v2 541; CHECK-NEXT: stxv v2, 0(r3) 542; CHECK-NEXT: blr 543; 544; CHECK-BE-LABEL: uhwVecConv2qp: 545; CHECK-BE: # %bb.0: # %entry 546; CHECK-BE-NEXT: vextractuh v2, v2, 0 547; CHECK-BE-NEXT: xscvudqp v2, v2 548; CHECK-BE-NEXT: stxv v2, 0(r3) 549; CHECK-BE-NEXT: blr 550entry: 551 %vecext = extractelement <8 x i16> %b, i32 0 552 %conv = uitofp i16 %vecext to fp128 553 store fp128 %conv, fp128* %a, align 16 554 ret void 555} 556 557; Function Attrs: norecurse nounwind 558define void @uhwVecConv2qp1(fp128* nocapture %a, <8 x i16> %b) { 559; CHECK-LABEL: uhwVecConv2qp1: 560; CHECK: # %bb.0: # %entry 561; CHECK-NEXT: vextractuh v2, v2, 12 562; CHECK-NEXT: xscvudqp v2, v2 563; CHECK-NEXT: stxv v2, 0(r3) 564; CHECK-NEXT: blr 565; 566; CHECK-BE-LABEL: uhwVecConv2qp1: 567; CHECK-BE: # %bb.0: # %entry 568; CHECK-BE-NEXT: vextractuh v2, v2, 2 569; CHECK-BE-NEXT: xscvudqp v2, v2 570; CHECK-BE-NEXT: stxv v2, 0(r3) 571; CHECK-BE-NEXT: blr 572entry: 573 %vecext = extractelement <8 x i16> %b, i32 1 574 %conv = uitofp i16 %vecext to fp128 575 store fp128 %conv, fp128* %a, align 16 576 ret void 577} 578 579; Function Attrs: norecurse nounwind 580define void @uhwVecConv2qp2(fp128* nocapture %a, <8 x i16> %b) { 581; CHECK-LABEL: uhwVecConv2qp2: 582; CHECK: # %bb.0: # %entry 583; CHECK-NEXT: vextractuh v2, v2, 10 584; CHECK-NEXT: xscvudqp v2, v2 585; CHECK-NEXT: stxv v2, 0(r3) 586; CHECK-NEXT: blr 587; 588; CHECK-BE-LABEL: uhwVecConv2qp2: 589; CHECK-BE: # %bb.0: # %entry 590; CHECK-BE-NEXT: vextractuh v2, v2, 4 591; CHECK-BE-NEXT: xscvudqp v2, v2 592; CHECK-BE-NEXT: stxv v2, 0(r3) 593; CHECK-BE-NEXT: blr 594entry: 595 %vecext = extractelement <8 x i16> %b, i32 2 596 %conv = uitofp i16 %vecext to fp128 597 store fp128 %conv, fp128* %a, align 16 598 ret void 599} 600 601; Function Attrs: norecurse nounwind 602define void @uhwVecConv2qp3(fp128* nocapture %a, <8 x i16> %b) { 603; CHECK-LABEL: uhwVecConv2qp3: 604; CHECK: # %bb.0: # %entry 605; CHECK-NEXT: vextractuh v2, v2, 8 606; CHECK-NEXT: xscvudqp v2, v2 607; CHECK-NEXT: stxv v2, 0(r3) 608; CHECK-NEXT: blr 609; 610; CHECK-BE-LABEL: uhwVecConv2qp3: 611; CHECK-BE: # %bb.0: # %entry 612; CHECK-BE-NEXT: vextractuh v2, v2, 6 613; CHECK-BE-NEXT: xscvudqp v2, v2 614; CHECK-BE-NEXT: stxv v2, 0(r3) 615; CHECK-BE-NEXT: blr 616entry: 617 %vecext = extractelement <8 x i16> %b, i32 3 618 %conv = uitofp i16 %vecext to fp128 619 store fp128 %conv, fp128* %a, align 16 620 ret void 621} 622 623; Function Attrs: norecurse nounwind 624define void @uhwVecConv2qp4(fp128* nocapture %a, <8 x i16> %b) { 625; CHECK-LABEL: uhwVecConv2qp4: 626; CHECK: # %bb.0: # %entry 627; CHECK-NEXT: vextractuh v2, v2, 6 628; CHECK-NEXT: xscvudqp v2, v2 629; CHECK-NEXT: stxv v2, 0(r3) 630; CHECK-NEXT: blr 631; 632; CHECK-BE-LABEL: uhwVecConv2qp4: 633; CHECK-BE: # %bb.0: # %entry 634; CHECK-BE-NEXT: vextractuh v2, v2, 8 635; CHECK-BE-NEXT: xscvudqp v2, v2 636; CHECK-BE-NEXT: stxv v2, 0(r3) 637; CHECK-BE-NEXT: blr 638entry: 639 %vecext = extractelement <8 x i16> %b, i32 4 640 %conv = uitofp i16 %vecext to fp128 641 store fp128 %conv, fp128* %a, align 16 642 ret void 643} 644 645; Function Attrs: norecurse nounwind 646define void @uhwVecConv2qp5(fp128* nocapture %a, <8 x i16> %b) { 647; CHECK-LABEL: uhwVecConv2qp5: 648; CHECK: # %bb.0: # %entry 649; CHECK-NEXT: vextractuh v2, v2, 4 650; CHECK-NEXT: xscvudqp v2, v2 651; CHECK-NEXT: stxv v2, 0(r3) 652; CHECK-NEXT: blr 653; 654; CHECK-BE-LABEL: uhwVecConv2qp5: 655; CHECK-BE: # %bb.0: # %entry 656; CHECK-BE-NEXT: vextractuh v2, v2, 10 657; CHECK-BE-NEXT: xscvudqp v2, v2 658; CHECK-BE-NEXT: stxv v2, 0(r3) 659; CHECK-BE-NEXT: blr 660entry: 661 %vecext = extractelement <8 x i16> %b, i32 5 662 %conv = uitofp i16 %vecext to fp128 663 store fp128 %conv, fp128* %a, align 16 664 ret void 665} 666 667; Function Attrs: norecurse nounwind 668define void @uhwVecConv2qp6(fp128* nocapture %a, <8 x i16> %b) { 669; CHECK-LABEL: uhwVecConv2qp6: 670; CHECK: # %bb.0: # %entry 671; CHECK-NEXT: vextractuh v2, v2, 2 672; CHECK-NEXT: xscvudqp v2, v2 673; CHECK-NEXT: stxv v2, 0(r3) 674; CHECK-NEXT: blr 675; 676; CHECK-BE-LABEL: uhwVecConv2qp6: 677; CHECK-BE: # %bb.0: # %entry 678; CHECK-BE-NEXT: vextractuh v2, v2, 12 679; CHECK-BE-NEXT: xscvudqp v2, v2 680; CHECK-BE-NEXT: stxv v2, 0(r3) 681; CHECK-BE-NEXT: blr 682entry: 683 %vecext = extractelement <8 x i16> %b, i32 6 684 %conv = uitofp i16 %vecext to fp128 685 store fp128 %conv, fp128* %a, align 16 686 ret void 687} 688 689; Function Attrs: norecurse nounwind 690define void @uhwVecConv2qp7(fp128* nocapture %a, <8 x i16> %b) { 691; CHECK-LABEL: uhwVecConv2qp7: 692; CHECK: # %bb.0: # %entry 693; CHECK-NEXT: vextractuh v2, v2, 0 694; CHECK-NEXT: xscvudqp v2, v2 695; CHECK-NEXT: stxv v2, 0(r3) 696; CHECK-NEXT: blr 697; 698; CHECK-BE-LABEL: uhwVecConv2qp7: 699; CHECK-BE: # %bb.0: # %entry 700; CHECK-BE-NEXT: vextractuh v2, v2, 14 701; CHECK-BE-NEXT: xscvudqp v2, v2 702; CHECK-BE-NEXT: stxv v2, 0(r3) 703; CHECK-BE-NEXT: blr 704entry: 705 %vecext = extractelement <8 x i16> %b, i32 7 706 %conv = uitofp i16 %vecext to fp128 707 store fp128 %conv, fp128* %a, align 16 708 ret void 709} 710 711; Vector extract Byte and convert to quad precision. 712 713; Function Attrs: norecurse nounwind 714define void @sbVecConv2qp(fp128* nocapture %a, <16 x i8> %b) { 715; CHECK-LABEL: sbVecConv2qp: 716; CHECK: # %bb.0: # %entry 717; CHECK-NEXT: vextractub v2, v2, 15 718; CHECK-NEXT: vextsb2d v2, v2 719; CHECK-NEXT: xscvsdqp v2, v2 720; CHECK-NEXT: stxv v2, 0(r3) 721; CHECK-NEXT: blr 722; 723; CHECK-BE-LABEL: sbVecConv2qp: 724; CHECK-BE: # %bb.0: # %entry 725; CHECK-BE-NEXT: vextractub v2, v2, 0 726; CHECK-BE-NEXT: vextsb2d v2, v2 727; CHECK-BE-NEXT: xscvsdqp v2, v2 728; CHECK-BE-NEXT: stxv v2, 0(r3) 729; CHECK-BE-NEXT: blr 730entry: 731 %vecext = extractelement <16 x i8> %b, i32 0 732 %conv = sitofp i8 %vecext to fp128 733 store fp128 %conv, fp128* %a, align 16 734 ret void 735} 736 737; Function Attrs: norecurse nounwind 738define void @sbVecConv2qp1(fp128* nocapture %a, <16 x i8> %b) { 739; CHECK-LABEL: sbVecConv2qp1: 740; CHECK: # %bb.0: # %entry 741; CHECK-NEXT: vextractub v2, v2, 14 742; CHECK-NEXT: vextsb2d v2, v2 743; CHECK-NEXT: xscvsdqp v2, v2 744; CHECK-NEXT: stxv v2, 0(r3) 745; CHECK-NEXT: blr 746; 747; CHECK-BE-LABEL: sbVecConv2qp1: 748; CHECK-BE: # %bb.0: # %entry 749; CHECK-BE-NEXT: vextractub v2, v2, 1 750; CHECK-BE-NEXT: vextsb2d v2, v2 751; CHECK-BE-NEXT: xscvsdqp v2, v2 752; CHECK-BE-NEXT: stxv v2, 0(r3) 753; CHECK-BE-NEXT: blr 754entry: 755 %vecext = extractelement <16 x i8> %b, i32 1 756 %conv = sitofp i8 %vecext to fp128 757 store fp128 %conv, fp128* %a, align 16 758 ret void 759} 760 761; Function Attrs: norecurse nounwind 762define void @sbVecConv2qp2(fp128* nocapture %a, <16 x i8> %b) { 763; CHECK-LABEL: sbVecConv2qp2: 764; CHECK: # %bb.0: # %entry 765; CHECK-NEXT: vextractub v2, v2, 13 766; CHECK-NEXT: vextsb2d v2, v2 767; CHECK-NEXT: xscvsdqp v2, v2 768; CHECK-NEXT: stxv v2, 0(r3) 769; CHECK-NEXT: blr 770; 771; CHECK-BE-LABEL: sbVecConv2qp2: 772; CHECK-BE: # %bb.0: # %entry 773; CHECK-BE-NEXT: vextractub v2, v2, 2 774; CHECK-BE-NEXT: vextsb2d v2, v2 775; CHECK-BE-NEXT: xscvsdqp v2, v2 776; CHECK-BE-NEXT: stxv v2, 0(r3) 777; CHECK-BE-NEXT: blr 778entry: 779 %vecext = extractelement <16 x i8> %b, i32 2 780 %conv = sitofp i8 %vecext to fp128 781 store fp128 %conv, fp128* %a, align 16 782 ret void 783} 784 785; Function Attrs: norecurse nounwind 786define void @sbVecConv2qp3(fp128* nocapture %a, <16 x i8> %b) { 787; CHECK-LABEL: sbVecConv2qp3: 788; CHECK: # %bb.0: # %entry 789; CHECK-NEXT: vextractub v2, v2, 12 790; CHECK-NEXT: vextsb2d v2, v2 791; CHECK-NEXT: xscvsdqp v2, v2 792; CHECK-NEXT: stxv v2, 0(r3) 793; CHECK-NEXT: blr 794; 795; CHECK-BE-LABEL: sbVecConv2qp3: 796; CHECK-BE: # %bb.0: # %entry 797; CHECK-BE-NEXT: vextractub v2, v2, 3 798; CHECK-BE-NEXT: vextsb2d v2, v2 799; CHECK-BE-NEXT: xscvsdqp v2, v2 800; CHECK-BE-NEXT: stxv v2, 0(r3) 801; CHECK-BE-NEXT: blr 802entry: 803 %vecext = extractelement <16 x i8> %b, i32 3 804 %conv = sitofp i8 %vecext to fp128 805 store fp128 %conv, fp128* %a, align 16 806 ret void 807} 808 809; Function Attrs: norecurse nounwind 810define void @sbVecConv2qp4(fp128* nocapture %a, <16 x i8> %b) { 811; CHECK-LABEL: sbVecConv2qp4: 812; CHECK: # %bb.0: # %entry 813; CHECK-NEXT: vextractub v2, v2, 11 814; CHECK-NEXT: vextsb2d v2, v2 815; CHECK-NEXT: xscvsdqp v2, v2 816; CHECK-NEXT: stxv v2, 0(r3) 817; CHECK-NEXT: blr 818; 819; CHECK-BE-LABEL: sbVecConv2qp4: 820; CHECK-BE: # %bb.0: # %entry 821; CHECK-BE-NEXT: vextractub v2, v2, 4 822; CHECK-BE-NEXT: vextsb2d v2, v2 823; CHECK-BE-NEXT: xscvsdqp v2, v2 824; CHECK-BE-NEXT: stxv v2, 0(r3) 825; CHECK-BE-NEXT: blr 826entry: 827 %vecext = extractelement <16 x i8> %b, i32 4 828 %conv = sitofp i8 %vecext to fp128 829 store fp128 %conv, fp128* %a, align 16 830 ret void 831} 832 833; Function Attrs: norecurse nounwind 834define void @sbVecConv2qp5(fp128* nocapture %a, <16 x i8> %b) { 835; CHECK-LABEL: sbVecConv2qp5: 836; CHECK: # %bb.0: # %entry 837; CHECK-NEXT: vextractub v2, v2, 10 838; CHECK-NEXT: vextsb2d v2, v2 839; CHECK-NEXT: xscvsdqp v2, v2 840; CHECK-NEXT: stxv v2, 0(r3) 841; CHECK-NEXT: blr 842; 843; CHECK-BE-LABEL: sbVecConv2qp5: 844; CHECK-BE: # %bb.0: # %entry 845; CHECK-BE-NEXT: vextractub v2, v2, 5 846; CHECK-BE-NEXT: vextsb2d v2, v2 847; CHECK-BE-NEXT: xscvsdqp v2, v2 848; CHECK-BE-NEXT: stxv v2, 0(r3) 849; CHECK-BE-NEXT: blr 850entry: 851 %vecext = extractelement <16 x i8> %b, i32 5 852 %conv = sitofp i8 %vecext to fp128 853 store fp128 %conv, fp128* %a, align 16 854 ret void 855} 856 857; Function Attrs: norecurse nounwind 858define void @sbVecConv2qp6(fp128* nocapture %a, <16 x i8> %b) { 859; CHECK-LABEL: sbVecConv2qp6: 860; CHECK: # %bb.0: # %entry 861; CHECK-NEXT: vextractub v2, v2, 9 862; CHECK-NEXT: vextsb2d v2, v2 863; CHECK-NEXT: xscvsdqp v2, v2 864; CHECK-NEXT: stxv v2, 0(r3) 865; CHECK-NEXT: blr 866; 867; CHECK-BE-LABEL: sbVecConv2qp6: 868; CHECK-BE: # %bb.0: # %entry 869; CHECK-BE-NEXT: vextractub v2, v2, 6 870; CHECK-BE-NEXT: vextsb2d v2, v2 871; CHECK-BE-NEXT: xscvsdqp v2, v2 872; CHECK-BE-NEXT: stxv v2, 0(r3) 873; CHECK-BE-NEXT: blr 874entry: 875 %vecext = extractelement <16 x i8> %b, i32 6 876 %conv = sitofp i8 %vecext to fp128 877 store fp128 %conv, fp128* %a, align 16 878 ret void 879} 880 881; Function Attrs: norecurse nounwind 882define void @sbVecConv2qp7(fp128* nocapture %a, <16 x i8> %b) { 883; CHECK-LABEL: sbVecConv2qp7: 884; CHECK: # %bb.0: # %entry 885; CHECK-NEXT: vextractub v2, v2, 8 886; CHECK-NEXT: vextsb2d v2, v2 887; CHECK-NEXT: xscvsdqp v2, v2 888; CHECK-NEXT: stxv v2, 0(r3) 889; CHECK-NEXT: blr 890; 891; CHECK-BE-LABEL: sbVecConv2qp7: 892; CHECK-BE: # %bb.0: # %entry 893; CHECK-BE-NEXT: vextractub v2, v2, 7 894; CHECK-BE-NEXT: vextsb2d v2, v2 895; CHECK-BE-NEXT: xscvsdqp v2, v2 896; CHECK-BE-NEXT: stxv v2, 0(r3) 897; CHECK-BE-NEXT: blr 898entry: 899 %vecext = extractelement <16 x i8> %b, i32 7 900 %conv = sitofp i8 %vecext to fp128 901 store fp128 %conv, fp128* %a, align 16 902 ret void 903} 904 905; Function Attrs: norecurse nounwind 906define void @sbVecConv2qp8(fp128* nocapture %a, <16 x i8> %b) { 907; CHECK-LABEL: sbVecConv2qp8: 908; CHECK: # %bb.0: # %entry 909; CHECK-NEXT: vextractub v2, v2, 7 910; CHECK-NEXT: vextsb2d v2, v2 911; CHECK-NEXT: xscvsdqp v2, v2 912; CHECK-NEXT: stxv v2, 0(r3) 913; CHECK-NEXT: blr 914; 915; CHECK-BE-LABEL: sbVecConv2qp8: 916; CHECK-BE: # %bb.0: # %entry 917; CHECK-BE-NEXT: vextractub v2, v2, 8 918; CHECK-BE-NEXT: vextsb2d v2, v2 919; CHECK-BE-NEXT: xscvsdqp v2, v2 920; CHECK-BE-NEXT: stxv v2, 0(r3) 921; CHECK-BE-NEXT: blr 922entry: 923 %vecext = extractelement <16 x i8> %b, i32 8 924 %conv = sitofp i8 %vecext to fp128 925 store fp128 %conv, fp128* %a, align 16 926 ret void 927} 928 929; Function Attrs: norecurse nounwind 930define void @sbVecConv2qp9(fp128* nocapture %a, <16 x i8> %b) { 931; CHECK-LABEL: sbVecConv2qp9: 932; CHECK: # %bb.0: # %entry 933; CHECK-NEXT: vextractub v2, v2, 6 934; CHECK-NEXT: vextsb2d v2, v2 935; CHECK-NEXT: xscvsdqp v2, v2 936; CHECK-NEXT: stxv v2, 0(r3) 937; CHECK-NEXT: blr 938; 939; CHECK-BE-LABEL: sbVecConv2qp9: 940; CHECK-BE: # %bb.0: # %entry 941; CHECK-BE-NEXT: vextractub v2, v2, 9 942; CHECK-BE-NEXT: vextsb2d v2, v2 943; CHECK-BE-NEXT: xscvsdqp v2, v2 944; CHECK-BE-NEXT: stxv v2, 0(r3) 945; CHECK-BE-NEXT: blr 946entry: 947 %vecext = extractelement <16 x i8> %b, i32 9 948 %conv = sitofp i8 %vecext to fp128 949 store fp128 %conv, fp128* %a, align 16 950 ret void 951} 952 953; Function Attrs: norecurse nounwind 954define void @sbVecConv2qp10(fp128* nocapture %a, <16 x i8> %b) { 955; CHECK-LABEL: sbVecConv2qp10: 956; CHECK: # %bb.0: # %entry 957; CHECK-NEXT: vextractub v2, v2, 5 958; CHECK-NEXT: vextsb2d v2, v2 959; CHECK-NEXT: xscvsdqp v2, v2 960; CHECK-NEXT: stxv v2, 0(r3) 961; CHECK-NEXT: blr 962; 963; CHECK-BE-LABEL: sbVecConv2qp10: 964; CHECK-BE: # %bb.0: # %entry 965; CHECK-BE-NEXT: vextractub v2, v2, 10 966; CHECK-BE-NEXT: vextsb2d v2, v2 967; CHECK-BE-NEXT: xscvsdqp v2, v2 968; CHECK-BE-NEXT: stxv v2, 0(r3) 969; CHECK-BE-NEXT: blr 970entry: 971 %vecext = extractelement <16 x i8> %b, i32 10 972 %conv = sitofp i8 %vecext to fp128 973 store fp128 %conv, fp128* %a, align 16 974 ret void 975} 976 977; Function Attrs: norecurse nounwind 978define void @sbVecConv2qp11(fp128* nocapture %a, <16 x i8> %b) { 979; CHECK-LABEL: sbVecConv2qp11: 980; CHECK: # %bb.0: # %entry 981; CHECK-NEXT: vextractub v2, v2, 4 982; CHECK-NEXT: vextsb2d v2, v2 983; CHECK-NEXT: xscvsdqp v2, v2 984; CHECK-NEXT: stxv v2, 0(r3) 985; CHECK-NEXT: blr 986; 987; CHECK-BE-LABEL: sbVecConv2qp11: 988; CHECK-BE: # %bb.0: # %entry 989; CHECK-BE-NEXT: vextractub v2, v2, 11 990; CHECK-BE-NEXT: vextsb2d v2, v2 991; CHECK-BE-NEXT: xscvsdqp v2, v2 992; CHECK-BE-NEXT: stxv v2, 0(r3) 993; CHECK-BE-NEXT: blr 994entry: 995 %vecext = extractelement <16 x i8> %b, i32 11 996 %conv = sitofp i8 %vecext to fp128 997 store fp128 %conv, fp128* %a, align 16 998 ret void 999} 1000 1001; Function Attrs: norecurse nounwind 1002define void @sbVecConv2qp12(fp128* nocapture %a, <16 x i8> %b) { 1003; CHECK-LABEL: sbVecConv2qp12: 1004; CHECK: # %bb.0: # %entry 1005; CHECK-NEXT: vextractub v2, v2, 3 1006; CHECK-NEXT: vextsb2d v2, v2 1007; CHECK-NEXT: xscvsdqp v2, v2 1008; CHECK-NEXT: stxv v2, 0(r3) 1009; CHECK-NEXT: blr 1010; 1011; CHECK-BE-LABEL: sbVecConv2qp12: 1012; CHECK-BE: # %bb.0: # %entry 1013; CHECK-BE-NEXT: vextractub v2, v2, 12 1014; CHECK-BE-NEXT: vextsb2d v2, v2 1015; CHECK-BE-NEXT: xscvsdqp v2, v2 1016; CHECK-BE-NEXT: stxv v2, 0(r3) 1017; CHECK-BE-NEXT: blr 1018entry: 1019 %vecext = extractelement <16 x i8> %b, i32 12 1020 %conv = sitofp i8 %vecext to fp128 1021 store fp128 %conv, fp128* %a, align 16 1022 ret void 1023} 1024 1025; Function Attrs: norecurse nounwind 1026define void @sbVecConv2qp13(fp128* nocapture %a, <16 x i8> %b) { 1027; CHECK-LABEL: sbVecConv2qp13: 1028; CHECK: # %bb.0: # %entry 1029; CHECK-NEXT: vextractub v2, v2, 2 1030; CHECK-NEXT: vextsb2d v2, v2 1031; CHECK-NEXT: xscvsdqp v2, v2 1032; CHECK-NEXT: stxv v2, 0(r3) 1033; CHECK-NEXT: blr 1034; 1035; CHECK-BE-LABEL: sbVecConv2qp13: 1036; CHECK-BE: # %bb.0: # %entry 1037; CHECK-BE-NEXT: vextractub v2, v2, 13 1038; CHECK-BE-NEXT: vextsb2d v2, v2 1039; CHECK-BE-NEXT: xscvsdqp v2, v2 1040; CHECK-BE-NEXT: stxv v2, 0(r3) 1041; CHECK-BE-NEXT: blr 1042entry: 1043 %vecext = extractelement <16 x i8> %b, i32 13 1044 %conv = sitofp i8 %vecext to fp128 1045 store fp128 %conv, fp128* %a, align 16 1046 ret void 1047} 1048 1049; Function Attrs: norecurse nounwind 1050define void @sbVecConv2qp14(fp128* nocapture %a, <16 x i8> %b) { 1051; CHECK-LABEL: sbVecConv2qp14: 1052; CHECK: # %bb.0: # %entry 1053; CHECK-NEXT: vextractub v2, v2, 1 1054; CHECK-NEXT: vextsb2d v2, v2 1055; CHECK-NEXT: xscvsdqp v2, v2 1056; CHECK-NEXT: stxv v2, 0(r3) 1057; CHECK-NEXT: blr 1058; 1059; CHECK-BE-LABEL: sbVecConv2qp14: 1060; CHECK-BE: # %bb.0: # %entry 1061; CHECK-BE-NEXT: vextractub v2, v2, 14 1062; CHECK-BE-NEXT: vextsb2d v2, v2 1063; CHECK-BE-NEXT: xscvsdqp v2, v2 1064; CHECK-BE-NEXT: stxv v2, 0(r3) 1065; CHECK-BE-NEXT: blr 1066entry: 1067 %vecext = extractelement <16 x i8> %b, i32 14 1068 %conv = sitofp i8 %vecext to fp128 1069 store fp128 %conv, fp128* %a, align 16 1070 ret void 1071} 1072 1073; Function Attrs: norecurse nounwind 1074define void @sbVecConv2qp15(fp128* nocapture %a, <16 x i8> %b) { 1075; CHECK-LABEL: sbVecConv2qp15: 1076; CHECK: # %bb.0: # %entry 1077; CHECK-NEXT: vextractub v2, v2, 0 1078; CHECK-NEXT: vextsb2d v2, v2 1079; CHECK-NEXT: xscvsdqp v2, v2 1080; CHECK-NEXT: stxv v2, 0(r3) 1081; CHECK-NEXT: blr 1082; 1083; CHECK-BE-LABEL: sbVecConv2qp15: 1084; CHECK-BE: # %bb.0: # %entry 1085; CHECK-BE-NEXT: vextractub v2, v2, 15 1086; CHECK-BE-NEXT: vextsb2d v2, v2 1087; CHECK-BE-NEXT: xscvsdqp v2, v2 1088; CHECK-BE-NEXT: stxv v2, 0(r3) 1089; CHECK-BE-NEXT: blr 1090entry: 1091 %vecext = extractelement <16 x i8> %b, i32 15 1092 %conv = sitofp i8 %vecext to fp128 1093 store fp128 %conv, fp128* %a, align 16 1094 ret void 1095} 1096 1097; Function Attrs: norecurse nounwind 1098define void @ubVecConv2qp(fp128* nocapture %a, <16 x i8> %b) { 1099; CHECK-LABEL: ubVecConv2qp: 1100; CHECK: # %bb.0: # %entry 1101; CHECK-NEXT: vextractub v2, v2, 15 1102; CHECK-NEXT: xscvudqp v2, v2 1103; CHECK-NEXT: stxv v2, 0(r3) 1104; CHECK-NEXT: blr 1105; 1106; CHECK-BE-LABEL: ubVecConv2qp: 1107; CHECK-BE: # %bb.0: # %entry 1108; CHECK-BE-NEXT: vextractub v2, v2, 0 1109; CHECK-BE-NEXT: xscvudqp v2, v2 1110; CHECK-BE-NEXT: stxv v2, 0(r3) 1111; CHECK-BE-NEXT: blr 1112entry: 1113 %vecext = extractelement <16 x i8> %b, i32 0 1114 %conv = uitofp i8 %vecext to fp128 1115 store fp128 %conv, fp128* %a, align 16 1116 ret void 1117} 1118 1119; Function Attrs: norecurse nounwind 1120define void @ubVecConv2qp1(fp128* nocapture %a, <16 x i8> %b) { 1121; CHECK-LABEL: ubVecConv2qp1: 1122; CHECK: # %bb.0: # %entry 1123; CHECK-NEXT: vextractub v2, v2, 14 1124; CHECK-NEXT: xscvudqp v2, v2 1125; CHECK-NEXT: stxv v2, 0(r3) 1126; CHECK-NEXT: blr 1127; 1128; CHECK-BE-LABEL: ubVecConv2qp1: 1129; CHECK-BE: # %bb.0: # %entry 1130; CHECK-BE-NEXT: vextractub v2, v2, 1 1131; CHECK-BE-NEXT: xscvudqp v2, v2 1132; CHECK-BE-NEXT: stxv v2, 0(r3) 1133; CHECK-BE-NEXT: blr 1134entry: 1135 %vecext = extractelement <16 x i8> %b, i32 1 1136 %conv = uitofp i8 %vecext to fp128 1137 store fp128 %conv, fp128* %a, align 16 1138 ret void 1139} 1140 1141; Function Attrs: norecurse nounwind 1142define void @ubVecConv2qp2(fp128* nocapture %a, <16 x i8> %b) { 1143; CHECK-LABEL: ubVecConv2qp2: 1144; CHECK: # %bb.0: # %entry 1145; CHECK-NEXT: vextractub v2, v2, 13 1146; CHECK-NEXT: xscvudqp v2, v2 1147; CHECK-NEXT: stxv v2, 0(r3) 1148; CHECK-NEXT: blr 1149; 1150; CHECK-BE-LABEL: ubVecConv2qp2: 1151; CHECK-BE: # %bb.0: # %entry 1152; CHECK-BE-NEXT: vextractub v2, v2, 2 1153; CHECK-BE-NEXT: xscvudqp v2, v2 1154; CHECK-BE-NEXT: stxv v2, 0(r3) 1155; CHECK-BE-NEXT: blr 1156entry: 1157 %vecext = extractelement <16 x i8> %b, i32 2 1158 %conv = uitofp i8 %vecext to fp128 1159 store fp128 %conv, fp128* %a, align 16 1160 ret void 1161} 1162 1163; Function Attrs: norecurse nounwind 1164define void @ubVecConv2qp3(fp128* nocapture %a, <16 x i8> %b) { 1165; CHECK-LABEL: ubVecConv2qp3: 1166; CHECK: # %bb.0: # %entry 1167; CHECK-NEXT: vextractub v2, v2, 12 1168; CHECK-NEXT: xscvudqp v2, v2 1169; CHECK-NEXT: stxv v2, 0(r3) 1170; CHECK-NEXT: blr 1171; 1172; CHECK-BE-LABEL: ubVecConv2qp3: 1173; CHECK-BE: # %bb.0: # %entry 1174; CHECK-BE-NEXT: vextractub v2, v2, 3 1175; CHECK-BE-NEXT: xscvudqp v2, v2 1176; CHECK-BE-NEXT: stxv v2, 0(r3) 1177; CHECK-BE-NEXT: blr 1178entry: 1179 %vecext = extractelement <16 x i8> %b, i32 3 1180 %conv = uitofp i8 %vecext to fp128 1181 store fp128 %conv, fp128* %a, align 16 1182 ret void 1183} 1184 1185; Function Attrs: norecurse nounwind 1186define void @ubVecConv2qp4(fp128* nocapture %a, <16 x i8> %b) { 1187; CHECK-LABEL: ubVecConv2qp4: 1188; CHECK: # %bb.0: # %entry 1189; CHECK-NEXT: vextractub v2, v2, 11 1190; CHECK-NEXT: xscvudqp v2, v2 1191; CHECK-NEXT: stxv v2, 0(r3) 1192; CHECK-NEXT: blr 1193; 1194; CHECK-BE-LABEL: ubVecConv2qp4: 1195; CHECK-BE: # %bb.0: # %entry 1196; CHECK-BE-NEXT: vextractub v2, v2, 4 1197; CHECK-BE-NEXT: xscvudqp v2, v2 1198; CHECK-BE-NEXT: stxv v2, 0(r3) 1199; CHECK-BE-NEXT: blr 1200entry: 1201 %vecext = extractelement <16 x i8> %b, i32 4 1202 %conv = uitofp i8 %vecext to fp128 1203 store fp128 %conv, fp128* %a, align 16 1204 ret void 1205} 1206 1207; Function Attrs: norecurse nounwind 1208define void @ubVecConv2qp5(fp128* nocapture %a, <16 x i8> %b) { 1209; CHECK-LABEL: ubVecConv2qp5: 1210; CHECK: # %bb.0: # %entry 1211; CHECK-NEXT: vextractub v2, v2, 10 1212; CHECK-NEXT: xscvudqp v2, v2 1213; CHECK-NEXT: stxv v2, 0(r3) 1214; CHECK-NEXT: blr 1215; 1216; CHECK-BE-LABEL: ubVecConv2qp5: 1217; CHECK-BE: # %bb.0: # %entry 1218; CHECK-BE-NEXT: vextractub v2, v2, 5 1219; CHECK-BE-NEXT: xscvudqp v2, v2 1220; CHECK-BE-NEXT: stxv v2, 0(r3) 1221; CHECK-BE-NEXT: blr 1222entry: 1223 %vecext = extractelement <16 x i8> %b, i32 5 1224 %conv = uitofp i8 %vecext to fp128 1225 store fp128 %conv, fp128* %a, align 16 1226 ret void 1227} 1228 1229; Function Attrs: norecurse nounwind 1230define void @ubVecConv2qp6(fp128* nocapture %a, <16 x i8> %b) { 1231; CHECK-LABEL: ubVecConv2qp6: 1232; CHECK: # %bb.0: # %entry 1233; CHECK-NEXT: vextractub v2, v2, 9 1234; CHECK-NEXT: xscvudqp v2, v2 1235; CHECK-NEXT: stxv v2, 0(r3) 1236; CHECK-NEXT: blr 1237; 1238; CHECK-BE-LABEL: ubVecConv2qp6: 1239; CHECK-BE: # %bb.0: # %entry 1240; CHECK-BE-NEXT: vextractub v2, v2, 6 1241; CHECK-BE-NEXT: xscvudqp v2, v2 1242; CHECK-BE-NEXT: stxv v2, 0(r3) 1243; CHECK-BE-NEXT: blr 1244entry: 1245 %vecext = extractelement <16 x i8> %b, i32 6 1246 %conv = uitofp i8 %vecext to fp128 1247 store fp128 %conv, fp128* %a, align 16 1248 ret void 1249} 1250 1251; Function Attrs: norecurse nounwind 1252define void @ubVecConv2qp7(fp128* nocapture %a, <16 x i8> %b) { 1253; CHECK-LABEL: ubVecConv2qp7: 1254; CHECK: # %bb.0: # %entry 1255; CHECK-NEXT: vextractub v2, v2, 8 1256; CHECK-NEXT: xscvudqp v2, v2 1257; CHECK-NEXT: stxv v2, 0(r3) 1258; CHECK-NEXT: blr 1259; 1260; CHECK-BE-LABEL: ubVecConv2qp7: 1261; CHECK-BE: # %bb.0: # %entry 1262; CHECK-BE-NEXT: vextractub v2, v2, 7 1263; CHECK-BE-NEXT: xscvudqp v2, v2 1264; CHECK-BE-NEXT: stxv v2, 0(r3) 1265; CHECK-BE-NEXT: blr 1266entry: 1267 %vecext = extractelement <16 x i8> %b, i32 7 1268 %conv = uitofp i8 %vecext to fp128 1269 store fp128 %conv, fp128* %a, align 16 1270 ret void 1271} 1272 1273; Function Attrs: norecurse nounwind 1274define void @ubVecConv2qp8(fp128* nocapture %a, <16 x i8> %b) { 1275; CHECK-LABEL: ubVecConv2qp8: 1276; CHECK: # %bb.0: # %entry 1277; CHECK-NEXT: vextractub v2, v2, 7 1278; CHECK-NEXT: xscvudqp v2, v2 1279; CHECK-NEXT: stxv v2, 0(r3) 1280; CHECK-NEXT: blr 1281; 1282; CHECK-BE-LABEL: ubVecConv2qp8: 1283; CHECK-BE: # %bb.0: # %entry 1284; CHECK-BE-NEXT: vextractub v2, v2, 8 1285; CHECK-BE-NEXT: xscvudqp v2, v2 1286; CHECK-BE-NEXT: stxv v2, 0(r3) 1287; CHECK-BE-NEXT: blr 1288entry: 1289 %vecext = extractelement <16 x i8> %b, i32 8 1290 %conv = uitofp i8 %vecext to fp128 1291 store fp128 %conv, fp128* %a, align 16 1292 ret void 1293} 1294 1295; Function Attrs: norecurse nounwind 1296define void @ubVecConv2qp9(fp128* nocapture %a, <16 x i8> %b) { 1297; CHECK-LABEL: ubVecConv2qp9: 1298; CHECK: # %bb.0: # %entry 1299; CHECK-NEXT: vextractub v2, v2, 6 1300; CHECK-NEXT: xscvudqp v2, v2 1301; CHECK-NEXT: stxv v2, 0(r3) 1302; CHECK-NEXT: blr 1303; 1304; CHECK-BE-LABEL: ubVecConv2qp9: 1305; CHECK-BE: # %bb.0: # %entry 1306; CHECK-BE-NEXT: vextractub v2, v2, 9 1307; CHECK-BE-NEXT: xscvudqp v2, v2 1308; CHECK-BE-NEXT: stxv v2, 0(r3) 1309; CHECK-BE-NEXT: blr 1310entry: 1311 %vecext = extractelement <16 x i8> %b, i32 9 1312 %conv = uitofp i8 %vecext to fp128 1313 store fp128 %conv, fp128* %a, align 16 1314 ret void 1315} 1316 1317; Function Attrs: norecurse nounwind 1318define void @ubVecConv2qp10(fp128* nocapture %a, <16 x i8> %b) { 1319; CHECK-LABEL: ubVecConv2qp10: 1320; CHECK: # %bb.0: # %entry 1321; CHECK-NEXT: vextractub v2, v2, 5 1322; CHECK-NEXT: xscvudqp v2, v2 1323; CHECK-NEXT: stxv v2, 0(r3) 1324; CHECK-NEXT: blr 1325; 1326; CHECK-BE-LABEL: ubVecConv2qp10: 1327; CHECK-BE: # %bb.0: # %entry 1328; CHECK-BE-NEXT: vextractub v2, v2, 10 1329; CHECK-BE-NEXT: xscvudqp v2, v2 1330; CHECK-BE-NEXT: stxv v2, 0(r3) 1331; CHECK-BE-NEXT: blr 1332entry: 1333 %vecext = extractelement <16 x i8> %b, i32 10 1334 %conv = uitofp i8 %vecext to fp128 1335 store fp128 %conv, fp128* %a, align 16 1336 ret void 1337} 1338 1339; Function Attrs: norecurse nounwind 1340define void @ubVecConv2qp11(fp128* nocapture %a, <16 x i8> %b) { 1341; CHECK-LABEL: ubVecConv2qp11: 1342; CHECK: # %bb.0: # %entry 1343; CHECK-NEXT: vextractub v2, v2, 4 1344; CHECK-NEXT: xscvudqp v2, v2 1345; CHECK-NEXT: stxv v2, 0(r3) 1346; CHECK-NEXT: blr 1347; 1348; CHECK-BE-LABEL: ubVecConv2qp11: 1349; CHECK-BE: # %bb.0: # %entry 1350; CHECK-BE-NEXT: vextractub v2, v2, 11 1351; CHECK-BE-NEXT: xscvudqp v2, v2 1352; CHECK-BE-NEXT: stxv v2, 0(r3) 1353; CHECK-BE-NEXT: blr 1354entry: 1355 %vecext = extractelement <16 x i8> %b, i32 11 1356 %conv = uitofp i8 %vecext to fp128 1357 store fp128 %conv, fp128* %a, align 16 1358 ret void 1359} 1360 1361; Function Attrs: norecurse nounwind 1362define void @ubVecConv2qp12(fp128* nocapture %a, <16 x i8> %b) { 1363; CHECK-LABEL: ubVecConv2qp12: 1364; CHECK: # %bb.0: # %entry 1365; CHECK-NEXT: vextractub v2, v2, 3 1366; CHECK-NEXT: xscvudqp v2, v2 1367; CHECK-NEXT: stxv v2, 0(r3) 1368; CHECK-NEXT: blr 1369; 1370; CHECK-BE-LABEL: ubVecConv2qp12: 1371; CHECK-BE: # %bb.0: # %entry 1372; CHECK-BE-NEXT: vextractub v2, v2, 12 1373; CHECK-BE-NEXT: xscvudqp v2, v2 1374; CHECK-BE-NEXT: stxv v2, 0(r3) 1375; CHECK-BE-NEXT: blr 1376entry: 1377 %vecext = extractelement <16 x i8> %b, i32 12 1378 %conv = uitofp i8 %vecext to fp128 1379 store fp128 %conv, fp128* %a, align 16 1380 ret void 1381} 1382 1383; Function Attrs: norecurse nounwind 1384define void @ubVecConv2qp13(fp128* nocapture %a, <16 x i8> %b) { 1385; CHECK-LABEL: ubVecConv2qp13: 1386; CHECK: # %bb.0: # %entry 1387; CHECK-NEXT: vextractub v2, v2, 2 1388; CHECK-NEXT: xscvudqp v2, v2 1389; CHECK-NEXT: stxv v2, 0(r3) 1390; CHECK-NEXT: blr 1391; 1392; CHECK-BE-LABEL: ubVecConv2qp13: 1393; CHECK-BE: # %bb.0: # %entry 1394; CHECK-BE-NEXT: vextractub v2, v2, 13 1395; CHECK-BE-NEXT: xscvudqp v2, v2 1396; CHECK-BE-NEXT: stxv v2, 0(r3) 1397; CHECK-BE-NEXT: blr 1398entry: 1399 %vecext = extractelement <16 x i8> %b, i32 13 1400 %conv = uitofp i8 %vecext to fp128 1401 store fp128 %conv, fp128* %a, align 16 1402 ret void 1403} 1404 1405; Function Attrs: norecurse nounwind 1406define void @ubVecConv2qp14(fp128* nocapture %a, <16 x i8> %b) { 1407; CHECK-LABEL: ubVecConv2qp14: 1408; CHECK: # %bb.0: # %entry 1409; CHECK-NEXT: vextractub v2, v2, 1 1410; CHECK-NEXT: xscvudqp v2, v2 1411; CHECK-NEXT: stxv v2, 0(r3) 1412; CHECK-NEXT: blr 1413; 1414; CHECK-BE-LABEL: ubVecConv2qp14: 1415; CHECK-BE: # %bb.0: # %entry 1416; CHECK-BE-NEXT: vextractub v2, v2, 14 1417; CHECK-BE-NEXT: xscvudqp v2, v2 1418; CHECK-BE-NEXT: stxv v2, 0(r3) 1419; CHECK-BE-NEXT: blr 1420entry: 1421 %vecext = extractelement <16 x i8> %b, i32 14 1422 %conv = uitofp i8 %vecext to fp128 1423 store fp128 %conv, fp128* %a, align 16 1424 ret void 1425} 1426 1427; Function Attrs: norecurse nounwind 1428define void @ubVecConv2qp15(fp128* nocapture %a, <16 x i8> %b) { 1429; CHECK-LABEL: ubVecConv2qp15: 1430; CHECK: # %bb.0: # %entry 1431; CHECK-NEXT: vextractub v2, v2, 0 1432; CHECK-NEXT: xscvudqp v2, v2 1433; CHECK-NEXT: stxv v2, 0(r3) 1434; CHECK-NEXT: blr 1435; 1436; CHECK-BE-LABEL: ubVecConv2qp15: 1437; CHECK-BE: # %bb.0: # %entry 1438; CHECK-BE-NEXT: vextractub v2, v2, 15 1439; CHECK-BE-NEXT: xscvudqp v2, v2 1440; CHECK-BE-NEXT: stxv v2, 0(r3) 1441; CHECK-BE-NEXT: blr 1442entry: 1443 %vecext = extractelement <16 x i8> %b, i32 15 1444 %conv = uitofp i8 %vecext to fp128 1445 store fp128 %conv, fp128* %a, align 16 1446 ret void 1447} 1448