1 /*-
2 * Copyright (c) 2001 Alcove - Nicolas Souchu
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/isa/ppc.c,v 1.26.2.5 2001/10/02 05:21:45 nsouch Exp $
27 */
28
29 #include "opt_ppc.h"
30 #ifndef PPC_DEBUG
31 #define PPC_DEBUG 0
32 #endif
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/bus.h>
38 #include <sys/malloc.h>
39 #include <sys/rman.h>
40 #include <sys/thread2.h>
41
42 #include <vm/vm.h>
43 #include <vm/pmap.h>
44 #include <machine/clock.h>
45 #include <machine/vmparam.h>
46
47 #include <bus/isa/isareg.h>
48 #include <bus/isa/isavar.h>
49
50 #include <bus/ppbus/ppbconf.h>
51 #include <bus/ppbus/ppb_msq.h>
52
53 #include "ppcreg.h"
54
55 #include "ppbus_if.h"
56
57 #define LOG_PPC(function, ppc, string) \
58 if (bootverbose) kprintf("%s: %s\n", function, string)
59
60
61 #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev))
62
63 devclass_t ppc_devclass;
64
65 static int ppc_probe(device_t dev);
66 static int ppc_attach(device_t dev);
67 static int ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val);
68
69 static void ppc_reset_epp(device_t);
70 static void ppc_ecp_sync(device_t);
71 static void ppcintr(void *arg);
72
73 static int ppc_exec_microseq(device_t, struct ppb_microseq **);
74 static int ppc_setmode(device_t, int);
75
76 static int ppc_read(device_t, char *, int, int);
77 static int ppc_write(device_t, char *, int, int);
78
79 static u_char ppc_io(device_t, int, u_char *, int, u_char);
80
81 static int ppc_setup_intr(device_t, device_t, struct resource *, int,
82 void (*)(void *), void *, void **, lwkt_serialize_t);
83 static int ppc_teardown_intr(device_t, device_t, struct resource *, void *);
84
85 static device_method_t ppc_methods[] = {
86 /* device interface */
87 DEVMETHOD(device_probe, ppc_probe),
88 DEVMETHOD(device_attach, ppc_attach),
89
90 /* bus interface */
91 DEVMETHOD(bus_read_ivar, ppc_read_ivar),
92 DEVMETHOD(bus_setup_intr, ppc_setup_intr),
93 DEVMETHOD(bus_teardown_intr, ppc_teardown_intr),
94 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
95
96 /* ppbus interface */
97 DEVMETHOD(ppbus_io, ppc_io),
98 DEVMETHOD(ppbus_exec_microseq, ppc_exec_microseq),
99 DEVMETHOD(ppbus_reset_epp, ppc_reset_epp),
100 DEVMETHOD(ppbus_setmode, ppc_setmode),
101 DEVMETHOD(ppbus_ecp_sync, ppc_ecp_sync),
102 DEVMETHOD(ppbus_read, ppc_read),
103 DEVMETHOD(ppbus_write, ppc_write),
104
105 DEVMETHOD_END
106 };
107
108 static driver_t ppc_driver = {
109 "ppc",
110 ppc_methods,
111 sizeof(struct ppc_data),
112 };
113
114 static char *ppc_models[] = {
115 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
116 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334",
117 "SMC FDC37C935", "PC87303", 0
118 };
119
120 /* list of available modes */
121 static char *ppc_avms[] = {
122 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
123 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
124 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP",
125 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0
126 };
127
128 /* list of current executing modes
129 * Note that few modes do not actually exist.
130 */
131 static char *ppc_modes[] = {
132 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP",
133 "EPP", "EPP", "EPP", "ECP",
134 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP",
135 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0
136 };
137
138 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 };
139
140 #ifdef __i386__
141 /*
142 * BIOS printer list - used by BIOS probe.
143 */
144 #define BIOS_PPC_PORTS 0x408
145 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS)
146 #define BIOS_MAX_PPC 4
147 #endif
148
149 /*
150 * ppc_ecp_sync() XXX
151 */
152 static void
ppc_ecp_sync(device_t dev)153 ppc_ecp_sync(device_t dev)
154 {
155 int i, r;
156 struct ppc_data *ppc = DEVTOSOFTC(dev);
157
158 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP))
159 return;
160
161 r = r_ecr(ppc);
162 if ((r & 0xe0) != PPC_ECR_EPP)
163 return;
164
165 for (i = 0; i < 100; i++) {
166 r = r_ecr(ppc);
167 if (r & 0x1)
168 return;
169 DELAY(100);
170 }
171
172 kprintf("ppc%d: ECP sync failed as data still " \
173 "present in FIFO.\n", ppc->ppc_unit);
174
175 return;
176 }
177
178 /*
179 * ppc_detect_fifo()
180 *
181 * Detect parallel port FIFO
182 */
183 static int
ppc_detect_fifo(struct ppc_data * ppc)184 ppc_detect_fifo(struct ppc_data *ppc)
185 {
186 char ecr_sav;
187 char ctr_sav, ctr, cc;
188 short i;
189
190 /* save registers */
191 ecr_sav = r_ecr(ppc);
192 ctr_sav = r_ctr(ppc);
193
194 /* enter ECP configuration mode, no interrupt, no DMA */
195 w_ecr(ppc, 0xf4);
196
197 /* read PWord size - transfers in FIFO mode must be PWord aligned */
198 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK);
199
200 /* XXX 16 and 32 bits implementations not supported */
201 if (ppc->ppc_pword != PPC_PWORD_8) {
202 LOG_PPC(__func__, ppc, "PWord not supported");
203 goto error;
204 }
205
206 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */
207 ctr = r_ctr(ppc);
208 w_ctr(ppc, ctr | PCD); /* set direction to 1 */
209
210 /* enter ECP test mode, no interrupt, no DMA */
211 w_ecr(ppc, 0xd4);
212
213 /* flush the FIFO */
214 for (i=0; i<1024; i++) {
215 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
216 break;
217 cc = r_fifo(ppc);
218 }
219
220 if (i >= 1024) {
221 LOG_PPC(__func__, ppc, "can't flush FIFO");
222 goto error;
223 }
224
225 /* enable interrupts, no DMA */
226 w_ecr(ppc, 0xd0);
227
228 /* determine readIntrThreshold
229 * fill the FIFO until serviceIntr is set
230 */
231 for (i=0; i<1024; i++) {
232 w_fifo(ppc, (char)i);
233 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) {
234 /* readThreshold reached */
235 ppc->ppc_rthr = i+1;
236 }
237 if (r_ecr(ppc) & PPC_FIFO_FULL) {
238 ppc->ppc_fifo = i+1;
239 break;
240 }
241 }
242
243 if (i >= 1024) {
244 LOG_PPC(__func__, ppc, "can't fill FIFO");
245 goto error;
246 }
247
248 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */
249 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */
250 w_ecr(ppc, 0xd0); /* enable interrupts */
251
252 /* determine writeIntrThreshold
253 * empty the FIFO until serviceIntr is set
254 */
255 for (i=ppc->ppc_fifo; i>0; i--) {
256 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) {
257 LOG_PPC(__func__, ppc, "invalid data in FIFO");
258 goto error;
259 }
260 if (r_ecr(ppc) & PPC_SERVICE_INTR) {
261 /* writeIntrThreshold reached */
262 ppc->ppc_wthr = ppc->ppc_fifo - i+1;
263 }
264 /* if FIFO empty before the last byte, error */
265 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) {
266 LOG_PPC(__func__, ppc, "data lost in FIFO");
267 goto error;
268 }
269 }
270
271 /* FIFO must be empty after the last byte */
272 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
273 LOG_PPC(__func__, ppc, "can't empty the FIFO");
274 goto error;
275 }
276
277 w_ctr(ppc, ctr_sav);
278 w_ecr(ppc, ecr_sav);
279
280 return (0);
281
282 error:
283 w_ctr(ppc, ctr_sav);
284 w_ecr(ppc, ecr_sav);
285
286 return (EINVAL);
287 }
288
289 static int
ppc_detect_port(struct ppc_data * ppc)290 ppc_detect_port(struct ppc_data *ppc)
291 {
292
293 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */
294 w_dtr(ppc, 0xaa);
295 if (r_dtr(ppc) != 0xaa)
296 return (0);
297
298 return (1);
299 }
300
301 /*
302 * EPP timeout, according to the PC87332 manual
303 * Semantics of clearing EPP timeout bit.
304 * PC87332 - reading SPP_STR does it...
305 * SMC - write 1 to EPP timeout bit XXX
306 * Others - (?) write 0 to EPP timeout bit
307 */
308 static void
ppc_reset_epp_timeout(struct ppc_data * ppc)309 ppc_reset_epp_timeout(struct ppc_data *ppc)
310 {
311 char r;
312
313 r = r_str(ppc);
314 w_str(ppc, r | 0x1);
315 w_str(ppc, r & 0xfe);
316
317 return;
318 }
319
320 static int
ppc_check_epp_timeout(struct ppc_data * ppc)321 ppc_check_epp_timeout(struct ppc_data *ppc)
322 {
323 ppc_reset_epp_timeout(ppc);
324
325 return (!(r_str(ppc) & TIMEOUT));
326 }
327
328 /*
329 * Configure current operating mode
330 */
331 static int
ppc_generic_setmode(struct ppc_data * ppc,int mode)332 ppc_generic_setmode(struct ppc_data *ppc, int mode)
333 {
334 u_char ecr = 0;
335
336 /* check if mode is available */
337 if (mode && !(ppc->ppc_avm & mode))
338 return (EINVAL);
339
340 /* if ECP mode, configure ecr register */
341 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
342 /* return to byte mode (keeping direction bit),
343 * no interrupt, no DMA to be able to change to
344 * ECP
345 */
346 w_ecr(ppc, PPC_ECR_RESET);
347 ecr = PPC_DISABLE_INTR;
348
349 if (mode & PPB_EPP)
350 return (EINVAL);
351 else if (mode & PPB_ECP)
352 /* select ECP mode */
353 ecr |= PPC_ECR_ECP;
354 else if (mode & PPB_PS2)
355 /* select PS2 mode with ECP */
356 ecr |= PPC_ECR_PS2;
357 else
358 /* select COMPATIBLE/NIBBLE mode */
359 ecr |= PPC_ECR_STD;
360
361 w_ecr(ppc, ecr);
362 }
363
364 ppc->ppc_mode = mode;
365
366 return (0);
367 }
368
369 /*
370 * The ppc driver is free to choose options like FIFO or DMA
371 * if ECP mode is available.
372 *
373 * The 'RAW' option allows the upper drivers to force the ppc mode
374 * even with FIFO, DMA available.
375 */
376 static int
ppc_smclike_setmode(struct ppc_data * ppc,int mode)377 ppc_smclike_setmode(struct ppc_data *ppc, int mode)
378 {
379 u_char ecr = 0;
380
381 /* check if mode is available */
382 if (mode && !(ppc->ppc_avm & mode))
383 return (EINVAL);
384
385 /* if ECP mode, configure ecr register */
386 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
387 /* return to byte mode (keeping direction bit),
388 * no interrupt, no DMA to be able to change to
389 * ECP or EPP mode
390 */
391 w_ecr(ppc, PPC_ECR_RESET);
392 ecr = PPC_DISABLE_INTR;
393
394 if (mode & PPB_EPP)
395 /* select EPP mode */
396 ecr |= PPC_ECR_EPP;
397 else if (mode & PPB_ECP)
398 /* select ECP mode */
399 ecr |= PPC_ECR_ECP;
400 else if (mode & PPB_PS2)
401 /* select PS2 mode with ECP */
402 ecr |= PPC_ECR_PS2;
403 else
404 /* select COMPATIBLE/NIBBLE mode */
405 ecr |= PPC_ECR_STD;
406
407 w_ecr(ppc, ecr);
408 }
409
410 ppc->ppc_mode = mode;
411
412 return (0);
413 }
414
415 #ifdef PPC_PROBE_CHIPSET
416 /*
417 * ppc_pc873xx_detect
418 *
419 * Probe for a Natsemi PC873xx-family part.
420 *
421 * References in this function are to the National Semiconductor
422 * PC87332 datasheet TL/C/11930, May 1995 revision.
423 */
424 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0};
425 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0};
426 static int pc873xx_irqtab[] = {5, 7, 5, 0};
427
428 static int pc873xx_regstab[] = {
429 PC873_FER, PC873_FAR, PC873_PTR,
430 PC873_FCR, PC873_PCR, PC873_PMC,
431 PC873_TUP, PC873_SID, PC873_PNP0,
432 PC873_PNP1, PC873_LPTBA, -1
433 };
434
435 static char *pc873xx_rnametab[] = {
436 "FER", "FAR", "PTR", "FCR", "PCR",
437 "PMC", "TUP", "SID", "PNP0", "PNP1",
438 "LPTBA", NULL
439 };
440
441 static int
ppc_pc873xx_detect(struct ppc_data * ppc,int chipset_mode)442 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */
443 {
444 static int index = 0;
445 int idport, irq;
446 int ptr, pcr, val, i;
447
448 while ((idport = pc873xx_basetab[index++])) {
449
450 /* XXX should check first to see if this location is already claimed */
451
452 /*
453 * Pull the 873xx through the power-on ID cycle (2.2,1.).
454 * We can't use this to locate the chip as it may already have
455 * been used by the BIOS.
456 */
457 (void)inb(idport); (void)inb(idport);
458 (void)inb(idport); (void)inb(idport);
459
460 /*
461 * Read the SID byte. Possible values are :
462 *
463 * 01010xxx PC87334
464 * 0001xxxx PC87332
465 * 01110xxx PC87306
466 * 00110xxx PC87303
467 */
468 outb(idport, PC873_SID);
469 val = inb(idport + 1);
470 if ((val & 0xf0) == 0x10) {
471 ppc->ppc_model = NS_PC87332;
472 } else if ((val & 0xf8) == 0x70) {
473 ppc->ppc_model = NS_PC87306;
474 } else if ((val & 0xf8) == 0x50) {
475 ppc->ppc_model = NS_PC87334;
476 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the
477 documentation, but probing
478 yielded 0x40... */
479 ppc->ppc_model = NS_PC87303;
480 } else {
481 if (bootverbose && (val != 0xff))
482 kprintf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val);
483 continue ; /* not recognised */
484 }
485
486 /* print registers */
487 if (bootverbose) {
488 kprintf("PC873xx");
489 for (i=0; pc873xx_regstab[i] != -1; i++) {
490 outb(idport, pc873xx_regstab[i]);
491 kprintf(" %s=0x%x", pc873xx_rnametab[i],
492 inb(idport + 1) & 0xff);
493 }
494 kprintf("\n");
495 }
496
497 /*
498 * We think we have one. Is it enabled and where we want it to be?
499 */
500 outb(idport, PC873_FER);
501 val = inb(idport + 1);
502 if (!(val & PC873_PPENABLE)) {
503 if (bootverbose)
504 kprintf("PC873xx parallel port disabled\n");
505 continue;
506 }
507 outb(idport, PC873_FAR);
508 val = inb(idport + 1);
509 /* XXX we should create a driver instance for every port found */
510 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) {
511
512 /* First try to change the port address to that requested... */
513
514 switch(ppc->ppc_base) {
515 case 0x378:
516 val &= 0xfc;
517 break;
518
519 case 0x3bc:
520 val &= 0xfd;
521 break;
522
523 case 0x278:
524 val &= 0xfe;
525 break;
526
527 default:
528 val &= 0xfd;
529 break;
530 }
531
532 outb(idport, PC873_FAR);
533 outb(idport + 1, val);
534 outb(idport + 1, val);
535
536 /* Check for success by reading back the value we supposedly
537 wrote and comparing...*/
538
539 outb(idport, PC873_FAR);
540 val = inb(idport + 1) & 0x3;
541
542 /* If we fail, report the failure... */
543
544 if (pc873xx_porttab[val] != ppc->ppc_base) {
545 if (bootverbose)
546 kprintf("PC873xx at 0x%x not for driver at port 0x%x\n",
547 pc873xx_porttab[val], ppc->ppc_base);
548 }
549 continue;
550 }
551
552 outb(idport, PC873_PTR);
553 ptr = inb(idport + 1);
554
555 /* get irq settings */
556 if (ppc->ppc_base == 0x378)
557 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5;
558 else
559 irq = pc873xx_irqtab[val];
560
561 if (bootverbose)
562 kprintf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base);
563
564 /*
565 * Check if irq settings are correct
566 */
567 if (irq != ppc->ppc_irq) {
568 /*
569 * If the chipset is not locked and base address is 0x378,
570 * we have another chance
571 */
572 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) {
573 if (ppc->ppc_irq == 7) {
574 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
575 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
576 } else {
577 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
578 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
579 }
580 if (bootverbose)
581 kprintf("PC873xx irq set to %d\n", ppc->ppc_irq);
582 } else {
583 if (bootverbose)
584 kprintf("PC873xx sorry, can't change irq setting\n");
585 }
586 } else {
587 if (bootverbose)
588 kprintf("PC873xx irq settings are correct\n");
589 }
590
591 outb(idport, PC873_PCR);
592 pcr = inb(idport + 1);
593
594 if ((ptr & PC873_CFGLOCK) || !chipset_mode) {
595 if (bootverbose)
596 kprintf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked");
597
598 ppc->ppc_avm |= PPB_NIBBLE;
599 if (bootverbose)
600 kprintf(", NIBBLE");
601
602 if (pcr & PC873_EPPEN) {
603 ppc->ppc_avm |= PPB_EPP;
604
605 if (bootverbose)
606 kprintf(", EPP");
607
608 if (pcr & PC873_EPP19)
609 ppc->ppc_epp = EPP_1_9;
610 else
611 ppc->ppc_epp = EPP_1_7;
612
613 if ((ppc->ppc_model == NS_PC87332) && bootverbose) {
614 outb(idport, PC873_PTR);
615 ptr = inb(idport + 1);
616 if (ptr & PC873_EPPRDIR)
617 kprintf(", Regular mode");
618 else
619 kprintf(", Automatic mode");
620 }
621 } else if (pcr & PC873_ECPEN) {
622 ppc->ppc_avm |= PPB_ECP;
623 if (bootverbose)
624 kprintf(", ECP");
625
626 if (pcr & PC873_ECPCLK) { /* XXX */
627 ppc->ppc_avm |= PPB_PS2;
628 if (bootverbose)
629 kprintf(", PS/2");
630 }
631 } else {
632 outb(idport, PC873_PTR);
633 ptr = inb(idport + 1);
634 if (ptr & PC873_EXTENDED) {
635 ppc->ppc_avm |= PPB_SPP;
636 if (bootverbose)
637 kprintf(", SPP");
638 }
639 }
640 } else {
641 if (bootverbose)
642 kprintf("PC873xx unlocked");
643
644 if (chipset_mode & PPB_ECP) {
645 if ((chipset_mode & PPB_EPP) && bootverbose)
646 kprintf(", ECP+EPP not supported");
647
648 pcr &= ~PC873_EPPEN;
649 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */
650 outb(idport + 1, pcr);
651 outb(idport + 1, pcr);
652
653 if (bootverbose)
654 kprintf(", ECP");
655
656 } else if (chipset_mode & PPB_EPP) {
657 pcr &= ~(PC873_ECPEN | PC873_ECPCLK);
658 pcr |= (PC873_EPPEN | PC873_EPP19);
659 outb(idport + 1, pcr);
660 outb(idport + 1, pcr);
661
662 ppc->ppc_epp = EPP_1_9; /* XXX */
663
664 if (bootverbose)
665 kprintf(", EPP1.9");
666
667 /* enable automatic direction turnover */
668 if (ppc->ppc_model == NS_PC87332) {
669 outb(idport, PC873_PTR);
670 ptr = inb(idport + 1);
671 ptr &= ~PC873_EPPRDIR;
672 outb(idport + 1, ptr);
673 outb(idport + 1, ptr);
674
675 if (bootverbose)
676 kprintf(", Automatic mode");
677 }
678 } else {
679 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN);
680 outb(idport + 1, pcr);
681 outb(idport + 1, pcr);
682
683 /* configure extended bit in PTR */
684 outb(idport, PC873_PTR);
685 ptr = inb(idport + 1);
686
687 if (chipset_mode & PPB_PS2) {
688 ptr |= PC873_EXTENDED;
689
690 if (bootverbose)
691 kprintf(", PS/2");
692
693 } else {
694 /* default to NIBBLE mode */
695 ptr &= ~PC873_EXTENDED;
696
697 if (bootverbose)
698 kprintf(", NIBBLE");
699 }
700 outb(idport + 1, ptr);
701 outb(idport + 1, ptr);
702 }
703
704 ppc->ppc_avm = chipset_mode;
705 }
706
707 if (bootverbose)
708 kprintf("\n");
709
710 ppc->ppc_type = PPC_TYPE_GENERIC;
711 ppc_generic_setmode(ppc, chipset_mode);
712
713 return(chipset_mode);
714 }
715 return(-1);
716 }
717
718 /*
719 * ppc_smc37c66xgt_detect
720 *
721 * SMC FDC37C66xGT configuration.
722 */
723 static int
ppc_smc37c66xgt_detect(struct ppc_data * ppc,int chipset_mode)724 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode)
725 {
726 int i;
727 u_char r;
728 int type = -1;
729 int csr = SMC66x_CSR; /* initial value is 0x3F0 */
730
731 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 };
732
733
734 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
735
736 /*
737 * Detection: enter configuration mode and read CRD register.
738 */
739
740 crit_enter();
741 outb(csr, SMC665_iCODE);
742 outb(csr, SMC665_iCODE);
743 crit_exit();
744
745 outb(csr, 0xd);
746 if (inb(cio) == 0x65) {
747 type = SMC_37C665GT;
748 goto config;
749 }
750
751 for (i = 0; i < 2; i++) {
752 crit_enter();
753 outb(csr, SMC666_iCODE);
754 outb(csr, SMC666_iCODE);
755 crit_exit();
756
757 outb(csr, 0xd);
758 if (inb(cio) == 0x66) {
759 type = SMC_37C666GT;
760 break;
761 }
762
763 /* Another chance, CSR may be hard-configured to be at 0x370 */
764 csr = SMC666_CSR;
765 }
766
767 config:
768 /*
769 * If chipset not found, do not continue.
770 */
771 if (type == -1)
772 return (-1);
773
774 /* select CR1 */
775 outb(csr, 0x1);
776
777 /* read the port's address: bits 0 and 1 of CR1 */
778 r = inb(cio) & SMC_CR1_ADDR;
779 if (port_address[(int)r] != ppc->ppc_base)
780 return (-1);
781
782 ppc->ppc_model = type;
783
784 /*
785 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
786 * If SPP mode is detected, try to set ECP+EPP mode
787 */
788
789 if (bootverbose) {
790 outb(csr, 0x1);
791 kprintf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit,
792 inb(cio) & 0xff);
793
794 outb(csr, 0x4);
795 kprintf(" CR4=0x%x", inb(cio) & 0xff);
796 }
797
798 /* select CR1 */
799 outb(csr, 0x1);
800
801 if (!chipset_mode) {
802 /* autodetect mode */
803
804 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
805 if (type == SMC_37C666GT) {
806 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
807 if (bootverbose)
808 kprintf(" configuration hardwired, supposing " \
809 "ECP+EPP SPP");
810
811 } else
812 if ((inb(cio) & SMC_CR1_MODE) == 0) {
813 /* already in extended parallel port mode, read CR4 */
814 outb(csr, 0x4);
815 r = (inb(cio) & SMC_CR4_EMODE);
816
817 switch (r) {
818 case SMC_SPP:
819 ppc->ppc_avm |= PPB_SPP;
820 if (bootverbose)
821 kprintf(" SPP");
822 break;
823
824 case SMC_EPPSPP:
825 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
826 if (bootverbose)
827 kprintf(" EPP SPP");
828 break;
829
830 case SMC_ECP:
831 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
832 if (bootverbose)
833 kprintf(" ECP SPP");
834 break;
835
836 case SMC_ECPEPP:
837 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
838 if (bootverbose)
839 kprintf(" ECP+EPP SPP");
840 break;
841 }
842 } else {
843 /* not an extended port mode */
844 ppc->ppc_avm |= PPB_SPP;
845 if (bootverbose)
846 kprintf(" SPP");
847 }
848
849 } else {
850 /* mode forced */
851 ppc->ppc_avm = chipset_mode;
852
853 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
854 if (type == SMC_37C666GT)
855 goto end_detect;
856
857 r = inb(cio);
858 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) {
859 /* do not use ECP when the mode is not forced to */
860 outb(cio, r | SMC_CR1_MODE);
861 if (bootverbose)
862 kprintf(" SPP");
863 } else {
864 /* an extended mode is selected */
865 outb(cio, r & ~SMC_CR1_MODE);
866
867 /* read CR4 register and reset mode field */
868 outb(csr, 0x4);
869 r = inb(cio) & ~SMC_CR4_EMODE;
870
871 if (chipset_mode & PPB_ECP) {
872 if (chipset_mode & PPB_EPP) {
873 outb(cio, r | SMC_ECPEPP);
874 if (bootverbose)
875 kprintf(" ECP+EPP");
876 } else {
877 outb(cio, r | SMC_ECP);
878 if (bootverbose)
879 kprintf(" ECP");
880 }
881 } else {
882 /* PPB_EPP is set */
883 outb(cio, r | SMC_EPPSPP);
884 if (bootverbose)
885 kprintf(" EPP SPP");
886 }
887 }
888 ppc->ppc_avm = chipset_mode;
889 }
890
891 /* set FIFO threshold to 16 */
892 if (ppc->ppc_avm & PPB_ECP) {
893 /* select CRA */
894 outb(csr, 0xa);
895 outb(cio, 16);
896 }
897
898 end_detect:
899
900 if (bootverbose)
901 kprintf ("\n");
902
903 if (ppc->ppc_avm & PPB_EPP) {
904 /* select CR4 */
905 outb(csr, 0x4);
906 r = inb(cio);
907
908 /*
909 * Set the EPP protocol...
910 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7
911 */
912 if (ppc->ppc_epp == EPP_1_9)
913 outb(cio, (r & ~SMC_CR4_EPPTYPE));
914 else
915 outb(cio, (r | SMC_CR4_EPPTYPE));
916 }
917
918 /* end config mode */
919 outb(csr, 0xaa);
920
921 ppc->ppc_type = PPC_TYPE_SMCLIKE;
922 ppc_smclike_setmode(ppc, chipset_mode);
923
924 return (chipset_mode);
925 }
926
927 /*
928 * SMC FDC37C935 configuration
929 * Found on many Alpha machines
930 */
931 static int
ppc_smc37c935_detect(struct ppc_data * ppc,int chipset_mode)932 ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode)
933 {
934 int type = -1;
935
936 crit_enter();
937 outb(SMC935_CFG, 0x55); /* enter config mode */
938 outb(SMC935_CFG, 0x55);
939 crit_exit();
940
941 outb(SMC935_IND, SMC935_ID); /* check device id */
942 if (inb(SMC935_DAT) == 0x2)
943 type = SMC_37C935;
944
945 if (type == -1) {
946 outb(SMC935_CFG, 0xaa); /* exit config mode */
947 return (-1);
948 }
949
950 ppc->ppc_model = type;
951
952 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */
953 outb(SMC935_DAT, 3); /* which is logical device 3 */
954
955 /* set io port base */
956 outb(SMC935_IND, SMC935_PORTHI);
957 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8));
958 outb(SMC935_IND, SMC935_PORTLO);
959 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff));
960
961 if (!chipset_mode)
962 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */
963 else {
964 ppc->ppc_avm = chipset_mode;
965 outb(SMC935_IND, SMC935_PPMODE);
966 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */
967
968 /* SPP + EPP or just plain SPP */
969 if (chipset_mode & (PPB_SPP)) {
970 if (chipset_mode & PPB_EPP) {
971 if (ppc->ppc_epp == EPP_1_9) {
972 outb(SMC935_IND, SMC935_PPMODE);
973 outb(SMC935_DAT, SMC935_EPP19SPP);
974 }
975 if (ppc->ppc_epp == EPP_1_7) {
976 outb(SMC935_IND, SMC935_PPMODE);
977 outb(SMC935_DAT, SMC935_EPP17SPP);
978 }
979 } else {
980 outb(SMC935_IND, SMC935_PPMODE);
981 outb(SMC935_DAT, SMC935_SPP);
982 }
983 }
984
985 /* ECP + EPP or just plain ECP */
986 if (chipset_mode & PPB_ECP) {
987 if (chipset_mode & PPB_EPP) {
988 if (ppc->ppc_epp == EPP_1_9) {
989 outb(SMC935_IND, SMC935_PPMODE);
990 outb(SMC935_DAT, SMC935_ECPEPP19);
991 }
992 if (ppc->ppc_epp == EPP_1_7) {
993 outb(SMC935_IND, SMC935_PPMODE);
994 outb(SMC935_DAT, SMC935_ECPEPP17);
995 }
996 } else {
997 outb(SMC935_IND, SMC935_PPMODE);
998 outb(SMC935_DAT, SMC935_ECP);
999 }
1000 }
1001 }
1002
1003 outb(SMC935_CFG, 0xaa); /* exit config mode */
1004
1005 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1006 ppc_smclike_setmode(ppc, chipset_mode);
1007
1008 return (chipset_mode);
1009 }
1010
1011 /*
1012 * Winbond W83877F stuff
1013 *
1014 * EFER: extended function enable register
1015 * EFIR: extended function index register
1016 * EFDR: extended function data register
1017 */
1018 #define efir ((efer == 0x250) ? 0x251 : 0x3f0)
1019 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1)
1020
1021 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 };
1022 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 };
1023 static int w83877f_keyiter[] = { 1, 2, 2, 1 };
1024 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 };
1025
1026 static int
ppc_w83877f_detect(struct ppc_data * ppc,int chipset_mode)1027 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode)
1028 {
1029 int i, j, efer;
1030 unsigned char r, hefere, hefras;
1031
1032 for (i = 0; i < 4; i ++) {
1033 /* first try to enable configuration registers */
1034 efer = w83877f_efers[i];
1035
1036 /* write the key to the EFER */
1037 for (j = 0; j < w83877f_keyiter[i]; j ++)
1038 outb (efer, w83877f_keys[i]);
1039
1040 /* then check HEFERE and HEFRAS bits */
1041 outb (efir, 0x0c);
1042 hefere = inb(efdr) & WINB_HEFERE;
1043
1044 outb (efir, 0x16);
1045 hefras = inb(efdr) & WINB_HEFRAS;
1046
1047 /*
1048 * HEFRAS HEFERE
1049 * 0 1 write 89h to 250h (power-on default)
1050 * 1 0 write 86h twice to 3f0h
1051 * 1 1 write 87h twice to 3f0h
1052 * 0 0 write 88h to 250h
1053 */
1054 if ((hefere | hefras) == w83877f_hefs[i])
1055 goto found;
1056 }
1057
1058 return (-1); /* failed */
1059
1060 found:
1061 /* check base port address - read from CR23 */
1062 outb(efir, 0x23);
1063 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */
1064 return (-1);
1065
1066 /* read CHIP ID from CR9/bits0-3 */
1067 outb(efir, 0x9);
1068
1069 switch (inb(efdr) & WINB_CHIPID) {
1070 case WINB_W83877F_ID:
1071 ppc->ppc_model = WINB_W83877F;
1072 break;
1073
1074 case WINB_W83877AF_ID:
1075 ppc->ppc_model = WINB_W83877AF;
1076 break;
1077
1078 default:
1079 ppc->ppc_model = WINB_UNKNOWN;
1080 }
1081
1082 if (bootverbose) {
1083 /* dump of registers */
1084 kprintf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]);
1085 for (i = 0; i <= 0xd; i ++) {
1086 outb(efir, i);
1087 kprintf("0x%x ", inb(efdr));
1088 }
1089 for (i = 0x10; i <= 0x17; i ++) {
1090 outb(efir, i);
1091 kprintf("0x%x ", inb(efdr));
1092 }
1093 outb(efir, 0x1e);
1094 kprintf("0x%x ", inb(efdr));
1095 for (i = 0x20; i <= 0x29; i ++) {
1096 outb(efir, i);
1097 kprintf("0x%x ", inb(efdr));
1098 }
1099 kprintf("\n");
1100 kprintf("ppc%d:", ppc->ppc_unit);
1101 }
1102
1103 ppc->ppc_type = PPC_TYPE_GENERIC;
1104
1105 if (!chipset_mode) {
1106 /* autodetect mode */
1107
1108 /* select CR0 */
1109 outb(efir, 0x0);
1110 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1);
1111
1112 /* select CR9 */
1113 outb(efir, 0x9);
1114 r |= (inb(efdr) & WINB_PRTMODS2);
1115
1116 switch (r) {
1117 case WINB_W83757:
1118 if (bootverbose)
1119 kprintf("ppc%d: W83757 compatible mode\n",
1120 ppc->ppc_unit);
1121 return (-1); /* generic or SMC-like */
1122
1123 case WINB_EXTFDC:
1124 case WINB_EXTADP:
1125 case WINB_EXT2FDD:
1126 case WINB_JOYSTICK:
1127 if (bootverbose)
1128 kprintf(" not in parallel port mode\n");
1129 return (-1);
1130
1131 case (WINB_PARALLEL | WINB_EPP_SPP):
1132 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
1133 if (bootverbose)
1134 kprintf(" EPP SPP");
1135 break;
1136
1137 case (WINB_PARALLEL | WINB_ECP):
1138 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1139 if (bootverbose)
1140 kprintf(" ECP SPP");
1141 break;
1142
1143 case (WINB_PARALLEL | WINB_ECP_EPP):
1144 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
1145 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1146
1147 if (bootverbose)
1148 kprintf(" ECP+EPP SPP");
1149 break;
1150 default:
1151 kprintf("%s: unknown case (0x%x)!\n", __func__, r);
1152 }
1153
1154 } else {
1155 /* mode forced */
1156
1157 /* select CR9 and set PRTMODS2 bit */
1158 outb(efir, 0x9);
1159 outb(efdr, inb(efdr) & ~WINB_PRTMODS2);
1160
1161 /* select CR0 and reset PRTMODSx bits */
1162 outb(efir, 0x0);
1163 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1));
1164
1165 if (chipset_mode & PPB_ECP) {
1166 if (chipset_mode & PPB_EPP) {
1167 outb(efdr, inb(efdr) | WINB_ECP_EPP);
1168 if (bootverbose)
1169 kprintf(" ECP+EPP");
1170
1171 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1172
1173 } else {
1174 outb(efdr, inb(efdr) | WINB_ECP);
1175 if (bootverbose)
1176 kprintf(" ECP");
1177 }
1178 } else {
1179 /* select EPP_SPP otherwise */
1180 outb(efdr, inb(efdr) | WINB_EPP_SPP);
1181 if (bootverbose)
1182 kprintf(" EPP SPP");
1183 }
1184 ppc->ppc_avm = chipset_mode;
1185 }
1186
1187 if (bootverbose)
1188 kprintf("\n");
1189
1190 /* exit configuration mode */
1191 outb(efer, 0xaa);
1192
1193 switch (ppc->ppc_type) {
1194 case PPC_TYPE_SMCLIKE:
1195 ppc_smclike_setmode(ppc, chipset_mode);
1196 break;
1197 default:
1198 ppc_generic_setmode(ppc, chipset_mode);
1199 break;
1200 }
1201
1202 return (chipset_mode);
1203 }
1204 #endif
1205
1206 /*
1207 * ppc_generic_detect
1208 */
1209 static int
ppc_generic_detect(struct ppc_data * ppc,int chipset_mode)1210 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode)
1211 {
1212 /* default to generic */
1213 ppc->ppc_type = PPC_TYPE_GENERIC;
1214
1215 if (bootverbose)
1216 kprintf("ppc%d:", ppc->ppc_unit);
1217
1218 /* first, check for ECP */
1219 w_ecr(ppc, PPC_ECR_PS2);
1220 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) {
1221 ppc->ppc_dtm |= PPB_ECP | PPB_SPP;
1222 if (bootverbose)
1223 kprintf(" ECP SPP");
1224
1225 /* search for SMC style ECP+EPP mode */
1226 w_ecr(ppc, PPC_ECR_EPP);
1227 }
1228
1229 /* try to reset EPP timeout bit */
1230 if (ppc_check_epp_timeout(ppc)) {
1231 ppc->ppc_dtm |= PPB_EPP;
1232
1233 if (ppc->ppc_dtm & PPB_ECP) {
1234 /* SMC like chipset found */
1235 ppc->ppc_model = SMC_LIKE;
1236 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1237
1238 if (bootverbose)
1239 kprintf(" ECP+EPP");
1240 } else {
1241 if (bootverbose)
1242 kprintf(" EPP");
1243 }
1244 } else {
1245 /* restore to standard mode */
1246 w_ecr(ppc, PPC_ECR_STD);
1247 }
1248
1249 /* XXX try to detect NIBBLE and PS2 modes */
1250 ppc->ppc_dtm |= PPB_NIBBLE;
1251
1252 if (bootverbose)
1253 kprintf(" SPP");
1254
1255 if (chipset_mode)
1256 ppc->ppc_avm = chipset_mode;
1257 else
1258 ppc->ppc_avm = ppc->ppc_dtm;
1259
1260 if (bootverbose)
1261 kprintf("\n");
1262
1263 switch (ppc->ppc_type) {
1264 case PPC_TYPE_SMCLIKE:
1265 ppc_smclike_setmode(ppc, chipset_mode);
1266 break;
1267 default:
1268 ppc_generic_setmode(ppc, chipset_mode);
1269 break;
1270 }
1271
1272 return (chipset_mode);
1273 }
1274
1275 /*
1276 * ppc_detect()
1277 *
1278 * mode is the mode suggested at boot
1279 */
1280 static int
ppc_detect(struct ppc_data * ppc,int chipset_mode)1281 ppc_detect(struct ppc_data *ppc, int chipset_mode)
1282 {
1283 #ifdef PPC_PROBE_CHIPSET
1284 int i, mode;
1285
1286 /* list of supported chipsets */
1287 int (*chipset_detect[])(struct ppc_data *, int) = {
1288 ppc_pc873xx_detect,
1289 ppc_smc37c66xgt_detect,
1290 ppc_w83877f_detect,
1291 ppc_smc37c935_detect,
1292 ppc_generic_detect,
1293 NULL
1294 };
1295 #endif
1296
1297 /* if can't find the port and mode not forced return error */
1298 if (!ppc_detect_port(ppc) && chipset_mode == 0)
1299 return (EIO); /* failed, port not present */
1300
1301 /* assume centronics compatible mode is supported */
1302 ppc->ppc_avm = PPB_COMPATIBLE;
1303
1304 #ifdef PPC_PROBE_CHIPSET
1305 /* we have to differenciate available chipset modes,
1306 * chipset running modes and IEEE-1284 operating modes
1307 *
1308 * after detection, the port must support running in compatible mode
1309 */
1310 if (ppc->ppc_flags & 0x40) {
1311 if (bootverbose)
1312 kprintf("ppc: chipset forced to generic\n");
1313 #endif
1314
1315 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode);
1316
1317 #ifdef PPC_PROBE_CHIPSET
1318 } else {
1319 for (i=0; chipset_detect[i] != NULL; i++) {
1320 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) {
1321 ppc->ppc_mode = mode;
1322 break;
1323 }
1324 }
1325 }
1326 #endif
1327
1328 /* configure/detect ECP FIFO */
1329 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80))
1330 ppc_detect_fifo(ppc);
1331
1332 return (0);
1333 }
1334
1335 /*
1336 * ppc_exec_microseq()
1337 *
1338 * Execute a microsequence.
1339 * Microsequence mechanism is supposed to handle fast I/O operations.
1340 */
1341 static int
ppc_exec_microseq(device_t dev,struct ppb_microseq ** p_msq)1342 ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq)
1343 {
1344 struct ppc_data *ppc = DEVTOSOFTC(dev);
1345 struct ppb_microseq *mi;
1346 char cc, *p;
1347 int i, iter, len;
1348 int error;
1349
1350 int reg;
1351 char mask;
1352 int accum = 0;
1353 char *ptr = NULL;
1354
1355 struct ppb_microseq *stack = NULL;
1356
1357 /* microsequence registers are equivalent to PC-like port registers */
1358
1359 #define r_reg(register,ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, register))
1360 #define w_reg(register, ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, register, byte))
1361
1362 #define INCR_PC (mi ++) /* increment program counter */
1363
1364 mi = *p_msq;
1365 for (;;) {
1366 switch (mi->opcode) {
1367 case MS_OP_RSET:
1368 cc = r_reg(mi->arg[0].i, ppc);
1369 cc &= (char)mi->arg[2].i; /* clear mask */
1370 cc |= (char)mi->arg[1].i; /* assert mask */
1371 w_reg(mi->arg[0].i, ppc, cc);
1372 INCR_PC;
1373 break;
1374
1375 case MS_OP_RASSERT_P:
1376 reg = mi->arg[1].i;
1377 ptr = ppc->ppc_ptr;
1378
1379 if ((len = mi->arg[0].i) == MS_ACCUM) {
1380 accum = ppc->ppc_accum;
1381 for (; accum; accum--)
1382 w_reg(reg, ppc, *ptr++);
1383 ppc->ppc_accum = accum;
1384 } else
1385 for (i=0; i<len; i++)
1386 w_reg(reg, ppc, *ptr++);
1387 ppc->ppc_ptr = ptr;
1388
1389 INCR_PC;
1390 break;
1391
1392 case MS_OP_RFETCH_P:
1393 reg = mi->arg[1].i;
1394 mask = (char)mi->arg[2].i;
1395 ptr = ppc->ppc_ptr;
1396
1397 if ((len = mi->arg[0].i) == MS_ACCUM) {
1398 accum = ppc->ppc_accum;
1399 for (; accum; accum--)
1400 *ptr++ = r_reg(reg, ppc) & mask;
1401 ppc->ppc_accum = accum;
1402 } else
1403 for (i=0; i<len; i++)
1404 *ptr++ = r_reg(reg, ppc) & mask;
1405 ppc->ppc_ptr = ptr;
1406
1407 INCR_PC;
1408 break;
1409
1410 case MS_OP_RFETCH:
1411 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) &
1412 (char)mi->arg[1].i;
1413 INCR_PC;
1414 break;
1415
1416 case MS_OP_RASSERT:
1417 case MS_OP_DELAY:
1418
1419 /* let's suppose the next instr. is the same */
1420 prefetch:
1421 for (;mi->opcode == MS_OP_RASSERT; INCR_PC)
1422 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i);
1423
1424 if (mi->opcode == MS_OP_DELAY) {
1425 DELAY(mi->arg[0].i);
1426 INCR_PC;
1427 goto prefetch;
1428 }
1429 break;
1430
1431 case MS_OP_ADELAY:
1432 if (mi->arg[0].i)
1433 tsleep(ppc_exec_microseq, 0, "ppbdelay",
1434 mi->arg[0].i * (hz/1000));
1435 INCR_PC;
1436 break;
1437
1438 case MS_OP_TRIG:
1439 reg = mi->arg[0].i;
1440 iter = mi->arg[1].i;
1441 p = (char *)mi->arg[2].p;
1442
1443 /* XXX delay limited to 255 us */
1444 for (i=0; i<iter; i++) {
1445 w_reg(reg, ppc, *p++);
1446 DELAY((unsigned char)*p++);
1447 }
1448 INCR_PC;
1449 break;
1450
1451 case MS_OP_SET:
1452 ppc->ppc_accum = mi->arg[0].i;
1453 INCR_PC;
1454 break;
1455
1456 case MS_OP_DBRA:
1457 if (--ppc->ppc_accum > 0)
1458 mi += mi->arg[0].i;
1459 INCR_PC;
1460 break;
1461
1462 case MS_OP_BRSET:
1463 cc = r_str(ppc);
1464 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i)
1465 mi += mi->arg[1].i;
1466 INCR_PC;
1467 break;
1468
1469 case MS_OP_BRCLEAR:
1470 cc = r_str(ppc);
1471 if ((cc & (char)mi->arg[0].i) == 0)
1472 mi += mi->arg[1].i;
1473 INCR_PC;
1474 break;
1475
1476 case MS_OP_BRSTAT:
1477 cc = r_str(ppc);
1478 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) ==
1479 (char)mi->arg[0].i)
1480 mi += mi->arg[2].i;
1481 INCR_PC;
1482 break;
1483
1484 case MS_OP_C_CALL:
1485 /*
1486 * If the C call returns !0 then end the microseq.
1487 * The current state of ptr is passed to the C function
1488 */
1489 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr)))
1490 return (error);
1491
1492 INCR_PC;
1493 break;
1494
1495 case MS_OP_PTR:
1496 ppc->ppc_ptr = (char *)mi->arg[0].p;
1497 INCR_PC;
1498 break;
1499
1500 case MS_OP_CALL:
1501 if (stack)
1502 panic("%s: too much calls", __func__);
1503
1504 if (mi->arg[0].p) {
1505 /* store the state of the actual
1506 * microsequence
1507 */
1508 stack = mi;
1509
1510 /* jump to the new microsequence */
1511 mi = (struct ppb_microseq *)mi->arg[0].p;
1512 } else
1513 INCR_PC;
1514
1515 break;
1516
1517 case MS_OP_SUBRET:
1518 /* retrieve microseq and pc state before the call */
1519 mi = stack;
1520
1521 /* reset the stack */
1522 stack = NULL;
1523
1524 /* XXX return code */
1525
1526 INCR_PC;
1527 break;
1528
1529 case MS_OP_PUT:
1530 case MS_OP_GET:
1531 case MS_OP_RET:
1532 /* can't return to ppb level during the execution
1533 * of a submicrosequence */
1534 if (stack)
1535 panic("%s: can't return to ppb level",
1536 __func__);
1537
1538 /* update pc for ppb level of execution */
1539 *p_msq = mi;
1540
1541 /* return to ppb level of execution */
1542 return (0);
1543
1544 default:
1545 panic("%s: unknown microsequence opcode 0x%x",
1546 __func__, mi->opcode);
1547 }
1548 }
1549
1550 /* unreached */
1551 }
1552
1553 static void
ppcintr(void * arg)1554 ppcintr(void *arg)
1555 {
1556 device_t dev = (device_t)arg;
1557 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(dev);
1558 u_char ctr, ecr, str;
1559
1560 str = r_str(ppc);
1561 ctr = r_ctr(ppc);
1562 ecr = r_ecr(ppc);
1563
1564 #if PPC_DEBUG > 1
1565 kprintf("![%x/%x/%x]", ctr, ecr, str);
1566 #endif
1567
1568 /* don't use ecp mode with IRQENABLE set */
1569 if (ctr & IRQENABLE) {
1570 return;
1571 }
1572
1573 /* interrupts are generated by nFault signal
1574 * only in ECP mode */
1575 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) {
1576 /* check if ppc driver has programmed the
1577 * nFault interrupt */
1578 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) {
1579
1580 w_ecr(ppc, ecr | PPC_nFAULT_INTR);
1581 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT;
1582 } else {
1583 /* shall be handled by underlying layers XXX */
1584 return;
1585 }
1586 }
1587
1588 if (ppc->ppc_irqstat & PPC_IRQ_DMA) {
1589 /* disable interrupts (should be done by hardware though) */
1590 w_ecr(ppc, ecr | PPC_SERVICE_INTR);
1591 ppc->ppc_irqstat &= ~PPC_IRQ_DMA;
1592 ecr = r_ecr(ppc);
1593
1594 /* check if DMA completed */
1595 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) {
1596 #ifdef PPC_DEBUG
1597 kprintf("a");
1598 #endif
1599 /* stop DMA */
1600 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA);
1601 ecr = r_ecr(ppc);
1602
1603 if (ppc->ppc_dmastat == PPC_DMA_STARTED) {
1604 #ifdef PPC_DEBUG
1605 kprintf("d");
1606 #endif
1607 isa_dmadone(
1608 ppc->ppc_dmaflags,
1609 ppc->ppc_dmaddr,
1610 ppc->ppc_dmacnt,
1611 ppc->ppc_dmachan);
1612
1613 ppc->ppc_dmastat = PPC_DMA_COMPLETE;
1614
1615 /* wakeup the waiting process */
1616 wakeup((caddr_t)ppc);
1617 }
1618 }
1619 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) {
1620
1621 /* classic interrupt I/O */
1622 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO;
1623 }
1624
1625 return;
1626 }
1627
1628 static int
ppc_read(device_t dev,char * buf,int len,int mode)1629 ppc_read(device_t dev, char *buf, int len, int mode)
1630 {
1631 return (EINVAL);
1632 }
1633
1634 /*
1635 * Call this function if you want to send data in any advanced mode
1636 * of your parallel port: FIFO, DMA
1637 *
1638 * If what you want is not possible (no ECP, no DMA...),
1639 * EINVAL is returned
1640 */
1641 static int
ppc_write(device_t dev,char * buf,int len,int how)1642 ppc_write(device_t dev, char *buf, int len, int how)
1643 {
1644 struct ppc_data *ppc = DEVTOSOFTC(dev);
1645 char ecr, ecr_sav, ctr, ctr_sav;
1646 int error = 0;
1647 int spin;
1648
1649 #ifdef PPC_DEBUG
1650 kprintf("w");
1651 #endif
1652
1653 ecr_sav = r_ecr(ppc);
1654 ctr_sav = r_ctr(ppc);
1655
1656 /*
1657 * Send buffer with DMA, FIFO and interrupts
1658 */
1659 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_registered)) {
1660
1661 if (ppc->ppc_dmachan > 0) {
1662
1663 /* byte mode, no intr, no DMA, dir=0, flush fifo
1664 */
1665 ecr = PPC_ECR_STD | PPC_DISABLE_INTR;
1666 w_ecr(ppc, ecr);
1667
1668 /* disable nAck interrupts */
1669 ctr = r_ctr(ppc);
1670 ctr &= ~IRQENABLE;
1671 w_ctr(ppc, ctr);
1672
1673 ppc->ppc_dmaflags = ISADMA_WRITE;
1674 ppc->ppc_dmaddr = (caddr_t)buf;
1675 ppc->ppc_dmacnt = (u_int)len;
1676
1677 switch (ppc->ppc_mode) {
1678 case PPB_COMPATIBLE:
1679 /* compatible mode with FIFO, no intr, DMA, dir=0 */
1680 ecr = PPC_ECR_FIFO | PPC_DISABLE_INTR | PPC_ENABLE_DMA;
1681 break;
1682 case PPB_ECP:
1683 ecr = PPC_ECR_ECP | PPC_DISABLE_INTR | PPC_ENABLE_DMA;
1684 break;
1685 default:
1686 error = EINVAL;
1687 goto error;
1688 }
1689
1690 w_ecr(ppc, ecr);
1691 ecr = r_ecr(ppc);
1692
1693 /* enter splhigh() not to be preempted
1694 * by the dma interrupt, we may miss
1695 * the wakeup otherwise
1696 */
1697 crit_enter();
1698
1699 ppc->ppc_dmastat = PPC_DMA_INIT;
1700
1701 /* enable interrupts */
1702 ecr &= ~PPC_SERVICE_INTR;
1703 ppc->ppc_irqstat = PPC_IRQ_DMA;
1704 w_ecr(ppc, ecr);
1705
1706 isa_dmastart(
1707 ppc->ppc_dmaflags,
1708 ppc->ppc_dmaddr,
1709 ppc->ppc_dmacnt,
1710 ppc->ppc_dmachan);
1711 #ifdef PPC_DEBUG
1712 kprintf("s%d", ppc->ppc_dmacnt);
1713 #endif
1714 ppc->ppc_dmastat = PPC_DMA_STARTED;
1715
1716 /* Wait for the DMA completed interrupt. We hope we won't
1717 * miss it, otherwise a signal will be necessary to unlock the
1718 * process.
1719 */
1720 do {
1721 /* release CPU */
1722 error = tsleep((caddr_t)ppc, PCATCH, "ppcdma", 0);
1723
1724 } while (error == EWOULDBLOCK);
1725
1726 crit_exit();
1727
1728 if (error) {
1729 #ifdef PPC_DEBUG
1730 kprintf("i");
1731 #endif
1732 /* stop DMA */
1733 isa_dmadone(
1734 ppc->ppc_dmaflags,
1735 ppc->ppc_dmaddr, ppc->ppc_dmacnt,
1736 ppc->ppc_dmachan);
1737
1738 /* no dma, no interrupt, flush the fifo */
1739 w_ecr(ppc, PPC_ECR_RESET);
1740
1741 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED;
1742 goto error;
1743 }
1744
1745 /* wait for an empty fifo */
1746 while (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
1747
1748 for (spin=100; spin; spin--)
1749 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
1750 goto fifo_empty;
1751 #ifdef PPC_DEBUG
1752 kprintf("Z");
1753 #endif
1754 error = tsleep((caddr_t)ppc, PCATCH, "ppcfifo", hz/100);
1755 if (error != EWOULDBLOCK) {
1756 #ifdef PPC_DEBUG
1757 kprintf("I");
1758 #endif
1759 /* no dma, no interrupt, flush the fifo */
1760 w_ecr(ppc, PPC_ECR_RESET);
1761
1762 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED;
1763 error = EINTR;
1764 goto error;
1765 }
1766 }
1767
1768 fifo_empty:
1769 /* no dma, no interrupt, flush the fifo */
1770 w_ecr(ppc, PPC_ECR_RESET);
1771
1772 } else
1773 error = EINVAL; /* XXX we should FIFO and
1774 * interrupts */
1775 } else
1776 error = EINVAL;
1777
1778 error:
1779
1780 /* PDRQ must be kept unasserted until nPDACK is
1781 * deasserted for a minimum of 350ns (SMC datasheet)
1782 *
1783 * Consequence may be a FIFO that never empty
1784 */
1785 DELAY(1);
1786
1787 w_ecr(ppc, ecr_sav);
1788 w_ctr(ppc, ctr_sav);
1789
1790 return (error);
1791 }
1792
1793 static void
ppc_reset_epp(device_t dev)1794 ppc_reset_epp(device_t dev)
1795 {
1796 struct ppc_data *ppc = DEVTOSOFTC(dev);
1797
1798 ppc_reset_epp_timeout(ppc);
1799
1800 return;
1801 }
1802
1803 static int
ppc_setmode(device_t dev,int mode)1804 ppc_setmode(device_t dev, int mode)
1805 {
1806 struct ppc_data *ppc = DEVTOSOFTC(dev);
1807
1808 switch (ppc->ppc_type) {
1809 case PPC_TYPE_SMCLIKE:
1810 return (ppc_smclike_setmode(ppc, mode));
1811 break;
1812
1813 case PPC_TYPE_GENERIC:
1814 default:
1815 return (ppc_generic_setmode(ppc, mode));
1816 break;
1817 }
1818
1819 /* not reached */
1820 return (ENXIO);
1821 }
1822
1823 static struct isa_pnp_id lpc_ids[] = {
1824 { 0x0004d041, "Standard parallel printer port" }, /* PNP0400 */
1825 { 0x0104d041, "ECP parallel printer port" }, /* PNP0401 */
1826 { 0 }
1827 };
1828
1829 static int
ppc_probe(device_t dev)1830 ppc_probe(device_t dev)
1831 {
1832 #ifdef __i386__
1833 static short next_bios_ppc = 0;
1834 #endif
1835 struct ppc_data *ppc;
1836 device_t parent;
1837 int error;
1838 u_long port;
1839
1840 parent = device_get_parent(dev);
1841
1842 error = ISA_PNP_PROBE(parent, dev, lpc_ids);
1843 if (error == ENXIO)
1844 return (ENXIO);
1845 else if (error != 0) /* XXX shall be set after detection */
1846 device_set_desc(dev, "Parallel port");
1847
1848 /*
1849 * Allocate the ppc_data structure.
1850 */
1851 ppc = DEVTOSOFTC(dev);
1852 bzero(ppc, sizeof(struct ppc_data));
1853
1854 ppc->rid_irq = ppc->rid_drq = ppc->rid_ioport = 0;
1855 ppc->res_irq = ppc->res_drq = ppc->res_ioport = 0;
1856
1857 /* retrieve ISA parameters */
1858 error = bus_get_resource(dev, SYS_RES_IOPORT, 0, &port, NULL);
1859
1860 #ifdef __i386__
1861 /*
1862 * If port not specified, use bios list.
1863 */
1864 if (error) {
1865 if((next_bios_ppc < BIOS_MAX_PPC) &&
1866 (*(BIOS_PORTS+next_bios_ppc) != 0) ) {
1867 port = *(BIOS_PORTS+next_bios_ppc++);
1868 if (bootverbose)
1869 device_printf(dev, "parallel port found at 0x%x\n",
1870 (int) port);
1871 } else {
1872 device_printf(dev, "parallel port not found.\n");
1873 return ENXIO;
1874 }
1875 bus_set_resource(dev, SYS_RES_IOPORT, 0, port,
1876 IO_LPTSIZE_EXTENDED, -1);
1877 }
1878 #endif
1879
1880 /* IO port is mandatory */
1881
1882 /* Try "extended" IO port range...*/
1883 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1884 &ppc->rid_ioport, 0, ~0,
1885 IO_LPTSIZE_EXTENDED, RF_ACTIVE);
1886
1887 if (ppc->res_ioport != NULL) {
1888 if (bootverbose)
1889 device_printf(dev, "using extended I/O port range\n");
1890 } else {
1891 /* Failed? If so, then try the "normal" IO port range... */
1892 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1893 &ppc->rid_ioport, 0, ~0,
1894 IO_LPTSIZE_NORMAL,
1895 RF_ACTIVE);
1896 if (ppc->res_ioport != NULL) {
1897 if (bootverbose)
1898 device_printf(dev, "using normal I/O port range\n");
1899 } else {
1900 device_printf(dev, "cannot reserve I/O port range\n");
1901 goto error;
1902 }
1903 }
1904
1905 ppc->ppc_base = rman_get_start(ppc->res_ioport);
1906
1907 ppc->bsh = rman_get_bushandle(ppc->res_ioport);
1908 ppc->bst = rman_get_bustag(ppc->res_ioport);
1909
1910 ppc->ppc_flags = device_get_flags(dev);
1911
1912 if (!(ppc->ppc_flags & 0x20)) {
1913 ppc->res_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &ppc->rid_irq,
1914 0ul, ~0ul, 1, RF_SHAREABLE);
1915 ppc->res_drq = bus_alloc_resource(dev, SYS_RES_DRQ, &ppc->rid_drq,
1916 0ul, ~0ul, 1, RF_ACTIVE);
1917 }
1918
1919 if (ppc->res_irq)
1920 ppc->ppc_irq = rman_get_start(ppc->res_irq);
1921 if (ppc->res_drq)
1922 ppc->ppc_dmachan = rman_get_start(ppc->res_drq);
1923
1924 ppc->ppc_unit = device_get_unit(dev);
1925 ppc->ppc_model = GENERIC;
1926
1927 ppc->ppc_mode = PPB_COMPATIBLE;
1928 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4;
1929
1930 ppc->ppc_type = PPC_TYPE_GENERIC;
1931
1932 /*
1933 * Try to detect the chipset and its mode.
1934 */
1935 if (ppc_detect(ppc, ppc->ppc_flags & 0xf))
1936 goto error;
1937
1938 return (0);
1939
1940 error:
1941 if (ppc->res_irq != NULL) {
1942 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1943 ppc->res_irq);
1944 }
1945 if (ppc->res_ioport != NULL) {
1946 bus_deactivate_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1947 ppc->res_ioport);
1948 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1949 ppc->res_ioport);
1950 }
1951 if (ppc->res_drq != NULL) {
1952 bus_deactivate_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1953 ppc->res_drq);
1954 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1955 ppc->res_drq);
1956 }
1957 return (ENXIO);
1958 }
1959
1960 static int
ppc_attach(device_t dev)1961 ppc_attach(device_t dev)
1962 {
1963 struct ppc_data *ppc = DEVTOSOFTC(dev);
1964
1965 device_t ppbus;
1966 device_t parent = device_get_parent(dev);
1967
1968 device_printf(dev, "%s chipset (%s) in %s mode%s\n",
1969 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm],
1970 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ?
1971 ppc_epp_protocol[ppc->ppc_epp] : "");
1972
1973 if (ppc->ppc_fifo)
1974 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n",
1975 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr);
1976
1977 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_dmachan > 0)) {
1978 /* acquire the DMA channel forever */ /* XXX */
1979 isa_dma_acquire(ppc->ppc_dmachan);
1980 isa_dmainit(ppc->ppc_dmachan, 1024); /* nlpt.BUFSIZE */
1981 }
1982
1983 /* add ppbus as a child of this isa to parallel bridge */
1984 ppbus = device_add_child(dev, "ppbus", -1);
1985
1986 /*
1987 * Probe the ppbus and attach devices found.
1988 */
1989 device_probe_and_attach(ppbus);
1990
1991 /* register the ppc interrupt handler as default */
1992 if (ppc->res_irq) {
1993 /* default to the tty mask for registration */ /* XXX */
1994 if (BUS_SETUP_INTR(parent, dev, ppc->res_irq, 0,
1995 ppcintr, dev,
1996 &ppc->intr_cookie, NULL, NULL) == 0) {
1997 /* remember the ppcintr is registered */
1998 ppc->ppc_registered = 1;
1999 }
2000 }
2001
2002 return (0);
2003 }
2004
2005 static u_char
ppc_io(device_t ppcdev,int iop,u_char * addr,int cnt,u_char byte)2006 ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte)
2007 {
2008 struct ppc_data *ppc = DEVTOSOFTC(ppcdev);
2009 switch (iop) {
2010 case PPB_OUTSB_EPP:
2011 bus_space_write_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt);
2012 break;
2013 case PPB_OUTSW_EPP:
2014 bus_space_write_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
2015 break;
2016 case PPB_OUTSL_EPP:
2017 bus_space_write_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
2018 break;
2019 case PPB_INSB_EPP:
2020 bus_space_read_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt);
2021 break;
2022 case PPB_INSW_EPP:
2023 bus_space_read_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
2024 break;
2025 case PPB_INSL_EPP:
2026 bus_space_read_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
2027 break;
2028 case PPB_RDTR:
2029 return (r_dtr(ppc));
2030 break;
2031 case PPB_RSTR:
2032 return (r_str(ppc));
2033 break;
2034 case PPB_RCTR:
2035 return (r_ctr(ppc));
2036 break;
2037 case PPB_REPP_A:
2038 return (r_epp_A(ppc));
2039 break;
2040 case PPB_REPP_D:
2041 return (r_epp_D(ppc));
2042 break;
2043 case PPB_RECR:
2044 return (r_ecr(ppc));
2045 break;
2046 case PPB_RFIFO:
2047 return (r_fifo(ppc));
2048 break;
2049 case PPB_WDTR:
2050 w_dtr(ppc, byte);
2051 break;
2052 case PPB_WSTR:
2053 w_str(ppc, byte);
2054 break;
2055 case PPB_WCTR:
2056 w_ctr(ppc, byte);
2057 break;
2058 case PPB_WEPP_A:
2059 w_epp_A(ppc, byte);
2060 break;
2061 case PPB_WEPP_D:
2062 w_epp_D(ppc, byte);
2063 break;
2064 case PPB_WECR:
2065 w_ecr(ppc, byte);
2066 break;
2067 case PPB_WFIFO:
2068 w_fifo(ppc, byte);
2069 break;
2070 default:
2071 panic("%s: unknown I/O operation", __func__);
2072 break;
2073 }
2074
2075 return (0); /* not significative */
2076 }
2077
2078 static int
ppc_read_ivar(device_t bus,device_t dev,int index,uintptr_t * val)2079 ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val)
2080 {
2081 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
2082
2083 switch (index) {
2084 case PPC_IVAR_EPP_PROTO:
2085 *val = (u_long)ppc->ppc_epp;
2086 break;
2087 case PPC_IVAR_IRQ:
2088 *val = (u_long)ppc->ppc_irq;
2089 break;
2090 default:
2091 return (ENOENT);
2092 }
2093
2094 return (0);
2095 }
2096
2097 /*
2098 * Resource is useless here since ppbus devices' interrupt handlers are
2099 * multiplexed to the same resource initially allocated by ppc
2100 */
2101 static int
ppc_setup_intr(device_t bus,device_t child,struct resource * r,int flags,void (* ihand)(void *),void * arg,void ** cookiep,lwkt_serialize_t serializer)2102 ppc_setup_intr(device_t bus, device_t child, struct resource *r, int flags,
2103 void (*ihand)(void *), void *arg,
2104 void **cookiep, lwkt_serialize_t serializer)
2105 {
2106 int error;
2107 struct ppc_data *ppc = DEVTOSOFTC(bus);
2108
2109 if (ppc->ppc_registered) {
2110 /* XXX refuse registration if DMA is in progress */
2111
2112 /* first, unregister the default interrupt handler */
2113 if ((error = BUS_TEARDOWN_INTR(device_get_parent(bus),
2114 bus, ppc->res_irq, ppc->intr_cookie)))
2115 return (error);
2116
2117 /* bus_deactivate_resource(bus, SYS_RES_IRQ, ppc->rid_irq, */
2118 /* ppc->res_irq); */
2119
2120 /* DMA/FIFO operation won't be possible anymore */
2121 ppc->ppc_registered = 0;
2122 }
2123
2124 /* pass registration to the upper layer, ignore the incoming resource */
2125 return (BUS_SETUP_INTR(device_get_parent(bus), child,
2126 r, flags, ihand, arg, cookiep,
2127 serializer, NULL));
2128 }
2129
2130 /*
2131 * When no underlying device has a registered interrupt, register the ppc
2132 * layer one
2133 */
2134 static int
ppc_teardown_intr(device_t bus,device_t child,struct resource * r,void * ih)2135 ppc_teardown_intr(device_t bus, device_t child, struct resource *r, void *ih)
2136 {
2137 int error;
2138 struct ppc_data *ppc = DEVTOSOFTC(bus);
2139 device_t parent = device_get_parent(bus);
2140
2141 /* pass unregistration to the upper layer */
2142 if ((error = BUS_TEARDOWN_INTR(parent, child, r, ih)))
2143 return (error);
2144
2145 /* default to the tty mask for registration */ /* XXX */
2146 if (ppc->ppc_irq &&
2147 !(error = BUS_SETUP_INTR(parent, bus, ppc->res_irq,
2148 0, ppcintr, bus,
2149 &ppc->intr_cookie, NULL, NULL))
2150 ) {
2151 /* remember the ppcintr is registered */
2152 ppc->ppc_registered = 1;
2153 }
2154
2155 return (error);
2156 }
2157
2158 DRIVER_MODULE(ppc, isa, ppc_driver, ppc_devclass, NULL, NULL);
2159 DRIVER_MODULE(ppc, acpi, ppc_driver, ppc_devclass, NULL, NULL);
2160