1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright 1997, Stefan Esser <se@freebsd.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
11 * disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 */
28
29 #ifndef _PCIVAR_H_
30 #define _PCIVAR_H_
31
32 #include <sys/queue.h>
33 #include <sys/_eventhandler.h>
34
35 /* some PCI bus constants */
36 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */
37 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */
38 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */
39
40 typedef uint64_t pci_addr_t;
41
42 /* Config registers for PCI-PCI and PCI-Cardbus bridges. */
43 struct pcicfg_bridge {
44 uint8_t br_seclat;
45 uint8_t br_subbus;
46 uint8_t br_secbus;
47 uint8_t br_pribus;
48 uint16_t br_control;
49 };
50
51 /* Interesting values for PCI power management */
52 struct pcicfg_pp {
53 uint16_t pp_cap; /* PCI power management capabilities */
54 uint8_t pp_status; /* conf. space addr. of PM control/status reg */
55 uint8_t pp_bse; /* conf. space addr. of PM BSE reg */
56 uint8_t pp_data; /* conf. space addr. of PM data reg */
57 };
58
59 struct pci_map {
60 pci_addr_t pm_value; /* Raw BAR value */
61 pci_addr_t pm_size;
62 uint16_t pm_reg;
63 STAILQ_ENTRY(pci_map) pm_link;
64 };
65
66 struct vpd_readonly {
67 char keyword[2];
68 char *value;
69 int len;
70 };
71
72 struct vpd_write {
73 char keyword[2];
74 char *value;
75 int start;
76 int len;
77 };
78
79 struct pcicfg_vpd {
80 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */
81 char vpd_cached;
82 char *vpd_ident; /* string identifier */
83 int vpd_rocnt;
84 struct vpd_readonly *vpd_ros;
85 int vpd_wcnt;
86 struct vpd_write *vpd_w;
87 };
88
89 /* Interesting values for PCI MSI */
90 struct pcicfg_msi {
91 uint16_t msi_ctrl; /* Message Control */
92 uint8_t msi_location; /* Offset of MSI capability registers. */
93 uint8_t msi_msgnum; /* Number of messages */
94 int msi_alloc; /* Number of allocated messages. */
95 uint64_t msi_addr; /* Contents of address register. */
96 uint16_t msi_data; /* Contents of data register. */
97 u_int msi_handlers;
98 };
99
100 /* Interesting values for PCI MSI-X */
101 struct msix_vector {
102 uint64_t mv_address; /* Contents of address register. */
103 uint32_t mv_data; /* Contents of data register. */
104 int mv_irq;
105 };
106
107 struct msix_table_entry {
108 u_int mte_vector; /* 1-based index into msix_vectors array. */
109 u_int mte_handlers;
110 };
111
112 struct pcicfg_msix {
113 uint16_t msix_ctrl; /* Message Control */
114 uint16_t msix_msgnum; /* Number of messages */
115 uint8_t msix_location; /* Offset of MSI-X capability registers. */
116 uint8_t msix_table_bar; /* BAR containing vector table. */
117 uint8_t msix_pba_bar; /* BAR containing PBA. */
118 uint32_t msix_table_offset;
119 uint32_t msix_pba_offset;
120 int msix_alloc; /* Number of allocated vectors. */
121 int msix_table_len; /* Length of virtual table. */
122 struct msix_table_entry *msix_table; /* Virtual table. */
123 struct msix_vector *msix_vectors; /* Array of allocated vectors. */
124 struct resource *msix_table_res; /* Resource containing vector table. */
125 struct resource *msix_pba_res; /* Resource containing PBA. */
126 };
127
128 struct pci_id_ofw_iommu {
129 uint32_t id;
130 uint32_t xref;
131 };
132
133 /* Interesting values for HyperTransport */
134 struct pcicfg_ht {
135 uint8_t ht_slave; /* Non-zero if device is an HT slave. */
136 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */
137 uint16_t ht_msictrl; /* MSI mapping control */
138 uint64_t ht_msiaddr; /* MSI mapping base address */
139 };
140
141 /* Interesting values for PCI-express */
142 struct pcicfg_pcie {
143 uint8_t pcie_location; /* Offset of PCI-e capability registers. */
144 uint8_t pcie_type; /* Device type. */
145 uint16_t pcie_flags; /* Device capabilities register. */
146 uint16_t pcie_device_ctl; /* Device control register. */
147 uint16_t pcie_link_ctl; /* Link control register. */
148 uint16_t pcie_slot_ctl; /* Slot control register. */
149 uint16_t pcie_root_ctl; /* Root control register. */
150 uint16_t pcie_device_ctl2; /* Second device control register. */
151 uint16_t pcie_link_ctl2; /* Second link control register. */
152 uint16_t pcie_slot_ctl2; /* Second slot control register. */
153 };
154
155 struct pcicfg_pcix {
156 uint16_t pcix_command;
157 uint8_t pcix_location; /* Offset of PCI-X capability registers. */
158 };
159
160 struct pcicfg_vf {
161 int index;
162 };
163
164 struct pci_ea_entry {
165 int eae_bei;
166 uint32_t eae_flags;
167 uint64_t eae_base;
168 uint64_t eae_max_offset;
169 uint32_t eae_cfg_offset;
170 STAILQ_ENTRY(pci_ea_entry) eae_link;
171 };
172
173 struct pcicfg_ea {
174 int ea_location; /* Structure offset in Configuration Header */
175 STAILQ_HEAD(, pci_ea_entry) ea_entries; /* EA entries */
176 };
177
178 #define PCICFG_VF 0x0001 /* Device is an SR-IOV Virtual Function */
179
180 /* config header information common to all header types */
181 typedef struct pcicfg {
182 device_t dev; /* device which owns this */
183
184 STAILQ_HEAD(, pci_map) maps; /* BARs */
185
186 uint16_t subvendor; /* card vendor ID */
187 uint16_t subdevice; /* card device ID, assigned by card vendor */
188 uint16_t vendor; /* chip vendor ID */
189 uint16_t device; /* chip device ID, assigned by chip vendor */
190
191 uint16_t cmdreg; /* disable/enable chip and PCI options */
192 uint16_t statreg; /* supported PCI features and error state */
193
194 uint8_t baseclass; /* chip PCI class */
195 uint8_t subclass; /* chip PCI subclass */
196 uint8_t progif; /* chip PCI programming interface */
197 uint8_t revid; /* chip revision ID */
198
199 uint8_t hdrtype; /* chip config header type */
200 uint8_t cachelnsz; /* cache line size in 4byte units */
201 uint8_t intpin; /* PCI interrupt pin */
202 uint8_t intline; /* interrupt line (IRQ for PC arch) */
203
204 uint8_t mingnt; /* min. useful bus grant time in 250ns units */
205 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */
206 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */
207
208 uint8_t mfdev; /* multi-function device (from hdrtype reg) */
209 uint8_t nummaps; /* actual number of PCI maps used */
210
211 uint32_t domain; /* PCI domain */
212 uint8_t bus; /* config space bus address */
213 uint8_t slot; /* config space slot address */
214 uint8_t func; /* config space function number */
215
216 uint32_t flags; /* flags defined above */
217
218 struct pcicfg_bridge bridge; /* Bridges */
219 struct pcicfg_pp pp; /* Power management */
220 struct pcicfg_vpd vpd; /* Vital product data */
221 struct pcicfg_msi msi; /* PCI MSI */
222 struct pcicfg_msix msix; /* PCI MSI-X */
223 struct pcicfg_ht ht; /* HyperTransport */
224 struct pcicfg_pcie pcie; /* PCI Express */
225 struct pcicfg_pcix pcix; /* PCI-X */
226 struct pcicfg_iov *iov; /* SR-IOV */
227 struct pcicfg_vf vf; /* SR-IOV Virtual Function */
228 struct pcicfg_ea ea; /* Enhanced Allocation */
229 } pcicfgregs;
230
231 /* additional type 1 device config header information (PCI to PCI bridge) */
232
233 typedef struct {
234 pci_addr_t pmembase; /* base address of prefetchable memory */
235 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
236 uint32_t membase; /* base address of memory window */
237 uint32_t memlimit; /* topmost address of memory window */
238 uint32_t iobase; /* base address of port window */
239 uint32_t iolimit; /* topmost address of port window */
240 uint16_t secstat; /* secondary bus status register */
241 uint16_t bridgectl; /* bridge control register */
242 uint8_t seclat; /* CardBus latency timer */
243 } pcih1cfgregs;
244
245 /* additional type 2 device config header information (CardBus bridge) */
246
247 typedef struct {
248 uint32_t membase0; /* base address of memory window */
249 uint32_t memlimit0; /* topmost address of memory window */
250 uint32_t membase1; /* base address of memory window */
251 uint32_t memlimit1; /* topmost address of memory window */
252 uint32_t iobase0; /* base address of port window */
253 uint32_t iolimit0; /* topmost address of port window */
254 uint32_t iobase1; /* base address of port window */
255 uint32_t iolimit1; /* topmost address of port window */
256 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */
257 uint16_t secstat; /* secondary bus status register */
258 uint16_t bridgectl; /* bridge control register */
259 uint8_t seclat; /* CardBus latency timer */
260 } pcih2cfgregs;
261
262 extern uint32_t pci_numdevs;
263 extern int pci_enable_aspm;
264
265 /*
266 * The bitfield has to be stable and match the fields below (so that
267 * match_flag_vendor must be bit 0) so we have to do the endian dance. We can't
268 * use enums or #define constants because then the macros for subsetting matches
269 * wouldn't work. These tables are parsed by devmatch and others to connect
270 * modules with devices on the PCI bus.
271 */
272 struct pci_device_table {
273 #if BYTE_ORDER == LITTLE_ENDIAN
274 uint16_t
275 match_flag_vendor:1,
276 match_flag_device:1,
277 match_flag_subvendor:1,
278 match_flag_subdevice:1,
279 match_flag_class:1,
280 match_flag_subclass:1,
281 match_flag_revid:1,
282 match_flag_unused:9;
283 #else
284 uint16_t
285 match_flag_unused:9,
286 match_flag_revid:1,
287 match_flag_subclass:1,
288 match_flag_class:1,
289 match_flag_subdevice:1,
290 match_flag_subvendor:1,
291 match_flag_device:1,
292 match_flag_vendor:1;
293 #endif
294 uint16_t vendor;
295 uint16_t device;
296 uint16_t subvendor;
297 uint16_t subdevice;
298 uint16_t class_id;
299 uint16_t subclass;
300 uint16_t revid;
301 uint16_t unused;
302 uintptr_t driver_data;
303 char *descr;
304 };
305
306 #define PCI_DEV(v, d) \
307 .match_flag_vendor = 1, .vendor = (v), \
308 .match_flag_device = 1, .device = (d)
309 #define PCI_SUBDEV(sv, sd) \
310 .match_flag_subvendor = 1, .subvendor = (sv), \
311 .match_flag_subdevice = 1, .subdevice = (sd)
312 #define PCI_CLASS(x) \
313 .match_flag_class = 1, .class_id = (x)
314 #define PCI_SUBCLASS(x) \
315 .match_flag_subclass = 1, .subclass = (x)
316 #define PCI_REVID(x) \
317 .match_flag_revid = 1, .revid = (x)
318 #define PCI_DESCR(x) \
319 .descr = (x)
320 #define PCI_PNP_STR \
321 "M16:mask;U16:vendor;U16:device;U16:subvendor;U16:subdevice;" \
322 "U16:class;U16:subclass;U16:revid;"
323 #define PCI_PNP_INFO(table) \
324 MODULE_PNP_INFO(PCI_PNP_STR, pci, table, table, \
325 sizeof(table) / sizeof(table[0]))
326
327 const struct pci_device_table *pci_match_device(device_t child,
328 const struct pci_device_table *id, size_t nelt);
329 #define PCI_MATCH(child, table) \
330 pci_match_device(child, (table), nitems(table));
331
332 /* Only if the prerequisites are present */
333 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
334 struct pci_devinfo {
335 STAILQ_ENTRY(pci_devinfo) pci_links;
336 struct resource_list resources;
337 pcicfgregs cfg;
338 struct pci_conf conf;
339 };
340 #endif
341
342 #ifdef _SYS_BUS_H_
343
344 #include "pci_if.h"
345
346 enum pci_device_ivars {
347 PCI_IVAR_SUBVENDOR,
348 PCI_IVAR_SUBDEVICE,
349 PCI_IVAR_VENDOR,
350 PCI_IVAR_DEVICE,
351 PCI_IVAR_DEVID,
352 PCI_IVAR_CLASS,
353 PCI_IVAR_SUBCLASS,
354 PCI_IVAR_PROGIF,
355 PCI_IVAR_REVID,
356 PCI_IVAR_INTPIN,
357 PCI_IVAR_IRQ,
358 PCI_IVAR_DOMAIN,
359 PCI_IVAR_BUS,
360 PCI_IVAR_SLOT,
361 PCI_IVAR_FUNCTION,
362 PCI_IVAR_ETHADDR,
363 PCI_IVAR_CMDREG,
364 PCI_IVAR_CACHELNSZ,
365 PCI_IVAR_MINGNT,
366 PCI_IVAR_MAXLAT,
367 PCI_IVAR_LATTIMER
368 };
369
370 /*
371 * Simplified accessors for pci devices
372 */
373 #define PCI_ACCESSOR(var, ivar, type) \
374 __BUS_ACCESSOR(pci, var, PCI, ivar, type)
375
PCI_ACCESSOR(subvendor,SUBVENDOR,uint16_t)376 PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t)
377 PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t)
378 PCI_ACCESSOR(vendor, VENDOR, uint16_t)
379 PCI_ACCESSOR(device, DEVICE, uint16_t)
380 PCI_ACCESSOR(devid, DEVID, uint32_t)
381 PCI_ACCESSOR(class, CLASS, uint8_t)
382 PCI_ACCESSOR(subclass, SUBCLASS, uint8_t)
383 PCI_ACCESSOR(progif, PROGIF, uint8_t)
384 PCI_ACCESSOR(revid, REVID, uint8_t)
385 PCI_ACCESSOR(intpin, INTPIN, uint8_t)
386 PCI_ACCESSOR(irq, IRQ, uint8_t)
387 PCI_ACCESSOR(domain, DOMAIN, uint32_t)
388 PCI_ACCESSOR(bus, BUS, uint8_t)
389 PCI_ACCESSOR(slot, SLOT, uint8_t)
390 PCI_ACCESSOR(function, FUNCTION, uint8_t)
391 PCI_ACCESSOR(ether, ETHADDR, uint8_t *)
392 PCI_ACCESSOR(cmdreg, CMDREG, uint8_t)
393 PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t)
394 PCI_ACCESSOR(mingnt, MINGNT, uint8_t)
395 PCI_ACCESSOR(maxlat, MAXLAT, uint8_t)
396 PCI_ACCESSOR(lattimer, LATTIMER, uint8_t)
397
398 #undef PCI_ACCESSOR
399
400 /*
401 * Operations on configuration space.
402 */
403 static __inline uint32_t
404 pci_read_config(device_t dev, int reg, int width)
405 {
406 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
407 }
408
409 static __inline void
pci_write_config(device_t dev,int reg,uint32_t val,int width)410 pci_write_config(device_t dev, int reg, uint32_t val, int width)
411 {
412 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
413 }
414
415 /*
416 * Ivars for pci bridges.
417 */
418
419 /*typedef enum pci_device_ivars pcib_device_ivars;*/
420 enum pcib_device_ivars {
421 PCIB_IVAR_DOMAIN,
422 PCIB_IVAR_BUS
423 };
424
425 #define PCIB_ACCESSOR(var, ivar, type) \
426 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type)
427
PCIB_ACCESSOR(domain,DOMAIN,uint32_t)428 PCIB_ACCESSOR(domain, DOMAIN, uint32_t)
429 PCIB_ACCESSOR(bus, BUS, uint32_t)
430
431 #undef PCIB_ACCESSOR
432
433 /*
434 * PCI interrupt validation. Invalid interrupt values such as 0 or 128
435 * on i386 or other platforms should be mapped out in the MD pcireadconf
436 * code and not here, since the only MI invalid IRQ is 255.
437 */
438 #define PCI_INVALID_IRQ 255
439 #define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ)
440
441 /*
442 * Convenience functions.
443 *
444 * These should be used in preference to manually manipulating
445 * configuration space.
446 */
447 static __inline int
448 pci_enable_busmaster(device_t dev)
449 {
450 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev));
451 }
452
453 static __inline int
pci_disable_busmaster(device_t dev)454 pci_disable_busmaster(device_t dev)
455 {
456 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev));
457 }
458
459 static __inline int
pci_enable_io(device_t dev,int space)460 pci_enable_io(device_t dev, int space)
461 {
462 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space));
463 }
464
465 static __inline int
pci_disable_io(device_t dev,int space)466 pci_disable_io(device_t dev, int space)
467 {
468 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space));
469 }
470
471 static __inline int
pci_get_vpd_ident(device_t dev,const char ** identptr)472 pci_get_vpd_ident(device_t dev, const char **identptr)
473 {
474 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr));
475 }
476
477 static __inline int
pci_get_vpd_readonly(device_t dev,const char * kw,const char ** vptr)478 pci_get_vpd_readonly(device_t dev, const char *kw, const char **vptr)
479 {
480 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, vptr));
481 }
482
483 /*
484 * Check if the address range falls within the VGA defined address range(s)
485 */
486 static __inline int
pci_is_vga_ioport_range(rman_res_t start,rman_res_t end)487 pci_is_vga_ioport_range(rman_res_t start, rman_res_t end)
488 {
489
490 return (((start >= 0x3b0 && end <= 0x3bb) ||
491 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0);
492 }
493
494 static __inline int
pci_is_vga_memory_range(rman_res_t start,rman_res_t end)495 pci_is_vga_memory_range(rman_res_t start, rman_res_t end)
496 {
497
498 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0);
499 }
500
501 /*
502 * PCI power states are as defined by ACPI:
503 *
504 * D0 State in which device is on and running. It is receiving full
505 * power from the system and delivering full functionality to the user.
506 * D1 Class-specific low-power state in which device context may or may not
507 * be lost. Buses in D1 cannot do anything to the bus that would force
508 * devices on that bus to lose context.
509 * D2 Class-specific low-power state in which device context may or may
510 * not be lost. Attains greater power savings than D1. Buses in D2
511 * can cause devices on that bus to lose some context. Devices in D2
512 * must be prepared for the bus to be in D2 or higher.
513 * D3 State in which the device is off and not running. Device context is
514 * lost. Power can be removed from the device.
515 */
516 #define PCI_POWERSTATE_D0 0
517 #define PCI_POWERSTATE_D1 1
518 #define PCI_POWERSTATE_D2 2
519 #define PCI_POWERSTATE_D3 3
520 #define PCI_POWERSTATE_UNKNOWN -1
521
522 static __inline int
pci_set_powerstate(device_t dev,int state)523 pci_set_powerstate(device_t dev, int state)
524 {
525 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
526 }
527
528 static __inline int
pci_get_powerstate(device_t dev)529 pci_get_powerstate(device_t dev)
530 {
531 return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
532 }
533
534 static __inline int
pci_find_cap(device_t dev,int capability,int * capreg)535 pci_find_cap(device_t dev, int capability, int *capreg)
536 {
537 return (PCI_FIND_CAP(device_get_parent(dev), dev, capability, capreg));
538 }
539
540 static __inline int
pci_find_next_cap(device_t dev,int capability,int start,int * capreg)541 pci_find_next_cap(device_t dev, int capability, int start, int *capreg)
542 {
543 return (PCI_FIND_NEXT_CAP(device_get_parent(dev), dev, capability, start,
544 capreg));
545 }
546
547 static __inline int
pci_find_extcap(device_t dev,int capability,int * capreg)548 pci_find_extcap(device_t dev, int capability, int *capreg)
549 {
550 return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg));
551 }
552
553 static __inline int
pci_find_next_extcap(device_t dev,int capability,int start,int * capreg)554 pci_find_next_extcap(device_t dev, int capability, int start, int *capreg)
555 {
556 return (PCI_FIND_NEXT_EXTCAP(device_get_parent(dev), dev, capability,
557 start, capreg));
558 }
559
560 static __inline int
pci_find_htcap(device_t dev,int capability,int * capreg)561 pci_find_htcap(device_t dev, int capability, int *capreg)
562 {
563 return (PCI_FIND_HTCAP(device_get_parent(dev), dev, capability, capreg));
564 }
565
566 static __inline int
pci_find_next_htcap(device_t dev,int capability,int start,int * capreg)567 pci_find_next_htcap(device_t dev, int capability, int start, int *capreg)
568 {
569 return (PCI_FIND_NEXT_HTCAP(device_get_parent(dev), dev, capability,
570 start, capreg));
571 }
572
573 static __inline int
pci_alloc_msi(device_t dev,int * count)574 pci_alloc_msi(device_t dev, int *count)
575 {
576 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count));
577 }
578
579 static __inline int
pci_alloc_msix(device_t dev,int * count)580 pci_alloc_msix(device_t dev, int *count)
581 {
582 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count));
583 }
584
585 static __inline void
pci_enable_msi(device_t dev,uint64_t address,uint16_t data)586 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
587 {
588 PCI_ENABLE_MSI(device_get_parent(dev), dev, address, data);
589 }
590
591 static __inline void
pci_enable_msix(device_t dev,u_int index,uint64_t address,uint32_t data)592 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
593 {
594 PCI_ENABLE_MSIX(device_get_parent(dev), dev, index, address, data);
595 }
596
597 static __inline void
pci_disable_msi(device_t dev)598 pci_disable_msi(device_t dev)
599 {
600 PCI_DISABLE_MSI(device_get_parent(dev), dev);
601 }
602
603 static __inline int
pci_remap_msix(device_t dev,int count,const u_int * vectors)604 pci_remap_msix(device_t dev, int count, const u_int *vectors)
605 {
606 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors));
607 }
608
609 static __inline int
pci_release_msi(device_t dev)610 pci_release_msi(device_t dev)
611 {
612 return (PCI_RELEASE_MSI(device_get_parent(dev), dev));
613 }
614
615 static __inline int
pci_msi_count(device_t dev)616 pci_msi_count(device_t dev)
617 {
618 return (PCI_MSI_COUNT(device_get_parent(dev), dev));
619 }
620
621 static __inline int
pci_msix_count(device_t dev)622 pci_msix_count(device_t dev)
623 {
624 return (PCI_MSIX_COUNT(device_get_parent(dev), dev));
625 }
626
627 static __inline int
pci_msix_pba_bar(device_t dev)628 pci_msix_pba_bar(device_t dev)
629 {
630 return (PCI_MSIX_PBA_BAR(device_get_parent(dev), dev));
631 }
632
633 static __inline int
pci_msix_table_bar(device_t dev)634 pci_msix_table_bar(device_t dev)
635 {
636 return (PCI_MSIX_TABLE_BAR(device_get_parent(dev), dev));
637 }
638
639 static __inline int
pci_get_id(device_t dev,enum pci_id_type type,uintptr_t * id)640 pci_get_id(device_t dev, enum pci_id_type type, uintptr_t *id)
641 {
642 return (PCI_GET_ID(device_get_parent(dev), dev, type, id));
643 }
644
645 /*
646 * This is the deprecated interface, there is no way to tell the difference
647 * between a failure and a valid value that happens to be the same as the
648 * failure value.
649 */
650 static __inline uint16_t
pci_get_rid(device_t dev)651 pci_get_rid(device_t dev)
652 {
653 uintptr_t rid;
654
655 if (pci_get_id(dev, PCI_ID_RID, &rid) != 0)
656 return (0);
657
658 return (rid);
659 }
660
661 static __inline void
pci_child_added(device_t dev)662 pci_child_added(device_t dev)
663 {
664
665 return (PCI_CHILD_ADDED(device_get_parent(dev), dev));
666 }
667
668 device_t pci_find_bsf(uint8_t, uint8_t, uint8_t);
669 device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t);
670 device_t pci_find_device(uint16_t, uint16_t);
671 device_t pci_find_class(uint8_t class, uint8_t subclass);
672 device_t pci_find_class_from(uint8_t class, uint8_t subclass, device_t devfrom);
673
674 /* Can be used by drivers to manage the MSI-X table. */
675 int pci_pending_msix(device_t dev, u_int index);
676
677 int pci_msi_device_blacklisted(device_t dev);
678 int pci_msix_device_blacklisted(device_t dev);
679
680 void pci_ht_map_msi(device_t dev, uint64_t addr);
681
682 device_t pci_find_pcie_root_port(device_t dev);
683 int pci_get_relaxed_ordering_enabled(device_t dev);
684 int pci_get_max_payload(device_t dev);
685 int pci_get_max_read_req(device_t dev);
686 void pci_restore_state(device_t dev);
687 void pci_save_state(device_t dev);
688 int pci_set_max_read_req(device_t dev, int size);
689 int pci_power_reset(device_t dev);
690 uint32_t pcie_read_config(device_t dev, int reg, int width);
691 void pcie_write_config(device_t dev, int reg, uint32_t value, int width);
692 uint32_t pcie_adjust_config(device_t dev, int reg, uint32_t mask,
693 uint32_t value, int width);
694 void pcie_apei_error(device_t dev, int sev, uint8_t *aer);
695 bool pcie_flr(device_t dev, u_int max_delay, bool force);
696 int pcie_get_max_completion_timeout(device_t dev);
697 bool pcie_wait_for_pending_transactions(device_t dev, u_int max_delay);
698 int pcie_link_reset(device_t port, int pcie_location);
699
700 void pci_print_faulted_dev(void);
701
702 #endif /* _SYS_BUS_H_ */
703
704 /*
705 * cdev switch for control device, initialised in generic PCI code
706 */
707 extern struct cdevsw pcicdev;
708
709 /*
710 * List of all PCI devices, generation count for the list.
711 */
712 STAILQ_HEAD(devlist, pci_devinfo);
713
714 extern struct devlist pci_devq;
715 extern uint32_t pci_generation;
716
717 struct pci_map *pci_find_bar(device_t dev, int reg);
718 struct pci_map *pci_first_bar(device_t dev);
719 struct pci_map *pci_next_bar(struct pci_map *pm);
720 int pci_bar_enabled(device_t dev, struct pci_map *pm);
721 struct pcicfg_vpd *pci_fetch_vpd_list(device_t dev);
722
723 #define VGA_PCI_BIOS_SHADOW_ADDR 0xC0000
724 #define VGA_PCI_BIOS_SHADOW_SIZE 131072
725
726 int vga_pci_is_boot_display(device_t dev);
727 void * vga_pci_map_bios(device_t dev, size_t *size);
728 void vga_pci_unmap_bios(device_t dev, void *bios);
729 int vga_pci_repost(device_t dev);
730
731 /**
732 * Global eventhandlers invoked when PCI devices are added or removed
733 * from the system.
734 */
735 typedef void (*pci_event_fn)(void *arg, device_t dev);
736 EVENTHANDLER_DECLARE(pci_add_device, pci_event_fn);
737 EVENTHANDLER_DECLARE(pci_delete_device, pci_event_fn);
738
739 #endif /* _PCIVAR_H_ */
740