1 /* $OpenBSD: pci.h,v 1.16 2024/01/16 23:38:13 jsg Exp $ */
2 /*
3 * Copyright (c) 2015 Mark Kettenis
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 #ifndef _LINUX_PCI_H_
19 #define _LINUX_PCI_H_
20
21 #include <sys/types.h>
22 /* sparc64 cpu.h needs time.h and siginfo.h (indirect via param.h) */
23 #include <sys/param.h>
24 #include <machine/cpu.h>
25
26 #include <dev/pci/pcireg.h>
27 #include <dev/pci/pcivar.h>
28 #include <dev/pci/pcidevs.h>
29 #include <uvm/uvm_extern.h>
30
31 #include <linux/io.h>
32 #include <linux/ioport.h>
33 #include <linux/kobject.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/mod_devicetable.h>
36
37 struct pci_dev;
38
39 struct pci_bus {
40 pci_chipset_tag_t pc;
41 unsigned char number;
42 int domain_nr;
43 pcitag_t *bridgetag;
44 struct pci_dev *self;
45 };
46
47 struct pci_acpi {
48 struct aml_node *node;
49 };
50
51 struct pci_dev {
52 struct pci_bus _bus;
53 struct pci_bus *bus;
54
55 unsigned int devfn;
56 uint16_t vendor;
57 uint16_t device;
58 uint16_t subsystem_vendor;
59 uint16_t subsystem_device;
60 uint8_t revision;
61 uint32_t class; /* class:subclass:interface */
62
63 pci_chipset_tag_t pc;
64 pcitag_t tag;
65 struct pci_softc *pci;
66
67 int irq;
68 int msi_enabled;
69 uint8_t no_64bit_msi;
70 uint8_t ltr_path;
71
72 struct pci_acpi dev;
73 };
74 #define PCI_ANY_ID (uint16_t) (~0U)
75
76 #define PCI_DEVICE(v, p) \
77 .vendor = (v), \
78 .device = (p), \
79 .subvendor = PCI_ANY_ID, \
80 .subdevice = PCI_ANY_ID
81
82 #ifndef PCI_MEM_START
83 #define PCI_MEM_START 0
84 #endif
85
86 #ifndef PCI_MEM_END
87 #define PCI_MEM_END 0xffffffff
88 #endif
89
90 #ifndef PCI_MEM64_END
91 #define PCI_MEM64_END 0xffffffffffffffff
92 #endif
93
94 #define PCI_VENDOR_ID_APPLE PCI_VENDOR_APPLE
95 #define PCI_VENDOR_ID_ASUSTEK PCI_VENDOR_ASUSTEK
96 #define PCI_VENDOR_ID_ATI PCI_VENDOR_ATI
97 #define PCI_VENDOR_ID_DELL PCI_VENDOR_DELL
98 #define PCI_VENDOR_ID_HP PCI_VENDOR_HP
99 #define PCI_VENDOR_ID_IBM PCI_VENDOR_IBM
100 #define PCI_VENDOR_ID_INTEL PCI_VENDOR_INTEL
101 #define PCI_VENDOR_ID_SONY PCI_VENDOR_SONY
102 #define PCI_VENDOR_ID_VIA PCI_VENDOR_VIATECH
103
104 #define PCI_DEVICE_ID_ATI_RADEON_QY PCI_PRODUCT_ATI_RADEON_QY
105
106 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
107 #define PCI_SUBDEVICE_ID_QEMU 0x1100
108
109 #define PCI_DEVFN(slot, func) ((slot) << 3 | (func))
110 #define PCI_SLOT(devfn) ((devfn) >> 3)
111 #define PCI_FUNC(devfn) ((devfn) & 0x7)
112 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff)
113
114 #define pci_dev_put(x)
115
116 #define PCI_EXP_DEVSTA 0x0a
117 #define PCI_EXP_DEVSTA_TRPND 0x0020
118 #define PCI_EXP_LNKCAP 0x0c
119 #define PCI_EXP_LNKCAP_CLKPM 0x00040000
120 #define PCI_EXP_LNKCTL 0x10
121 #define PCI_EXP_LNKCTL_HAWD 0x0200
122 #define PCI_EXP_LNKCTL2 0x30
123 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010
124 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380
125 #define PCI_EXP_LNKCTL2_TLS PCI_PCIE_LCSR2_TLS
126 #define PCI_EXP_LNKCTL2_TLS_2_5GT PCI_PCIE_LCSR2_TLS_2_5
127 #define PCI_EXP_LNKCTL2_TLS_5_0GT PCI_PCIE_LCSR2_TLS_5
128 #define PCI_EXP_LNKCTL2_TLS_8_0GT PCI_PCIE_LCSR2_TLS_8
129
130 #define PCI_COMMAND PCI_COMMAND_STATUS_REG
131 #define PCI_COMMAND_MEMORY PCI_COMMAND_MEM_ENABLE
132
133 static inline int
pci_read_config_dword(struct pci_dev * pdev,int reg,u32 * val)134 pci_read_config_dword(struct pci_dev *pdev, int reg, u32 *val)
135 {
136 *val = pci_conf_read(pdev->pc, pdev->tag, reg);
137 return 0;
138 }
139
140 static inline int
pci_read_config_word(struct pci_dev * pdev,int reg,u16 * val)141 pci_read_config_word(struct pci_dev *pdev, int reg, u16 *val)
142 {
143 uint32_t v;
144
145 v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x2));
146 *val = (v >> ((reg & 0x2) * 8));
147 return 0;
148 }
149
150 static inline int
pci_read_config_byte(struct pci_dev * pdev,int reg,u8 * val)151 pci_read_config_byte(struct pci_dev *pdev, int reg, u8 *val)
152 {
153 uint32_t v;
154
155 v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x3));
156 *val = (v >> ((reg & 0x3) * 8));
157 return 0;
158 }
159
160 static inline int
pci_write_config_dword(struct pci_dev * pdev,int reg,u32 val)161 pci_write_config_dword(struct pci_dev *pdev, int reg, u32 val)
162 {
163 pci_conf_write(pdev->pc, pdev->tag, reg, val);
164 return 0;
165 }
166
167 static inline int
pci_write_config_word(struct pci_dev * pdev,int reg,u16 val)168 pci_write_config_word(struct pci_dev *pdev, int reg, u16 val)
169 {
170 uint32_t v;
171
172 v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x2));
173 v &= ~(0xffff << ((reg & 0x2) * 8));
174 v |= (val << ((reg & 0x2) * 8));
175 pci_conf_write(pdev->pc, pdev->tag, (reg & ~0x2), v);
176 return 0;
177 }
178
179 static inline int
pci_write_config_byte(struct pci_dev * pdev,int reg,u8 val)180 pci_write_config_byte(struct pci_dev *pdev, int reg, u8 val)
181 {
182 uint32_t v;
183
184 v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x3));
185 v &= ~(0xff << ((reg & 0x3) * 8));
186 v |= (val << ((reg & 0x3) * 8));
187 pci_conf_write(pdev->pc, pdev->tag, (reg & ~0x3), v);
188 return 0;
189 }
190
191 static inline int
pci_bus_read_config_word(struct pci_bus * bus,unsigned int devfn,int reg,u16 * val)192 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
193 int reg, u16 *val)
194 {
195 pcitag_t tag = pci_make_tag(bus->pc, bus->number,
196 PCI_SLOT(devfn), PCI_FUNC(devfn));
197 uint32_t v;
198
199 v = pci_conf_read(bus->pc, tag, (reg & ~0x2));
200 *val = (v >> ((reg & 0x2) * 8));
201 return 0;
202 }
203
204 static inline int
pci_bus_read_config_byte(struct pci_bus * bus,unsigned int devfn,int reg,u8 * val)205 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
206 int reg, u8 *val)
207 {
208 pcitag_t tag = pci_make_tag(bus->pc, bus->number,
209 PCI_SLOT(devfn), PCI_FUNC(devfn));
210 uint32_t v;
211
212 v = pci_conf_read(bus->pc, tag, (reg & ~0x3));
213 *val = (v >> ((reg & 0x3) * 8));
214 return 0;
215 }
216
217 static inline int
pci_bus_write_config_byte(struct pci_bus * bus,unsigned int devfn,int reg,u8 val)218 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
219 int reg, u8 val)
220 {
221 pcitag_t tag = pci_make_tag(bus->pc, bus->number,
222 PCI_SLOT(devfn), PCI_FUNC(devfn));
223 uint32_t v;
224
225 v = pci_conf_read(bus->pc, tag, (reg & ~0x3));
226 v &= ~(0xff << ((reg & 0x3) * 8));
227 v |= (val << ((reg & 0x3) * 8));
228 pci_conf_write(bus->pc, tag, (reg & ~0x3), v);
229 return 0;
230 }
231
232 static inline int
pci_pcie_cap(struct pci_dev * pdev)233 pci_pcie_cap(struct pci_dev *pdev)
234 {
235 int pos;
236 if (!pci_get_capability(pdev->pc, pdev->tag, PCI_CAP_PCIEXPRESS,
237 &pos, NULL))
238 return -EINVAL;
239 return pos;
240 }
241
242 bool pcie_aspm_enabled(struct pci_dev *);
243
244 static inline bool
pci_is_pcie(struct pci_dev * pdev)245 pci_is_pcie(struct pci_dev *pdev)
246 {
247 return (pci_pcie_cap(pdev) > 0);
248 }
249
250 static inline bool
pci_is_root_bus(struct pci_bus * pbus)251 pci_is_root_bus(struct pci_bus *pbus)
252 {
253 return (pbus->bridgetag == NULL);
254 }
255
256 static inline struct pci_dev *
pci_upstream_bridge(struct pci_dev * pdev)257 pci_upstream_bridge(struct pci_dev *pdev)
258 {
259 if (pci_is_root_bus(pdev->bus))
260 return NULL;
261 return pdev->bus->self;
262 }
263
264 /* XXX check for ACPI _PR3 */
265 static inline bool
pci_pr3_present(struct pci_dev * pdev)266 pci_pr3_present(struct pci_dev *pdev)
267 {
268 return false;
269 }
270
271 static inline int
pcie_capability_read_dword(struct pci_dev * pdev,int off,u32 * val)272 pcie_capability_read_dword(struct pci_dev *pdev, int off, u32 *val)
273 {
274 int pos;
275 if (!pci_get_capability(pdev->pc, pdev->tag, PCI_CAP_PCIEXPRESS,
276 &pos, NULL)) {
277 *val = 0;
278 return -EINVAL;
279 }
280 *val = pci_conf_read(pdev->pc, pdev->tag, pos + off);
281 return 0;
282 }
283
284 static inline int
pcie_capability_read_word(struct pci_dev * pdev,int off,u16 * val)285 pcie_capability_read_word(struct pci_dev *pdev, int off, u16 *val)
286 {
287 int pos;
288 if (!pci_get_capability(pdev->pc, pdev->tag, PCI_CAP_PCIEXPRESS,
289 &pos, NULL)) {
290 *val = 0;
291 return -EINVAL;
292 }
293 pci_read_config_word(pdev, pos + off, val);
294 return 0;
295 }
296
297 static inline int
pcie_capability_write_word(struct pci_dev * pdev,int off,u16 val)298 pcie_capability_write_word(struct pci_dev *pdev, int off, u16 val)
299 {
300 int pos;
301 if (!pci_get_capability(pdev->pc, pdev->tag, PCI_CAP_PCIEXPRESS,
302 &pos, NULL))
303 return -EINVAL;
304 pci_write_config_word(pdev, pos + off, val);
305 return 0;
306 }
307
308 static inline int
pcie_capability_set_word(struct pci_dev * pdev,int off,u16 val)309 pcie_capability_set_word(struct pci_dev *pdev, int off, u16 val)
310 {
311 u16 r;
312 pcie_capability_read_word(pdev, off, &r);
313 r |= val;
314 pcie_capability_write_word(pdev, off, r);
315 return 0;
316 }
317
318 static inline int
pcie_capability_clear_and_set_word(struct pci_dev * pdev,int off,u16 c,u16 s)319 pcie_capability_clear_and_set_word(struct pci_dev *pdev, int off, u16 c, u16 s)
320 {
321 u16 r;
322 pcie_capability_read_word(pdev, off, &r);
323 r &= ~c;
324 r |= s;
325 pcie_capability_write_word(pdev, off, r);
326 return 0;
327 }
328
329 static inline int
pcie_get_readrq(struct pci_dev * pdev)330 pcie_get_readrq(struct pci_dev *pdev)
331 {
332 uint16_t val;
333
334 pcie_capability_read_word(pdev, PCI_PCIE_DCSR, &val);
335
336 return 128 << ((val & PCI_PCIE_DCSR_MPS) >> 12);
337 }
338
339 static inline int
pcie_set_readrq(struct pci_dev * pdev,int rrq)340 pcie_set_readrq(struct pci_dev *pdev, int rrq)
341 {
342 uint16_t val;
343
344 pcie_capability_read_word(pdev, PCI_PCIE_DCSR, &val);
345 val &= ~PCI_PCIE_DCSR_MPS;
346 val |= (ffs(rrq) - 8) << 12;
347 return pcie_capability_write_word(pdev, PCI_PCIE_DCSR, val);
348 }
349
350 static inline void
pci_set_master(struct pci_dev * pdev)351 pci_set_master(struct pci_dev *pdev)
352 {
353 }
354
355 static inline void
pci_clear_master(struct pci_dev * pdev)356 pci_clear_master(struct pci_dev *pdev)
357 {
358 }
359
360 static inline void
pci_save_state(struct pci_dev * pdev)361 pci_save_state(struct pci_dev *pdev)
362 {
363 }
364
365 static inline void
pci_restore_state(struct pci_dev * pdev)366 pci_restore_state(struct pci_dev *pdev)
367 {
368 }
369
370 static inline int
pci_enable_msi(struct pci_dev * pdev)371 pci_enable_msi(struct pci_dev *pdev)
372 {
373 return 0;
374 }
375
376 static inline void
pci_disable_msi(struct pci_dev * pdev)377 pci_disable_msi(struct pci_dev *pdev)
378 {
379 }
380
381 typedef enum {
382 PCI_D0,
383 PCI_D1,
384 PCI_D2,
385 PCI_D3hot,
386 PCI_D3cold
387 } pci_power_t;
388
389 enum pci_bus_speed {
390 PCIE_SPEED_2_5GT,
391 PCIE_SPEED_5_0GT,
392 PCIE_SPEED_8_0GT,
393 PCIE_SPEED_16_0GT,
394 PCIE_SPEED_32_0GT,
395 PCIE_SPEED_64_0GT,
396 PCI_SPEED_UNKNOWN
397 };
398
399 enum pcie_link_width {
400 PCIE_LNK_X1 = 1,
401 PCIE_LNK_X2 = 2,
402 PCIE_LNK_X4 = 4,
403 PCIE_LNK_X8 = 8,
404 PCIE_LNK_X12 = 12,
405 PCIE_LNK_X16 = 16,
406 PCIE_LNK_X32 = 32,
407 PCIE_LNK_WIDTH_UNKNOWN = 0xff
408 };
409
410 typedef unsigned int pci_ers_result_t;
411 typedef unsigned int pci_channel_state_t;
412
413 #define PCI_ERS_RESULT_DISCONNECT 0
414 #define PCI_ERS_RESULT_RECOVERED 1
415
416 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *);
417 enum pcie_link_width pcie_get_width_cap(struct pci_dev *);
418 int pci_resize_resource(struct pci_dev *, int, int);
419
420 static inline void
pcie_bandwidth_available(struct pci_dev * pdev,struct pci_dev ** ldev,enum pci_bus_speed * speed,enum pcie_link_width * width)421 pcie_bandwidth_available(struct pci_dev *pdev, struct pci_dev **ldev,
422 enum pci_bus_speed *speed, enum pcie_link_width *width)
423 {
424 struct pci_dev *bdev = pdev->bus->self;
425 if (bdev == NULL)
426 return;
427
428 if (speed)
429 *speed = pcie_get_speed_cap(bdev);
430 if (width)
431 *width = pcie_get_width_cap(bdev);
432 }
433
434 static inline int
pci_enable_device(struct pci_dev * pdev)435 pci_enable_device(struct pci_dev *pdev)
436 {
437 return 0;
438 }
439
440 static inline void
pci_disable_device(struct pci_dev * pdev)441 pci_disable_device(struct pci_dev *pdev)
442 {
443 }
444
445 static inline int
pci_wait_for_pending_transaction(struct pci_dev * pdev)446 pci_wait_for_pending_transaction(struct pci_dev *pdev)
447 {
448 return 0;
449 }
450
451 static inline bool
pci_is_thunderbolt_attached(struct pci_dev * pdev)452 pci_is_thunderbolt_attached(struct pci_dev *pdev)
453 {
454 return false;
455 }
456
457 static inline void
pci_set_drvdata(struct pci_dev * pdev,void * data)458 pci_set_drvdata(struct pci_dev *pdev, void *data)
459 {
460 }
461
462 static inline int
pci_domain_nr(struct pci_bus * pbus)463 pci_domain_nr(struct pci_bus *pbus)
464 {
465 return pbus->domain_nr;
466 }
467
468 static inline int
pci_irq_vector(struct pci_dev * pdev,unsigned int num)469 pci_irq_vector(struct pci_dev *pdev, unsigned int num)
470 {
471 return pdev->irq;
472 }
473
474 static inline void
pci_free_irq_vectors(struct pci_dev * pdev)475 pci_free_irq_vectors(struct pci_dev *pdev)
476 {
477 }
478
479 static inline int
pci_set_power_state(struct pci_dev * dev,int state)480 pci_set_power_state(struct pci_dev *dev, int state)
481 {
482 return 0;
483 }
484
485 struct pci_driver;
486
487 static inline int
pci_register_driver(struct pci_driver * pci_drv)488 pci_register_driver(struct pci_driver *pci_drv)
489 {
490 return 0;
491 }
492
493 static inline void
pci_unregister_driver(void * d)494 pci_unregister_driver(void *d)
495 {
496 }
497
498 static inline u16
pci_dev_id(struct pci_dev * dev)499 pci_dev_id(struct pci_dev *dev)
500 {
501 return dev->devfn | (dev->bus->number << 8);
502 }
503
504 static inline const struct pci_device_id *
pci_match_id(const struct pci_device_id * ids,struct pci_dev * pdev)505 pci_match_id(const struct pci_device_id *ids, struct pci_dev *pdev)
506 {
507 int i = 0;
508
509 for (i = 0; ids[i].vendor != 0; i++) {
510 if ((ids[i].vendor == pdev->vendor) &&
511 (ids[i].device == pdev->device ||
512 ids[i].device == PCI_ANY_ID) &&
513 (ids[i].subvendor == PCI_ANY_ID) &&
514 (ids[i].subdevice == PCI_ANY_ID))
515 return &ids[i];
516 }
517 return NULL;
518 }
519
520 #define PCI_CLASS_DISPLAY_VGA \
521 ((PCI_CLASS_DISPLAY << 8) | PCI_SUBCLASS_DISPLAY_VGA)
522 #define PCI_CLASS_DISPLAY_OTHER \
523 ((PCI_CLASS_DISPLAY << 8) | PCI_SUBCLASS_DISPLAY_MISC)
524 #define PCI_CLASS_ACCELERATOR_PROCESSING \
525 (PCI_CLASS_ACCELERATOR << 8)
526
527 #endif /* _LINUX_PCI_H_ */
528