1 /*
2 * QEMU IDE Emulation: PCI Bus support.
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "qemu/osdep.h"
27 #include "hw/irq.h"
28 #include "hw/pci/pci.h"
29 #include "migration/vmstate.h"
30 #include "sysemu/dma.h"
31 #include "qemu/error-report.h"
32 #include "qemu/module.h"
33 #include "hw/ide/pci.h"
34 #include "ide-internal.h"
35 #include "trace.h"
36
37 #define BMDMA_PAGE_SIZE 4096
38
39 #define BM_MIGRATION_COMPAT_STATUS_BITS \
40 (IDE_RETRY_DMA | IDE_RETRY_PIO | \
41 IDE_RETRY_READ | IDE_RETRY_FLUSH)
42
pci_ide_status_read(void * opaque,hwaddr addr,unsigned size)43 static uint64_t pci_ide_status_read(void *opaque, hwaddr addr, unsigned size)
44 {
45 IDEBus *bus = opaque;
46
47 if (addr != 2 || size != 1) {
48 return ((uint64_t)1 << (size * 8)) - 1;
49 }
50 return ide_status_read(bus, addr + 2);
51 }
52
pci_ide_ctrl_write(void * opaque,hwaddr addr,uint64_t data,unsigned size)53 static void pci_ide_ctrl_write(void *opaque, hwaddr addr,
54 uint64_t data, unsigned size)
55 {
56 IDEBus *bus = opaque;
57
58 if (addr != 2 || size != 1) {
59 return;
60 }
61 ide_ctrl_write(bus, addr + 2, data);
62 }
63
64 const MemoryRegionOps pci_ide_cmd_le_ops = {
65 .read = pci_ide_status_read,
66 .write = pci_ide_ctrl_write,
67 .endianness = DEVICE_LITTLE_ENDIAN,
68 };
69
pci_ide_data_read(void * opaque,hwaddr addr,unsigned size)70 static uint64_t pci_ide_data_read(void *opaque, hwaddr addr, unsigned size)
71 {
72 IDEBus *bus = opaque;
73
74 if (size == 1) {
75 return ide_ioport_read(bus, addr);
76 } else if (addr == 0) {
77 if (size == 2) {
78 return ide_data_readw(bus, addr);
79 } else {
80 return ide_data_readl(bus, addr);
81 }
82 }
83 return ((uint64_t)1 << (size * 8)) - 1;
84 }
85
pci_ide_data_write(void * opaque,hwaddr addr,uint64_t data,unsigned size)86 static void pci_ide_data_write(void *opaque, hwaddr addr,
87 uint64_t data, unsigned size)
88 {
89 IDEBus *bus = opaque;
90
91 if (size == 1) {
92 ide_ioport_write(bus, addr, data);
93 } else if (addr == 0) {
94 if (size == 2) {
95 ide_data_writew(bus, addr, data);
96 } else {
97 ide_data_writel(bus, addr, data);
98 }
99 }
100 }
101
102 const MemoryRegionOps pci_ide_data_le_ops = {
103 .read = pci_ide_data_read,
104 .write = pci_ide_data_write,
105 .endianness = DEVICE_LITTLE_ENDIAN,
106 };
107
pci_ide_update_mode(PCIIDEState * s)108 void pci_ide_update_mode(PCIIDEState *s)
109 {
110 PCIDevice *d = PCI_DEVICE(s);
111 uint8_t mode = d->config[PCI_CLASS_PROG];
112
113 /*
114 * This function only configures the BARs/ioports for now: PCI IDE
115 * controllers must manage their own IRQ routing
116 */
117
118 switch (mode & 0xf) {
119 case 0xa:
120 /* Both channels legacy mode */
121
122 /*
123 * TODO: according to the PCI IDE specification the BARs should
124 * be completely disabled, however Linux for the pegasos2
125 * machine stil accesses the BAR addresses after switching to legacy
126 * mode. Hence we leave them active for now.
127 */
128
129 /* Clear interrupt pin */
130 pci_config_set_interrupt_pin(d->config, 0);
131
132 /* Add legacy IDE ports */
133 if (!s->bus[0].portio_list.owner) {
134 portio_list_init(&s->bus[0].portio_list, OBJECT(d),
135 ide_portio_list, &s->bus[0], "ide");
136 portio_list_add(&s->bus[0].portio_list,
137 pci_address_space_io(d), 0x1f0);
138 }
139
140 if (!s->bus[0].portio2_list.owner) {
141 portio_list_init(&s->bus[0].portio2_list, OBJECT(d),
142 ide_portio2_list, &s->bus[0], "ide");
143 portio_list_add(&s->bus[0].portio2_list,
144 pci_address_space_io(d), 0x3f6);
145 }
146
147 if (!s->bus[1].portio_list.owner) {
148 portio_list_init(&s->bus[1].portio_list, OBJECT(d),
149 ide_portio_list, &s->bus[1], "ide");
150 portio_list_add(&s->bus[1].portio_list,
151 pci_address_space_io(d), 0x170);
152 }
153
154 if (!s->bus[1].portio2_list.owner) {
155 portio_list_init(&s->bus[1].portio2_list, OBJECT(d),
156 ide_portio2_list, &s->bus[1], "ide");
157 portio_list_add(&s->bus[1].portio2_list,
158 pci_address_space_io(d), 0x376);
159 }
160 break;
161
162 case 0xf:
163 /* Both channels native mode */
164
165 /* Set interrupt pin */
166 pci_config_set_interrupt_pin(d->config, 1);
167
168 /* Remove legacy IDE ports */
169 if (s->bus[0].portio_list.owner) {
170 portio_list_del(&s->bus[0].portio_list);
171 portio_list_destroy(&s->bus[0].portio_list);
172 }
173
174 if (s->bus[0].portio2_list.owner) {
175 portio_list_del(&s->bus[0].portio2_list);
176 portio_list_destroy(&s->bus[0].portio2_list);
177 }
178
179 if (s->bus[1].portio_list.owner) {
180 portio_list_del(&s->bus[1].portio_list);
181 portio_list_destroy(&s->bus[1].portio_list);
182 }
183
184 if (s->bus[1].portio2_list.owner) {
185 portio_list_del(&s->bus[1].portio2_list);
186 portio_list_destroy(&s->bus[1].portio2_list);
187 }
188 break;
189 }
190 }
191
bmdma_active_if(BMDMAState * bmdma)192 static IDEState *bmdma_active_if(BMDMAState *bmdma)
193 {
194 assert(bmdma->bus->retry_unit != (uint8_t)-1);
195 return bmdma->bus->ifs + bmdma->bus->retry_unit;
196 }
197
bmdma_start_dma(const IDEDMA * dma,IDEState * s,BlockCompletionFunc * dma_cb)198 static void bmdma_start_dma(const IDEDMA *dma, IDEState *s,
199 BlockCompletionFunc *dma_cb)
200 {
201 BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
202
203 bm->dma_cb = dma_cb;
204 bm->cur_prd_last = 0;
205 bm->cur_prd_addr = 0;
206 bm->cur_prd_len = 0;
207
208 if (bm->status & BM_STATUS_DMAING) {
209 bm->dma_cb(bmdma_active_if(bm), 0);
210 }
211 }
212
213 /**
214 * Prepare an sglist based on available PRDs.
215 * @limit: How many bytes to prepare total.
216 *
217 * Returns the number of bytes prepared, -1 on error.
218 * IDEState.io_buffer_size will contain the number of bytes described
219 * by the PRDs, whether or not we added them to the sglist.
220 */
bmdma_prepare_buf(const IDEDMA * dma,int32_t limit)221 static int32_t bmdma_prepare_buf(const IDEDMA *dma, int32_t limit)
222 {
223 BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
224 IDEState *s = bmdma_active_if(bm);
225 PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
226 struct {
227 uint32_t addr;
228 uint32_t size;
229 } prd;
230 int l, len;
231
232 pci_dma_sglist_init(&s->sg, pci_dev,
233 s->nsector / (BMDMA_PAGE_SIZE / BDRV_SECTOR_SIZE) + 1);
234 s->io_buffer_size = 0;
235 for(;;) {
236 if (bm->cur_prd_len == 0) {
237 /* end of table (with a fail safe of one page) */
238 if (bm->cur_prd_last ||
239 (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE) {
240 return s->sg.size;
241 }
242 pci_dma_read(pci_dev, bm->cur_addr, &prd, 8);
243 bm->cur_addr += 8;
244 prd.addr = le32_to_cpu(prd.addr);
245 prd.size = le32_to_cpu(prd.size);
246 len = prd.size & 0xfffe;
247 if (len == 0)
248 len = 0x10000;
249 bm->cur_prd_len = len;
250 bm->cur_prd_addr = prd.addr;
251 bm->cur_prd_last = (prd.size & 0x80000000);
252 }
253 l = bm->cur_prd_len;
254 if (l > 0) {
255 uint64_t sg_len;
256
257 /* Don't add extra bytes to the SGList; consume any remaining
258 * PRDs from the guest, but ignore them. */
259 sg_len = MIN(limit - s->sg.size, bm->cur_prd_len);
260 if (sg_len) {
261 qemu_sglist_add(&s->sg, bm->cur_prd_addr, sg_len);
262 }
263
264 bm->cur_prd_addr += l;
265 bm->cur_prd_len -= l;
266 s->io_buffer_size += l;
267 }
268 }
269
270 qemu_sglist_destroy(&s->sg);
271 s->io_buffer_size = 0;
272 return -1;
273 }
274
275 /* return 0 if buffer completed */
bmdma_rw_buf(const IDEDMA * dma,bool is_write)276 static int bmdma_rw_buf(const IDEDMA *dma, bool is_write)
277 {
278 BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
279 IDEState *s = bmdma_active_if(bm);
280 PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
281 struct {
282 uint32_t addr;
283 uint32_t size;
284 } prd;
285 int l, len;
286
287 for(;;) {
288 l = s->io_buffer_size - s->io_buffer_index;
289 if (l <= 0)
290 break;
291 if (bm->cur_prd_len == 0) {
292 /* end of table (with a fail safe of one page) */
293 if (bm->cur_prd_last ||
294 (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
295 return 0;
296 pci_dma_read(pci_dev, bm->cur_addr, &prd, 8);
297 bm->cur_addr += 8;
298 prd.addr = le32_to_cpu(prd.addr);
299 prd.size = le32_to_cpu(prd.size);
300 len = prd.size & 0xfffe;
301 if (len == 0)
302 len = 0x10000;
303 bm->cur_prd_len = len;
304 bm->cur_prd_addr = prd.addr;
305 bm->cur_prd_last = (prd.size & 0x80000000);
306 }
307 if (l > bm->cur_prd_len)
308 l = bm->cur_prd_len;
309 if (l > 0) {
310 if (is_write) {
311 pci_dma_write(pci_dev, bm->cur_prd_addr,
312 s->io_buffer + s->io_buffer_index, l);
313 } else {
314 pci_dma_read(pci_dev, bm->cur_prd_addr,
315 s->io_buffer + s->io_buffer_index, l);
316 }
317 bm->cur_prd_addr += l;
318 bm->cur_prd_len -= l;
319 s->io_buffer_index += l;
320 }
321 }
322 return 1;
323 }
324
bmdma_set_inactive(const IDEDMA * dma,bool more)325 static void bmdma_set_inactive(const IDEDMA *dma, bool more)
326 {
327 BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
328
329 bm->dma_cb = NULL;
330 if (more) {
331 bm->status |= BM_STATUS_DMAING;
332 } else {
333 bm->status &= ~BM_STATUS_DMAING;
334 }
335 }
336
bmdma_restart_dma(const IDEDMA * dma)337 static void bmdma_restart_dma(const IDEDMA *dma)
338 {
339 BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
340
341 bm->cur_addr = bm->addr;
342 }
343
bmdma_cancel(BMDMAState * bm)344 static void bmdma_cancel(BMDMAState *bm)
345 {
346 if (bm->status & BM_STATUS_DMAING) {
347 /* cancel DMA request */
348 bmdma_set_inactive(&bm->dma, false);
349 }
350 }
351
bmdma_reset(const IDEDMA * dma)352 static void bmdma_reset(const IDEDMA *dma)
353 {
354 BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
355
356 trace_bmdma_reset();
357 bmdma_cancel(bm);
358 bm->cmd = 0;
359 bm->status = 0;
360 bm->addr = 0;
361 bm->cur_addr = 0;
362 bm->cur_prd_last = 0;
363 bm->cur_prd_addr = 0;
364 bm->cur_prd_len = 0;
365 }
366
bmdma_irq(void * opaque,int n,int level)367 static void bmdma_irq(void *opaque, int n, int level)
368 {
369 BMDMAState *bm = opaque;
370
371 if (!level) {
372 /* pass through lower */
373 qemu_set_irq(bm->irq, level);
374 return;
375 }
376
377 bm->status |= BM_STATUS_INT;
378
379 /* trigger the real irq */
380 qemu_set_irq(bm->irq, level);
381 }
382
bmdma_cmd_writeb(BMDMAState * bm,uint32_t val)383 void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val)
384 {
385 trace_bmdma_cmd_writeb(val);
386
387 /* Ignore writes to SSBM if it keeps the old value */
388 if ((val & BM_CMD_START) != (bm->cmd & BM_CMD_START)) {
389 if (!(val & BM_CMD_START)) {
390 ide_cancel_dma_sync(ide_bus_active_if(bm->bus));
391 bm->status &= ~BM_STATUS_DMAING;
392 } else {
393 bm->cur_addr = bm->addr;
394 if (!(bm->status & BM_STATUS_DMAING)) {
395 bm->status |= BM_STATUS_DMAING;
396 /* start dma transfer if possible */
397 if (bm->dma_cb)
398 bm->dma_cb(bmdma_active_if(bm), 0);
399 }
400 }
401 }
402
403 bm->cmd = val & 0x09;
404 }
405
bmdma_status_writeb(BMDMAState * bm,uint32_t val)406 void bmdma_status_writeb(BMDMAState *bm, uint32_t val)
407 {
408 bm->status = (val & 0x60) | (bm->status & BM_STATUS_DMAING)
409 | (bm->status & ~val & (BM_STATUS_ERROR | BM_STATUS_INT));
410 }
411
bmdma_addr_read(void * opaque,hwaddr addr,unsigned width)412 static uint64_t bmdma_addr_read(void *opaque, hwaddr addr,
413 unsigned width)
414 {
415 BMDMAState *bm = opaque;
416 uint32_t mask = (1ULL << (width * 8)) - 1;
417 uint64_t data;
418
419 data = (bm->addr >> (addr * 8)) & mask;
420 trace_bmdma_addr_read(data);
421 return data;
422 }
423
bmdma_addr_write(void * opaque,hwaddr addr,uint64_t data,unsigned width)424 static void bmdma_addr_write(void *opaque, hwaddr addr,
425 uint64_t data, unsigned width)
426 {
427 BMDMAState *bm = opaque;
428 int shift = addr * 8;
429 uint32_t mask = (1ULL << (width * 8)) - 1;
430
431 trace_bmdma_addr_write(data);
432 bm->addr &= ~(mask << shift);
433 bm->addr |= ((data & mask) << shift) & ~3;
434 }
435
436 MemoryRegionOps bmdma_addr_ioport_ops = {
437 .read = bmdma_addr_read,
438 .write = bmdma_addr_write,
439 .endianness = DEVICE_LITTLE_ENDIAN,
440 };
441
ide_bmdma_current_needed(void * opaque)442 static bool ide_bmdma_current_needed(void *opaque)
443 {
444 BMDMAState *bm = opaque;
445
446 return (bm->cur_prd_len != 0);
447 }
448
ide_bmdma_status_needed(void * opaque)449 static bool ide_bmdma_status_needed(void *opaque)
450 {
451 BMDMAState *bm = opaque;
452
453 /* Older versions abused some bits in the status register for internal
454 * error state. If any of these bits are set, we must add a subsection to
455 * transfer the real status register */
456 uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
457
458 return ((bm->status & abused_bits) != 0);
459 }
460
ide_bmdma_pre_save(void * opaque)461 static int ide_bmdma_pre_save(void *opaque)
462 {
463 BMDMAState *bm = opaque;
464 uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
465
466 if (!(bm->status & BM_STATUS_DMAING) && bm->dma_cb) {
467 bm->bus->error_status =
468 ide_dma_cmd_to_retry(bmdma_active_if(bm)->dma_cmd);
469 }
470 bm->migration_retry_unit = bm->bus->retry_unit;
471 bm->migration_retry_sector_num = bm->bus->retry_sector_num;
472 bm->migration_retry_nsector = bm->bus->retry_nsector;
473 bm->migration_compat_status =
474 (bm->status & ~abused_bits) | (bm->bus->error_status & abused_bits);
475
476 return 0;
477 }
478
479 /* This function accesses bm->bus->error_status which is loaded only after
480 * BMDMA itself. This is why the function is called from ide_pci_post_load
481 * instead of being registered with VMState where it would run too early. */
ide_bmdma_post_load(void * opaque,int version_id)482 static int ide_bmdma_post_load(void *opaque, int version_id)
483 {
484 BMDMAState *bm = opaque;
485 uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
486
487 if (bm->status == 0) {
488 bm->status = bm->migration_compat_status & ~abused_bits;
489 bm->bus->error_status |= bm->migration_compat_status & abused_bits;
490 }
491 if (bm->bus->error_status) {
492 bm->bus->retry_sector_num = bm->migration_retry_sector_num;
493 bm->bus->retry_nsector = bm->migration_retry_nsector;
494 bm->bus->retry_unit = bm->migration_retry_unit;
495 }
496
497 return 0;
498 }
499
500 static const VMStateDescription vmstate_bmdma_current = {
501 .name = "ide bmdma_current",
502 .version_id = 1,
503 .minimum_version_id = 1,
504 .needed = ide_bmdma_current_needed,
505 .fields = (const VMStateField[]) {
506 VMSTATE_UINT32(cur_addr, BMDMAState),
507 VMSTATE_UINT32(cur_prd_last, BMDMAState),
508 VMSTATE_UINT32(cur_prd_addr, BMDMAState),
509 VMSTATE_UINT32(cur_prd_len, BMDMAState),
510 VMSTATE_END_OF_LIST()
511 }
512 };
513
514 static const VMStateDescription vmstate_bmdma_status = {
515 .name ="ide bmdma/status",
516 .version_id = 1,
517 .minimum_version_id = 1,
518 .needed = ide_bmdma_status_needed,
519 .fields = (const VMStateField[]) {
520 VMSTATE_UINT8(status, BMDMAState),
521 VMSTATE_END_OF_LIST()
522 }
523 };
524
525 static const VMStateDescription vmstate_bmdma = {
526 .name = "ide bmdma",
527 .version_id = 3,
528 .minimum_version_id = 0,
529 .pre_save = ide_bmdma_pre_save,
530 .fields = (const VMStateField[]) {
531 VMSTATE_UINT8(cmd, BMDMAState),
532 VMSTATE_UINT8(migration_compat_status, BMDMAState),
533 VMSTATE_UINT32(addr, BMDMAState),
534 VMSTATE_INT64(migration_retry_sector_num, BMDMAState),
535 VMSTATE_UINT32(migration_retry_nsector, BMDMAState),
536 VMSTATE_UINT8(migration_retry_unit, BMDMAState),
537 VMSTATE_END_OF_LIST()
538 },
539 .subsections = (const VMStateDescription * const []) {
540 &vmstate_bmdma_current,
541 &vmstate_bmdma_status,
542 NULL
543 }
544 };
545
ide_pci_post_load(void * opaque,int version_id)546 static int ide_pci_post_load(void *opaque, int version_id)
547 {
548 PCIIDEState *d = opaque;
549 int i;
550
551 for(i = 0; i < 2; i++) {
552 /* current versions always store 0/1, but older version
553 stored bigger values. We only need last bit */
554 d->bmdma[i].migration_retry_unit &= 1;
555 ide_bmdma_post_load(&d->bmdma[i], -1);
556 }
557
558 return 0;
559 }
560
561 const VMStateDescription vmstate_ide_pci = {
562 .name = "ide",
563 .version_id = 3,
564 .minimum_version_id = 0,
565 .post_load = ide_pci_post_load,
566 .fields = (const VMStateField[]) {
567 VMSTATE_PCI_DEVICE(parent_obj, PCIIDEState),
568 VMSTATE_STRUCT_ARRAY(bmdma, PCIIDEState, 2, 0,
569 vmstate_bmdma, BMDMAState),
570 VMSTATE_IDE_BUS_ARRAY(bus, PCIIDEState, 2),
571 VMSTATE_IDE_DRIVES(bus[0].ifs, PCIIDEState),
572 VMSTATE_IDE_DRIVES(bus[1].ifs, PCIIDEState),
573 VMSTATE_END_OF_LIST()
574 }
575 };
576
577 /* hd_table must contain 4 block drivers */
pci_ide_create_devs(PCIDevice * dev)578 void pci_ide_create_devs(PCIDevice *dev)
579 {
580 PCIIDEState *d = PCI_IDE(dev);
581 DriveInfo *hd_table[2 * MAX_IDE_DEVS];
582 static const int bus[4] = { 0, 0, 1, 1 };
583 static const int unit[4] = { 0, 1, 0, 1 };
584 int i;
585
586 ide_drive_get(hd_table, ARRAY_SIZE(hd_table));
587 for (i = 0; i < 4; i++) {
588 if (hd_table[i]) {
589 ide_bus_create_drive(d->bus + bus[i], unit[i], hd_table[i]);
590 }
591 }
592 }
593
594 static const struct IDEDMAOps bmdma_ops = {
595 .start_dma = bmdma_start_dma,
596 .prepare_buf = bmdma_prepare_buf,
597 .rw_buf = bmdma_rw_buf,
598 .restart_dma = bmdma_restart_dma,
599 .set_inactive = bmdma_set_inactive,
600 .reset = bmdma_reset,
601 };
602
bmdma_init(IDEBus * bus,BMDMAState * bm,PCIIDEState * d)603 void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d)
604 {
605 if (bus->dma == &bm->dma) {
606 return;
607 }
608
609 bm->dma.ops = &bmdma_ops;
610 bus->dma = &bm->dma;
611 bm->irq = bus->irq;
612 bus->irq = qemu_allocate_irq(bmdma_irq, bm, 0);
613 bm->bus = bus;
614 bm->pci_dev = d;
615 }
616
pci_ide_init(Object * obj)617 static void pci_ide_init(Object *obj)
618 {
619 PCIIDEState *d = PCI_IDE(obj);
620
621 qdev_init_gpio_out_named(DEVICE(d), d->isa_irq, "isa-irq",
622 ARRAY_SIZE(d->isa_irq));
623 }
624
625 static const TypeInfo pci_ide_type_info = {
626 .name = TYPE_PCI_IDE,
627 .parent = TYPE_PCI_DEVICE,
628 .instance_size = sizeof(PCIIDEState),
629 .instance_init = pci_ide_init,
630 .abstract = true,
631 .interfaces = (InterfaceInfo[]) {
632 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
633 { },
634 },
635 };
636
pci_ide_register_types(void)637 static void pci_ide_register_types(void)
638 {
639 type_register_static(&pci_ide_type_info);
640 }
641
642 type_init(pci_ide_register_types)
643