1 /* $NetBSD: pci_map.c,v 1.32 2014/12/26 05:09:03 msaitoh Exp $ */
2
3 /*-
4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Charles M. Hannum; by William R. Studenmund; by Jason R. Thorpe.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * PCI device mapping.
34 */
35
36 #include <sys/cdefs.h>
37 __KERNEL_RCSID(0, "$NetBSD: pci_map.c,v 1.32 2014/12/26 05:09:03 msaitoh Exp $");
38
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/device.h>
42
43 #include <dev/pci/pcireg.h>
44 #include <dev/pci/pcivar.h>
45
46 static int
pci_io_find(pci_chipset_tag_t pc,pcitag_t tag,int reg,pcireg_t type,bus_addr_t * basep,bus_size_t * sizep,int * flagsp)47 pci_io_find(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type,
48 bus_addr_t *basep, bus_size_t *sizep, int *flagsp)
49 {
50 pcireg_t address, mask;
51 int s;
52
53 if (reg < PCI_MAPREG_START ||
54 #if 0
55 /*
56 * Can't do this check; some devices have mapping registers
57 * way out in left field.
58 */
59 reg >= PCI_MAPREG_END ||
60 #endif
61 (reg & 3))
62 panic("pci_io_find: bad request");
63
64 /*
65 * Section 6.2.5.1, `Address Maps', tells us that:
66 *
67 * 1) The builtin software should have already mapped the device in a
68 * reasonable way.
69 *
70 * 2) A device which wants 2^n bytes of memory will hardwire the bottom
71 * n bits of the address to 0. As recommended, we write all 1s and see
72 * what we get back.
73 */
74 s = splhigh();
75 address = pci_conf_read(pc, tag, reg);
76 pci_conf_write(pc, tag, reg, 0xffffffff);
77 mask = pci_conf_read(pc, tag, reg);
78 pci_conf_write(pc, tag, reg, address);
79 splx(s);
80
81 if (PCI_MAPREG_TYPE(address) != PCI_MAPREG_TYPE_IO) {
82 aprint_debug("pci_io_find: expected type i/o, found mem\n");
83 return 1;
84 }
85
86 if (PCI_MAPREG_IO_SIZE(mask) == 0) {
87 aprint_debug("pci_io_find: void region\n");
88 return 1;
89 }
90
91 if (basep != NULL)
92 *basep = PCI_MAPREG_IO_ADDR(address);
93 if (sizep != NULL)
94 *sizep = PCI_MAPREG_IO_SIZE(mask);
95 if (flagsp != NULL)
96 *flagsp = 0;
97
98 return 0;
99 }
100
101 static int
pci_mem_find(pci_chipset_tag_t pc,pcitag_t tag,int reg,pcireg_t type,bus_addr_t * basep,bus_size_t * sizep,int * flagsp)102 pci_mem_find(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type,
103 bus_addr_t *basep, bus_size_t *sizep, int *flagsp)
104 {
105 pcireg_t address, mask, address1 = 0, mask1 = 0xffffffff;
106 u_int64_t waddress, wmask;
107 int s, is64bit, isrom;
108
109 is64bit = (PCI_MAPREG_MEM_TYPE(type) == PCI_MAPREG_MEM_TYPE_64BIT);
110 isrom = (reg == PCI_MAPREG_ROM);
111
112 if ((!isrom) && (reg < PCI_MAPREG_START ||
113 #if 0
114 /*
115 * Can't do this check; some devices have mapping registers
116 * way out in left field.
117 */
118 reg >= PCI_MAPREG_END ||
119 #endif
120 (reg & 3)))
121 panic("pci_mem_find: bad request");
122
123 if (is64bit && (reg + 4) >= PCI_MAPREG_END)
124 panic("pci_mem_find: bad 64-bit request");
125
126 /*
127 * Section 6.2.5.1, `Address Maps', tells us that:
128 *
129 * 1) The builtin software should have already mapped the device in a
130 * reasonable way.
131 *
132 * 2) A device which wants 2^n bytes of memory will hardwire the bottom
133 * n bits of the address to 0. As recommended, we write all 1s and see
134 * what we get back. Only probe the upper BAR of a mem64 BAR if bit 31
135 * is readonly.
136 */
137 s = splhigh();
138 address = pci_conf_read(pc, tag, reg);
139 pci_conf_write(pc, tag, reg, 0xffffffff);
140 mask = pci_conf_read(pc, tag, reg);
141 pci_conf_write(pc, tag, reg, address);
142 if (is64bit) {
143 address1 = pci_conf_read(pc, tag, reg + 4);
144 if ((mask & 0x80000000) == 0) {
145 pci_conf_write(pc, tag, reg + 4, 0xffffffff);
146 mask1 = pci_conf_read(pc, tag, reg + 4);
147 pci_conf_write(pc, tag, reg + 4, address1);
148 }
149 }
150 splx(s);
151
152 if (!isrom) {
153 /*
154 * roms should have an enable bit instead of a memory
155 * type decoder bit. For normal BARs, make sure that
156 * the address decoder type matches what we asked for.
157 */
158 if (PCI_MAPREG_TYPE(address) != PCI_MAPREG_TYPE_MEM) {
159 printf("pci_mem_find: expected type mem, found i/o\n");
160 return 1;
161 }
162 /* XXX Allow 64bit bars for 32bit requests.*/
163 if (PCI_MAPREG_MEM_TYPE(address) !=
164 PCI_MAPREG_MEM_TYPE(type) &&
165 PCI_MAPREG_MEM_TYPE(address) !=
166 PCI_MAPREG_MEM_TYPE_64BIT) {
167 printf("pci_mem_find: "
168 "expected mem type %08x, found %08x\n",
169 PCI_MAPREG_MEM_TYPE(type),
170 PCI_MAPREG_MEM_TYPE(address));
171 return 1;
172 }
173 }
174
175 waddress = (u_int64_t)address1 << 32UL | address;
176 wmask = (u_int64_t)mask1 << 32UL | mask;
177
178 if ((is64bit && PCI_MAPREG_MEM64_SIZE(wmask) == 0) ||
179 (!is64bit && PCI_MAPREG_MEM_SIZE(mask) == 0)) {
180 aprint_debug("pci_mem_find: void region\n");
181 return 1;
182 }
183
184 switch (PCI_MAPREG_MEM_TYPE(address)) {
185 case PCI_MAPREG_MEM_TYPE_32BIT:
186 case PCI_MAPREG_MEM_TYPE_32BIT_1M:
187 break;
188 case PCI_MAPREG_MEM_TYPE_64BIT:
189 /*
190 * Handle the case of a 64-bit memory register on a
191 * platform with 32-bit addressing. Make sure that
192 * the address assigned and the device's memory size
193 * fit in 32 bits. We implicitly assume that if
194 * bus_addr_t is 64-bit, then so is bus_size_t.
195 */
196 if (sizeof(u_int64_t) > sizeof(bus_addr_t) &&
197 (address1 != 0 || mask1 != 0xffffffff)) {
198 printf("pci_mem_find: 64-bit memory map which is "
199 "inaccessible on a 32-bit platform\n");
200 return 1;
201 }
202 break;
203 default:
204 printf("pci_mem_find: reserved mapping register type\n");
205 return 1;
206 }
207
208 if (sizeof(u_int64_t) > sizeof(bus_addr_t)) {
209 if (basep != NULL)
210 *basep = PCI_MAPREG_MEM_ADDR(address);
211 if (sizep != NULL)
212 *sizep = PCI_MAPREG_MEM_SIZE(mask);
213 } else {
214 if (basep != NULL)
215 *basep = PCI_MAPREG_MEM64_ADDR(waddress);
216 if (sizep != NULL)
217 *sizep = PCI_MAPREG_MEM64_SIZE(wmask);
218 }
219 if (flagsp != NULL)
220 *flagsp = (isrom || PCI_MAPREG_MEM_PREFETCHABLE(address)) ?
221 BUS_SPACE_MAP_PREFETCHABLE : 0;
222
223 return 0;
224 }
225
226 #define _PCI_MAPREG_TYPEBITS(reg) \
227 (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO ? \
228 reg & PCI_MAPREG_TYPE_MASK : \
229 reg & (PCI_MAPREG_TYPE_MASK|PCI_MAPREG_MEM_TYPE_MASK))
230
231 pcireg_t
pci_mapreg_type(pci_chipset_tag_t pc,pcitag_t tag,int reg)232 pci_mapreg_type(pci_chipset_tag_t pc, pcitag_t tag, int reg)
233 {
234
235 return _PCI_MAPREG_TYPEBITS(pci_conf_read(pc, tag, reg));
236 }
237
238 int
pci_mapreg_probe(pci_chipset_tag_t pc,pcitag_t tag,int reg,pcireg_t * typep)239 pci_mapreg_probe(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t *typep)
240 {
241 pcireg_t address, mask;
242 int s;
243
244 s = splhigh();
245 address = pci_conf_read(pc, tag, reg);
246 pci_conf_write(pc, tag, reg, 0xffffffff);
247 mask = pci_conf_read(pc, tag, reg);
248 pci_conf_write(pc, tag, reg, address);
249 splx(s);
250
251 if (mask == 0) /* unimplemented mapping register */
252 return 0;
253
254 if (typep != NULL)
255 *typep = _PCI_MAPREG_TYPEBITS(address);
256 return 1;
257 }
258
259 int
pci_mapreg_info(pci_chipset_tag_t pc,pcitag_t tag,int reg,pcireg_t type,bus_addr_t * basep,bus_size_t * sizep,int * flagsp)260 pci_mapreg_info(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type,
261 bus_addr_t *basep, bus_size_t *sizep, int *flagsp)
262 {
263
264 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO)
265 return pci_io_find(pc, tag, reg, type, basep, sizep,
266 flagsp);
267 else
268 return pci_mem_find(pc, tag, reg, type, basep, sizep,
269 flagsp);
270 }
271
272 int
pci_mapreg_map(const struct pci_attach_args * pa,int reg,pcireg_t type,int busflags,bus_space_tag_t * tagp,bus_space_handle_t * handlep,bus_addr_t * basep,bus_size_t * sizep)273 pci_mapreg_map(const struct pci_attach_args *pa, int reg, pcireg_t type,
274 int busflags, bus_space_tag_t *tagp, bus_space_handle_t *handlep,
275 bus_addr_t *basep, bus_size_t *sizep)
276 {
277 return pci_mapreg_submap(pa, reg, type, busflags, 0, 0, tagp,
278 handlep, basep, sizep);
279 }
280
281 int
pci_mapreg_submap(const struct pci_attach_args * pa,int reg,pcireg_t type,int busflags,bus_size_t maxsize,bus_size_t offset,bus_space_tag_t * tagp,bus_space_handle_t * handlep,bus_addr_t * basep,bus_size_t * sizep)282 pci_mapreg_submap(const struct pci_attach_args *pa, int reg, pcireg_t type,
283 int busflags, bus_size_t maxsize, bus_size_t offset, bus_space_tag_t *tagp,
284 bus_space_handle_t *handlep, bus_addr_t *basep, bus_size_t *sizep)
285 {
286 bus_space_tag_t tag;
287 bus_space_handle_t handle;
288 bus_addr_t base;
289 bus_size_t size;
290 int flags;
291
292 if (PCI_MAPREG_TYPE(type) == PCI_MAPREG_TYPE_IO) {
293 if ((pa->pa_flags & PCI_FLAGS_IO_OKAY) == 0)
294 return 1;
295 if (pci_io_find(pa->pa_pc, pa->pa_tag, reg, type, &base,
296 &size, &flags))
297 return 1;
298 tag = pa->pa_iot;
299 } else {
300 if ((pa->pa_flags & PCI_FLAGS_MEM_OKAY) == 0)
301 return 1;
302 if (pci_mem_find(pa->pa_pc, pa->pa_tag, reg, type, &base,
303 &size, &flags))
304 return 1;
305 tag = pa->pa_memt;
306 }
307
308 if (reg == PCI_MAPREG_ROM) {
309 pcireg_t mask;
310 int s;
311 /* we have to enable the ROM address decoder... */
312 s = splhigh();
313 mask = pci_conf_read(pa->pa_pc, pa->pa_tag, reg);
314 mask |= PCI_MAPREG_ROM_ENABLE;
315 pci_conf_write(pa->pa_pc, pa->pa_tag, reg, mask);
316 splx(s);
317 }
318
319 /* If we're called with maxsize/offset of 0, behave like
320 * pci_mapreg_map.
321 */
322
323 maxsize = (maxsize != 0) ? maxsize : size;
324 base += offset;
325
326 if ((size < maxsize) || (size < (offset + maxsize)))
327 return 1;
328
329 if (bus_space_map(tag, base, maxsize, busflags | flags, &handle))
330 return 1;
331
332 if (tagp != NULL)
333 *tagp = tag;
334 if (handlep != NULL)
335 *handlep = handle;
336 if (basep != NULL)
337 *basep = base;
338 if (sizep != NULL)
339 *sizep = maxsize;
340
341 return 0;
342 }
343
344 int
pci_find_rom(const struct pci_attach_args * pa,bus_space_tag_t bst,bus_space_handle_t bsh,bus_size_t sz,int type,bus_space_handle_t * romh,bus_size_t * romsz)345 pci_find_rom(const struct pci_attach_args *pa, bus_space_tag_t bst,
346 bus_space_handle_t bsh, bus_size_t sz, int type,
347 bus_space_handle_t *romh, bus_size_t *romsz)
348 {
349 bus_size_t offset = 0, imagesz;
350 uint16_t ptr;
351 int done = 0;
352
353 /*
354 * no upper bound check; i cannot imagine a 4GB ROM, but
355 * it appears the spec would allow it!
356 */
357 if (sz < 1024)
358 return 1;
359
360 while (offset < sz && !done){
361 struct pci_rom_header hdr;
362 struct pci_rom rom;
363
364 hdr.romh_magic = bus_space_read_2(bst, bsh,
365 offset + offsetof (struct pci_rom_header, romh_magic));
366 hdr.romh_data_ptr = bus_space_read_2(bst, bsh,
367 offset + offsetof (struct pci_rom_header, romh_data_ptr));
368
369 /* no warning: quite possibly ROM is simply not populated */
370 if (hdr.romh_magic != PCI_ROM_HEADER_MAGIC)
371 return 1;
372
373 ptr = offset + hdr.romh_data_ptr;
374
375 if (ptr > sz) {
376 printf("pci_find_rom: rom data ptr out of range\n");
377 return 1;
378 }
379
380 rom.rom_signature = bus_space_read_4(bst, bsh, ptr);
381 rom.rom_vendor = bus_space_read_2(bst, bsh, ptr +
382 offsetof(struct pci_rom, rom_vendor));
383 rom.rom_product = bus_space_read_2(bst, bsh, ptr +
384 offsetof(struct pci_rom, rom_product));
385 rom.rom_class = bus_space_read_1(bst, bsh,
386 ptr + offsetof (struct pci_rom, rom_class));
387 rom.rom_subclass = bus_space_read_1(bst, bsh,
388 ptr + offsetof (struct pci_rom, rom_subclass));
389 rom.rom_interface = bus_space_read_1(bst, bsh,
390 ptr + offsetof (struct pci_rom, rom_interface));
391 rom.rom_len = bus_space_read_2(bst, bsh,
392 ptr + offsetof (struct pci_rom, rom_len));
393 rom.rom_code_type = bus_space_read_1(bst, bsh,
394 ptr + offsetof (struct pci_rom, rom_code_type));
395 rom.rom_indicator = bus_space_read_1(bst, bsh,
396 ptr + offsetof (struct pci_rom, rom_indicator));
397
398 if (rom.rom_signature != PCI_ROM_SIGNATURE) {
399 printf("pci_find_rom: bad rom data signature\n");
400 return 1;
401 }
402
403 imagesz = rom.rom_len * 512;
404
405 if ((rom.rom_vendor == PCI_VENDOR(pa->pa_id)) &&
406 (rom.rom_product == PCI_PRODUCT(pa->pa_id)) &&
407 (rom.rom_class == PCI_CLASS(pa->pa_class)) &&
408 (rom.rom_subclass == PCI_SUBCLASS(pa->pa_class)) &&
409 (rom.rom_interface == PCI_INTERFACE(pa->pa_class)) &&
410 (rom.rom_code_type == type)) {
411 *romsz = imagesz;
412 bus_space_subregion(bst, bsh, offset, imagesz, romh);
413 return 0;
414 }
415
416 /* last image check */
417 if (rom.rom_indicator & PCI_ROM_INDICATOR_LAST)
418 return 1;
419
420 /* offset by size */
421 offset += imagesz;
422 }
423 return 1;
424 }
425