1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2011 Hudson River Trading LLC
5 * Written by: John H. Baldwin <jhb@FreeBSD.org>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 /*
32 * Support APIs for Host to PCI bridge drivers and drivers that
33 * provide PCI domains.
34 */
35
36 #include <sys/param.h>
37 #include <sys/bus.h>
38 #include <sys/malloc.h>
39 #include <sys/rman.h>
40 #include <sys/systm.h>
41
42 #include <dev/pci/pcireg.h>
43 #include <dev/pci/pcivar.h>
44 #include <dev/pci/pcib_private.h>
45
46 /*
47 * Try to read the bus number of a host-PCI bridge using appropriate config
48 * registers.
49 */
50 int
host_pcib_get_busno(pci_read_config_fn read_config,int bus,int slot,int func,uint8_t * busnum)51 host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
52 uint8_t *busnum)
53 {
54 uint32_t id;
55
56 id = read_config(0, bus, slot, func, PCIR_DEVVENDOR, 4);
57 if (id == 0xffffffff)
58 return (0);
59
60 switch (id) {
61 case 0x12258086:
62 /* Intel 824?? */
63 /* XXX This is a guess */
64 /* *busnum = read_config(0, bus, slot, func, 0x41, 1); */
65 *busnum = bus;
66 break;
67 case 0x84c48086:
68 /* Intel 82454KX/GX (Orion) */
69 *busnum = read_config(0, bus, slot, func, 0x4a, 1);
70 break;
71 case 0x84ca8086:
72 /*
73 * For the 450nx chipset, there is a whole bundle of
74 * things pretending to be host bridges. The MIOC will
75 * be seen first and isn't really a pci bridge (the
76 * actual buses are attached to the PXB's). We need to
77 * read the registers of the MIOC to figure out the
78 * bus numbers for the PXB channels.
79 *
80 * Since the MIOC doesn't have a pci bus attached, we
81 * pretend it wasn't there.
82 */
83 return (0);
84 case 0x84cb8086:
85 switch (slot) {
86 case 0x12:
87 /* Intel 82454NX PXB#0, Bus#A */
88 *busnum = read_config(0, bus, 0x10, func, 0xd0, 1);
89 break;
90 case 0x13:
91 /* Intel 82454NX PXB#0, Bus#B */
92 *busnum = read_config(0, bus, 0x10, func, 0xd1, 1) + 1;
93 break;
94 case 0x14:
95 /* Intel 82454NX PXB#1, Bus#A */
96 *busnum = read_config(0, bus, 0x10, func, 0xd3, 1);
97 break;
98 case 0x15:
99 /* Intel 82454NX PXB#1, Bus#B */
100 *busnum = read_config(0, bus, 0x10, func, 0xd4, 1) + 1;
101 break;
102 }
103 break;
104
105 /* ServerWorks -- vendor 0x1166 */
106 case 0x00051166:
107 case 0x00061166:
108 case 0x00081166:
109 case 0x00091166:
110 case 0x00101166:
111 case 0x00111166:
112 case 0x00171166:
113 case 0x01011166:
114 case 0x010f1014:
115 case 0x01101166:
116 case 0x02011166:
117 case 0x02251166:
118 case 0x03021014:
119 *busnum = read_config(0, bus, slot, func, 0x44, 1);
120 break;
121
122 /* Compaq/HP -- vendor 0x0e11 */
123 case 0x60100e11:
124 *busnum = read_config(0, bus, slot, func, 0xc8, 1);
125 break;
126 default:
127 /* Don't know how to read bus number. */
128 return 0;
129 }
130
131 return 1;
132 }
133
134 #ifdef NEW_PCIB
135 /*
136 * Return a pointer to a pretty name for a PCI device. If the device
137 * has a driver attached, the device's name is used, otherwise a name
138 * is generated from the device's PCI address.
139 */
140 const char *
pcib_child_name(device_t child)141 pcib_child_name(device_t child)
142 {
143 static char buf[64];
144
145 if (device_get_nameunit(child) != NULL)
146 return (device_get_nameunit(child));
147 snprintf(buf, sizeof(buf), "pci%d:%d:%d:%d", pci_get_domain(child),
148 pci_get_bus(child), pci_get_slot(child), pci_get_function(child));
149 return (buf);
150 }
151
152 /*
153 * Some Host-PCI bridge drivers know which resource ranges they can
154 * decode and should only allocate subranges to child PCI devices.
155 * This API provides a way to manage this. The bridge driver should
156 * initialize this structure during attach and call
157 * pcib_host_res_decodes() on each resource range it decodes. It can
158 * then use pcib_host_res_alloc() and pcib_host_res_adjust() as helper
159 * routines for BUS_ALLOC_RESOURCE() and BUS_ADJUST_RESOURCE(). This
160 * API assumes that resources for any decoded ranges can be safely
161 * allocated from the parent via bus_generic_alloc_resource().
162 */
163 int
pcib_host_res_init(device_t pcib,struct pcib_host_resources * hr)164 pcib_host_res_init(device_t pcib, struct pcib_host_resources *hr)
165 {
166
167 hr->hr_pcib = pcib;
168 resource_list_init(&hr->hr_rl);
169 return (0);
170 }
171
172 int
pcib_host_res_free(device_t pcib,struct pcib_host_resources * hr)173 pcib_host_res_free(device_t pcib, struct pcib_host_resources *hr)
174 {
175
176 resource_list_free(&hr->hr_rl);
177 return (0);
178 }
179
180 int
pcib_host_res_decodes(struct pcib_host_resources * hr,int type,rman_res_t start,rman_res_t end,u_int flags)181 pcib_host_res_decodes(struct pcib_host_resources *hr, int type, rman_res_t start,
182 rman_res_t end, u_int flags)
183 {
184 struct resource_list_entry *rle;
185 int rid;
186
187 if (bootverbose)
188 device_printf(hr->hr_pcib, "decoding %d %srange %#jx-%#jx\n",
189 type, flags & RF_PREFETCHABLE ? "prefetchable ": "", start,
190 end);
191 rid = resource_list_add_next(&hr->hr_rl, type, start, end,
192 end - start + 1);
193 if (flags & RF_PREFETCHABLE) {
194 KASSERT(type == SYS_RES_MEMORY,
195 ("only memory is prefetchable"));
196 rle = resource_list_find(&hr->hr_rl, type, rid);
197 rle->flags = RLE_PREFETCH;
198 }
199 return (0);
200 }
201
202 struct resource *
pcib_host_res_alloc(struct pcib_host_resources * hr,device_t dev,int type,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_int flags)203 pcib_host_res_alloc(struct pcib_host_resources *hr, device_t dev, int type,
204 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
205 {
206 struct resource_list_entry *rle;
207 struct resource *r;
208 rman_res_t new_start, new_end;
209
210 if (flags & RF_PREFETCHABLE)
211 KASSERT(type == SYS_RES_MEMORY,
212 ("only memory is prefetchable"));
213
214 rle = resource_list_find(&hr->hr_rl, type, 0);
215 if (rle == NULL) {
216 /*
217 * No decoding ranges for this resource type, just pass
218 * the request up to the parent.
219 */
220 return (bus_generic_alloc_resource(hr->hr_pcib, dev, type, rid,
221 start, end, count, flags));
222 }
223
224 restart:
225 /* Try to allocate from each decoded range. */
226 for (; rle != NULL; rle = STAILQ_NEXT(rle, link)) {
227 if (rle->type != type)
228 continue;
229 if (((flags & RF_PREFETCHABLE) != 0) !=
230 ((rle->flags & RLE_PREFETCH) != 0))
231 continue;
232 new_start = ummax(start, rle->start);
233 new_end = ummin(end, rle->end);
234 if (new_start > new_end ||
235 new_start + count - 1 > new_end ||
236 new_start + count < new_start)
237 continue;
238 r = bus_generic_alloc_resource(hr->hr_pcib, dev, type, rid,
239 new_start, new_end, count, flags);
240 if (r != NULL) {
241 if (bootverbose)
242 device_printf(hr->hr_pcib,
243 "allocated type %d (%#jx-%#jx) for rid %x of %s\n",
244 type, rman_get_start(r), rman_get_end(r),
245 *rid, pcib_child_name(dev));
246 return (r);
247 }
248 }
249
250 /*
251 * If we failed to find a prefetch range for a memory
252 * resource, try again without prefetch.
253 */
254 if (flags & RF_PREFETCHABLE) {
255 flags &= ~RF_PREFETCHABLE;
256 rle = resource_list_find(&hr->hr_rl, type, 0);
257 goto restart;
258 }
259 return (NULL);
260 }
261
262 int
pcib_host_res_adjust(struct pcib_host_resources * hr,device_t dev,struct resource * r,rman_res_t start,rman_res_t end)263 pcib_host_res_adjust(struct pcib_host_resources *hr, device_t dev,
264 struct resource *r, rman_res_t start, rman_res_t end)
265 {
266 struct resource_list_entry *rle;
267
268 rle = resource_list_find(&hr->hr_rl, rman_get_type(r), 0);
269 if (rle == NULL) {
270 /*
271 * No decoding ranges for this resource type, just pass
272 * the request up to the parent.
273 */
274 return (bus_generic_adjust_resource(hr->hr_pcib, dev, r, start,
275 end));
276 }
277
278 /* Only allow adjustments that stay within a decoded range. */
279 for (; rle != NULL; rle = STAILQ_NEXT(rle, link)) {
280 if (rle->start <= start && rle->end >= end)
281 return (bus_generic_adjust_resource(hr->hr_pcib, dev,
282 r, start, end));
283 }
284 return (ERANGE);
285 }
286
287 #ifdef PCI_RES_BUS
288 struct pci_domain {
289 int pd_domain;
290 struct rman pd_bus_rman;
291 TAILQ_ENTRY(pci_domain) pd_link;
292 };
293
294 static TAILQ_HEAD(, pci_domain) domains = TAILQ_HEAD_INITIALIZER(domains);
295
296 /*
297 * Each PCI domain maintains its own resource manager for PCI bus
298 * numbers in that domain. Domain objects are created on first use.
299 * Host to PCI bridge drivers and PCI-PCI bridge drivers should
300 * allocate their bus ranges from their domain.
301 */
302 static struct pci_domain *
pci_find_domain(int domain)303 pci_find_domain(int domain)
304 {
305 struct pci_domain *d;
306 char buf[64];
307 int error;
308
309 TAILQ_FOREACH(d, &domains, pd_link) {
310 if (d->pd_domain == domain)
311 return (d);
312 }
313
314 snprintf(buf, sizeof(buf), "PCI domain %d bus numbers", domain);
315 d = malloc(sizeof(*d) + strlen(buf) + 1, M_DEVBUF, M_WAITOK | M_ZERO);
316 d->pd_domain = domain;
317 d->pd_bus_rman.rm_start = 0;
318 d->pd_bus_rman.rm_end = PCI_BUSMAX;
319 d->pd_bus_rman.rm_type = RMAN_ARRAY;
320 strcpy((char *)(d + 1), buf);
321 d->pd_bus_rman.rm_descr = (char *)(d + 1);
322 error = rman_init(&d->pd_bus_rman);
323 if (error == 0)
324 error = rman_manage_region(&d->pd_bus_rman, 0, PCI_BUSMAX);
325 if (error)
326 panic("Failed to initialize PCI domain %d rman", domain);
327 TAILQ_INSERT_TAIL(&domains, d, pd_link);
328 return (d);
329 }
330
331 struct resource *
pci_domain_alloc_bus(int domain,device_t dev,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_int flags)332 pci_domain_alloc_bus(int domain, device_t dev, int *rid, rman_res_t start,
333 rman_res_t end, rman_res_t count, u_int flags)
334 {
335 struct pci_domain *d;
336 struct resource *res;
337
338 if (domain < 0 || domain > PCI_DOMAINMAX)
339 return (NULL);
340 d = pci_find_domain(domain);
341 res = rman_reserve_resource(&d->pd_bus_rman, start, end, count, flags,
342 dev);
343 if (res == NULL)
344 return (NULL);
345
346 rman_set_rid(res, *rid);
347 rman_set_type(res, PCI_RES_BUS);
348 return (res);
349 }
350
351 int
pci_domain_adjust_bus(int domain,device_t dev,struct resource * r,rman_res_t start,rman_res_t end)352 pci_domain_adjust_bus(int domain, device_t dev, struct resource *r,
353 rman_res_t start, rman_res_t end)
354 {
355 #ifdef INVARIANTS
356 struct pci_domain *d;
357 #endif
358
359 if (domain < 0 || domain > PCI_DOMAINMAX)
360 return (EINVAL);
361 #ifdef INVARIANTS
362 d = pci_find_domain(domain);
363 KASSERT(rman_is_region_manager(r, &d->pd_bus_rman), ("bad resource"));
364 #endif
365 return (rman_adjust_resource(r, start, end));
366 }
367
368 int
pci_domain_release_bus(int domain,device_t dev,struct resource * r)369 pci_domain_release_bus(int domain, device_t dev, struct resource *r)
370 {
371 #ifdef INVARIANTS
372 struct pci_domain *d;
373 #endif
374
375 if (domain < 0 || domain > PCI_DOMAINMAX)
376 return (EINVAL);
377 #ifdef INVARIANTS
378 d = pci_find_domain(domain);
379 KASSERT(rman_is_region_manager(r, &d->pd_bus_rman), ("bad resource"));
380 #endif
381 return (rman_release_resource(r));
382 }
383
384 int
pci_domain_activate_bus(int domain,device_t dev,struct resource * r)385 pci_domain_activate_bus(int domain, device_t dev, struct resource *r)
386 {
387 #ifdef INVARIANTS
388 struct pci_domain *d;
389 #endif
390
391 if (domain < 0 || domain > PCI_DOMAINMAX)
392 return (EINVAL);
393 #ifdef INVARIANTS
394 d = pci_find_domain(domain);
395 KASSERT(rman_is_region_manager(r, &d->pd_bus_rman), ("bad resource"));
396 #endif
397 return (rman_activate_resource(r));
398 }
399
400 int
pci_domain_deactivate_bus(int domain,device_t dev,struct resource * r)401 pci_domain_deactivate_bus(int domain, device_t dev, struct resource *r)
402 {
403 #ifdef INVARIANTS
404 struct pci_domain *d;
405 #endif
406
407 if (domain < 0 || domain > PCI_DOMAINMAX)
408 return (EINVAL);
409 #ifdef INVARIANTS
410 d = pci_find_domain(domain);
411 KASSERT(rman_is_region_manager(r, &d->pd_bus_rman), ("bad resource"));
412 #endif
413 return (rman_deactivate_resource(r));
414 }
415 #endif /* PCI_RES_BUS */
416
417 #endif /* NEW_PCIB */
418