1 /* $NetBSD: pcibios.c,v 1.40 2019/11/10 21:16:28 chs Exp $ */
2
3 /*-
4 * Copyright (c) 1999 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * Copyright (c) 1999, by UCHIYAMA Yasushi
35 * All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 * 1. Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * 2. The name of the developer may NOT be used to endorse or promote products
43 * derived from this software without specific prior written permission.
44 *
45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
55 * SUCH DAMAGE.
56 */
57
58 /*
59 * Interface to the PCI BIOS and PCI Interrupt Routing table.
60 */
61
62 #include <sys/cdefs.h>
63 __KERNEL_RCSID(0, "$NetBSD: pcibios.c,v 1.40 2019/11/10 21:16:28 chs Exp $");
64
65 #include "opt_pcibios.h"
66 #include "opt_pcifixup.h"
67
68 #include <sys/param.h>
69 #include <sys/systm.h>
70 #include <sys/device.h>
71 #include <sys/malloc.h>
72
73 #include <dev/isa/isareg.h>
74 #include <machine/isa_machdep.h>
75
76 #include <dev/pci/pcireg.h>
77 #include <dev/pci/pcivar.h>
78 #include <dev/pci/pcidevs.h>
79
80 #include <i386/pci/pcibios.h>
81
82 #if defined(PCIBIOS_INTR_FIXUP) || defined(PCIBIOS_ADDR_FIXUP) || \
83 defined(PCIBIOS_BUS_FIXUP)
84 #error The options PCIBIOS_INTR_FIXUP, PCIBIOS_ADDR_FIXUP, and PCIBIOS_BUS_FIXUP have been obsoleted by PCI_INTR_FIXUP, PCI_ADDR_FIXUP, and PCI_BUS_FIXUP. Please adjust your kernel configuration file.
85 #endif
86
87 #ifdef PCI_INTR_FIXUP
88 #include <i386/pci/pci_intr_fixup.h>
89 #endif
90
91 #include <machine/bios32.h>
92
93 #ifdef PCIBIOSVERBOSE
94 int pcibiosverbose = 1;
95 #endif
96
97 int pcibios_present;
98
99 struct pcibios_pir_header pcibios_pir_header;
100 struct pcibios_intr_routing *pcibios_pir_table;
101 int pcibios_pir_table_nentries;
102 int pcibios_max_bus;
103
104 struct bios32_entry pcibios_entry;
105
106 void pcibios_pir_init(void);
107
108 int pcibios_get_status(uint32_t *, uint32_t *, uint32_t *,
109 uint32_t *, uint32_t *, uint32_t *, uint32_t *);
110 int pcibios_get_intr_routing(struct pcibios_intr_routing *,
111 int *, uint16_t *);
112
113 int pcibios_return_code(uint16_t, const char *);
114
115 void pcibios_print_exclirq(void);
116
117 #ifdef PCIBIOS_LIBRETTO_FIXUP
118 /* for Libretto L2/L3 hack */
119 static void pcibios_fixup_pir_table(void);
120 static void pcibios_fixup_pir_table_mask(struct pcibios_linkmap *);
121
122 struct pcibios_linkmap pir_mask[] = {
123 { 2, 0x0040 },
124 { 7, 0x0080 },
125 { 8, 0x0020 },
126 { 0, 0x0000 }
127 };
128 #endif
129
130 #ifdef PCIBIOS_SHARP_MM20_FIXUP
131 static void pcibios_mm20_fixup(void);
132 #endif
133
134 #ifdef PCIINTR_DEBUG
135 void pcibios_print_pir_table(void);
136 #endif
137
138 #define PCI_IRQ_TABLE_START 0xf0000
139 #define PCI_IRQ_TABLE_END 0xfffff
140
141 void
pcibios_init(void)142 pcibios_init(void)
143 {
144 struct bios32_entry_info ei;
145 uint32_t rev_maj, rev_min, mech1, mech2, scmech1, scmech2;
146
147 if (bios32_service(BIOS32_MAKESIG('$', 'P', 'C', 'I'),
148 &pcibios_entry, &ei) == 0) {
149 /*
150 * No PCI BIOS found; will fall back on old
151 * mechanism.
152 */
153 return;
154 }
155
156 /*
157 * We've located the PCI BIOS service; get some information
158 * about it.
159 */
160 if (pcibios_get_status(&rev_maj, &rev_min, &mech1, &mech2,
161 &scmech1, &scmech2, &pcibios_max_bus) != PCIBIOS_SUCCESS) {
162 /*
163 * We can't use the PCI BIOS; will fall back on old
164 * mechanism.
165 */
166 return;
167 }
168
169 aprint_normal("PCI BIOS rev. %d.%d found at %#" PRIxPADDR "\n",
170 rev_maj, rev_min >> 4, ei.bei_entry);
171 aprint_verbose("pcibios: config mechanism %s%s, special cycles %s%s, "
172 "last bus %d\n",
173 mech1 ? "[1]" : "[x]",
174 mech2 ? "[2]" : "[x]",
175 scmech1 ? "[1]" : "[x]",
176 scmech2 ? "[2]" : "[x]",
177 pcibios_max_bus);
178
179 /*
180 * The PCI BIOS tells us the config mechanism; fill it in now
181 * so that pci_mode_detect() doesn't have to look for it.
182 */
183 pci_mode_set(mech1 ? 1 : 2);
184
185 pcibios_present = 1;
186
187 /*
188 * Find the PCI IRQ Routing table.
189 */
190 pcibios_pir_init();
191
192 #ifdef PCI_INTR_FIXUP
193 if (pcibios_pir_table != NULL) {
194 int rv;
195 uint16_t pciirq;
196
197 /*
198 * Fixup interrupt routing.
199 */
200 rv = pci_intr_fixup(NULL, x86_bus_space_io, &pciirq);
201 switch (rv) {
202 case -1:
203 /* Non-fatal error. */
204 aprint_error("Warning: unable to fix up PCI interrupt "
205 "routing\n");
206 break;
207
208 case 1:
209 /* Fatal error. */
210 panic("pcibios_init: interrupt fixup failed");
211 break;
212 }
213
214 /*
215 * XXX Clear `pciirq' from the ISA interrupt allocation
216 * XXX mask.
217 */
218 }
219 #endif
220 }
221
222 void
pcibios_pir_init(void)223 pcibios_pir_init(void)
224 {
225 char *devinfo;
226 paddr_t pa;
227 char *p;
228 unsigned char cksum;
229 uint16_t tablesize;
230 uint8_t rev_maj, rev_min;
231 int i;
232
233 for (pa = PCI_IRQ_TABLE_START; pa < PCI_IRQ_TABLE_END; pa += 16) {
234 p = (void *)ISA_HOLE_VADDR(pa);
235 if (*(int *)p != BIOS32_MAKESIG('$', 'P', 'I', 'R')) {
236 /*
237 * XXX: Some laptops (Toshiba/Libretto L series)
238 * use _PIR instead of $PIR. So we try that too.
239 */
240 if (*(int *)p != BIOS32_MAKESIG('_', 'P', 'I', 'R'))
241 continue;
242 }
243
244 rev_min = *(p + 4);
245 rev_maj = *(p + 5);
246 tablesize = *(uint16_t *)(p + 6);
247
248 cksum = 0;
249 for (i = 0; i < tablesize; i++)
250 cksum += *(unsigned char *)(p + i);
251
252 aprint_normal(
253 "PCI IRQ Routing Table rev. %d.%d found at %#" PRIxPADDR
254 ", size %d bytes (%d entries)\n", rev_maj, rev_min, pa,
255 tablesize, (tablesize - 32) / 16);
256
257 if (cksum != 0) {
258 aprint_error("pcibios_pir_init: bad IRQ table checksum\n");
259 continue;
260 }
261
262 if (tablesize < 32 || (tablesize % 16) != 0) {
263 aprint_error("pcibios_pir_init: bad IRQ table size\n");
264 continue;
265 }
266
267 if (rev_maj != 1 || rev_min != 0) {
268 aprint_error("pcibios_pir_init: unsupported IRQ table "
269 "version\n");
270 continue;
271 }
272
273 /*
274 * We can handle this table! Make a copy of it.
275 */
276 memcpy(&pcibios_pir_header, p, 32);
277 pcibios_pir_table = malloc(tablesize - 32, M_DEVBUF,
278 M_WAITOK);
279 memcpy(pcibios_pir_table, p + 32, tablesize - 32);
280 pcibios_pir_table_nentries = (tablesize - 32) / 16;
281
282 aprint_verbose("PCI Interrupt Router at %03d:%02d:%01d",
283 pcibios_pir_header.router_bus,
284 PIR_DEVFUNC_DEVICE(pcibios_pir_header.router_devfunc),
285 PIR_DEVFUNC_FUNCTION(pcibios_pir_header.router_devfunc));
286 if (pcibios_pir_header.compat_router != 0) {
287 devinfo = malloc(256, M_DEVBUF, M_WAITOK);
288 pci_devinfo(pcibios_pir_header.compat_router,
289 0, 0, devinfo, 256);
290 aprint_verbose(" (%s compatible)", devinfo);
291 free(devinfo, M_DEVBUF);
292 }
293 aprint_verbose("\n");
294 pcibios_print_exclirq();
295
296 #ifdef PCIBIOS_LIBRETTO_FIXUP
297 /* for Libretto L2/L3 hack */
298 pcibios_fixup_pir_table();
299 #endif
300 #ifdef PCIBIOS_SHARP_MM20_FIXUP
301 pcibios_mm20_fixup();
302 #endif
303 #ifdef PCIINTR_DEBUG
304 pcibios_print_pir_table();
305 #endif
306 return;
307 }
308
309 /*
310 * If there was no PIR table found, try using the PCI BIOS
311 * Get Interrupt Routing call.
312 *
313 * XXX The interface to this call sucks; just allocate enough
314 * XXX room for 32 entries.
315 */
316 pcibios_pir_table_nentries = 32;
317 pcibios_pir_table = malloc(pcibios_pir_table_nentries *
318 sizeof(*pcibios_pir_table), M_DEVBUF, M_WAITOK);
319 if (pcibios_get_intr_routing(pcibios_pir_table,
320 &pcibios_pir_table_nentries,
321 &pcibios_pir_header.exclusive_irq) != PCIBIOS_SUCCESS) {
322 aprint_normal("No PCI IRQ Routing information available.\n");
323 free(pcibios_pir_table, M_DEVBUF);
324 pcibios_pir_table = NULL;
325 pcibios_pir_table_nentries = 0;
326 return;
327 }
328 aprint_verbose("PCI BIOS has %d Interrupt Routing table entries\n",
329 pcibios_pir_table_nentries);
330 pcibios_print_exclirq();
331
332 #ifdef PCIBIOS_LIBRETTO_FIXUP
333 /* for Libretto L2/L3 hack */
334 pcibios_fixup_pir_table();
335 #endif
336 #ifdef PCIBIOS_SHARP_MM20_FIXUP
337 pcibios_mm20_fixup();
338 #endif
339 #ifdef PCIINTR_DEBUG
340 pcibios_print_pir_table();
341 #endif
342 }
343
344 int
pcibios_get_status(uint32_t * rev_maj,uint32_t * rev_min,uint32_t * mech1,uint32_t * mech2,uint32_t * scmech1,uint32_t * scmech2,uint32_t * maxbus)345 pcibios_get_status(uint32_t *rev_maj, uint32_t *rev_min,
346 uint32_t *mech1, uint32_t *mech2, uint32_t *scmech1, uint32_t *scmech2,
347 uint32_t *maxbus)
348 {
349 uint16_t ax, bx, cx;
350 uint32_t edx;
351 int rv;
352
353 __asm volatile("lcall *(%%edi) ; \
354 jc 1f ; \
355 xor %%ah, %%ah ; \
356 1:"
357 : "=a" (ax), "=b" (bx), "=c" (cx), "=d" (edx)
358 : "0" (0xb101), "D" (&pcibios_entry));
359
360 rv = pcibios_return_code(ax, "pcibios_get_status");
361 if (rv != PCIBIOS_SUCCESS)
362 return (rv);
363
364 if (edx != BIOS32_MAKESIG('P', 'C', 'I', ' '))
365 return (PCIBIOS_SERVICE_NOT_PRESENT); /* XXX */
366
367 /*
368 * Fill in the various pieces if info we're looking for.
369 */
370 *mech1 = ax & 1;
371 *mech2 = ax & (1 << 1);
372 *scmech1 = ax & (1 << 4);
373 *scmech2 = ax & (1 << 5);
374 *rev_maj = (bx >> 8) & 0xff;
375 *rev_min = bx & 0xff;
376 *maxbus = cx & 0xff;
377
378 return (PCIBIOS_SUCCESS);
379 }
380
381 int
pcibios_get_intr_routing(struct pcibios_intr_routing * table,int * nentries,uint16_t * exclirq)382 pcibios_get_intr_routing(struct pcibios_intr_routing *table,
383 int *nentries, uint16_t *exclirq)
384 {
385 uint16_t ax, bx;
386 int rv;
387 struct {
388 uint16_t size;
389 void *offset;
390 uint16_t segment;
391 } __packed args;
392
393 args.size = *nentries * sizeof(*table);
394 args.offset = (void *)table;
395 args.segment = GSEL(GDATA_SEL, SEL_KPL);
396
397 memset(table, 0, args.size);
398
399 __asm volatile("lcall *(%%esi) ; \
400 jc 1f ; \
401 xor %%ah, %%ah ; \
402 1: movw %w2, %%ds ; \
403 movw %w2, %%es"
404 : "=a" (ax), "=b" (bx)
405 : "r" GSEL(GDATA_SEL, SEL_KPL), "0" (0xb10e), "1" (0),
406 "D" (&args), "S" (&pcibios_entry));
407
408 rv = pcibios_return_code(ax, "pcibios_get_intr_routing");
409 if (rv != PCIBIOS_SUCCESS)
410 return (rv);
411
412 *nentries = args.size / sizeof(*table);
413 *exclirq = bx;
414
415 return (PCIBIOS_SUCCESS);
416 }
417
418 int
pcibios_return_code(uint16_t ax,const char * func)419 pcibios_return_code(uint16_t ax, const char *func)
420 {
421 const char *errstr;
422 int rv = ax >> 8;
423
424 switch (rv) {
425 case PCIBIOS_SUCCESS:
426 return (PCIBIOS_SUCCESS);
427
428 case PCIBIOS_SERVICE_NOT_PRESENT:
429 errstr = "service not present";
430 break;
431
432 case PCIBIOS_FUNCTION_NOT_SUPPORTED:
433 errstr = "function not supported";
434 break;
435
436 case PCIBIOS_BAD_VENDOR_ID:
437 errstr = "bad vendor ID";
438 break;
439
440 case PCIBIOS_DEVICE_NOT_FOUND:
441 errstr = "device not found";
442 break;
443
444 case PCIBIOS_BAD_REGISTER_NUMBER:
445 errstr = "bad register number";
446 break;
447
448 case PCIBIOS_SET_FAILED:
449 errstr = "set failed";
450 break;
451
452 case PCIBIOS_BUFFER_TOO_SMALL:
453 errstr = "buffer too small";
454 break;
455
456 default:
457 aprint_error("%s: unknown return code 0x%x\n", func, rv);
458 return (rv);
459 }
460
461 aprint_error("%s: %s\n", func, errstr);
462 return (rv);
463 }
464
465 void
pcibios_print_exclirq(void)466 pcibios_print_exclirq(void)
467 {
468 int i;
469
470 if (pcibios_pir_header.exclusive_irq) {
471 aprint_verbose("PCI Exclusive IRQs:");
472 for (i = 0; i < 16; i++) {
473 if (pcibios_pir_header.exclusive_irq & (1 << i))
474 aprint_verbose(" %d", i);
475 }
476 aprint_verbose("\n");
477 }
478 }
479
480 #ifdef PCIBIOS_LIBRETTO_FIXUP
481 /* for Libretto L2/L3 hack */
482 static void
pcibios_fixup_pir_table(void)483 pcibios_fixup_pir_table(void)
484 {
485 struct pcibios_linkmap *m;
486
487 for (m = pir_mask; m->link != 0; m++)
488 pcibios_fixup_pir_table_mask(m);
489 }
490
491 void
pcibios_fixup_pir_table_mask(struct pcibios_linkmap * mask)492 pcibios_fixup_pir_table_mask(struct pcibios_linkmap *mask)
493 {
494 int i, j;
495
496 for (i = 0; i < pcibios_pir_table_nentries; i++) {
497 for (j = 0; j < 4; j++) {
498 if (pcibios_pir_table[i].linkmap[j].link == mask->link) {
499 pcibios_pir_table[i].linkmap[j].bitmap
500 &= mask->bitmap;
501 }
502 }
503 }
504 }
505 #endif
506
507 #ifdef PCIINTR_DEBUG
508 void
pcibios_print_pir_table(void)509 pcibios_print_pir_table(void)
510 {
511 int i, j;
512
513 for (i = 0; i < pcibios_pir_table_nentries; i++) {
514 printf("PIR Entry %d:\n", i);
515 printf("\tBus: %d Device: %d\n",
516 pcibios_pir_table[i].bus,
517 PIR_DEVFUNC_DEVICE(pcibios_pir_table[i].device));
518 for (j = 0; j < 4; j++) {
519 printf("\t\tINT%c: link 0x%02x bitmap 0x%04x\n",
520 'A' + j,
521 pcibios_pir_table[i].linkmap[j].link,
522 pcibios_pir_table[i].linkmap[j].bitmap);
523 }
524 }
525 }
526 #endif
527
528 #ifdef PCIBIOS_SHARP_MM20_FIXUP
529 /*
530 * This is a gross hack to get the interrupt from the EHCI controller
531 * working on a Sharp MM20. The BIOS is just incredibly buggy.
532 *
533 * The story thus far:
534 * The modern way to route the interrupt is to use ACPI. But using
535 * ACPI fails with an error message about an uninitialized local
536 * variable in the AML code. (It works in Windows, but fails in NetBSD
537 * and Linux.)
538 *
539 * The second attempt is to use PCI Interrupt Routing table. But this
540 * fails because the table does not contain any information about the
541 * interrupt from the EHCI controller. This is probably due to the fact
542 * that the table is compatible with ALi M1543, but the MM20 has an ALi M1563.
543 * The M1563 has additional interrupt lines. The ali1543.c code also
544 * cannot handle the M1653's extended interrupts. And fixing this is
545 * difficult since getting a data sheet from ALi requires signing an NDA.
546 *
547 * The third attempt is to use a BIOS call to route the interrupt
548 * (as FreeBSD does) with manually generated information. But the BIOS call
549 * fails because the BIOS code is not quite position independent. It makes
550 * some assumption about where the code segment register points.
551 *
552 * So the solution is to use the third attempt, but with a patched version
553 * of the BIOS.
554 * -- lennart@augustsson.net
555 */
556
557 #define BIOS32_START 0xe0000
558 #define BIOS32_SIZE 0x20000
559
560 static char pcibios_shadow[BIOS32_SIZE];
561 static struct bios32_entry pcibios_entry_shadow;
562
563 /*
564 * Copy BIOS and zap offending instruction.
565 * The bad instruction is
566 * mov %cs:0x63c(%ebx),%ah
567 * NetBSD does not have the code segment set up for this to work.
568 * Using the value 0xff for the table entry seems to work.
569 * The replacement is
570 * mov $0xff,%ah; nop; nop; nop; nop; nop
571 */
572 static void
pcibios_copy_bios(void)573 pcibios_copy_bios(void)
574 {
575 uint8_t *bad_instr;
576
577 memcpy(pcibios_shadow, ISA_HOLE_VADDR(BIOS32_START), BIOS32_SIZE);
578 pcibios_entry_shadow = pcibios_entry;
579 pcibios_entry_shadow.offset =
580 (void*)((u_long)pcibios_shadow +
581 (u_long)pcibios_entry.offset -
582 (u_long)ISA_HOLE_VADDR(BIOS32_START));
583
584 bad_instr = (uint8_t *)pcibios_entry_shadow.offset + 0x499;
585 if (*bad_instr != 0x2e)
586 panic("bad bios");
587 bad_instr[0] = 0xb4; bad_instr[1] = 0xff; /* mov $0xff,%ah */
588 bad_instr[2] = 0x90; /* nop */
589 bad_instr[3] = 0x90; /* nop */
590 bad_instr[4] = 0x90; /* nop */
591 bad_instr[5] = 0x90; /* nop */
592 bad_instr[6] = 0x90; /* nop */
593 }
594
595 /*
596 * Call BIOS to route an interrupt.
597 * The PCI device is identified by bus,device,func.
598 * The interrupt is on pin PIN (A-D) and interrupt IRQ.
599 * BIOS knows the magic for the interrupt controller.
600 */
601 static int
pcibios_biosroute(int bus,int device,int func,int pin,int irq)602 pcibios_biosroute(int bus, int device, int func, int pin, int irq)
603 {
604 uint16_t ax, bx, cx;
605 int rv;
606
607 aprint_debug("pcibios_biosroute: b,d,f=%d,%d,%d pin=%x irq=%d\n",
608 bus, device, func, pin+0xa, irq);
609
610 bx = (bus << 8) | (device << 3) | func;
611 cx = (irq << 8) | (0xa + pin);
612
613 __asm volatile("lcall *(%%esi) ; \
614 jc 1f ; \
615 xor %%ah, %%ah ; \
616 1: movw %w1, %%ds ; \
617 movw %w1, %%es"
618 : "=a" (ax)
619 : "r" GSEL(GDATA_SEL, SEL_KPL), "0" (0xb10f),
620 "b" (bx), "c" (cx),
621 "S" (&pcibios_entry_shadow));
622
623 rv = pcibios_return_code(ax, "pcibios_biosroute");
624
625 return rv;
626 }
627
628 #define MM20_PCI_BUS 0
629 #define MM20_PCI_EHCI_DEV 15
630 #define MM20_PCI_EHCI_FUNC 3
631 #define MM20_PCI_EHCI_PIN 3
632 #define MM20_PCI_EHCI_INTR 11
633 #define MM20_PCI_ISA_DEV 3
634 #define MM20_PCI_ISA_FUNC 0
635
636 static void
pcibios_mm20_fixup(void)637 pcibios_mm20_fixup(void)
638 {
639 pci_chipset_tag_t pc;
640 pcitag_t tag;
641
642 /* Copy BIOS */
643 pcibios_copy_bios();
644 /* Route the interrupt for the EHCI controller. */
645 (void)pcibios_biosroute(MM20_PCI_BUS,
646 MM20_PCI_EHCI_DEV,
647 MM20_PCI_EHCI_FUNC,
648 MM20_PCI_EHCI_PIN,
649 MM20_PCI_EHCI_INTR);
650
651 /* Fake some tags. */
652 pc = NULL;
653 tag = pci_make_tag(pc, MM20_PCI_BUS, MM20_PCI_EHCI_DEV,
654 MM20_PCI_EHCI_FUNC);
655 /* Set interrupt register in EHCI controller */
656 pci_conf_write(pc, tag, PCI_INTERRUPT_REG,
657 0x50000400 + MM20_PCI_EHCI_INTR);
658 tag = pci_make_tag(pc, MM20_PCI_BUS, MM20_PCI_ISA_DEV,
659 MM20_PCI_ISA_FUNC);
660 /* Set some unknown registers in the ISA bridge. */
661 pci_conf_write(pc, tag, 0x58, 0xd87f5300);
662 pci_conf_write(pc, tag, 0x74, 0x00000009);
663 }
664
665 #endif /* PCIBIOS_SHARP_MM20_FIXUP */
666