1 /* $NetBSD: aic79xxvar.h,v 1.29 2021/10/15 22:32:28 andvar Exp $ */
2
3 /*
4 * Core definitions and data structures sharable across OS platforms.
5 *
6 * Copyright (c) 1994-2002 Justin T. Gibbs.
7 * Copyright (c) 2000-2002 Adaptec Inc.
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * substantially similar to the "NO WARRANTY" disclaimer below
18 * ("Disclaimer") and any redistribution must be conditioned upon
19 * including a substantially similar Disclaimer requirement for further
20 * binary redistribution.
21 * 3. Neither the names of the above-listed copyright holders nor the names
22 * of any contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * Alternatively, this software may be distributed under the terms of the
26 * GNU General Public License ("GPL") version 2 as published by the Free
27 * Software Foundation.
28 *
29 * NO WARRANTY
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGES.
41 *
42 * Id: //depot/aic7xxx/aic7xxx/aic79xx.h#94 $
43 *
44 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx.h,v 1.15 2003/06/28 04:45:25 gibbs Exp $
45 */
46 /*
47 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003
48 */
49
50 #ifndef _AIC79XXVAR_H_
51 #define _AIC79XXVAR_H_
52
53 /* Register Definitions */
54 #include <dev/microcode/aic7xxx/aic79xx_reg.h>
55
56 /************************* Forward Declarations *******************************/
57 struct ahd_platform_data;
58 struct scb_platform_data;
59
60 /****************************** Useful Macros *********************************/
61 #ifndef MAX
62 #define MAX(a,b) (((a) > (b)) ? (a) : (b))
63 #endif
64
65 #ifndef MIN
66 #define MIN(a,b) (((a) < (b)) ? (a) : (b))
67 #endif
68
69 #ifndef TRUE
70 #define TRUE 1
71 #endif
72 #ifndef FALSE
73 #define FALSE 0
74 #endif
75
76 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array))
77
78 #define ALL_CHANNELS '\0'
79 #define ALL_TARGETS_MASK 0xFFFF
80 #define INITIATOR_WILDCARD (~0)
81 #define SCB_LIST_NULL 0xFF00
82 #define SCB_LIST_NULL_LE (ahd_htole16(SCB_LIST_NULL))
83 #define QOUTFIFO_ENTRY_VALID 0x8000
84 #define QOUTFIFO_ENTRY_VALID_LE (ahd_htole16(0x8000))
85 #define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL)
86
87 #define SCSIID_TARGET(ahd, scsiid) \
88 (((scsiid) & TID) >> TID_SHIFT)
89 #define SCSIID_OUR_ID(scsiid) \
90 ((scsiid) & OID)
91 #define SCSIID_CHANNEL(ahd, scsiid) ('A')
92 #define SCB_IS_SCSIBUS_B(ahd, scb) (0)
93 #define SCB_GET_OUR_ID(scb) \
94 SCSIID_OUR_ID((scb)->hscb->scsiid)
95 #define SCB_GET_TARGET(ahd, scb) \
96 SCSIID_TARGET((ahd), (scb)->hscb->scsiid)
97 #define SCB_GET_CHANNEL(ahd, scb) \
98 SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid)
99 #define SCB_GET_LUN(scb) \
100 ((scb)->hscb->lun)
101 #define SCB_GET_TARGET_OFFSET(ahd, scb) \
102 SCB_GET_TARGET(ahd, scb)
103 #define SCB_GET_TARGET_MASK(ahd, scb) \
104 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb)))
105 #ifdef AHD_DEBUG
106 #define SCB_IS_SILENT(scb) \
107 ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \
108 && (((scb)->flags & SCB_SILENT) != 0))
109 #else
110 #define SCB_IS_SILENT(scb) \
111 (((scb)->flags & SCB_SILENT) != 0)
112 #endif
113 /*
114 * TCLs have the following format: TTTTLLLLLLLL
115 */
116 #define TCL_TARGET_OFFSET(tcl) \
117 ((((tcl) >> 4) & TID) >> 4)
118 #define TCL_LUN(tcl) \
119 (tcl & (AHD_NUM_LUNS - 1))
120 #define BUILD_TCL(scsiid, lun) \
121 ((lun) | (((scsiid) & TID) << 4))
122 #define BUILD_TCL_RAW(target, channel, lun) \
123 ((lun) | ((target) << 8))
124
125 #define SCB_GET_TAG(scb) \
126 ahd_le16toh(scb->hscb->tag)
127
128 #ifndef AHD_TARGET_MODE
129 #undef AHD_TMODE_ENABLE
130 #define AHD_TMODE_ENABLE 0
131 #endif
132
133 #define AHD_BUILD_COL_IDX(target, lun) \
134 (((lun) << 4) | target)
135
136 #define AHD_GET_SCB_COL_IDX(ahd, scb) \
137 ((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb))
138
139 #define AHD_SET_SCB_COL_IDX(scb, col_idx) \
140 do { \
141 (scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID; \
142 (scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1); \
143 } while (0)
144
145 #define AHD_COPY_SCB_COL_IDX(dst, src) \
146 do { \
147 dst->hscb->scsiid = src->hscb->scsiid; \
148 dst->hscb->lun = src->hscb->lun; \
149 } while (0)
150
151 #define AHD_NEVER_COL_IDX 0xFFFF
152
153 /**************************** Driver Constants ********************************/
154 /*
155 * The maximum number of supported targets.
156 */
157 #define AHD_NUM_TARGETS 16
158
159 /*
160 * The maximum number of supported luns.
161 * The identify message only supports 64 luns in non-packetized transfers.
162 * You can have 2^64 luns when information unit transfers are enabled,
163 * but until we see a need to support that many, we support 256.
164 */
165 #define AHD_NUM_LUNS_NONPKT 64
166 #define AHD_NUM_LUNS 256
167
168 /*
169 * The maximum transfer per S/G segment.
170 * Limited by MAXPHYS or a 24bit counter.
171 */
172 #define AHD_MAXTRANSFER_SIZE MIN(MAXPHYS,0x00ffffff)
173
174 /*
175 * The maximum amount of SCB storage in hardware on a controller.
176 * This value represents an upper bound. Due to software design,
177 * we may not be able to use this number.
178 */
179 #define AHD_SCB_MAX 512
180
181 /*
182 * The maximum number of concurrent transactions supported per driver instance.
183 * Sequencer Control Blocks (SCBs) store per-transaction information.
184 */
185 #define AHD_MAX_QUEUE AHD_SCB_MAX
186
187 /*
188 * Define the size of our QIN and QOUT FIFOs. They must be a power of 2
189 * in size and accommodate as many transactions as can be queued concurrently.
190 */
191 #define AHD_QIN_SIZE AHD_MAX_QUEUE
192 #define AHD_QOUT_SIZE AHD_MAX_QUEUE
193
194 #define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1))
195 /*
196 * The maximum amount of SCB storage we allocate in host memory.
197 */
198 #define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE
199
200 /*
201 * Ring Buffer of incoming target commands.
202 * We allocate 256 to simplify the logic in the sequencer
203 * by using the natural wrap point of an 8bit counter.
204 */
205 #define AHD_TMODE_CMDS 256
206
207 /* Reset line assertion time in us */
208 #define AHD_BUSRESET_DELAY 25
209
210 /******************* Chip Characteristics/Operating Settings *****************/
211 /*
212 * Chip Type
213 * The chip order is from least sophisticated to most sophisticated.
214 */
215 typedef enum {
216 AHD_NONE = 0x0000,
217 AHD_CHIPID_MASK = 0x00FF,
218 AHD_AIC7901 = 0x0001,
219 AHD_AIC7902 = 0x0002,
220 AHD_AIC7901A = 0x0003,
221 AHD_PCI = 0x0100, /* Bus type PCI */
222 AHD_PCIX = 0x0200, /* Bus type PCIX */
223 AHD_BUS_MASK = 0x0F00
224 } ahd_chip;
225
226 /*
227 * Features available in each chip type.
228 */
229 typedef enum {
230 AHD_FENONE = 0x00000,
231 AHD_WIDE = 0x00001,/* Wide Channel */
232 AHD_MULTI_FUNC = 0x00100,/* Multi-Function/Channel Device */
233 AHD_TARGETMODE = 0x01000,/* Has tested target mode support */
234 AHD_MULTIROLE = 0x02000,/* Space for two roles at a time */
235 AHD_RTI = 0x04000,/* Retained Training Support */
236 AHD_NEW_IOCELL_OPTS = 0x08000,/* More Signal knobs in the IOCELL */
237 AHD_NEW_DFCNTRL_OPTS = 0x10000,/* SCSIENWRDIS bit */
238 AHD_REMOVABLE = 0x00000,/* Hot-Swap supported - None so far*/
239 AHD_AIC7901_FE = AHD_FENONE,
240 AHD_AIC7901A_FE = AHD_FENONE,
241 AHD_AIC7902_FE = AHD_MULTI_FUNC
242 } ahd_feature;
243
244 /*
245 * Bugs in the silicon that we work around in software.
246 */
247 typedef enum {
248 AHD_BUGNONE = 0x0000,
249 /*
250 * Rev A hardware fails to update LAST/CURR/NEXTSCB
251 * correctly in certain packetized selection cases.
252 */
253 AHD_SENT_SCB_UPDATE_BUG = 0x0001,
254 /* The wrong SCB is accessed to check the abort pending bit. */
255 AHD_ABORT_LQI_BUG = 0x0002,
256 /* Packetized bitbucket crosses packet boundaries. */
257 AHD_PKT_BITBUCKET_BUG = 0x0004,
258 /* The selection timer runs twice as long as its setting. */
259 AHD_LONG_SETIMO_BUG = 0x0008,
260 /* The Non-LQ CRC error status is delayed until phase change. */
261 AHD_NLQICRC_DELAYED_BUG = 0x0010,
262 /* The chip must be reset for all outgoing bus resets. */
263 AHD_SCSIRST_BUG = 0x0020,
264 /* Some PCIX fields must be saved and restored across chip reset. */
265 AHD_PCIX_CHIPRST_BUG = 0x0040,
266 /* MMAPIO is not functional in PCI-X mode. */
267 AHD_PCIX_MMAPIO_BUG = 0x0080,
268 /* Reads to SCBRAM fail to reset the discard timer. */
269 AHD_PCIX_SCBRAM_RD_BUG = 0x0100,
270 /* Bug workarounds that can be disabled on non-PCIX busses. */
271 AHD_PCIX_BUG_MASK = AHD_PCIX_CHIPRST_BUG
272 | AHD_PCIX_MMAPIO_BUG
273 | AHD_PCIX_SCBRAM_RD_BUG,
274 /*
275 * LQOSTOP0 status set even for forced selections with ATN
276 * to perform non-packetized message delivery.
277 */
278 AHD_LQO_ATNO_BUG = 0x0200,
279 /* FIFO auto-flush does not always trigger. */
280 AHD_AUTOFLUSH_BUG = 0x0400,
281 /* The CLRLQO registers are not self-clearing. */
282 AHD_CLRLQO_AUTOCLR_BUG = 0x0800,
283 /* The PACKETIZED status bit refers to the previous connection. */
284 AHD_PKTIZED_STATUS_BUG = 0x1000,
285 /* "Short Luns" are not placed into outgoing LQ packets correctly. */
286 AHD_PKT_LUN_BUG = 0x2000,
287 /*
288 * Only the FIFO allocated to the non-packetized connection may
289 * be in use during a non-packetzied connection.
290 */
291 AHD_NONPACKFIFO_BUG = 0x4000,
292 /*
293 * Writing to a DFF SCBPTR register may fail if concurrent with
294 * a hardware write to the other DFF SCBPTR register. This is
295 * not currently a concern in our sequencer since all chips with
296 * this bug have the AHD_NONPACKFIFO_BUG and all writes of concern
297 * occur in non-packetized connections.
298 */
299 AHD_MDFF_WSCBPTR_BUG = 0x8000,
300 /* SGHADDR updates are slow. */
301 AHD_REG_SLOW_SETTLE_BUG = 0x10000,
302 /*
303 * Changing the MODE_PTR coincident with an interrupt that
304 * switches to a different mode will cause the interrupt to
305 * be in the mode written outside of interrupt context.
306 */
307 AHD_SET_MODE_BUG = 0x20000,
308 /* Non-packetized busfree revision does not work. */
309 AHD_BUSFREEREV_BUG = 0x40000,
310 /*
311 * Paced transfers are indicated with a non-standard PPR
312 * option bit in the neg table, 160MHz is indicated by
313 * sync factor 0x7, and the offset if off by a factor of 2.
314 */
315 AHD_PACED_NEGTABLE_BUG = 0x80000,
316 /* LQOOVERRUN false positives. */
317 AHD_LQOOVERRUN_BUG = 0x100000,
318 /*
319 * Controller write to INTSTAT will lose to a host
320 * write to CLRINT.
321 */
322 AHD_INTCOLLISION_BUG = 0x200000,
323 /*
324 * The GEM318 violates the SCSI spec by not waiting
325 * the mandated bus settle delay between phase changes
326 * in some situations. Some aic79xx chip revs. are more
327 * strict in this regard and will treat REQ assertions
328 * that fall within the bus settle delay window as
329 * glitches. This flag tells the firmware to tolerate
330 * early REQ assertions.
331 */
332 AHD_EARLY_REQ_BUG = 0x400000,
333 /*
334 * The LED does not stay on long enough in packetized modes.
335 */
336 AHD_FAINT_LED_BUG = 0x800000
337 } ahd_bug;
338
339 /*
340 * Configuration specific settings.
341 * The driver determines these settings by probing the
342 * chip/controller's configuration.
343 */
344 typedef enum {
345 AHD_FNONE = 0x00000,
346 AHD_BOOT_CHANNEL = 0x00001,/* We were set as the boot channel. */
347 AHD_USEDEFAULTS = 0x00004,/*
348 * For cards without an seeprom
349 * or a BIOS to initialize the chip's
350 * SRAM, we use the default target
351 * settings.
352 */
353 AHD_SEQUENCER_DEBUG = 0x00008,
354 AHD_RESET_BUS_A = 0x00010,
355 AHD_EXTENDED_TRANS_A = 0x00020,
356 AHD_TERM_ENB_A = 0x00040,
357 AHD_SPCHK_ENB_A = 0x00080,
358 AHD_STPWLEVEL_A = 0x00100,
359 AHD_INITIATORROLE = 0x00200,/*
360 * Allow initiator operations on
361 * this controller.
362 */
363 AHD_TARGETROLE = 0x00400,/*
364 * Allow target operations on this
365 * controller.
366 */
367 AHD_RESOURCE_SHORTAGE = 0x00800,
368 AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */
369 AHD_INT50_SPEEDFLEX = 0x02000,/*
370 * Internal 50pin connector
371 * sits behind an aic3860
372 */
373 AHD_BIOS_ENABLED = 0x04000,
374 AHD_ALL_INTERRUPTS = 0x08000,
375 AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */
376 AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */
377 AHD_CURRENT_SENSING = 0x40000,
378 AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */
379 AHD_HP_BOARD = 0x100000,
380 AHD_RESET_POLL_ACTIVE = 0x200000,
381 AHD_UPDATE_PEND_CMDS = 0x400000,
382 AHD_RUNNING_QOUTFIFO = 0x800000,
383 AHD_HAD_FIRST_SEL = 0x1000000
384 } ahd_flag;
385
386 /************************* Hardware SCB Definition ***************************/
387
388 /*
389 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB
390 * consists of a "hardware SCB" mirroring the fields available on the card
391 * and additional information the kernel stores for each transaction.
392 *
393 * To minimize space utilization, a portion of the hardware scb stores
394 * different data during different portions of a SCSI transaction.
395 * As initialized by the host driver for the initiator role, this area
396 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After
397 * the cdb has been presented to the target, this area serves to store
398 * residual transfer information and the SCSI status byte.
399 * For the target role, the contents of this area do not change, but
400 * still serve a different purpose than for the initiator role. See
401 * struct target_data for details.
402 */
403
404 /*
405 * Status information embedded in the shared portion of
406 * an SCB after passing the cdb to the target. The kernel
407 * driver will only read this data for transactions that
408 * complete abnormally.
409 */
410 struct initiator_status {
411 uint32_t residual_datacnt; /* Residual in the current S/G seg */
412 uint32_t residual_sgptr; /* The next S/G for this transfer */
413 uint8_t scsi_status; /* Standard SCSI status byte */
414 };
415
416 struct target_status {
417 uint32_t residual_datacnt; /* Residual in the current S/G seg */
418 uint32_t residual_sgptr; /* The next S/G for this transfer */
419 uint8_t scsi_status; /* SCSI status to give to initiator */
420 uint8_t target_phases; /* Bitmap of phases to execute */
421 uint8_t data_phase; /* Data-In or Data-Out */
422 uint8_t initiator_tag; /* Initiator's transaction tag */
423 };
424
425 /*
426 * Initiator mode SCB shared data area.
427 * If the embedded CDB is 12 bytes or less, we embed
428 * the sense buffer address in the SCB. This allows
429 * us to retrieve sense information without interrupting
430 * the host in packetized mode.
431 */
432 typedef uint32_t sense_addr_t;
433 #define MAX_CDB_LEN 16
434 #define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t))
435 union initiator_data {
436 struct {
437 uint64_t cdbptr;
438 uint8_t cdblen;
439 } cdb_from_host;
440 uint8_t cdb[MAX_CDB_LEN];
441 struct {
442 uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR];
443 sense_addr_t sense_addr;
444 } cdb_plus_saddr;
445 };
446
447 /*
448 * Target mode version of the shared data SCB segment.
449 */
450 struct target_data {
451 uint32_t spare[2];
452 uint8_t scsi_status; /* SCSI status to give to initiator */
453 uint8_t target_phases; /* Bitmap of phases to execute */
454 uint8_t data_phase; /* Data-In or Data-Out */
455 uint8_t initiator_tag; /* Initiator's transaction tag */
456 };
457
458 struct hardware_scb {
459 /*0*/ union {
460 union initiator_data idata;
461 struct target_data tdata;
462 struct initiator_status istatus;
463 struct target_status tstatus;
464 } shared_data;
465 /*
466 * A word about residuals.
467 * The scb is presented to the sequencer with the dataptr and datacnt
468 * fields initialized to the contents of the first S/G element to
469 * transfer. The sgptr field is initialized to the bus address for
470 * the S/G element that follows the first in the in core S/G array
471 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid
472 * S/G entry for this transfer (single S/G element transfer with the
473 * first elements address and length preloaded in the dataptr/datacnt
474 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL.
475 * The SG_FULL_RESID flag ensures that the residual will be correctly
476 * noted even if no data transfers occur. Once the data phase is entered,
477 * the residual sgptr and datacnt are loaded from the sgptr and the
478 * datacnt fields. After each S/G element's dataptr and length are
479 * loaded into the hardware, the residual sgptr is advanced. After
480 * each S/G element is expired, its datacnt field is checked to see
481 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the
482 * residual sg ptr and the transfer is considered complete. If the
483 * sequencer determines that there is a residual in the transfer, or
484 * there is non-zero status, it will set the SG_STATUS_VALID flag in
485 * sgptr and DMA the scb back into host memory. To summarize:
486 *
487 * Sequencer:
488 * o A residual has occurred if SG_FULL_RESID is set in sgptr,
489 * or residual_sgptr does not have SG_LIST_NULL set.
490 *
491 * o We are transferring the last segment if residual_datacnt has
492 * the SG_LAST_SEG flag set.
493 *
494 * Host:
495 * o A residual can only have occurred if a completed scb has the
496 * SG_STATUS_VALID flag set. Inspection of the SCSI status field,
497 * the residual_datacnt, and the residual_sgptr field will tell
498 * for sure.
499 *
500 * o residual_sgptr and sgptr refer to the "next" sg entry
501 * and so may point beyond the last valid sg entry for the
502 * transfer.
503 */
504 #define SG_PTR_MASK 0xFFFFFFF8
505 /*16*/ uint16_t tag; /* Reused by Sequencer. */
506 /*18*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */
507 /*19*/ uint8_t scsiid; /*
508 * Selection out Id
509 * Our Id (bits 0-3) Their ID (bits 4-7)
510 */
511 /*20*/ uint8_t lun;
512 /*21*/ uint8_t task_attribute;
513 /*22*/ uint8_t cdb_len;
514 /*23*/ uint8_t task_management;
515 /*24*/ uint64_t dataptr;
516 /*32*/ uint32_t datacnt; /* Byte 3 is spare. */
517 /*36*/ uint32_t sgptr;
518 /*40*/ uint32_t hscb_busaddr;
519 /*44*/ uint32_t next_hscb_busaddr;
520 /********** Long lun field only downloaded for full 8 byte lun support ********/
521 /*48*/ uint8_t pkt_long_lun[8];
522 /******* Fields below are not Downloaded (Sequencer may use for scratch) ******/
523 /*56*/ uint8_t spare[8];
524 };
525
526 /************************ Kernel SCB Definitions ******************************/
527 /*
528 * Some fields of the SCB are OS dependent. Here we collect the
529 * definitions for elements that all OS platforms need to include
530 * in there SCB definition.
531 */
532
533 /*
534 * Definition of a scatter/gather element as transferred to the controller.
535 * The aic7xxx chips only support a 24bit length. We use the top byte of
536 * the length to store additional address bits and a flag to indicate
537 * that a given segment terminates the transfer. This gives us an
538 * addressable range of 512GB on machines with 64bit PCI or with chips
539 * that can support dual address cycles on 32bit PCI buses.
540 */
541 struct ahd_dma_seg {
542 uint32_t addr;
543 uint32_t len;
544 #define AHD_DMA_LAST_SEG 0x80000000
545 #define AHD_SG_HIGH_ADDR_MASK 0x7F000000
546 #define AHD_SG_LEN_MASK 0x00FFFFFF
547 };
548
549 struct ahd_dma64_seg {
550 uint64_t addr;
551 uint32_t len;
552 uint32_t pad;
553 };
554
555 struct map_node {
556 bus_dmamap_t dmamap;
557 bus_addr_t physaddr;
558 uint8_t *vaddr;
559 bus_dma_segment_t dmasegs;
560 int nseg;
561 SLIST_ENTRY(map_node) links;
562 };
563
564 struct ahd_pci_busdata {
565 pci_chipset_tag_t pc;
566 pcitag_t tag;
567 u_int dev;
568 u_int func;
569 int pcix_off;
570 };
571
572 /*
573 * The current state of this SCB.
574 */
575 typedef enum {
576 SCB_FLAG_NONE = 0x00000,
577 SCB_TRANSMISSION_ERROR = 0x00001,/*
578 * We detected a parity or CRC
579 * error that has effected the
580 * payload of the command. This
581 * flag is checked when normal
582 * status is returned to catch
583 * the case of a target not
584 * responding to our attempt
585 * to report the error.
586 */
587 SCB_OTHERTCL_TIMEOUT = 0x00002,/*
588 * Another device was active
589 * during the first timeout for
590 * this SCB so we gave ourselves
591 * an additional timeout period
592 * in case it was hogging the
593 * bus.
594 */
595 SCB_DEVICE_RESET = 0x00004,
596 SCB_SENSE = 0x00008,
597 SCB_CDB32_PTR = 0x00010,
598 SCB_RECOVERY_SCB = 0x00020,
599 SCB_AUTO_NEGOTIATE = 0x00040,/* Negotiate to achieve goal. */
600 SCB_NEGOTIATE = 0x00080,/* Negotiation forced for command. */
601 SCB_ABORT = 0x00100,
602 SCB_ACTIVE = 0x00200,
603 SCB_TARGET_IMMEDIATE = 0x00400,
604 SCB_PACKETIZED = 0x00800,
605 SCB_EXPECT_PPR_BUSFREE = 0x01000,
606 SCB_PKT_SENSE = 0x02000,
607 SCB_CMDPHASE_ABORT = 0x04000,
608 SCB_ON_COL_LIST = 0x08000,
609 SCB_SILENT = 0x10000,/*
610 * Be quiet about transmission type
611 * errors. They are expected and we
612 * don't want to upset the user. This
613 * flag is typically used during DV.
614 */
615 SCB_FREEZE_QUEUE = 0x20000,
616 SCB_REQUEUE = 0x40000,
617 } scb_flag;
618
619 struct scb {
620 struct hardware_scb *hscb;
621 union {
622 SLIST_ENTRY(scb) sle;
623 LIST_ENTRY(scb) le;
624 TAILQ_ENTRY(scb) tqe;
625 } links;
626 union {
627 SLIST_ENTRY(scb) sle;
628 LIST_ENTRY(scb) le;
629 TAILQ_ENTRY(scb) tqe;
630 } links2;
631 #define pending_links links2.le
632 #define collision_links links2.le
633 struct scb *col_scb;
634 struct scsipi_xfer *xs;
635
636 struct ahd_softc *ahd_softc;
637 scb_flag flags;
638 bus_dmamap_t dmamap;
639 struct scb_platform_data *platform_data;
640 struct map_node *hscb_map;
641 struct map_node *sg_map;
642 struct map_node *sense_map;
643 void *sg_list;
644 uint8_t *sense_data;
645 bus_addr_t sg_list_busaddr;
646 bus_addr_t sense_busaddr;
647 u_int sg_count;/* How full ahd_dma_seg is */
648 #define AHD_MAX_LQ_CRC_ERRORS 5
649 u_int crc_retry_count;
650 };
651
652 TAILQ_HEAD(scb_tailq, scb);
653 LIST_HEAD(scb_list, scb);
654
655 struct scb_data {
656 /*
657 * TAILQ of lists of free SCBs grouped by device
658 * collision domains.
659 */
660 struct scb_tailq free_scbs;
661
662 /*
663 * Per-device lists of SCBs whose tag ID would collide
664 * with an already active tag on the device.
665 */
666 struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT];
667
668 /*
669 * SCBs that will not collide with any active device.
670 */
671 struct scb_list any_dev_free_scb_list;
672
673 /*
674 * Mapping from tag to SCB.
675 */
676 struct scb *scbindex[AHD_SCB_MAX];
677
678 SLIST_HEAD(, map_node) hscb_maps;
679 SLIST_HEAD(, map_node) sg_maps;
680 SLIST_HEAD(, map_node) sense_maps;
681
682 int scbs_left; /* unallocated scbs in head map_node */
683 int sgs_left; /* unallocated sgs in head map_node */
684 int sense_left; /* unallocated sense in head map_node */
685 uint16_t numscbs;
686 uint16_t maxhscbs; /* Number of SCBs on the card */
687 uint8_t init_level; /*
688 * How far we've initialized
689 * this structure.
690 */
691 };
692
693 /************************ Target Mode Definitions *****************************/
694
695 /*
696 * Connection descriptor for select-in requests in target mode.
697 */
698 struct target_cmd {
699 uint8_t scsiid; /* Our ID and the initiator's ID */
700 uint8_t identify; /* Identify message */
701 uint8_t bytes[22]; /*
702 * Bytes contains any additional message
703 * bytes terminated by 0xFF. The remainder
704 * is the cdb to execute.
705 */
706 uint8_t cmd_valid; /*
707 * When a command is complete, the firmware
708 * will set cmd_valid to all bits set.
709 * After the host has seen the command,
710 * the bits are cleared. This allows us
711 * to just peek at host memory to determine
712 * if more work is complete. cmd_valid is on
713 * an 8 byte boundary to simplify setting
714 * it on aic7880 hardware which only has
715 * limited direct access to the DMA FIFO.
716 */
717 uint8_t pad[7];
718 };
719
720 /*
721 * Number of events we can buffer up if we run out
722 * of immediate notify ccbs.
723 */
724 #define AHD_TMODE_EVENT_BUFFER_SIZE 8
725 struct ahd_tmode_event {
726 uint8_t initiator_id;
727 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */
728 #define EVENT_TYPE_BUS_RESET 0xFF
729 uint8_t event_arg;
730 };
731
732 /*
733 * Per enabled lun target mode state.
734 * As this state is directly influenced by the host OS'es target mode
735 * environment, we let the OS module define it. Forward declare the
736 * structure here so we can store arrays of them, etc. in OS neutral
737 * data structures.
738 */
739 #ifdef AHD_TARGET_MODE
740 struct ahd_tmode_lstate {
741 struct cam_path *path;
742 struct ccb_hdr_slist accept_tios;
743 struct ccb_hdr_slist immed_notifies;
744 struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE];
745 uint8_t event_r_idx;
746 uint8_t event_w_idx;
747 };
748 #else
749 struct ahd_tmode_lstate;
750 #endif
751
752 /******************** Transfer Negotiation Datastructures *********************/
753 #define AHD_TRANS_CUR 0x01 /* Modify current negotiation status */
754 #define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */
755 #define AHD_TRANS_GOAL 0x04 /* Modify negotiation goal */
756 #define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */
757 #define AHD_PERIOD_10MHz 0x19
758
759 #define AHD_WIDTH_UNKNOWN 0xFF
760 #define AHD_PERIOD_UNKNOWN 0xFF
761 #define AHD_OFFSET_UNKNOWN 0xFF
762 #define AHD_PPR_OPTS_UNKNOWN 0xFF
763
764 /*
765 * Transfer Negotiation Information.
766 */
767 struct ahd_transinfo {
768 uint8_t protocol_version; /* SCSI Revision level */
769 uint8_t transport_version; /* SPI Revision level */
770 uint8_t width; /* Bus width */
771 uint8_t period; /* Sync rate factor */
772 uint8_t offset; /* Sync offset */
773 uint8_t ppr_options; /* Parallel Protocol Request options */
774 };
775
776 /*
777 * Per-initiator current, goal and user transfer negotiation information. */
778 struct ahd_initiator_tinfo {
779 struct ahd_transinfo curr;
780 struct ahd_transinfo goal;
781 struct ahd_transinfo user;
782 };
783
784 /*
785 * Per enabled target ID state.
786 * Pointers to lun target state as well as sync/wide negotiation information
787 * for each initiator<->target mapping. For the initiator role we pretend
788 * that we are the target and the targets are the initiators since the
789 * negotiation is the same regardless of role.
790 */
791 struct ahd_tmode_tstate {
792 struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS];
793 struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS];
794
795 /*
796 * Per initiator state bitmasks.
797 */
798 uint16_t auto_negotiate;/* Auto Negotiation Required */
799 uint16_t discenable; /* Disconnection allowed */
800 uint16_t tagenable; /* Tagged Queuing allowed */
801 };
802
803 /*
804 * Points of interest along the negotiated transfer scale.
805 */
806 #define AHD_SYNCRATE_160 0x8
807 #define AHD_SYNCRATE_PACED 0x8
808 #define AHD_SYNCRATE_DT 0x9
809 #define AHD_SYNCRATE_ULTRA2 0xa
810 #define AHD_SYNCRATE_ULTRA 0xc
811 #define AHD_SYNCRATE_FAST 0x19
812 #define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST
813 #define AHD_SYNCRATE_SYNC 0x32
814 #define AHD_SYNCRATE_MIN 0x60
815 #define AHD_SYNCRATE_ASYNC 0xFF
816 #define AHD_SYNCRATE_MAX AHD_SYNCRATE_160
817
818 /* Safe and valid period for async negotiations. */
819 #define AHD_ASYNC_XFER_PERIOD 0x44
820
821 /*
822 * In RevA, the synctable uses a 120MHz rate for the period
823 * factor 8 and 160MHz for the period factor 7. The 120MHz
824 * rate never made it into the official SCSI spec, so we must
825 * compensate when setting the negotiation table for Rev A
826 * parts.
827 */
828 #define AHD_SYNCRATE_REVA_120 0x8
829 #define AHD_SYNCRATE_REVA_160 0x7
830
831 /***************************** Lookup Tables **********************************/
832 /*
833 * Phase -> name and message out response
834 * to parity errors in each phase table.
835 */
836 struct ahd_phase_table_entry {
837 uint8_t phase;
838 uint8_t mesg_out; /* Message response to parity errors */
839 const char *phasemsg;
840 };
841
842 /************************** Serial EEPROM Format ******************************/
843
844 struct seeprom_config {
845 /*
846 * Per SCSI ID Configuration Flags
847 */
848 uint16_t device_flags[16]; /* words 0-15 */
849 #define CFXFER 0x003F /* synchronous transfer rate */
850 #define CFXFER_ASYNC 0x3F
851 #define CFQAS 0x0040 /* Negotiate QAS */
852 #define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */
853 #define CFSTART 0x0100 /* send start unit SCSI command */
854 #define CFINCBIOS 0x0200 /* include in BIOS scan */
855 #define CFDISC 0x0400 /* enable disconnection */
856 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */
857 #define CFWIDEB 0x1000 /* wide bus device */
858 #define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */
859
860 /*
861 * BIOS Control Bits
862 */
863 uint16_t bios_control; /* word 16 */
864 #define CFSUPREM 0x0001 /* support all removable drives */
865 #define CFSUPREMB 0x0002 /* support removable boot drives */
866 #define CFBIOSSTATE 0x000C /* BIOS Action State */
867 #define CFBS_DISABLED 0x00
868 #define CFBS_ENABLED 0x04
869 #define CFBS_DISABLED_SCAN 0x08
870 #define CFENABLEDV 0x0010 /* Perform Domain Validation */
871 #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */
872 #define CFSPARITY 0x0040 /* SCSI parity */
873 #define CFEXTEND 0x0080 /* extended translation enabled */
874 #define CFBOOTCD 0x0100 /* Support Bootable CD-ROM */
875 #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */
876 #define CFMSG_VERBOSE 0x0000
877 #define CFMSG_SILENT 0x0200
878 #define CFMSG_DIAG 0x0400
879 #define CFRESETB 0x0800 /* reset SCSI bus at boot */
880 /* UNUSED 0xf000 */
881
882 /*
883 * Host Adapter Control Bits
884 */
885 uint16_t adapter_control; /* word 17 */
886 #define CFAUTOTERM 0x0001 /* Perform Auto termination */
887 #define CFSTERM 0x0002 /* SCSI low byte termination */
888 #define CFWSTERM 0x0004 /* SCSI high byte termination */
889 #define CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/
890 #define CFSELOWTERM 0x0010 /* Ultra2 secondary low term */
891 #define CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */
892 #define CFSTPWLEVEL 0x0040 /* Termination level control */
893 #define CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */
894 #define CFTERM_MENU 0x0100 /* BIOS displays termination menu */
895 #define CFCLUSTERENB 0x8000 /* Cluster Enable */
896
897 /*
898 * Bus Release Time, Host Adapter ID
899 */
900 uint16_t brtime_id; /* word 18 */
901 #define CFSCSIID 0x000f /* host adapter SCSI ID */
902 /* UNUSED 0x00f0 */
903 #define CFBRTIME 0xff00 /* bus release time/PCI Latency Time */
904
905 /*
906 * Maximum targets
907 */
908 uint16_t max_targets; /* word 19 */
909 #define CFMAXTARG 0x00ff /* maximum targets */
910 #define CFBOOTLUN 0x0f00 /* Lun to boot from */
911 #define CFBOOTID 0xf000 /* Target to boot from */
912 uint16_t res_1[10]; /* words 20-29 */
913 uint16_t signature; /* BIOS Signature */
914 #define CFSIGNATURE 0x400
915 uint16_t checksum; /* word 31 */
916 };
917
918 /*
919 * Vital Product Data used during POST and by the BIOS.
920 */
921 struct vpd_config {
922 uint8_t bios_flags;
923 #define VPDMASTERBIOS 0x0001
924 #define VPDBOOTHOST 0x0002
925 uint8_t reserved_1[21];
926 uint8_t resource_type;
927 uint8_t resource_len[2];
928 uint8_t resource_data[8];
929 uint8_t vpd_tag;
930 uint16_t vpd_len;
931 uint8_t vpd_keyword[2];
932 uint8_t length;
933 uint8_t revision;
934 uint8_t device_flags;
935 uint8_t termnation_menus[2];
936 uint8_t fifo_threshold;
937 uint8_t end_tag;
938 uint8_t vpd_checksum;
939 uint16_t default_target_flags;
940 uint16_t default_bios_flags;
941 uint16_t default_ctrl_flags;
942 uint8_t default_irq;
943 uint8_t pci_lattime;
944 uint8_t max_target;
945 uint8_t boot_lun;
946 uint16_t signature;
947 uint8_t reserved_2;
948 uint8_t checksum;
949 uint8_t reserved_3[4];
950 };
951
952 /****************************** Flexport Logic ********************************/
953 #define FLXADDR_TERMCTL 0x0
954 #define FLX_TERMCTL_ENSECHIGH 0x8
955 #define FLX_TERMCTL_ENSECLOW 0x4
956 #define FLX_TERMCTL_ENPRIHIGH 0x2
957 #define FLX_TERMCTL_ENPRILOW 0x1
958 #define FLXADDR_ROMSTAT_CURSENSECTL 0x1
959 #define FLX_ROMSTAT_SEECFG 0xF0
960 #define FLX_ROMSTAT_EECFG 0x0F
961 #define FLX_ROMSTAT_SEE_93C66 0x00
962 #define FLX_ROMSTAT_SEE_NONE 0xF0
963 #define FLX_ROMSTAT_EE_512x8 0x0
964 #define FLX_ROMSTAT_EE_1MBx8 0x1
965 #define FLX_ROMSTAT_EE_2MBx8 0x2
966 #define FLX_ROMSTAT_EE_4MBx8 0x3
967 #define FLX_ROMSTAT_EE_16MBx8 0x4
968 #define CURSENSE_ENB 0x1
969 #define FLXADDR_FLEXSTAT 0x2
970 #define FLX_FSTAT_BUSY 0x1
971 #define FLXADDR_CURRENT_STAT 0x4
972 #define FLX_CSTAT_SEC_HIGH 0xC0
973 #define FLX_CSTAT_SEC_LOW 0x30
974 #define FLX_CSTAT_PRI_HIGH 0x0C
975 #define FLX_CSTAT_PRI_LOW 0x03
976 #define FLX_CSTAT_MASK 0x03
977 #define FLX_CSTAT_SHIFT 2
978 #define FLX_CSTAT_OKAY 0x0
979 #define FLX_CSTAT_OVER 0x1
980 #define FLX_CSTAT_UNDER 0x2
981 #define FLX_CSTAT_INVALID 0x3
982
983 int ahd_read_seeprom(struct ahd_softc *, uint16_t *, u_int, u_int,
984 int);
985
986 int ahd_write_seeprom(struct ahd_softc *, uint16_t *, u_int, u_int);
987 int ahd_wait_seeprom(struct ahd_softc *);
988 int ahd_verify_vpd_cksum(struct vpd_config *);
989 int ahd_verify_cksum(struct seeprom_config *);
990 int ahd_acquire_seeprom(struct ahd_softc *);
991 void ahd_release_seeprom(struct ahd_softc *);
992
993 /**************************** Message Buffer *********************************/
994 typedef enum {
995 MSG_FLAG_NONE = 0x00,
996 MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01,
997 MSG_FLAG_IU_REQ_CHANGED = 0x02,
998 MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04,
999 MSG_FLAG_EXPECT_QASREJ_BUSFREE = 0x08,
1000 MSG_FLAG_PACKETIZED = 0x10
1001 } ahd_msg_flags;
1002
1003 typedef enum {
1004 MSG_TYPE_NONE = 0x00,
1005 MSG_TYPE_INITIATOR_MSGOUT = 0x01,
1006 MSG_TYPE_INITIATOR_MSGIN = 0x02,
1007 MSG_TYPE_TARGET_MSGOUT = 0x03,
1008 MSG_TYPE_TARGET_MSGIN = 0x04
1009 } ahd_msg_type;
1010
1011 typedef enum {
1012 MSGLOOP_IN_PROG,
1013 MSGLOOP_MSGCOMPLETE,
1014 MSGLOOP_TERMINATED
1015 } msg_loop_stat;
1016
1017 /*********************** Software Configuration Structure *********************/
1018 struct ahd_suspend_channel_state {
1019 uint8_t scsiseq;
1020 uint8_t sxfrctl0;
1021 uint8_t sxfrctl1;
1022 uint8_t simode0;
1023 uint8_t simode1;
1024 uint8_t seltimer;
1025 uint8_t seqctl;
1026 };
1027
1028 struct ahd_suspend_state {
1029 struct ahd_suspend_channel_state channel[2];
1030 uint8_t optionmode;
1031 uint8_t dscommand0;
1032 uint8_t dspcistatus;
1033 /* hsmailbox */
1034 uint8_t crccontrol1;
1035 uint8_t scbbaddr;
1036 /* Host and sequencer SCB counts */
1037 uint8_t dff_thrsh;
1038 uint8_t *scratch_ram;
1039 uint8_t *btt;
1040 };
1041
1042 typedef int (*ahd_bus_intr_t)(struct ahd_softc *);
1043
1044 typedef enum {
1045 AHD_MODE_DFF0,
1046 AHD_MODE_DFF1,
1047 AHD_MODE_CCHAN,
1048 AHD_MODE_SCSI,
1049 AHD_MODE_CFG,
1050 AHD_MODE_UNKNOWN
1051 } ahd_mode;
1052
1053 #define AHD_MK_MSK(x) (0x01 << (x))
1054 #define AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0)
1055 #define AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1)
1056 #define AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN)
1057 #define AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI)
1058 #define AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG)
1059 #define AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN)
1060 #define AHD_MODE_ANY_MSK (~0)
1061
1062 typedef uint8_t ahd_mode_state;
1063
1064 typedef void ahd_callback_t (void *);
1065
1066 struct ahd_softc {
1067 device_t sc_dev;
1068
1069 struct scsipi_channel sc_channel;
1070 device_t sc_child;
1071 struct scsipi_adapter sc_adapter;
1072
1073 bus_space_tag_t tags[2];
1074 bus_space_handle_t bshs[2];
1075
1076 struct scb_data scb_data;
1077
1078 struct hardware_scb *next_queued_hscb;
1079 struct map_node *next_queued_hscb_map;
1080
1081 /*
1082 * SCBs that have been sent to the controller
1083 */
1084 LIST_HEAD(, scb) pending_scbs;
1085
1086 /*
1087 * Current register window mode information.
1088 */
1089 ahd_mode dst_mode;
1090 ahd_mode src_mode;
1091
1092 /*
1093 * Saved register window mode information
1094 * used for restore on next unpause.
1095 */
1096 ahd_mode saved_dst_mode;
1097 ahd_mode saved_src_mode;
1098
1099 /*
1100 * Platform specific data.
1101 */
1102 struct ahd_platform_data *platform_data;
1103
1104 /*
1105 * Bus specific device information.
1106 */
1107 ahd_bus_intr_t bus_intr;
1108
1109 /*
1110 * Target mode related state kept on a per enabled lun basis.
1111 * Targets that are not enabled will have null entries.
1112 * As an initiator, we keep one target entry for our initiator
1113 * ID to store our sync/wide transfer settings.
1114 */
1115 struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS];
1116
1117 char inited_target[AHD_NUM_TARGETS];
1118
1119 /*
1120 * The black hole device responsible for handling requests for
1121 * disabled luns on enabled targets.
1122 */
1123 struct ahd_tmode_lstate *black_hole;
1124
1125 /*
1126 * Device instance currently on the bus awaiting a continue TIO
1127 * for a command that was not given the disconnect privilege.
1128 */
1129 struct ahd_tmode_lstate *pending_device;
1130
1131 /*
1132 * Timer handles for timer driven callbacks.
1133 */
1134 ahd_timer_t reset_timer;
1135 ahd_timer_t stat_timer;
1136
1137 /*
1138 * Statistics.
1139 */
1140 #define AHD_STAT_UPDATE_US 250000 /* 250ms */
1141 #define AHD_STAT_BUCKETS 4
1142 u_int cmdcmplt_bucket;
1143 uint32_t cmdcmplt_counts[AHD_STAT_BUCKETS];
1144 uint32_t cmdcmplt_total;
1145
1146 /*
1147 * Card characteristics
1148 */
1149 ahd_chip chip;
1150 ahd_feature features;
1151 ahd_bug bugs;
1152 ahd_flag flags;
1153 struct seeprom_config *seep_config;
1154
1155 /* Values to store in the SEQCTL register for pause and unpause */
1156 uint8_t unpause;
1157 uint8_t pause;
1158
1159 /* Command Queues */
1160 uint16_t qoutfifonext;
1161 uint16_t qoutfifonext_valid_tag;
1162 uint16_t qinfifonext;
1163 uint16_t qinfifo[AHD_SCB_MAX];
1164 uint16_t *qoutfifo;
1165
1166 /* Critical Section Data */
1167 struct cs *critical_sections;
1168 u_int num_critical_sections;
1169
1170 /* Buffer for handling packetized bitbucket. */
1171 uint8_t *overrun_buf;
1172
1173 /* Links for chaining softcs */
1174 TAILQ_ENTRY(ahd_softc) links;
1175
1176 /* Channel Names ('A', 'B', etc.) */
1177 char channel;
1178
1179 /* Initiator Bus ID */
1180 uint8_t our_id;
1181
1182 /*
1183 * Target incoming command FIFO.
1184 */
1185 struct target_cmd *targetcmds;
1186 uint8_t tqinfifonext;
1187
1188 /*
1189 * Cached version of the hs_mailbox so we can avoid
1190 * pausing the sequencer during mailbox updates.
1191 */
1192 uint8_t hs_mailbox;
1193
1194 /*
1195 * Incoming and outgoing message handling.
1196 */
1197 uint8_t send_msg_perror;
1198 ahd_msg_flags msg_flags;
1199 ahd_msg_type msg_type;
1200 uint8_t msgout_buf[12];/* Message we are sending */
1201 uint8_t msgin_buf[12];/* Message we are receiving */
1202 u_int msgout_len; /* Length of message to send */
1203 u_int msgout_index; /* Current index in msgout */
1204 u_int msgin_index; /* Current index in msgin */
1205
1206 /*
1207 * Mapping information for data structures shared
1208 * between the sequencer and kernel.
1209 */
1210 bus_dma_tag_t parent_dmat;
1211 bus_dma_tag_t shared_data_dmat;
1212 struct map_node shared_data_map;
1213 int shared_data_size;
1214 int sc_dmaflags;
1215
1216 /* Information saved through suspend/resume cycles */
1217 struct ahd_suspend_state suspend_state;
1218
1219 /* Number of enabled target mode device on this card */
1220 u_int enabled_luns;
1221
1222 /* Initialization level of this data structure */
1223 u_int init_level;
1224
1225 /* PCI cacheline size. */
1226 u_int pci_cachesize;
1227
1228 /* IO Cell Parameters */
1229 uint8_t iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS];
1230
1231 u_int stack_size;
1232 uint16_t *saved_stack;
1233
1234 /* Per-Unit descriptive information */
1235 const char *description;
1236 const char *bus_description;
1237 const char *name;
1238 int unit;
1239
1240 /* Selection Timer settings */
1241 int seltime;
1242
1243 /*
1244 * Interrupt coalescing settings.
1245 */
1246 #define AHD_INT_COALESCING_TIMER_DEFAULT 250 /*us*/
1247 #define AHD_INT_COALESCING_MAXCMDS_DEFAULT 10
1248 #define AHD_INT_COALESCING_MAXCMDS_MAX 127
1249 #define AHD_INT_COALESCING_MINCMDS_DEFAULT 5
1250 #define AHD_INT_COALESCING_MINCMDS_MAX 127
1251 #define AHD_INT_COALESCING_THRESHOLD_DEFAULT 2000
1252 #define AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT 1000
1253 u_int int_coalescing_timer;
1254 u_int int_coalescing_maxcmds;
1255 u_int int_coalescing_mincmds;
1256 u_int int_coalescing_threshold;
1257 u_int int_coalescing_stop_threshold;
1258
1259 uint16_t user_discenable;/* Disconnection allowed */
1260 uint16_t user_tagenable;/* Tagged Queuing allowed */
1261
1262 /* Adapter interrupt routine */
1263 void* ih;
1264 struct ahd_pci_busdata *bus_data;
1265 };
1266
1267 TAILQ_HEAD(ahd_softc_tailq, ahd_softc);
1268 extern struct ahd_softc_tailq ahd_tailq;
1269
1270 /*************************** IO Cell Configuration ****************************/
1271 #define AHD_PRECOMP_SLEW_INDEX \
1272 (AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0)
1273
1274 #define AHD_AMPLITUDE_INDEX \
1275 (AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0)
1276
1277 #define AHD_SET_SLEWRATE(ahd, new_slew) \
1278 do { \
1279 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_SLEWRATE_MASK; \
1280 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \
1281 (((new_slew) << AHD_SLEWRATE_SHIFT) & AHD_SLEWRATE_MASK); \
1282 } while (0)
1283
1284 #define AHD_SET_PRECOMP(ahd, new_pcomp) \
1285 do { \
1286 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; \
1287 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \
1288 (((new_pcomp) << AHD_PRECOMP_SHIFT) & AHD_PRECOMP_MASK); \
1289 } while (0)
1290
1291 #define AHD_SET_AMPLITUDE(ahd, new_amp) \
1292 do { \
1293 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] &= ~AHD_AMPLITUDE_MASK; \
1294 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] |= \
1295 (((new_amp) << AHD_AMPLITUDE_SHIFT) & AHD_AMPLITUDE_MASK); \
1296 } while (0)
1297
1298 /************************ Active Device Information ***************************/
1299 typedef enum {
1300 ROLE_UNKNOWN,
1301 ROLE_INITIATOR,
1302 ROLE_TARGET
1303 } role_t;
1304
1305 struct ahd_devinfo {
1306 int our_scsiid;
1307 int target_offset;
1308 uint16_t target_mask;
1309 u_int target;
1310 u_int lun;
1311 char channel;
1312 role_t role; /*
1313 * Only guaranteed to be correct if not
1314 * in the busfree state.
1315 */
1316 };
1317
1318 /****************************** PCI Structures ********************************/
1319 #define AHD_PCI_IOADDR0 PCI_MAPREG_START /* I/O BAR*/
1320 #define AHD_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Memory BAR */
1321 #define AHD_PCI_IOADDR1 (PCI_MAPREG_START + 12)/* Second I/O BAR */
1322
1323 typedef int (ahd_device_setup_t)(struct ahd_softc *, struct pci_attach_args *);
1324
1325 struct ahd_pci_identity {
1326 uint64_t full_id;
1327 uint64_t id_mask;
1328 const char *name;
1329 ahd_device_setup_t *setup;
1330 };
1331
1332 /***************************** VL/EISA Declarations ***************************/
1333 struct aic7770_identity {
1334 uint32_t full_id;
1335 uint32_t id_mask;
1336 const char *name;
1337 ahd_device_setup_t *setup;
1338 };
1339 extern struct aic7770_identity aic7770_ident_table [];
1340 extern const int ahd_num_aic7770_devs;
1341
1342 #define AHD_EISA_SLOT_OFFSET 0xc00
1343 #define AHD_EISA_IOSIZE 0x100
1344
1345 /*************************** Function Declarations ****************************/
1346 /******************************************************************************/
1347 void ahd_reset_cmds_pending(struct ahd_softc *);
1348 u_int ahd_find_busy_tcl(struct ahd_softc *, u_int);
1349 void ahd_busy_tcl(struct ahd_softc *, u_int, u_int);
1350 static __inline void ahd_unbusy_tcl(struct ahd_softc *, u_int);
1351 static __inline void
ahd_unbusy_tcl(struct ahd_softc * ahd,u_int tcl)1352 ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl)
1353 {
1354 ahd_busy_tcl(ahd, tcl, SCB_LIST_NULL);
1355 }
1356
1357 /************************** SCB and SCB queue management **********************/
1358 int ahd_probe_scbs(struct ahd_softc *);
1359 void ahd_qinfifo_requeue_tail(struct ahd_softc *,
1360 struct scb *);
1361 int ahd_match_scb(struct ahd_softc *, struct scb *,
1362 int, char, int, u_int, role_t);
1363
1364 /****************************** Initialization ********************************/
1365 /*struct ahd_softc *ahd_alloc(void *, char *);*/
1366 int ahd_softc_init(struct ahd_softc *);
1367 void ahd_controller_info(struct ahd_softc *, char *, size_t);
1368 int ahd_init(struct ahd_softc *);
1369 int ahd_default_config(struct ahd_softc *);
1370 int ahd_parse_vpddata(struct ahd_softc *,
1371 struct vpd_config *);
1372 int ahd_parse_cfgdata(struct ahd_softc *,
1373 struct seeprom_config *);
1374 void ahd_intr_enable(struct ahd_softc *, int);
1375 void ahd_update_coalescing_values(struct ahd_softc *,
1376 u_int, u_int, u_int);
1377 void ahd_enable_coalescing(struct ahd_softc *, int);
1378 void ahd_pause_and_flushwork(struct ahd_softc *);
1379 int ahd_suspend(struct ahd_softc *);
1380 int ahd_resume(struct ahd_softc *);
1381 void ahd_set_unit(struct ahd_softc *, int);
1382 void ahd_set_name(struct ahd_softc *, const char *);
1383 struct scb *ahd_get_scb(struct ahd_softc *, u_int);
1384 void ahd_free_scb(struct ahd_softc *, struct scb *);
1385 int ahd_alloc_scbs(struct ahd_softc *);
1386 void ahd_free(struct ahd_softc *);
1387 int ahd_reset(struct ahd_softc *, int);
1388 void ahd_shutdown(void *);
1389 int ahd_write_flexport(struct ahd_softc *,
1390 u_int, u_int);
1391 int ahd_read_flexport(struct ahd_softc *, u_int,
1392 uint8_t *);
1393 int ahd_wait_flexport(struct ahd_softc *);
1394
1395 /*************************** Interrupt Services *******************************/
1396 void ahd_clear_intstat(struct ahd_softc *);
1397 void ahd_flush_qoutfifo(struct ahd_softc *);
1398 void ahd_run_qoutfifo(struct ahd_softc *);
1399 void ahd_run_post_qoutfifo(struct ahd_softc *);
1400 #ifdef AHD_TARGET_MODE
1401 void ahd_run_tqinfifo(struct ahd_softc *, int);
1402 #endif
1403 void ahd_handle_hwerrint(struct ahd_softc *);
1404 void ahd_handle_seqint(struct ahd_softc *, u_int);
1405 void ahd_handle_scsiint(struct ahd_softc *, u_int);
1406 void ahd_clear_critical_section(struct ahd_softc *);
1407
1408 /***************************** Error Recovery *********************************/
1409 typedef enum {
1410 SEARCH_COMPLETE,
1411 SEARCH_COUNT,
1412 SEARCH_REMOVE,
1413 SEARCH_PRINT
1414 } ahd_search_action;
1415 int ahd_search_qinfifo(struct ahd_softc *, int, char, int,
1416 u_int, role_t, uint32_t, ahd_search_action);
1417 int ahd_search_disc_list(struct ahd_softc *, int, char,
1418 int, u_int, int, int, int);
1419 void ahd_freeze_devq(struct ahd_softc *, struct scb *);
1420 int ahd_reset_channel(struct ahd_softc *, char, int);
1421 int ahd_abort_scbs(struct ahd_softc *, int, char, int,
1422 u_int, role_t, uint32_t);
1423 void ahd_restart(struct ahd_softc *);
1424 void ahd_clear_fifo(struct ahd_softc *, u_int);
1425 void ahd_handle_scb_status(struct ahd_softc *, struct scb *);
1426 void ahd_handle_scsi_status(struct ahd_softc *,
1427 struct scb *);
1428 void ahd_calc_residual(struct ahd_softc *, struct scb *);
1429 /*************************** Utility Functions ********************************/
1430 struct ahd_phase_table_entry*
1431 ahd_lookup_phase_entry(int);
1432 void ahd_compile_devinfo(struct ahd_devinfo *, u_int, u_int,
1433 u_int, char, role_t);
1434 /************************** Transfer Negotiation ******************************/
1435 void ahd_find_syncrate(struct ahd_softc *, u_int *,
1436 u_int *, u_int);
1437 void ahd_validate_offset(struct ahd_softc *,
1438 struct ahd_initiator_tinfo *, u_int, u_int *,
1439 int, role_t);
1440 void ahd_validate_width(struct ahd_softc *,
1441 struct ahd_initiator_tinfo *, u_int *, role_t);
1442 /*
1443 * Negotiation types. These are used to qualify if we should renegotiate
1444 * even if our goal and current transport parameters are identical.
1445 */
1446 typedef enum {
1447 AHD_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */
1448 AHD_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */
1449 AHD_NEG_ALWAYS /* Renegotiate even if goal is async. */
1450 } ahd_neg_type;
1451 int ahd_update_neg_request(struct ahd_softc *,
1452 struct ahd_devinfo *, struct ahd_tmode_tstate *,
1453 struct ahd_initiator_tinfo *, ahd_neg_type);
1454 void ahd_set_width(struct ahd_softc *,
1455 struct ahd_devinfo *, u_int, u_int, int);
1456 void ahd_set_syncrate(struct ahd_softc *,
1457 struct ahd_devinfo *, u_int, u_int, u_int,
1458 u_int, int);
1459 typedef enum {
1460 AHD_QUEUE_NONE,
1461 AHD_QUEUE_BASIC,
1462 AHD_QUEUE_TAGGED
1463 } ahd_queue_alg;
1464
1465 void ahd_set_tags(struct ahd_softc *, struct ahd_devinfo *,
1466 ahd_queue_alg);
1467
1468 /**************************** Target Mode *************************************/
1469 #ifdef AHD_TARGET_MODE
1470 void ahd_send_lstate_events(struct ahd_softc *,
1471 struct ahd_tmode_lstate *);
1472 void ahd_handle_en_lun(struct ahd_softc *,
1473 struct cam_sim *, union ccb *);
1474 cam_status ahd_find_tmode_devs(struct ahd_softc *, struct cam_sim *,
1475 union ccb *, struct ahd_tmode_tstate **,
1476 struct ahd_tmode_lstate **, int);
1477 #ifndef AHD_TMODE_ENABLE
1478 #define AHD_TMODE_ENABLE 0
1479 #endif
1480 #endif
1481 /******************************* Debug ***************************************/
1482 #ifdef AHD_DEBUG
1483 extern uint32_t ahd_debug;
1484 #define AHD_SHOW_MISC 0x00001
1485 #define AHD_SHOW_SENSE 0x00002
1486 #define AHD_SHOW_RECOVERY 0x00004
1487 #define AHD_DUMP_SEEPROM 0x00008
1488 #define AHD_SHOW_TERMCTL 0x00010
1489 #define AHD_SHOW_MEMORY 0x00020
1490 #define AHD_SHOW_MESSAGES 0x00040
1491 #define AHD_SHOW_MODEPTR 0x00080
1492 #define AHD_SHOW_SELTO 0x00100
1493 #define AHD_SHOW_FIFOS 0x00200
1494 #define AHD_SHOW_QFULL 0x00400
1495 #define AHD_SHOW_DV 0x00800
1496 #define AHD_SHOW_MASKED_ERRORS 0x01000
1497 #define AHD_SHOW_QUEUE 0x02000
1498 #define AHD_SHOW_TQIN 0x04000
1499 #define AHD_SHOW_SG 0x08000
1500 #define AHD_SHOW_INT_COALESCING 0x10000
1501 #define AHD_DEBUG_SEQUENCER 0x20000
1502 #endif
1503 void ahd_print_scb(struct scb *);
1504 void ahd_print_devinfo(struct ahd_softc *,
1505 struct ahd_devinfo *);
1506 void ahd_dump_sglist(struct scb *);
1507 void ahd_dump_all_cards_state(void);
1508 void ahd_dump_card_state(struct ahd_softc *);
1509 int ahd_print_register(ahd_reg_parse_entry_t *, u_int,
1510 const char *, u_int, u_int, u_int *, u_int);
1511 void ahd_dump_scbs(struct ahd_softc *);
1512 #endif /* _AIC79XXVAR_H_ */
1513