1 /* $OpenBSD: phb.c,v 1.23 2022/04/06 18:59:27 naddy Exp $ */
2 /*
3 * Copyright (c) 2020 Mark Kettenis <kettenis@openbsd.org>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 #include <sys/param.h>
19 #include <sys/systm.h>
20 #include <sys/device.h>
21 #include <sys/extent.h>
22
23 #include <machine/bus.h>
24 #include <machine/fdt.h>
25 #include <machine/opal.h>
26
27 #include <dev/pci/pcidevs.h>
28 #include <dev/pci/pcireg.h>
29 #include <dev/pci/pcivar.h>
30
31 #include <dev/ofw/openfirm.h>
32 #include <dev/ofw/fdt.h>
33
34 extern paddr_t physmax; /* machdep.c */
35
36 #define IODA_TVE_SELECT (1ULL << 59)
37
38 #define IODA_TCE_TABLE_SIZE_MAX (1ULL << 42)
39
40 #define IODA_TCE_READ (1ULL << 0)
41 #define IODA_TCE_WRITE (1ULL << 1)
42
43 #define PHB_DMA_OFFSET (1ULL << 32)
44
45 struct phb_dmamem;
46
47 struct phb_range {
48 uint32_t flags;
49 uint64_t pci_base;
50 uint64_t phys_base;
51 uint64_t size;
52 };
53
54 struct phb_softc {
55 struct device sc_dev;
56 bus_space_tag_t sc_iot;
57 bus_dma_tag_t sc_dmat;
58
59 int sc_node;
60 int sc_acells;
61 int sc_scells;
62 int sc_pacells;
63 int sc_pscells;
64 struct phb_range *sc_ranges;
65 int sc_nranges;
66
67 uint64_t sc_phb_id;
68 uint64_t sc_pe_number;
69 struct phb_dmamem *sc_tce_table;
70 uint32_t sc_msi_ranges[2];
71 uint32_t sc_xive;
72
73 struct bus_space sc_bus_iot;
74 struct bus_space sc_bus_memt;
75 struct machine_bus_dma_tag sc_bus_dmat;
76
77 struct ppc64_pci_chipset sc_pc;
78 struct extent *sc_busex;
79 struct extent *sc_memex;
80 struct extent *sc_ioex;
81 int sc_bus;
82 };
83
84 struct phb_dmamem {
85 bus_dmamap_t pdm_map;
86 bus_dma_segment_t pdm_seg;
87 size_t pdm_size;
88 caddr_t pdm_kva;
89 };
90
91 #define PHB_DMA_MAP(_pdm) ((_pdm)->pdm_map)
92 #define PHB_DMA_LEN(_pdm) ((_pdm)->pdm_size)
93 #define PHB_DMA_DVA(_pdm) ((_pdm)->pdm_map->dm_segs[0].ds_addr)
94 #define PHB_DMA_KVA(_pdm) ((void *)(_pdm)->pdm_kva)
95
96 struct phb_dmamem *phb_dmamem_alloc(bus_dma_tag_t, bus_size_t,
97 bus_size_t);
98 void phb_dmamem_free(bus_dma_tag_t, struct phb_dmamem *);
99
100 int phb_match(struct device *, void *, void *);
101 void phb_attach(struct device *, struct device *, void *);
102
103 const struct cfattach phb_ca = {
104 sizeof (struct phb_softc), phb_match, phb_attach
105 };
106
107 struct cfdriver phb_cd = {
108 NULL, "phb", DV_DULL
109 };
110
111 void phb_setup_tce_table(struct phb_softc *sc);
112
113 void phb_attach_hook(struct device *, struct device *,
114 struct pcibus_attach_args *);
115 int phb_bus_maxdevs(void *, int);
116 pcitag_t phb_make_tag(void *, int, int, int);
117 void phb_decompose_tag(void *, pcitag_t, int *, int *, int *);
118 int phb_conf_size(void *, pcitag_t);
119 pcireg_t phb_conf_read(void *, pcitag_t, int);
120 void phb_conf_write(void *, pcitag_t, int, pcireg_t);
121
122 int phb_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
123 const char *phb_intr_string(void *, pci_intr_handle_t);
124 void *phb_intr_establish(void *, pci_intr_handle_t, int, struct cpu_info *,
125 int (*)(void *), void *, char *);
126 void phb_intr_disestablish(void *, void *);
127
128 int phb_bs_iomap(bus_space_tag_t, bus_addr_t, bus_size_t, int,
129 bus_space_handle_t *);
130 int phb_bs_memmap(bus_space_tag_t, bus_addr_t, bus_size_t, int,
131 bus_space_handle_t *);
132 paddr_t phb_bs_mmap(bus_space_tag_t, bus_addr_t, off_t, int, int);
133 int phb_dmamap_load_buffer(bus_dma_tag_t, bus_dmamap_t, void *,
134 bus_size_t, struct proc *, int, paddr_t *, int *, int);
135 int phb_dmamap_load_raw(bus_dma_tag_t, bus_dmamap_t,
136 bus_dma_segment_t *, int, bus_size_t, int);
137
138 int
phb_match(struct device * parent,void * match,void * aux)139 phb_match(struct device *parent, void *match, void *aux)
140 {
141 struct fdt_attach_args *faa = aux;
142
143 return (OF_is_compatible(faa->fa_node, "ibm,ioda2-phb") ||
144 OF_is_compatible(faa->fa_node, "ibm,ioda3-phb"));
145 }
146
147 void
phb_attach(struct device * parent,struct device * self,void * aux)148 phb_attach(struct device *parent, struct device *self, void *aux)
149 {
150 struct phb_softc *sc = (struct phb_softc *)self;
151 struct fdt_attach_args *faa = aux;
152 struct pcibus_attach_args pba;
153 uint32_t bus_range[2];
154 uint32_t *ranges;
155 uint32_t m64window[6];
156 uint32_t m64ranges[2];
157 int i, j, nranges, rangeslen;
158 uint32_t window;
159 uint32_t chip_id;
160 int64_t error;
161
162 if (faa->fa_nreg < 1) {
163 printf(": no registers\n");
164 return;
165 }
166
167 sc->sc_iot = faa->fa_iot;
168 sc->sc_dmat = faa->fa_dmat;
169 sc->sc_node = faa->fa_node;
170 sc->sc_phb_id = OF_getpropint64(sc->sc_node, "ibm,opal-phbid", 0);
171 sc->sc_pe_number = 0;
172
173 if (OF_getproplen(sc->sc_node, "ibm,chip-id") == sizeof(chip_id)) {
174 chip_id = OF_getpropint(sc->sc_node, "ibm,chip-id", 0);
175 printf(": chip 0x%x", chip_id);
176 }
177
178 /*
179 * Reset the IODA tables. Should clear any gunk left behind
180 * by Linux.
181 */
182 error = opal_pci_reset(sc->sc_phb_id, OPAL_RESET_PCI_IODA_TABLE,
183 OPAL_ASSERT_RESET);
184 if (error != OPAL_SUCCESS) {
185 printf(": can't reset IODA table\n");
186 return;
187 }
188
189 /*
190 * Keep things simple and use a single PE for everything below
191 * this host bridge.
192 */
193 error = opal_pci_set_pe(sc->sc_phb_id, sc->sc_pe_number, 0,
194 OPAL_IGNORE_RID_BUS_NUMBER, OPAL_IGNORE_RID_DEVICE_NUMBER,
195 OPAL_IGNORE_RID_FUNCTION_NUMBER, OPAL_MAP_PE);
196 if (error != OPAL_SUCCESS) {
197 printf(": can't map PHB PE\n");
198 return;
199 }
200
201 /* Enable bypass mode. */
202 error = opal_pci_map_pe_dma_window_real(sc->sc_phb_id,
203 sc->sc_pe_number, (sc->sc_pe_number << 1) | 1,
204 IODA_TVE_SELECT, physmax);
205 if (error != OPAL_SUCCESS) {
206 printf(": can't enable DMA bypass\n");
207 return;
208 }
209
210 /*
211 * Parse address ranges such that we can do the appropriate
212 * address translations.
213 */
214
215 sc->sc_acells = OF_getpropint(sc->sc_node, "#address-cells",
216 faa->fa_acells);
217 sc->sc_scells = OF_getpropint(sc->sc_node, "#size-cells",
218 faa->fa_scells);
219 sc->sc_pacells = faa->fa_acells;
220 sc->sc_pscells = faa->fa_scells;
221
222 rangeslen = OF_getproplen(sc->sc_node, "ranges");
223 if (rangeslen <= 0 || (rangeslen % sizeof(uint32_t)) ||
224 (rangeslen / sizeof(uint32_t)) % (sc->sc_acells +
225 sc->sc_pacells + sc->sc_scells)) {
226 printf(": invalid ranges property\n");
227 return;
228 }
229
230 ranges = malloc(rangeslen, M_TEMP, M_WAITOK);
231 OF_getpropintarray(sc->sc_node, "ranges", ranges, rangeslen);
232
233 /*
234 * Reserve an extra slot here and make sure it is filled
235 * with zeroes.
236 */
237 nranges = (rangeslen / sizeof(uint32_t)) /
238 (sc->sc_acells + sc->sc_pacells + sc->sc_scells);
239 sc->sc_ranges = mallocarray(nranges + 1,
240 sizeof(struct phb_range), M_DEVBUF, M_ZERO | M_WAITOK);
241 sc->sc_nranges = nranges + 1;
242
243 for (i = 0, j = 0; i < sc->sc_nranges; i++) {
244 sc->sc_ranges[i].flags = ranges[j++];
245 sc->sc_ranges[i].pci_base = ranges[j++];
246 if (sc->sc_acells - 1 == 2) {
247 sc->sc_ranges[i].pci_base <<= 32;
248 sc->sc_ranges[i].pci_base |= ranges[j++];
249 }
250 sc->sc_ranges[i].phys_base = ranges[j++];
251 if (sc->sc_pacells == 2) {
252 sc->sc_ranges[i].phys_base <<= 32;
253 sc->sc_ranges[i].phys_base |= ranges[j++];
254 }
255 sc->sc_ranges[i].size = ranges[j++];
256 if (sc->sc_scells == 2) {
257 sc->sc_ranges[i].size <<= 32;
258 sc->sc_ranges[i].size |= ranges[j++];
259 }
260 }
261
262 free(ranges, M_TEMP, rangeslen);
263
264 /*
265 * IBM has chosen a non-standard way to encode 64-bit mmio
266 * ranges. Stick the information into the slot we reserved
267 * above.
268 */
269 if (OF_getpropintarray(sc->sc_node, "ibm,opal-m64-window",
270 m64window, sizeof(m64window)) == sizeof(m64window)) {
271 sc->sc_ranges[sc->sc_nranges - 1].flags = 0x03000000;
272 sc->sc_ranges[sc->sc_nranges - 1].pci_base =
273 (uint64_t)m64window[0] << 32 | m64window[1];
274 sc->sc_ranges[sc->sc_nranges - 1].phys_base =
275 (uint64_t)m64window[2] << 32 | m64window[3];
276 sc->sc_ranges[sc->sc_nranges - 1].size =
277 (uint64_t)m64window[4] << 32 | m64window[5];
278 }
279
280 /*
281 * Enable all the 64-bit mmio windows we found.
282 */
283 m64ranges[0] = 0; m64ranges[1] = 16;
284 OF_getpropintarray(sc->sc_node, "ibm,opal-available-m64-ranges",
285 m64ranges, sizeof(m64ranges));
286 window = m64ranges[0];
287 for (i = 0; i < sc->sc_nranges; i++) {
288 /* Skip non-64-bit ranges. */
289 if ((sc->sc_ranges[i].flags & 0x03000000) != 0x03000000)
290 continue;
291
292 /* Bail if we're out of 64-bit mmio windows. */
293 if (window > m64ranges[1]) {
294 printf(": no 64-bit mmio window available\n");
295 return;
296 }
297
298 error = opal_pci_set_phb_mem_window(sc->sc_phb_id,
299 OPAL_M64_WINDOW_TYPE, window, sc->sc_ranges[i].phys_base,
300 sc->sc_ranges[i].pci_base, sc->sc_ranges[i].size);
301 if (error != OPAL_SUCCESS) {
302 printf(": can't set 64-bit mmio window\n");
303 return;
304 }
305 error = opal_pci_phb_mmio_enable(sc->sc_phb_id,
306 OPAL_M64_WINDOW_TYPE, window, OPAL_ENABLE_M64_SPLIT);
307 if (error != OPAL_SUCCESS) {
308 printf(": can't enable 64-bit mmio window\n");
309 return;
310 }
311
312 window++;
313 }
314
315 OF_getpropintarray(sc->sc_node, "ibm,opal-msi-ranges",
316 sc->sc_msi_ranges, sizeof(sc->sc_msi_ranges));
317
318 /* Create extents for our address spaces. */
319 sc->sc_busex = extent_create("pcibus", 0, 255,
320 M_DEVBUF, NULL, 0, EX_WAITOK | EX_FILLED);
321 sc->sc_memex = extent_create("pcimem", 0, (u_long)-1,
322 M_DEVBUF, NULL, 0, EX_WAITOK | EX_FILLED);
323 sc->sc_ioex = extent_create("pciio", 0, 0xffffffff,
324 M_DEVBUF, NULL, 0, EX_WAITOK | EX_FILLED);
325
326 /* Set up bus range. */
327 if (OF_getpropintarray(sc->sc_node, "bus-range", bus_range,
328 sizeof(bus_range)) != sizeof(bus_range) ||
329 bus_range[0] >= 256 || bus_range[1] >= 256) {
330 bus_range[0] = 0;
331 bus_range[1] = 255;
332 }
333 sc->sc_bus = bus_range[0];
334 extent_free(sc->sc_busex, bus_range[0],
335 bus_range[1] - bus_range[0] + 1, EX_WAITOK);
336
337 /* Set up mmio ranges. */
338 for (i = 0; i < sc->sc_nranges; i++) {
339 if ((sc->sc_ranges[i].flags & 0x02000000) != 0x02000000)
340 continue;
341
342 extent_free(sc->sc_memex, sc->sc_ranges[i].pci_base,
343 sc->sc_ranges[i].size, EX_WAITOK);
344 }
345
346 printf("\n");
347
348 /*
349 * The DMA controllers of many PCI devices developed for the
350 * x86 architectures may not support the full 64-bit PCI
351 * address space. Examples of such devices are Radeon GPUs
352 * that support only 36, 40 or 44 address lines. This means
353 * they can't enable the TVE selection bit to request IODA
354 * no-translate (bypass) operation.
355 *
356 * To allow such devices to work, we set up a TCE table that
357 * provides a 1:1 mapping of all physical memory where the
358 * physical page at address zero as mapped at 4 GB in PCI
359 * address space. If we fail to set up this TCE table we fall
360 * back on using no-translate operation, which means that
361 * devices that don't implement 64 address lines may not
362 * function properly.
363 */
364 phb_setup_tce_table(sc);
365
366 memcpy(&sc->sc_bus_iot, sc->sc_iot, sizeof(sc->sc_bus_iot));
367 sc->sc_bus_iot.bus_private = sc;
368 sc->sc_bus_iot._space_map = phb_bs_iomap;
369 sc->sc_bus_iot._space_read_2 = little_space_read_2;
370 sc->sc_bus_iot._space_read_4 = little_space_read_4;
371 sc->sc_bus_iot._space_read_8 = little_space_read_8;
372 sc->sc_bus_iot._space_write_2 = little_space_write_2;
373 sc->sc_bus_iot._space_write_4 = little_space_write_4;
374 sc->sc_bus_iot._space_write_8 = little_space_write_8;
375 memcpy(&sc->sc_bus_memt, sc->sc_iot, sizeof(sc->sc_bus_memt));
376 sc->sc_bus_memt.bus_private = sc;
377 sc->sc_bus_memt._space_map = phb_bs_memmap;
378 sc->sc_bus_memt._space_mmap = phb_bs_mmap;
379 sc->sc_bus_memt._space_read_2 = little_space_read_2;
380 sc->sc_bus_memt._space_read_4 = little_space_read_4;
381 sc->sc_bus_memt._space_read_8 = little_space_read_8;
382 sc->sc_bus_memt._space_write_2 = little_space_write_2;
383 sc->sc_bus_memt._space_write_4 = little_space_write_4;
384 sc->sc_bus_memt._space_write_8 = little_space_write_8;
385
386 memcpy(&sc->sc_bus_dmat, sc->sc_dmat, sizeof(sc->sc_bus_dmat));
387 sc->sc_bus_dmat._cookie = sc;
388 sc->sc_bus_dmat._dmamap_load_buffer = phb_dmamap_load_buffer;
389 sc->sc_bus_dmat._dmamap_load_raw = phb_dmamap_load_raw;
390
391 sc->sc_pc.pc_conf_v = sc;
392 sc->sc_pc.pc_attach_hook = phb_attach_hook;
393 sc->sc_pc.pc_bus_maxdevs = phb_bus_maxdevs;
394 sc->sc_pc.pc_make_tag = phb_make_tag;
395 sc->sc_pc.pc_decompose_tag = phb_decompose_tag;
396 sc->sc_pc.pc_conf_size = phb_conf_size;
397 sc->sc_pc.pc_conf_read = phb_conf_read;
398 sc->sc_pc.pc_conf_write = phb_conf_write;
399
400 sc->sc_pc.pc_intr_v = sc;
401 sc->sc_pc.pc_intr_map = phb_intr_map;
402 sc->sc_pc.pc_intr_map_msi = _pci_intr_map_msi;
403 sc->sc_pc.pc_intr_map_msix = _pci_intr_map_msix;
404 sc->sc_pc.pc_intr_string = phb_intr_string;
405 sc->sc_pc.pc_intr_establish = phb_intr_establish;
406 sc->sc_pc.pc_intr_disestablish = phb_intr_disestablish;
407
408 memset(&pba, 0, sizeof(pba));
409 pba.pba_busname = "pci";
410 pba.pba_iot = &sc->sc_bus_iot;
411 pba.pba_memt = &sc->sc_bus_memt;
412 pba.pba_dmat = &sc->sc_bus_dmat;
413 pba.pba_pc = &sc->sc_pc;
414 pba.pba_busex = sc->sc_busex;
415 pba.pba_memex = sc->sc_memex;
416 pba.pba_ioex = sc->sc_ioex;
417 pba.pba_domain = pci_ndomains++;
418 pba.pba_bus = sc->sc_bus;
419 pba.pba_flags |= PCI_FLAGS_MSI_ENABLED;
420
421 config_found(self, &pba, NULL);
422 }
423
424 void
phb_setup_tce_table(struct phb_softc * sc)425 phb_setup_tce_table(struct phb_softc *sc)
426 {
427 uint64_t tce_table_size, tce_page_size;
428 uint64_t *tce;
429 uint32_t *tce_sizes;
430 int tce_page_shift;
431 int i, len, offset, nentries;
432 paddr_t pa;
433 int64_t error;
434
435 /* Determine the maximum supported TCE page size. */
436 len = OF_getproplen(sc->sc_node, "ibm,supported-tce-sizes");
437 if (len <= 0 || (len % sizeof(uint32_t)))
438 return;
439 tce_sizes = malloc(len, M_TEMP, M_WAITOK);
440 OF_getpropintarray(sc->sc_node, "ibm,supported-tce-sizes",
441 tce_sizes, len);
442 tce_page_shift = 0;
443 for (i = 0; i < len / sizeof(uint32_t); i++)
444 tce_page_shift = MAX(tce_page_shift, tce_sizes[i]);
445 free(tce_sizes, M_TEMP, len);
446
447 /* Bail out if we don't support 1G pages. */
448 if (tce_page_shift < 30)
449 return;
450
451 /* Calculate the appropriate size of the TCE table. */
452 tce_page_size = (1ULL << tce_page_shift);
453 tce_table_size = PAGE_SIZE;
454 nentries = howmany(PHB_DMA_OFFSET + physmax, tce_page_size);
455 while (tce_table_size < nentries * sizeof(*tce))
456 tce_table_size *= 2;
457 if (tce_table_size > IODA_TCE_TABLE_SIZE_MAX)
458 return;
459
460 /* Allocate the TCE table. */
461 sc->sc_tce_table = phb_dmamem_alloc(sc->sc_dmat,
462 tce_table_size, tce_table_size);
463 if (sc->sc_tce_table == NULL) {
464 printf(": can't allocate DMA translation table\n");
465 return;
466 }
467
468 /* Fill TCE table. */
469 tce = PHB_DMA_KVA(sc->sc_tce_table);
470 offset = PHB_DMA_OFFSET >> tce_page_shift;
471 for (pa = 0, i = 0; pa < physmax; pa += tce_page_size, i++)
472 tce[i + offset] = pa | IODA_TCE_READ | IODA_TCE_WRITE;
473
474 /* Set up translations. */
475 error = opal_pci_map_pe_dma_window(sc->sc_phb_id,
476 sc->sc_pe_number, sc->sc_pe_number << 1, 1,
477 PHB_DMA_DVA(sc->sc_tce_table), PHB_DMA_LEN(sc->sc_tce_table),
478 tce_page_size);
479 if (error != OPAL_SUCCESS) {
480 printf("%s: can't enable DMA window\n", sc->sc_dev.dv_xname);
481 phb_dmamem_free(sc->sc_dmat, sc->sc_tce_table);
482 sc->sc_tce_table = NULL;
483 return;
484 }
485 }
486
487 void
phb_attach_hook(struct device * parent,struct device * self,struct pcibus_attach_args * pba)488 phb_attach_hook(struct device *parent, struct device *self,
489 struct pcibus_attach_args *pba)
490 {
491 }
492
493 int
phb_bus_maxdevs(void * v,int bus)494 phb_bus_maxdevs(void *v, int bus)
495 {
496 struct phb_softc *sc = v;
497
498 if (bus == sc->sc_bus || bus == sc->sc_bus + 1)
499 return 1;
500 return 32;
501 }
502
503 int
phb_find_node(int node,int bus,int device,int function)504 phb_find_node(int node, int bus, int device, int function)
505 {
506 uint32_t reg[5];
507 uint32_t phys_hi;
508 int child;
509
510 phys_hi = ((bus << 16) | (device << 11) | (function << 8));
511
512 for (child = OF_child(node); child; child = OF_peer(child)) {
513 if (OF_getpropintarray(child, "reg",
514 reg, sizeof(reg)) != sizeof(reg))
515 continue;
516
517 if (reg[0] == phys_hi)
518 return child;
519
520 node = phb_find_node(child, bus, device, function);
521 if (node)
522 return node;
523 }
524
525 return 0;
526 }
527
528 pcitag_t
phb_make_tag(void * v,int bus,int device,int function)529 phb_make_tag(void *v, int bus, int device, int function)
530 {
531 struct phb_softc *sc = v;
532 int node;
533
534 node = phb_find_node(sc->sc_node, bus, device, function);
535 return (((pcitag_t)node << 32) |
536 (bus << 8) | (device << 3) | (function << 0));
537 }
538
539 void
phb_decompose_tag(void * v,pcitag_t tag,int * bp,int * dp,int * fp)540 phb_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
541 {
542 if (bp != NULL)
543 *bp = (tag >> 8) & 0xff;
544 if (dp != NULL)
545 *dp = (tag >> 3) & 0x1f;
546 if (fp != NULL)
547 *fp = (tag >> 0) & 0x7;
548 }
549
550 int
phb_conf_size(void * v,pcitag_t tag)551 phb_conf_size(void *v, pcitag_t tag)
552 {
553 return PCIE_CONFIG_SPACE_SIZE;
554 }
555
556 pcireg_t
phb_conf_read(void * v,pcitag_t tag,int reg)557 phb_conf_read(void *v, pcitag_t tag, int reg)
558 {
559 struct phb_softc *sc = v;
560 int64_t error;
561 uint32_t data;
562 uint16_t pci_error_state;
563 uint8_t freeze_state;
564
565 tag = PCITAG_OFFSET(tag);
566 error = opal_pci_config_read_word(sc->sc_phb_id,
567 tag, reg, opal_phys(&data));
568 if (error == OPAL_SUCCESS && data != 0xffffffff)
569 return data;
570
571 /*
572 * Probing hardware that isn't there may ut the host bridge in
573 * an error state. Clear the error.
574 */
575 error = opal_pci_eeh_freeze_status(sc->sc_phb_id, sc->sc_pe_number,
576 opal_phys(&freeze_state), opal_phys(&pci_error_state), NULL);
577 if (freeze_state)
578 opal_pci_eeh_freeze_clear(sc->sc_phb_id, sc->sc_pe_number,
579 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
580
581 return 0xffffffff;
582 }
583
584 void
phb_conf_write(void * v,pcitag_t tag,int reg,pcireg_t data)585 phb_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
586 {
587 struct phb_softc *sc = v;
588
589 tag = PCITAG_OFFSET(tag);
590 opal_pci_config_write_word(sc->sc_phb_id, tag, reg, data);
591 }
592
593 int
phb_intr_map(struct pci_attach_args * pa,pci_intr_handle_t * ihp)594 phb_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
595 {
596 int pin = pa->pa_rawintrpin;
597
598 if (pin == 0 || pin > PCI_INTERRUPT_PIN_MAX)
599 return -1;
600
601 if (pa->pa_tag == 0)
602 return -1;
603
604 ihp->ih_pc = pa->pa_pc;
605 ihp->ih_tag = pa->pa_intrtag;
606 ihp->ih_intrpin = pa->pa_intrpin;
607 ihp->ih_type = PCI_INTX;
608
609 return 0;
610 }
611
612 const char *
phb_intr_string(void * v,pci_intr_handle_t ih)613 phb_intr_string(void *v, pci_intr_handle_t ih)
614 {
615 switch (ih.ih_type) {
616 case PCI_MSI32:
617 case PCI_MSI64:
618 return "msi";
619 case PCI_MSIX:
620 return "msix";
621 }
622
623 return "intx";
624 }
625
626 void *
phb_intr_establish(void * v,pci_intr_handle_t ih,int level,struct cpu_info * ci,int (* func)(void *),void * arg,char * name)627 phb_intr_establish(void *v, pci_intr_handle_t ih, int level,
628 struct cpu_info *ci, int (*func)(void *), void *arg, char *name)
629 {
630 struct phb_softc *sc = v;
631 void *cookie = NULL;
632
633 KASSERT(ih.ih_type != PCI_NONE);
634
635 if (ih.ih_type != PCI_INTX) {
636 uint32_t addr32, data;
637 uint64_t addr;
638 uint32_t xive;
639 int64_t error;
640
641 if (sc->sc_xive >= sc->sc_msi_ranges[1])
642 return NULL;
643
644 /* Allocate an MSI. */
645 xive = sc->sc_xive++;
646
647 error = opal_pci_set_xive_pe(sc->sc_phb_id,
648 sc->sc_pe_number, xive);
649 if (error != OPAL_SUCCESS)
650 return NULL;
651
652 /*
653 * Use a 32-bit MSI address whenever possible. Some
654 * older Radeon graphics cards advertise 64-bit MSI
655 * but only implement 40 bits.
656 */
657 error = opal_get_msi_32(sc->sc_phb_id, 0, xive,
658 1, opal_phys(&addr32), opal_phys(&data));
659 if (error == OPAL_SUCCESS)
660 addr = addr32;
661 if (error != OPAL_SUCCESS && ih.ih_type != PCI_MSI32) {
662 error = opal_get_msi_64(sc->sc_phb_id, 0, xive,
663 1, opal_phys(&addr), opal_phys(&data));
664 }
665 if (error != OPAL_SUCCESS)
666 return NULL;
667
668 cookie = intr_establish(sc->sc_msi_ranges[0] + xive,
669 IST_EDGE, level, ci, func, arg, name);
670 if (cookie == NULL)
671 return NULL;
672
673 if (ih.ih_type == PCI_MSIX) {
674 pci_msix_enable(ih.ih_pc, ih.ih_tag,
675 &sc->sc_bus_memt, ih.ih_intrpin, addr, data);
676 } else
677 pci_msi_enable(ih.ih_pc, ih.ih_tag, addr, data);
678 } else {
679 int bus, dev, fn;
680 uint32_t reg[4];
681 int node;
682
683 phb_decompose_tag(sc, ih.ih_tag, &bus, &dev, &fn);
684
685 reg[0] = bus << 16 | dev << 11 | fn << 8;
686 reg[1] = reg[2] = 0;
687 reg[3] = ih.ih_intrpin;
688
689 /* Host bridge child node holds the interrupt map. */
690 node = OF_child(sc->sc_node);
691 if (node == 0)
692 return NULL;
693
694 cookie = fdt_intr_establish_imap(node, reg, sizeof(reg),
695 level, func, arg, name);
696 }
697
698 return cookie;
699 }
700
701 void
phb_intr_disestablish(void * v,void * cookie)702 phb_intr_disestablish(void *v, void *cookie)
703 {
704 }
705
706 int
phb_bs_iomap(bus_space_tag_t t,bus_addr_t addr,bus_size_t size,int flags,bus_space_handle_t * bshp)707 phb_bs_iomap(bus_space_tag_t t, bus_addr_t addr, bus_size_t size,
708 int flags, bus_space_handle_t *bshp)
709 {
710 struct phb_softc *sc = t->bus_private;
711 int i;
712
713 for (i = 0; i < sc->sc_nranges; i++) {
714 uint64_t pci_start = sc->sc_ranges[i].pci_base;
715 uint64_t pci_end = pci_start + sc->sc_ranges[i].size;
716 uint64_t phys_start = sc->sc_ranges[i].phys_base;
717
718 if ((sc->sc_ranges[i].flags & 0x03000000) == 0x01000000 &&
719 addr >= pci_start && addr + size <= pci_end) {
720 return bus_space_map(sc->sc_iot,
721 addr - pci_start + phys_start, size, flags, bshp);
722 }
723 }
724
725 return ENXIO;
726 }
727
728 int
phb_bs_memmap(bus_space_tag_t t,bus_addr_t addr,bus_size_t size,int flags,bus_space_handle_t * bshp)729 phb_bs_memmap(bus_space_tag_t t, bus_addr_t addr, bus_size_t size,
730 int flags, bus_space_handle_t *bshp)
731 {
732 struct phb_softc *sc = t->bus_private;
733 int i;
734
735 for (i = 0; i < sc->sc_nranges; i++) {
736 uint64_t pci_start = sc->sc_ranges[i].pci_base;
737 uint64_t pci_end = pci_start + sc->sc_ranges[i].size;
738 uint64_t phys_start = sc->sc_ranges[i].phys_base;
739
740 if ((sc->sc_ranges[i].flags & 0x02000000) == 0x02000000 &&
741 addr >= pci_start && addr + size <= pci_end) {
742 return bus_space_map(sc->sc_iot,
743 addr - pci_start + phys_start, size, flags, bshp);
744 }
745 }
746
747 return ENXIO;
748 }
749
750 paddr_t
phb_bs_mmap(bus_space_tag_t t,bus_addr_t addr,off_t off,int prot,int flags)751 phb_bs_mmap(bus_space_tag_t t, bus_addr_t addr, off_t off,
752 int prot, int flags)
753 {
754 struct phb_softc *sc = t->bus_private;
755 int i;
756
757 for (i = 0; i < sc->sc_nranges; i++) {
758 uint64_t pci_start = sc->sc_ranges[i].pci_base;
759 uint64_t pci_end = pci_start + sc->sc_ranges[i].size;
760 uint64_t phys_start = sc->sc_ranges[i].phys_base;
761
762 if ((sc->sc_ranges[i].flags & 0x02000000) == 0x02000000 &&
763 addr >= pci_start && addr + PAGE_SIZE <= pci_end) {
764 return bus_space_mmap(sc->sc_iot,
765 addr - pci_start + phys_start, off, prot, flags);
766 }
767 }
768
769 return -1;
770 }
771
772 int
phb_dmamap_load_buffer(bus_dma_tag_t t,bus_dmamap_t map,void * buf,bus_size_t buflen,struct proc * p,int flags,paddr_t * lastaddrp,int * segp,int first)773 phb_dmamap_load_buffer(bus_dma_tag_t t, bus_dmamap_t map, void *buf,
774 bus_size_t buflen, struct proc *p, int flags, paddr_t *lastaddrp,
775 int *segp, int first)
776 {
777 struct phb_softc *sc = t->_cookie;
778 int seg, firstseg = *segp;
779 int error;
780
781 error = sc->sc_dmat->_dmamap_load_buffer(sc->sc_dmat, map, buf, buflen,
782 p, flags, lastaddrp, segp, first);
783 if (error)
784 return error;
785
786 /* For each segment. */
787 for (seg = firstseg; seg <= *segp; seg++) {
788 map->dm_segs[seg].ds_addr = map->dm_segs[seg]._ds_paddr;
789 if (sc->sc_tce_table)
790 map->dm_segs[seg].ds_addr += PHB_DMA_OFFSET;
791 else
792 map->dm_segs[seg].ds_addr |= IODA_TVE_SELECT;
793 }
794
795 return 0;
796 }
797
798 int
phb_dmamap_load_raw(bus_dma_tag_t t,bus_dmamap_t map,bus_dma_segment_t * segs,int nsegs,bus_size_t size,int flags)799 phb_dmamap_load_raw(bus_dma_tag_t t, bus_dmamap_t map,
800 bus_dma_segment_t *segs, int nsegs, bus_size_t size, int flags)
801 {
802 struct phb_softc *sc = t->_cookie;
803 int seg, error;
804
805 error = sc->sc_dmat->_dmamap_load_raw(sc->sc_dmat, map,
806 segs, nsegs, size, flags);
807 if (error)
808 return error;
809
810 /* For each segment. */
811 for (seg = 0; seg < map->dm_nsegs; seg++) {
812 map->dm_segs[seg].ds_addr = map->dm_segs[seg]._ds_paddr;
813 if (sc->sc_tce_table)
814 map->dm_segs[seg].ds_addr += PHB_DMA_OFFSET;
815 else
816 map->dm_segs[seg].ds_addr |= IODA_TVE_SELECT;
817 }
818
819 return 0;
820 }
821
822 struct phb_dmamem *
phb_dmamem_alloc(bus_dma_tag_t dmat,bus_size_t size,bus_size_t align)823 phb_dmamem_alloc(bus_dma_tag_t dmat, bus_size_t size, bus_size_t align)
824 {
825 struct phb_dmamem *pdm;
826 int nsegs;
827
828 pdm = malloc(sizeof(*pdm), M_DEVBUF, M_WAITOK | M_ZERO);
829 pdm->pdm_size = size;
830
831 if (bus_dmamap_create(dmat, size, 1, size, 0,
832 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &pdm->pdm_map) != 0)
833 goto pdmfree;
834
835 if (bus_dmamem_alloc(dmat, size, align, 0, &pdm->pdm_seg, 1,
836 &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO) != 0)
837 goto destroy;
838
839 if (bus_dmamem_map(dmat, &pdm->pdm_seg, nsegs, size,
840 &pdm->pdm_kva, BUS_DMA_WAITOK | BUS_DMA_NOCACHE) != 0)
841 goto free;
842
843 if (bus_dmamap_load_raw(dmat, pdm->pdm_map, &pdm->pdm_seg,
844 nsegs, size, BUS_DMA_WAITOK) != 0)
845 goto unmap;
846
847 return pdm;
848
849 unmap:
850 bus_dmamem_unmap(dmat, pdm->pdm_kva, size);
851 free:
852 bus_dmamem_free(dmat, &pdm->pdm_seg, 1);
853 destroy:
854 bus_dmamap_destroy(dmat, pdm->pdm_map);
855 pdmfree:
856 free(pdm, M_DEVBUF, sizeof(*pdm));
857
858 return NULL;
859 }
860
861 void
phb_dmamem_free(bus_dma_tag_t dmat,struct phb_dmamem * pdm)862 phb_dmamem_free(bus_dma_tag_t dmat, struct phb_dmamem *pdm)
863 {
864 bus_dmamem_unmap(dmat, pdm->pdm_kva, pdm->pdm_size);
865 bus_dmamem_free(dmat, &pdm->pdm_seg, 1);
866 bus_dmamap_destroy(dmat, pdm->pdm_map);
867 free(pdm, M_DEVBUF, sizeof(*pdm));
868 }
869