1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2011 NetApp, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #ifndef _PCI_EMUL_H_
30 #define _PCI_EMUL_H_
31
32 #include <sys/types.h>
33 #include <sys/queue.h>
34 #include <sys/kernel.h>
35 #include <sys/nv.h>
36 #include <sys/pciio.h>
37 #include <sys/_pthreadtypes.h>
38
39 #include <dev/pci/pcireg.h>
40
41 #include <assert.h>
42
43 #include "pci_irq.h"
44
45 #define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */
46 #define PCI_BARMAX_WITH_ROM (PCI_BARMAX + 1)
47 #define PCI_ROM_IDX (PCI_BARMAX + 1)
48
49 struct vmctx;
50 struct pci_devinst;
51 struct memory_region;
52 struct vm_snapshot_meta;
53
54 struct pci_devemu {
55 const char *pe_emu; /* Name of device emulation */
56
57 /* instance creation */
58 int (*pe_init)(struct pci_devinst *, nvlist_t *);
59 int (*pe_legacy_config)(nvlist_t *, const char *);
60 const char *pe_alias;
61
62 /* ACPI DSDT enumeration */
63 void (*pe_write_dsdt)(struct pci_devinst *);
64
65 /* config space read/write callbacks */
66 int (*pe_cfgwrite)(struct pci_devinst *pi, int offset,
67 int bytes, uint32_t val);
68 int (*pe_cfgread)(struct pci_devinst *pi, int offset,
69 int bytes, uint32_t *retval);
70
71 /* BAR read/write callbacks */
72 void (*pe_barwrite)(struct pci_devinst *pi, int baridx,
73 uint64_t offset, int size, uint64_t value);
74 uint64_t (*pe_barread)(struct pci_devinst *pi, int baridx,
75 uint64_t offset, int size);
76
77 void (*pe_baraddr)(struct pci_devinst *pi,
78 int baridx, int enabled, uint64_t address);
79
80 /* Save/restore device state */
81 int (*pe_snapshot)(struct vm_snapshot_meta *meta);
82 int (*pe_pause)(struct pci_devinst *pi);
83 int (*pe_resume)(struct pci_devinst *pi);
84
85 };
86 #define PCI_EMUL_SET(x) DATA_SET(pci_devemu_set, x)
87
88 enum pcibar_type {
89 PCIBAR_NONE,
90 PCIBAR_IO,
91 PCIBAR_MEM32,
92 PCIBAR_MEM64,
93 PCIBAR_MEMHI64,
94 PCIBAR_ROM,
95 };
96
97 struct pcibar {
98 enum pcibar_type type; /* io or memory */
99 uint64_t size;
100 uint64_t addr;
101 uint8_t lobits;
102 };
103
104 #define PI_NAMESZ 40
105
106 struct msix_table_entry {
107 uint64_t addr;
108 uint32_t msg_data;
109 uint32_t vector_control;
110 } __packed;
111
112 /*
113 * In case the structure is modified to hold extra information, use a define
114 * for the size that should be emulated.
115 */
116 #define MSIX_TABLE_ENTRY_SIZE 16
117 #define MAX_MSIX_TABLE_ENTRIES 2048
118 #define PBA_SIZE(msgnum) (roundup2((msgnum), 64) / 8)
119
120 struct pci_devinst {
121 struct pci_devemu *pi_d;
122 struct vmctx *pi_vmctx;
123 uint8_t pi_bus, pi_slot, pi_func;
124 char pi_name[PI_NAMESZ];
125 int pi_bar_getsize;
126 int pi_prevcap;
127 int pi_capend;
128
129 struct {
130 int8_t pin;
131 enum {
132 IDLE,
133 ASSERTED,
134 PENDING,
135 } state;
136 struct pci_irq irq;
137 pthread_mutex_t lock;
138 } pi_lintr;
139
140 struct {
141 int enabled;
142 uint64_t addr;
143 uint64_t msg_data;
144 int maxmsgnum;
145 } pi_msi;
146
147 struct {
148 int enabled;
149 int table_bar;
150 int pba_bar;
151 uint32_t table_offset;
152 int table_count;
153 uint32_t pba_offset;
154 int pba_size;
155 int function_mask;
156 struct msix_table_entry *table; /* allocated at runtime */
157 uint8_t *mapped_addr;
158 size_t mapped_size;
159 } pi_msix;
160
161 void *pi_arg; /* devemu-private data */
162
163 u_char pi_cfgdata[PCI_REGMAX + 1];
164 /* ROM is handled like a BAR */
165 struct pcibar pi_bar[PCI_BARMAX_WITH_ROM + 1];
166 uint64_t pi_romoffset;
167 };
168
169 struct msicap {
170 uint8_t capid;
171 uint8_t nextptr;
172 uint16_t msgctrl;
173 uint32_t addrlo;
174 uint32_t addrhi;
175 uint16_t msgdata;
176 } __packed;
177 static_assert(sizeof(struct msicap) == 14, "compile-time assertion failed");
178
179 struct msixcap {
180 uint8_t capid;
181 uint8_t nextptr;
182 uint16_t msgctrl;
183 uint32_t table_info; /* bar index and offset within it */
184 uint32_t pba_info; /* bar index and offset within it */
185 } __packed;
186 static_assert(sizeof(struct msixcap) == 12, "compile-time assertion failed");
187
188 struct pciecap {
189 uint8_t capid;
190 uint8_t nextptr;
191 uint16_t pcie_capabilities;
192
193 uint32_t dev_capabilities; /* all devices */
194 uint16_t dev_control;
195 uint16_t dev_status;
196
197 uint32_t link_capabilities; /* devices with links */
198 uint16_t link_control;
199 uint16_t link_status;
200
201 uint32_t slot_capabilities; /* ports with slots */
202 uint16_t slot_control;
203 uint16_t slot_status;
204
205 uint16_t root_control; /* root ports */
206 uint16_t root_capabilities;
207 uint32_t root_status;
208
209 uint32_t dev_capabilities2; /* all devices */
210 uint16_t dev_control2;
211 uint16_t dev_status2;
212
213 uint32_t link_capabilities2; /* devices with links */
214 uint16_t link_control2;
215 uint16_t link_status2;
216
217 uint32_t slot_capabilities2; /* ports with slots */
218 uint16_t slot_control2;
219 uint16_t slot_status2;
220 } __packed;
221 static_assert(sizeof(struct pciecap) == 60, "compile-time assertion failed");
222
223 typedef void (*pci_lintr_cb)(int b, int s, int pin, struct pci_irq *irq,
224 void *arg);
225 void pci_lintr_assert(struct pci_devinst *pi);
226 void pci_lintr_deassert(struct pci_devinst *pi);
227 void pci_lintr_request(struct pci_devinst *pi);
228 int pci_count_lintr(int bus);
229 void pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg);
230
231 int init_pci(struct vmctx *ctx);
232 void pci_callback(void);
233 uint32_t pci_config_read_reg(const struct pcisel *host_sel, nvlist_t *nvl,
234 uint32_t reg, uint8_t size, uint32_t def);
235 int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx,
236 enum pcibar_type type, uint64_t size);
237 int pci_emul_alloc_rom(struct pci_devinst *const pdi, const uint64_t size,
238 void **const addr);
239 int pci_emul_add_boot_device(struct pci_devinst *const pi,
240 const int bootindex);
241 int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum);
242 int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type);
243 void pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes,
244 uint32_t val, uint8_t capoff, int capid);
245 void pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old);
246 void pci_generate_msi(struct pci_devinst *pi, int msgnum);
247 void pci_generate_msix(struct pci_devinst *pi, int msgnum);
248 int pci_msi_enabled(struct pci_devinst *pi);
249 int pci_msix_enabled(struct pci_devinst *pi);
250 int pci_msix_table_bar(struct pci_devinst *pi);
251 int pci_msix_pba_bar(struct pci_devinst *pi);
252 int pci_msi_maxmsgnum(struct pci_devinst *pi);
253 int pci_parse_legacy_config(nvlist_t *nvl, const char *opt);
254 int pci_parse_slot(char *opt);
255 void pci_print_supported_devices(void);
256 void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr);
257 int pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum);
258 int pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
259 uint64_t value);
260 uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size);
261 void pci_write_dsdt(void);
262 uint64_t pci_ecfg_base(void);
263 int pci_bus_configured(int bus);
264
265 #ifdef BHYVE_SNAPSHOT
266 struct pci_devinst *pci_next(const struct pci_devinst *cursor);
267 int pci_snapshot(struct vm_snapshot_meta *meta);
268 int pci_pause(struct pci_devinst *pdi);
269 int pci_resume(struct pci_devinst *pdi);
270 #endif
271
272 static __inline void
pci_set_cfgdata8(struct pci_devinst * pi,int offset,uint8_t val)273 pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val)
274 {
275 assert(offset <= PCI_REGMAX);
276 *(uint8_t *)(pi->pi_cfgdata + offset) = val;
277 }
278
279 static __inline void
pci_set_cfgdata16(struct pci_devinst * pi,int offset,uint16_t val)280 pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val)
281 {
282 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
283 *(uint16_t *)(pi->pi_cfgdata + offset) = val;
284 }
285
286 static __inline void
pci_set_cfgdata32(struct pci_devinst * pi,int offset,uint32_t val)287 pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val)
288 {
289 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
290 *(uint32_t *)(pi->pi_cfgdata + offset) = val;
291 }
292
293 static __inline uint8_t
pci_get_cfgdata8(struct pci_devinst * pi,int offset)294 pci_get_cfgdata8(struct pci_devinst *pi, int offset)
295 {
296 assert(offset <= PCI_REGMAX);
297 return (*(uint8_t *)(pi->pi_cfgdata + offset));
298 }
299
300 static __inline uint16_t
pci_get_cfgdata16(struct pci_devinst * pi,int offset)301 pci_get_cfgdata16(struct pci_devinst *pi, int offset)
302 {
303 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
304 return (*(uint16_t *)(pi->pi_cfgdata + offset));
305 }
306
307 static __inline uint32_t
pci_get_cfgdata32(struct pci_devinst * pi,int offset)308 pci_get_cfgdata32(struct pci_devinst *pi, int offset)
309 {
310 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
311 return (*(uint32_t *)(pi->pi_cfgdata + offset));
312 }
313
314 #endif /* _PCI_EMUL_H_ */
315