1 /**************************************************************************
2
3 Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
4 Copyright © 2002 David Dawes
5
6 All Rights Reserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining a
9 copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sub license, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial portions
18 of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
24 ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /*
31 * Authors:
32 * Keith Whitwell <keith@tungstengraphics.com>
33 * David Dawes <dawes@xfree86.org>
34 *
35 */
36
37 #ifdef HAVE_CONFIG_H
38 #include "config.h"
39 #endif
40
41 #if 0
42 #define I830DEBUG
43 #endif
44
45 #include <stdint.h>
46
47 #ifndef REMAP_RESERVED
48 #define REMAP_RESERVED 0
49 #endif
50
51 #ifndef _I830_H_
52 #define _I830_H_
53
54 #include "xorg-server.h"
55 #include "xf86_OSproc.h"
56 #include "compiler.h"
57 #include "xf86Cursor.h"
58 #include "xf86xv.h"
59 #include "xf86Crtc.h"
60 #include "xf86RandR12.h"
61
62 #include "xorg-server.h"
63 #include <pciaccess.h>
64
65 #define _XF86DRI_SERVER_
66 #include "drm.h"
67 #include "dri2.h"
68 #include "intel_bufmgr.h"
69 #include "i915_drm.h"
70
71 #include "intel_driver.h"
72 #include "intel_options.h"
73 #include "intel_list.h"
74 #include "compat-api.h"
75
76 #if HAVE_UDEV
77 #include <libudev.h>
78 #endif
79
80 #if HAVE_DRI3
81 #include "misync.h"
82 #endif
83
84 /* remain compatible to xorg-server 1.6 */
85 #ifndef MONITOR_EDID_COMPLETE_RAWDATA
86 #define MONITOR_EDID_COMPLETE_RAWDATA EDID_COMPLETE_RAWDATA
87 #endif
88
89 #if XF86_CRTC_VERSION >= 5
90 #define INTEL_PIXMAP_SHARING 1
91 #endif
92
93 #define MAX_PIPES 4 /* consider making all users dynamic */
94
95 #include "common.h"
96
97 #define PITCH_NONE 0
98
99 /** enumeration of 3d consumers so some can maintain invariant state. */
100 enum last_3d {
101 LAST_3D_OTHER,
102 LAST_3D_VIDEO,
103 LAST_3D_RENDER,
104 LAST_3D_ROTATION
105 };
106
107 enum dri_type {
108 DRI_DISABLED,
109 DRI_NONE,
110 DRI_ACTIVE
111 };
112
113 typedef struct intel_screen_private {
114 ScrnInfoPtr scrn;
115 struct intel_device *dev;
116 int cpp;
117
118 #define RENDER_BATCH I915_EXEC_RENDER
119 #define BLT_BATCH I915_EXEC_BLT
120 unsigned int current_batch;
121
122 void *modes;
123 drm_intel_bo *front_buffer, *back_buffer;
124 long front_pitch, front_tiling;
125
126 dri_bufmgr *bufmgr;
127
128 #if USE_UXA
129 uint32_t batch_ptr[4096];
130 /** Byte offset in batch_ptr for the next dword to be emitted. */
131 unsigned int batch_used;
132 /** Position in batch_ptr at the start of the current BEGIN_BATCH */
133 unsigned int batch_emit_start;
134 /** Number of bytes to be emitted in the current BEGIN_BATCH. */
135 uint32_t batch_emitting;
136 dri_bo *batch_bo, *last_batch_bo[2];
137 /** Whether we're in a section of code that can't tolerate flushing */
138 Bool in_batch_atomic;
139 /** Ending batch_used that was verified by intel_start_batch_atomic() */
140 int batch_atomic_limit;
141 struct list batch_pixmaps;
142 drm_intel_bo *wa_scratch_bo;
143 OsTimerPtr cache_expire;
144 #endif
145
146 /* For Xvideo */
147 Bool use_overlay;
148 #ifdef INTEL_XVMC
149 /* For XvMC */
150 Bool XvMCEnabled;
151 #endif
152
153 CreateScreenResourcesProcPtr CreateScreenResources;
154
155 Bool shadow_present;
156
157 unsigned int tiling;
158 #define INTEL_TILING_FB 0x1
159 #define INTEL_TILING_2D 0x2
160 #define INTEL_TILING_3D 0x4
161 #define INTEL_TILING_ALL (~0)
162
163 Bool swapbuffers_wait;
164 Bool has_relaxed_fencing;
165
166 int Chipset;
167 EntityInfoPtr pEnt;
168 const struct intel_device_info *info;
169
170 unsigned int BR[20];
171 unsigned int BR_tiling[2];
172
173 CloseScreenProcPtr CloseScreen;
174
175 void (*context_switch) (struct intel_screen_private *intel,
176 int new_mode);
177 void (*vertex_flush) (struct intel_screen_private *intel);
178 void (*batch_flush) (struct intel_screen_private *intel);
179 void (*batch_commit_notify) (struct intel_screen_private *intel);
180
181 #if USE_UXA
182 struct _UxaDriver *uxa_driver;
183 int uxa_flags;
184 #endif
185 Bool need_sync;
186 int accel_pixmap_offset_alignment;
187 int accel_max_x;
188 int accel_max_y;
189 int max_bo_size;
190 int max_gtt_map_size;
191 int max_tiling_size;
192
193 Bool XvDisabled; /* Xv disabled in PreInit. */
194 Bool XvEnabled; /* Xv enabled for this generation. */
195 Bool XvPreferOverlay;
196
197 int colorKey;
198 XF86VideoAdaptorPtr adaptor;
199 #if !HAVE_NOTIFY_FD
200 ScreenBlockHandlerProcPtr BlockHandler;
201 #endif
202 Bool overlayOn;
203
204 struct {
205 drm_intel_bo *gen4_vs_bo;
206 drm_intel_bo *gen4_sf_bo;
207 drm_intel_bo *gen4_wm_packed_bo;
208 drm_intel_bo *gen4_wm_planar_bo;
209 drm_intel_bo *gen4_cc_bo;
210 drm_intel_bo *gen4_cc_vp_bo;
211 drm_intel_bo *gen4_sampler_bo;
212 drm_intel_bo *gen4_sip_kernel_bo;
213 drm_intel_bo *wm_prog_packed_bo;
214 drm_intel_bo *wm_prog_planar_bo;
215 drm_intel_bo *gen6_blend_bo;
216 drm_intel_bo *gen6_depth_stencil_bo;
217 } video;
218
219 #if USE_UXA
220 /* Render accel state */
221 float scale_units[2][2];
222 /** Transform pointers for src/mask, or NULL if identity */
223 PictTransform *transform[2];
224
225 PixmapPtr render_source, render_mask, render_dest;
226 PicturePtr render_source_picture, render_mask_picture, render_dest_picture;
227 Bool needs_3d_invariant;
228 Bool needs_render_state_emit;
229 Bool needs_render_vertex_emit;
230
231 /* i830 render accel state */
232 uint32_t render_dest_format;
233 uint32_t cblend, ablend, s8_blendctl;
234
235 /* i915 render accel state */
236 PixmapPtr texture[2];
237 uint32_t mapstate[6];
238 uint32_t samplerstate[6];
239
240 struct {
241 int op;
242 uint32_t dst_format;
243 } i915_render_state;
244
245 struct {
246 int num_sf_outputs;
247 int drawrect;
248 uint32_t blend;
249 dri_bo *samplers;
250 dri_bo *kernel;
251 } gen6_render_state;
252
253 uint32_t prim_offset;
254 void (*prim_emit)(struct intel_screen_private *intel,
255 int srcX, int srcY,
256 int maskX, int maskY,
257 int dstX, int dstY,
258 int w, int h);
259 int floats_per_vertex;
260 int last_floats_per_vertex;
261 uint16_t vertex_offset;
262 uint16_t vertex_count;
263 uint16_t vertex_index;
264 uint16_t vertex_used;
265 uint32_t vertex_id;
266 float vertex_ptr[4*1024];
267 dri_bo *vertex_bo;
268
269 uint8_t surface_data[16*1024];
270 uint16_t surface_used;
271 uint16_t surface_table;
272 uint32_t surface_reloc;
273 dri_bo *surface_bo;
274
275 /* 965 render acceleration state */
276 struct gen4_render_state *gen4_render_state;
277 #endif
278
279 /* DRI enabled this generation. */
280 enum dri_type dri2, dri3;
281 int drmSubFD;
282 char *deviceName;
283
284 Bool use_pageflipping;
285 Bool use_triple_buffer;
286 Bool force_fallback;
287 Bool has_kernel_flush;
288 Bool needs_flush;
289
290 /* Broken-out options. */
291 OptionInfoPtr Options;
292
293 /* Driver phase/state information */
294 Bool suspended;
295
296 enum last_3d last_3d;
297
298 /**
299 * User option to print acceleration fallback info to the server log.
300 */
301 Bool fallback_debug;
302 unsigned debug_flush;
303 #if HAVE_UDEV
304 struct udev_monitor *uevent_monitor;
305 pointer uevent_handler;
306 #endif
307 Bool has_prime_vmap_flush;
308
309 #if HAVE_DRI3
310 SyncScreenFuncsRec save_sync_screen_funcs;
311 #endif
312 void (*flush_rendering)(struct intel_screen_private *intel);
313 } intel_screen_private;
314
315 #define INTEL_INFO(intel) ((intel)->info)
316 #define IS_GENx(intel, X) (INTEL_INFO(intel)->gen >= 8*(X) && INTEL_INFO(intel)->gen < 8*((X)+1))
317 #define IS_GEN1(intel) IS_GENx(intel, 1)
318 #define IS_GEN2(intel) IS_GENx(intel, 2)
319 #define IS_GEN3(intel) IS_GENx(intel, 3)
320 #define IS_GEN4(intel) IS_GENx(intel, 4)
321 #define IS_GEN5(intel) IS_GENx(intel, 5)
322 #define IS_GEN6(intel) IS_GENx(intel, 6)
323 #define IS_GEN7(intel) IS_GENx(intel, 7)
324 #define IS_HSW(intel) (INTEL_INFO(intel)->gen == 075)
325
326 /* Some chips have specific errata (or limits) that we need to workaround. */
327 #define IS_I830(intel) (intel_get_device_id((intel)->dev) == PCI_CHIP_I830_M)
328 #define IS_845G(intel) (intel_get_device_id((intel)->dev) == PCI_CHIP_845_G)
329 #define IS_I865G(intel) (intel_get_device_id((intel)->dev) == PCI_CHIP_I865_G)
330
331 #define IS_I915G(pI810) (intel_get_device_id((intel)->dev) == PCI_CHIP_I915_G || intel_get_device_id((intel)->dev) == PCI_CHIP_E7221_G)
332 #define IS_I915GM(pI810) (intel_get_device_id((intel)->dev) == PCI_CHIP_I915_GM)
333
334 #define IS_965_Q(pI810) (intel_get_device_id((intel)->dev) == PCI_CHIP_I965_Q)
335
336 /* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */
337 #define SUPPORTS_YTILING(pI810) (INTEL_INFO(intel)->gen >= 040)
338 #define HAS_BLT(pI810) (INTEL_INFO(intel)->gen >= 060)
339
340 #ifndef I915_PARAM_HAS_PRIME_VMAP_FLUSH
341 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
342 #endif
343
344 enum {
345 DEBUG_FLUSH_BATCHES = 0x1,
346 DEBUG_FLUSH_CACHES = 0x2,
347 DEBUG_FLUSH_WAIT = 0x4,
348 };
349
350 extern Bool intel_mode_pre_init(ScrnInfoPtr pScrn, int fd, int cpp);
351 extern void intel_mode_init(struct intel_screen_private *intel);
352 extern void intel_mode_disable_unused_functions(ScrnInfoPtr scrn);
353 extern void intel_mode_remove_fb(intel_screen_private *intel);
354 extern void intel_mode_close(intel_screen_private *intel);
355 extern void intel_mode_fini(intel_screen_private *intel);
356 extern int intel_mode_read_drm_events(intel_screen_private *intel);
357 extern void intel_mode_hotplug(intel_screen_private *intel);
358
359 typedef void (*intel_drm_handler_proc)(ScrnInfoPtr scrn,
360 xf86CrtcPtr crtc,
361 uint64_t seq,
362 uint64_t usec,
363 void *data);
364
365 typedef void (*intel_drm_abort_proc)(ScrnInfoPtr scrn,
366 xf86CrtcPtr crtc,
367 void *data);
368
369 extern uint32_t intel_drm_queue_alloc(ScrnInfoPtr scrn, xf86CrtcPtr crtc, void *data, intel_drm_handler_proc handler, intel_drm_abort_proc abort);
370 extern void intel_drm_abort(ScrnInfoPtr scrn, Bool (*match)(void *data, void *match_data), void *match_data);
371 extern void intel_drm_abort_seq(ScrnInfoPtr scrn, uint32_t seq);
372
373 extern int intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, xf86CrtcPtr crtc);
374 extern int intel_crtc_id(xf86CrtcPtr crtc);
375 extern int intel_output_dpms_status(xf86OutputPtr output);
376 extern void intel_copy_fb(ScrnInfoPtr scrn);
377
378 int
379 intel_get_crtc_msc_ust(ScrnInfoPtr scrn, xf86CrtcPtr crtc, uint64_t *msc, uint64_t *ust);
380
381 uint32_t
382 intel_crtc_msc_to_sequence(ScrnInfoPtr scrn, xf86CrtcPtr crtc, uint64_t expect);
383
384 uint64_t
385 intel_sequence_to_crtc_msc(xf86CrtcPtr crtc, uint32_t sequence);
386
387 enum DRI2FrameEventType {
388 DRI2_SWAP,
389 DRI2_SWAP_CHAIN,
390 DRI2_FLIP,
391 DRI2_WAITMSC,
392 };
393
394 #if XORG_VERSION_CURRENT <= XORG_VERSION_NUMERIC(1,7,99,3,0)
395 typedef void (*DRI2SwapEventPtr)(ClientPtr client, void *data, int type,
396 CARD64 ust, CARD64 msc, CARD64 sbc);
397 #endif
398
399 typedef void (*intel_pageflip_handler_proc) (uint64_t frame,
400 uint64_t usec,
401 void *data);
402
403 typedef void (*intel_pageflip_abort_proc) (void *data);
404
405 typedef struct _DRI2FrameEvent {
406 struct intel_screen_private *intel;
407
408 XID drawable_id;
409 ClientPtr client;
410 enum DRI2FrameEventType type;
411 int frame;
412
413 struct list drawable_resource, client_resource;
414
415 /* for swaps & flips only */
416 DRI2SwapEventPtr event_complete;
417 void *event_data;
418 DRI2BufferPtr front;
419 DRI2BufferPtr back;
420
421 /* current scanout for triple buffer */
422 int old_width;
423 int old_height;
424 int old_pitch;
425 int old_tiling;
426 dri_bo *old_buffer;
427 } DRI2FrameEventRec, *DRI2FrameEventPtr;
428
429 extern Bool intel_do_pageflip(intel_screen_private *intel,
430 dri_bo *new_front,
431 int ref_crtc_hw_id,
432 Bool async,
433 void *pageflip_data,
434 intel_pageflip_handler_proc pageflip_handler,
435 intel_pageflip_abort_proc pageflip_abort);
436
437 static inline intel_screen_private *
intel_get_screen_private(ScrnInfoPtr scrn)438 intel_get_screen_private(ScrnInfoPtr scrn)
439 {
440 return (intel_screen_private *)(scrn->driverPrivate);
441 }
442
443 #ifndef ARRAY_SIZE
444 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
445 #endif
446
447 #ifndef ALIGN
448 #define ALIGN(i,m) (((i) + (m) - 1) & ~((m) - 1))
449 #endif
450
451 #ifndef MIN
452 #define MIN(a,b) ((a) < (b) ? (a) : (b))
453 #endif
454
455 extern void intel_video_init(ScreenPtr pScreen);
456 extern void intel_box_intersect(BoxPtr dest, BoxPtr a, BoxPtr b);
457 extern void intel_crtc_box(xf86CrtcPtr crtc, BoxPtr crtc_box);
458
459 extern xf86CrtcPtr intel_covering_crtc(ScrnInfoPtr scrn, BoxPtr box,
460 xf86CrtcPtr desired, BoxPtr crtc_box_ret);
461
462 Bool I830DRI2ScreenInit(ScreenPtr pScreen);
463 void I830DRI2CloseScreen(ScreenPtr pScreen);
464
465 /* intel_dri3.c */
466 Bool intel_dri3_screen_init(ScreenPtr screen);
467
468 extern Bool intel_crtc_on(xf86CrtcPtr crtc);
469 int intel_crtc_to_pipe(xf86CrtcPtr crtc);
470
471 /* intel_memory.c */
472 unsigned long intel_get_fence_size(intel_screen_private *intel, unsigned long size);
473 unsigned long intel_get_fence_pitch(intel_screen_private *intel, unsigned long pitch,
474 uint32_t tiling_mode);
475 Bool intel_check_display_stride(ScrnInfoPtr scrn, int stride, Bool tiling);
476 void intel_set_gem_max_sizes(ScrnInfoPtr scrn);
477
478 unsigned int
479 intel_compute_size(struct intel_screen_private *intel,
480 int w, int h, int bpp, unsigned usage,
481 uint32_t *tiling, int *stride);
482
483 drm_intel_bo *intel_allocate_framebuffer(ScrnInfoPtr scrn,
484 int width, int height, int cpp,
485 int *out_stride,
486 uint32_t *out_tiling);
487
get_drawable_pixmap(DrawablePtr drawable)488 static inline PixmapPtr get_drawable_pixmap(DrawablePtr drawable)
489 {
490 ScreenPtr screen = drawable->pScreen;
491
492 if (drawable->type == DRAWABLE_PIXMAP)
493 return (PixmapPtr) drawable;
494 else
495 return screen->GetWindowPixmap((WindowPtr) drawable);
496 }
497
pixmap_is_scanout(PixmapPtr pixmap)498 static inline Bool pixmap_is_scanout(PixmapPtr pixmap)
499 {
500 ScreenPtr screen = pixmap->drawable.pScreen;
501
502 return pixmap == screen->GetScreenPixmap(screen);
503 }
504
505 static inline int
intel_pixmap_pitch(PixmapPtr pixmap)506 intel_pixmap_pitch(PixmapPtr pixmap)
507 {
508 return (unsigned long)pixmap->devKind;
509 }
510
511 /*
512 * intel_sync.c
513 */
514
515 #if HAVE_DRI3
516 Bool intel_sync_init(ScreenPtr screen);
517 void intel_sync_close(ScreenPtr screen);
518 #else
intel_sync_init(ScreenPtr screen)519 static inline Bool intel_sync_init(ScreenPtr screen) { return 0; }
intel_sync_close(ScreenPtr screen)520 static inline void intel_sync_close(ScreenPtr screen) { }
521 #endif
522
523 /*
524 * intel_present.c
525 */
526
527 #if 0
528 #define DebugPresent(x) ErrorF x
529 #else
530 #define DebugPresent(x)
531 #endif
532
533 #if HAVE_PRESENT
534 Bool intel_present_screen_init(ScreenPtr screen);
535 #else
intel_present_screen_init(ScreenPtr screen)536 static inline Bool intel_present_screen_init(ScreenPtr screen) { return 0; }
537 #endif
538
539 dri_bo *
540 intel_get_pixmap_bo(PixmapPtr pixmap);
541
542 void
543 intel_set_pixmap_bo(PixmapPtr pixmap, dri_bo *bo);
544
545 void
546 intel_flush(intel_screen_private *intel);
547
548 #endif /* _I830_H_ */
549