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Searched defs:pll_regs (Results 1 – 25 of 267) sorted by relevance

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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h114 struct pll_regs { struct
115 u32 cscr; /* Clock Source Control Register */
116 u32 mpctl0; /* MCU PLL Control Register 0 */
117 u32 mpctl1; /* MCU PLL Control Register 1 */
118 u32 spctl0; /* System PLL Control Register 0 */
119 u32 spctl1; /* System PLL Control Register 1 */
120 u32 osc26mctl; /* Oscillator 26M Register */
121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */
122 u32 pcdr1; /* Peripheral Clock Divider Register 1 */
123 u32 pccr0; /* Peripheral Clock Control Register 0 */
[all …]
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h114 struct pll_regs { struct
115 u32 cscr; /* Clock Source Control Register */
116 u32 mpctl0; /* MCU PLL Control Register 0 */
117 u32 mpctl1; /* MCU PLL Control Register 1 */
118 u32 spctl0; /* System PLL Control Register 0 */
119 u32 spctl1; /* System PLL Control Register 1 */
120 u32 osc26mctl; /* Oscillator 26M Register */
121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */
122 u32 pcdr1; /* Peripheral Clock Divider Register 1 */
123 u32 pccr0; /* Peripheral Clock Control Register 0 */
[all …]
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h114 struct pll_regs { struct
115 u32 cscr; /* Clock Source Control Register */
116 u32 mpctl0; /* MCU PLL Control Register 0 */
117 u32 mpctl1; /* MCU PLL Control Register 1 */
118 u32 spctl0; /* System PLL Control Register 0 */
119 u32 spctl1; /* System PLL Control Register 1 */
120 u32 osc26mctl; /* Oscillator 26M Register */
121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */
122 u32 pcdr1; /* Peripheral Clock Divider Register 1 */
123 u32 pccr0; /* Peripheral Clock Control Register 0 */
[all …]
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h114 struct pll_regs { struct
115 u32 cscr; /* Clock Source Control Register */
116 u32 mpctl0; /* MCU PLL Control Register 0 */
117 u32 mpctl1; /* MCU PLL Control Register 1 */
118 u32 spctl0; /* System PLL Control Register 0 */
119 u32 spctl1; /* System PLL Control Register 1 */
120 u32 osc26mctl; /* Oscillator 26M Register */
121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */
122 u32 pcdr1; /* Peripheral Clock Divider Register 1 */
123 u32 pccr0; /* Peripheral Clock Control Register 0 */
[all …]
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h114 struct pll_regs { struct
115 u32 cscr; /* Clock Source Control Register */
116 u32 mpctl0; /* MCU PLL Control Register 0 */
117 u32 mpctl1; /* MCU PLL Control Register 1 */
118 u32 spctl0; /* System PLL Control Register 0 */
119 u32 spctl1; /* System PLL Control Register 1 */
120 u32 osc26mctl; /* Oscillator 26M Register */
121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */
122 u32 pcdr1; /* Peripheral Clock Divider Register 1 */
123 u32 pccr0; /* Peripheral Clock Control Register 0 */
[all …]
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h114 struct pll_regs { struct
115 u32 cscr; /* Clock Source Control Register */
116 u32 mpctl0; /* MCU PLL Control Register 0 */
117 u32 mpctl1; /* MCU PLL Control Register 1 */
118 u32 spctl0; /* System PLL Control Register 0 */
119 u32 spctl1; /* System PLL Control Register 1 */
120 u32 osc26mctl; /* Oscillator 26M Register */
121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */
122 u32 pcdr1; /* Peripheral Clock Divider Register 1 */
123 u32 pccr0; /* Peripheral Clock Control Register 0 */
[all …]
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h114 struct pll_regs { struct
115 u32 cscr; /* Clock Source Control Register */
116 u32 mpctl0; /* MCU PLL Control Register 0 */
117 u32 mpctl1; /* MCU PLL Control Register 1 */
118 u32 spctl0; /* System PLL Control Register 0 */
119 u32 spctl1; /* System PLL Control Register 1 */
120 u32 osc26mctl; /* Oscillator 26M Register */
121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */
122 u32 pcdr1; /* Peripheral Clock Divider Register 1 */
123 u32 pccr0; /* Peripheral Clock Control Register 0 */
[all …]
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h114 struct pll_regs { struct
115 u32 cscr; /* Clock Source Control Register */
116 u32 mpctl0; /* MCU PLL Control Register 0 */
117 u32 mpctl1; /* MCU PLL Control Register 1 */
118 u32 spctl0; /* System PLL Control Register 0 */
119 u32 spctl1; /* System PLL Control Register 1 */
120 u32 osc26mctl; /* Oscillator 26M Register */
121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */
122 u32 pcdr1; /* Peripheral Clock Divider Register 1 */
123 u32 pccr0; /* Peripheral Clock Control Register 0 */
[all …]
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h114 struct pll_regs { struct
115 u32 cscr; /* Clock Source Control Register */
116 u32 mpctl0; /* MCU PLL Control Register 0 */
117 u32 mpctl1; /* MCU PLL Control Register 1 */
118 u32 spctl0; /* System PLL Control Register 0 */
119 u32 spctl1; /* System PLL Control Register 1 */
120 u32 osc26mctl; /* Oscillator 26M Register */
121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */
122 u32 pcdr1; /* Peripheral Clock Divider Register 1 */
123 u32 pccr0; /* Peripheral Clock Control Register 0 */
[all …]
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h114 struct pll_regs { struct
115 u32 cscr; /* Clock Source Control Register */
116 u32 mpctl0; /* MCU PLL Control Register 0 */
117 u32 mpctl1; /* MCU PLL Control Register 1 */
118 u32 spctl0; /* System PLL Control Register 0 */
119 u32 spctl1; /* System PLL Control Register 1 */
120 u32 osc26mctl; /* Oscillator 26M Register */
121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */
122 u32 pcdr1; /* Peripheral Clock Divider Register 1 */
123 u32 pccr0; /* Peripheral Clock Control Register 0 */
[all …]
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h114 struct pll_regs { struct
115 u32 cscr; /* Clock Source Control Register */
116 u32 mpctl0; /* MCU PLL Control Register 0 */
117 u32 mpctl1; /* MCU PLL Control Register 1 */
118 u32 spctl0; /* System PLL Control Register 0 */
119 u32 spctl1; /* System PLL Control Register 1 */
120 u32 osc26mctl; /* Oscillator 26M Register */
121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */
122 u32 pcdr1; /* Peripheral Clock Divider Register 1 */
123 u32 pccr0; /* Peripheral Clock Control Register 0 */
[all …]
/dports/sysutils/u-boot-qemu-riscv64/u-boot-2021.07/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h114 struct pll_regs { struct
115 u32 cscr; /* Clock Source Control Register */
116 u32 mpctl0; /* MCU PLL Control Register 0 */
117 u32 mpctl1; /* MCU PLL Control Register 1 */
118 u32 spctl0; /* System PLL Control Register 0 */
119 u32 spctl1; /* System PLL Control Register 1 */
120 u32 osc26mctl; /* Oscillator 26M Register */
121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */
122 u32 pcdr1; /* Peripheral Clock Divider Register 1 */
123 u32 pccr0; /* Peripheral Clock Control Register 0 */
[all …]
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h114 struct pll_regs { struct
115 u32 cscr; /* Clock Source Control Register */
116 u32 mpctl0; /* MCU PLL Control Register 0 */
117 u32 mpctl1; /* MCU PLL Control Register 1 */
118 u32 spctl0; /* System PLL Control Register 0 */
119 u32 spctl1; /* System PLL Control Register 1 */
120 u32 osc26mctl; /* Oscillator 26M Register */
121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */
122 u32 pcdr1; /* Peripheral Clock Divider Register 1 */
123 u32 pccr0; /* Peripheral Clock Control Register 0 */
[all …]
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h114 struct pll_regs { struct
115 u32 cscr; /* Clock Source Control Register */
116 u32 mpctl0; /* MCU PLL Control Register 0 */
117 u32 mpctl1; /* MCU PLL Control Register 1 */
118 u32 spctl0; /* System PLL Control Register 0 */
119 u32 spctl1; /* System PLL Control Register 1 */
120 u32 osc26mctl; /* Oscillator 26M Register */
121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */
122 u32 pcdr1; /* Peripheral Clock Divider Register 1 */
123 u32 pccr0; /* Peripheral Clock Control Register 0 */
[all …]
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h114 struct pll_regs { struct
115 u32 cscr; /* Clock Source Control Register */
116 u32 mpctl0; /* MCU PLL Control Register 0 */
117 u32 mpctl1; /* MCU PLL Control Register 1 */
118 u32 spctl0; /* System PLL Control Register 0 */
119 u32 spctl1; /* System PLL Control Register 1 */
120 u32 osc26mctl; /* Oscillator 26M Register */
121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */
122 u32 pcdr1; /* Peripheral Clock Divider Register 1 */
123 u32 pccr0; /* Peripheral Clock Control Register 0 */
[all …]
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h114 struct pll_regs { struct
115 u32 cscr; /* Clock Source Control Register */
116 u32 mpctl0; /* MCU PLL Control Register 0 */
117 u32 mpctl1; /* MCU PLL Control Register 1 */
118 u32 spctl0; /* System PLL Control Register 0 */
119 u32 spctl1; /* System PLL Control Register 1 */
120 u32 osc26mctl; /* Oscillator 26M Register */
121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */
122 u32 pcdr1; /* Peripheral Clock Divider Register 1 */
123 u32 pccr0; /* Peripheral Clock Control Register 0 */
[all …]
/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h114 struct pll_regs { struct
115 u32 cscr; /* Clock Source Control Register */
116 u32 mpctl0; /* MCU PLL Control Register 0 */
117 u32 mpctl1; /* MCU PLL Control Register 1 */
118 u32 spctl0; /* System PLL Control Register 0 */
119 u32 spctl1; /* System PLL Control Register 1 */
120 u32 osc26mctl; /* Oscillator 26M Register */
121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */
122 u32 pcdr1; /* Peripheral Clock Divider Register 1 */
123 u32 pccr0; /* Peripheral Clock Control Register 0 */
[all …]
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h114 struct pll_regs { struct
115 u32 cscr; /* Clock Source Control Register */
116 u32 mpctl0; /* MCU PLL Control Register 0 */
117 u32 mpctl1; /* MCU PLL Control Register 1 */
118 u32 spctl0; /* System PLL Control Register 0 */
119 u32 spctl1; /* System PLL Control Register 1 */
120 u32 osc26mctl; /* Oscillator 26M Register */
121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */
122 u32 pcdr1; /* Peripheral Clock Divider Register 1 */
123 u32 pccr0; /* Peripheral Clock Control Register 0 */
[all …]
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h114 struct pll_regs { struct
115 u32 cscr; /* Clock Source Control Register */
116 u32 mpctl0; /* MCU PLL Control Register 0 */
117 u32 mpctl1; /* MCU PLL Control Register 1 */
118 u32 spctl0; /* System PLL Control Register 0 */
119 u32 spctl1; /* System PLL Control Register 1 */
120 u32 osc26mctl; /* Oscillator 26M Register */
121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */
122 u32 pcdr1; /* Peripheral Clock Divider Register 1 */
123 u32 pccr0; /* Peripheral Clock Control Register 0 */
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h114 struct pll_regs { struct
115 u32 cscr; /* Clock Source Control Register */
116 u32 mpctl0; /* MCU PLL Control Register 0 */
117 u32 mpctl1; /* MCU PLL Control Register 1 */
118 u32 spctl0; /* System PLL Control Register 0 */
119 u32 spctl1; /* System PLL Control Register 1 */
120 u32 osc26mctl; /* Oscillator 26M Register */
121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */
122 u32 pcdr1; /* Peripheral Clock Divider Register 1 */
123 u32 pccr0; /* Peripheral Clock Control Register 0 */
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h114 struct pll_regs { struct
115 u32 cscr; /* Clock Source Control Register */
116 u32 mpctl0; /* MCU PLL Control Register 0 */
117 u32 mpctl1; /* MCU PLL Control Register 1 */
118 u32 spctl0; /* System PLL Control Register 0 */
119 u32 spctl1; /* System PLL Control Register 1 */
120 u32 osc26mctl; /* Oscillator 26M Register */
121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */
122 u32 pcdr1; /* Peripheral Clock Divider Register 1 */
123 u32 pccr0; /* Peripheral Clock Control Register 0 */
[all …]
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h114 struct pll_regs { struct
115 u32 cscr; /* Clock Source Control Register */
116 u32 mpctl0; /* MCU PLL Control Register 0 */
117 u32 mpctl1; /* MCU PLL Control Register 1 */
118 u32 spctl0; /* System PLL Control Register 0 */
119 u32 spctl1; /* System PLL Control Register 1 */
120 u32 osc26mctl; /* Oscillator 26M Register */
121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */
122 u32 pcdr1; /* Peripheral Clock Divider Register 1 */
123 u32 pccr0; /* Peripheral Clock Control Register 0 */
[all …]
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h114 struct pll_regs { struct
115 u32 cscr; /* Clock Source Control Register */
116 u32 mpctl0; /* MCU PLL Control Register 0 */
117 u32 mpctl1; /* MCU PLL Control Register 1 */
118 u32 spctl0; /* System PLL Control Register 0 */
119 u32 spctl1; /* System PLL Control Register 1 */
120 u32 osc26mctl; /* Oscillator 26M Register */
121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */
122 u32 pcdr1; /* Peripheral Clock Divider Register 1 */
123 u32 pccr0; /* Peripheral Clock Control Register 0 */
[all …]
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h114 struct pll_regs { struct
115 u32 cscr; /* Clock Source Control Register */
116 u32 mpctl0; /* MCU PLL Control Register 0 */
117 u32 mpctl1; /* MCU PLL Control Register 1 */
118 u32 spctl0; /* System PLL Control Register 0 */
119 u32 spctl1; /* System PLL Control Register 1 */
120 u32 osc26mctl; /* Oscillator 26M Register */
121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */
122 u32 pcdr1; /* Peripheral Clock Divider Register 1 */
123 u32 pccr0; /* Peripheral Clock Control Register 0 */
[all …]
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h114 struct pll_regs { struct
115 u32 cscr; /* Clock Source Control Register */
116 u32 mpctl0; /* MCU PLL Control Register 0 */
117 u32 mpctl1; /* MCU PLL Control Register 1 */
118 u32 spctl0; /* System PLL Control Register 0 */
119 u32 spctl1; /* System PLL Control Register 1 */
120 u32 osc26mctl; /* Oscillator 26M Register */
121 u32 pcdr0; /* Peripheral Clock Divider Register 0 */
122 u32 pcdr1; /* Peripheral Clock Divider Register 1 */
123 u32 pccr0; /* Peripheral Clock Control Register 0 */
[all …]

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