1 /* $NetBSD: kfd_packet_manager_vi.c,v 1.2 2021/12/18 23:44:59 riastradh Exp $ */
2
3 /*
4 * Copyright 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: kfd_packet_manager_vi.c,v 1.2 2021/12/18 23:44:59 riastradh Exp $");
28
29 #include "kfd_kernel_queue.h"
30 #include "kfd_device_queue_manager.h"
31 #include "kfd_pm4_headers_vi.h"
32 #include "kfd_pm4_opcodes.h"
33
pm_build_pm4_header(unsigned int opcode,size_t packet_size)34 unsigned int pm_build_pm4_header(unsigned int opcode, size_t packet_size)
35 {
36 union PM4_MES_TYPE_3_HEADER header;
37
38 header.u32All = 0;
39 header.opcode = opcode;
40 header.count = packet_size / 4 - 2;
41 header.type = PM4_TYPE_3;
42
43 return header.u32All;
44 }
45
pm_map_process_vi(struct packet_manager * pm,uint32_t * buffer,struct qcm_process_device * qpd)46 static int pm_map_process_vi(struct packet_manager *pm, uint32_t *buffer,
47 struct qcm_process_device *qpd)
48 {
49 struct pm4_mes_map_process *packet;
50
51 packet = (struct pm4_mes_map_process *)buffer;
52
53 memset(buffer, 0, sizeof(struct pm4_mes_map_process));
54
55 packet->header.u32All = pm_build_pm4_header(IT_MAP_PROCESS,
56 sizeof(struct pm4_mes_map_process));
57 packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0;
58 packet->bitfields2.process_quantum = 1;
59 packet->bitfields2.pasid = qpd->pqm->process->pasid;
60 packet->bitfields3.page_table_base = qpd->page_table_base;
61 packet->bitfields10.gds_size = qpd->gds_size;
62 packet->bitfields10.num_gws = qpd->num_gws;
63 packet->bitfields10.num_oac = qpd->num_oac;
64 packet->bitfields10.num_queues = (qpd->is_debug) ? 0 : qpd->queue_count;
65
66 packet->sh_mem_config = qpd->sh_mem_config;
67 packet->sh_mem_bases = qpd->sh_mem_bases;
68 packet->sh_mem_ape1_base = qpd->sh_mem_ape1_base;
69 packet->sh_mem_ape1_limit = qpd->sh_mem_ape1_limit;
70
71 packet->sh_hidden_private_base_vmid = qpd->sh_hidden_private_base;
72
73 packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area);
74 packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area);
75
76 return 0;
77 }
78
pm_runlist_vi(struct packet_manager * pm,uint32_t * buffer,uint64_t ib,size_t ib_size_in_dwords,bool chain)79 static int pm_runlist_vi(struct packet_manager *pm, uint32_t *buffer,
80 uint64_t ib, size_t ib_size_in_dwords, bool chain)
81 {
82 struct pm4_mes_runlist *packet;
83 int concurrent_proc_cnt = 0;
84 struct kfd_dev *kfd = pm->dqm->dev;
85
86 if (WARN_ON(!ib))
87 return -EFAULT;
88
89 /* Determine the number of processes to map together to HW:
90 * it can not exceed the number of VMIDs available to the
91 * scheduler, and it is determined by the smaller of the number
92 * of processes in the runlist and kfd module parameter
93 * hws_max_conc_proc.
94 * Note: the arbitration between the number of VMIDs and
95 * hws_max_conc_proc has been done in
96 * kgd2kfd_device_init().
97 */
98 concurrent_proc_cnt = min(pm->dqm->processes_count,
99 kfd->max_proc_per_quantum);
100
101 packet = (struct pm4_mes_runlist *)buffer;
102
103 memset(buffer, 0, sizeof(struct pm4_mes_runlist));
104 packet->header.u32All = pm_build_pm4_header(IT_RUN_LIST,
105 sizeof(struct pm4_mes_runlist));
106
107 packet->bitfields4.ib_size = ib_size_in_dwords;
108 packet->bitfields4.chain = chain ? 1 : 0;
109 packet->bitfields4.offload_polling = 0;
110 packet->bitfields4.valid = 1;
111 packet->bitfields4.process_cnt = concurrent_proc_cnt;
112 packet->ordinal2 = lower_32_bits(ib);
113 packet->bitfields3.ib_base_hi = upper_32_bits(ib);
114
115 return 0;
116 }
117
pm_set_resources_vi(struct packet_manager * pm,uint32_t * buffer,struct scheduling_resources * res)118 int pm_set_resources_vi(struct packet_manager *pm, uint32_t *buffer,
119 struct scheduling_resources *res)
120 {
121 struct pm4_mes_set_resources *packet;
122
123 packet = (struct pm4_mes_set_resources *)buffer;
124 memset(buffer, 0, sizeof(struct pm4_mes_set_resources));
125
126 packet->header.u32All = pm_build_pm4_header(IT_SET_RESOURCES,
127 sizeof(struct pm4_mes_set_resources));
128
129 packet->bitfields2.queue_type =
130 queue_type__mes_set_resources__hsa_interface_queue_hiq;
131 packet->bitfields2.vmid_mask = res->vmid_mask;
132 packet->bitfields2.unmap_latency = KFD_UNMAP_LATENCY_MS / 100;
133 packet->bitfields7.oac_mask = res->oac_mask;
134 packet->bitfields8.gds_heap_base = res->gds_heap_base;
135 packet->bitfields8.gds_heap_size = res->gds_heap_size;
136
137 packet->gws_mask_lo = lower_32_bits(res->gws_mask);
138 packet->gws_mask_hi = upper_32_bits(res->gws_mask);
139
140 packet->queue_mask_lo = lower_32_bits(res->queue_mask);
141 packet->queue_mask_hi = upper_32_bits(res->queue_mask);
142
143 return 0;
144 }
145
pm_map_queues_vi(struct packet_manager * pm,uint32_t * buffer,struct queue * q,bool is_static)146 static int pm_map_queues_vi(struct packet_manager *pm, uint32_t *buffer,
147 struct queue *q, bool is_static)
148 {
149 struct pm4_mes_map_queues *packet;
150 bool use_static = is_static;
151
152 packet = (struct pm4_mes_map_queues *)buffer;
153 memset(buffer, 0, sizeof(struct pm4_mes_map_queues));
154
155 packet->header.u32All = pm_build_pm4_header(IT_MAP_QUEUES,
156 sizeof(struct pm4_mes_map_queues));
157 packet->bitfields2.num_queues = 1;
158 packet->bitfields2.queue_sel =
159 queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi;
160
161 packet->bitfields2.engine_sel =
162 engine_sel__mes_map_queues__compute_vi;
163 packet->bitfields2.queue_type =
164 queue_type__mes_map_queues__normal_compute_vi;
165
166 switch (q->properties.type) {
167 case KFD_QUEUE_TYPE_COMPUTE:
168 if (use_static)
169 packet->bitfields2.queue_type =
170 queue_type__mes_map_queues__normal_latency_static_queue_vi;
171 break;
172 case KFD_QUEUE_TYPE_DIQ:
173 packet->bitfields2.queue_type =
174 queue_type__mes_map_queues__debug_interface_queue_vi;
175 break;
176 case KFD_QUEUE_TYPE_SDMA:
177 case KFD_QUEUE_TYPE_SDMA_XGMI:
178 packet->bitfields2.engine_sel = q->properties.sdma_engine_id +
179 engine_sel__mes_map_queues__sdma0_vi;
180 use_static = false; /* no static queues under SDMA */
181 break;
182 default:
183 WARN(1, "queue type %d", q->properties.type);
184 return -EINVAL;
185 }
186 packet->bitfields3.doorbell_offset =
187 q->properties.doorbell_off;
188
189 packet->mqd_addr_lo =
190 lower_32_bits(q->gart_mqd_addr);
191
192 packet->mqd_addr_hi =
193 upper_32_bits(q->gart_mqd_addr);
194
195 packet->wptr_addr_lo =
196 lower_32_bits((uint64_t)q->properties.write_ptr);
197
198 packet->wptr_addr_hi =
199 upper_32_bits((uint64_t)q->properties.write_ptr);
200
201 return 0;
202 }
203
pm_unmap_queues_vi(struct packet_manager * pm,uint32_t * buffer,enum kfd_queue_type type,enum kfd_unmap_queues_filter filter,uint32_t filter_param,bool reset,unsigned int sdma_engine)204 static int pm_unmap_queues_vi(struct packet_manager *pm, uint32_t *buffer,
205 enum kfd_queue_type type,
206 enum kfd_unmap_queues_filter filter,
207 uint32_t filter_param, bool reset,
208 unsigned int sdma_engine)
209 {
210 struct pm4_mes_unmap_queues *packet;
211
212 packet = (struct pm4_mes_unmap_queues *)buffer;
213 memset(buffer, 0, sizeof(struct pm4_mes_unmap_queues));
214
215 packet->header.u32All = pm_build_pm4_header(IT_UNMAP_QUEUES,
216 sizeof(struct pm4_mes_unmap_queues));
217 switch (type) {
218 case KFD_QUEUE_TYPE_COMPUTE:
219 case KFD_QUEUE_TYPE_DIQ:
220 packet->bitfields2.engine_sel =
221 engine_sel__mes_unmap_queues__compute;
222 break;
223 case KFD_QUEUE_TYPE_SDMA:
224 case KFD_QUEUE_TYPE_SDMA_XGMI:
225 packet->bitfields2.engine_sel =
226 engine_sel__mes_unmap_queues__sdma0 + sdma_engine;
227 break;
228 default:
229 WARN(1, "queue type %d", type);
230 return -EINVAL;
231 }
232
233 if (reset)
234 packet->bitfields2.action =
235 action__mes_unmap_queues__reset_queues;
236 else
237 packet->bitfields2.action =
238 action__mes_unmap_queues__preempt_queues;
239
240 switch (filter) {
241 case KFD_UNMAP_QUEUES_FILTER_SINGLE_QUEUE:
242 packet->bitfields2.queue_sel =
243 queue_sel__mes_unmap_queues__perform_request_on_specified_queues;
244 packet->bitfields2.num_queues = 1;
245 packet->bitfields3b.doorbell_offset0 = filter_param;
246 break;
247 case KFD_UNMAP_QUEUES_FILTER_BY_PASID:
248 packet->bitfields2.queue_sel =
249 queue_sel__mes_unmap_queues__perform_request_on_pasid_queues;
250 packet->bitfields3a.pasid = filter_param;
251 break;
252 case KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES:
253 packet->bitfields2.queue_sel =
254 queue_sel__mes_unmap_queues__unmap_all_queues;
255 break;
256 case KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES:
257 /* in this case, we do not preempt static queues */
258 packet->bitfields2.queue_sel =
259 queue_sel__mes_unmap_queues__unmap_all_non_static_queues;
260 break;
261 default:
262 WARN(1, "filter %d", filter);
263 return -EINVAL;
264 }
265
266 return 0;
267
268 }
269
pm_query_status_vi(struct packet_manager * pm,uint32_t * buffer,uint64_t fence_address,uint32_t fence_value)270 static int pm_query_status_vi(struct packet_manager *pm, uint32_t *buffer,
271 uint64_t fence_address, uint32_t fence_value)
272 {
273 struct pm4_mes_query_status *packet;
274
275 packet = (struct pm4_mes_query_status *)buffer;
276 memset(buffer, 0, sizeof(struct pm4_mes_query_status));
277
278 packet->header.u32All = pm_build_pm4_header(IT_QUERY_STATUS,
279 sizeof(struct pm4_mes_query_status));
280
281 packet->bitfields2.context_id = 0;
282 packet->bitfields2.interrupt_sel =
283 interrupt_sel__mes_query_status__completion_status;
284 packet->bitfields2.command =
285 command__mes_query_status__fence_only_after_write_ack;
286
287 packet->addr_hi = upper_32_bits((uint64_t)fence_address);
288 packet->addr_lo = lower_32_bits((uint64_t)fence_address);
289 packet->data_hi = upper_32_bits((uint64_t)fence_value);
290 packet->data_lo = lower_32_bits((uint64_t)fence_value);
291
292 return 0;
293 }
294
pm_release_mem_vi(uint64_t gpu_addr,uint32_t * buffer)295 static int pm_release_mem_vi(uint64_t gpu_addr, uint32_t *buffer)
296 {
297 struct pm4_mec_release_mem *packet;
298
299 packet = (struct pm4_mec_release_mem *)buffer;
300 memset(buffer, 0, sizeof(*packet));
301
302 packet->header.u32All = pm_build_pm4_header(IT_RELEASE_MEM,
303 sizeof(*packet));
304
305 packet->bitfields2.event_type = CACHE_FLUSH_AND_INV_TS_EVENT;
306 packet->bitfields2.event_index = event_index___release_mem__end_of_pipe;
307 packet->bitfields2.tcl1_action_ena = 1;
308 packet->bitfields2.tc_action_ena = 1;
309 packet->bitfields2.cache_policy = cache_policy___release_mem__lru;
310 packet->bitfields2.atc = 0;
311
312 packet->bitfields3.data_sel = data_sel___release_mem__send_32_bit_low;
313 packet->bitfields3.int_sel =
314 int_sel___release_mem__send_interrupt_after_write_confirm;
315
316 packet->bitfields4.address_lo_32b = (gpu_addr & 0xffffffff) >> 2;
317 packet->address_hi = upper_32_bits(gpu_addr);
318
319 packet->data_lo = 0;
320
321 return 0;
322 }
323
324 const struct packet_manager_funcs kfd_vi_pm_funcs = {
325 .map_process = pm_map_process_vi,
326 .runlist = pm_runlist_vi,
327 .set_resources = pm_set_resources_vi,
328 .map_queues = pm_map_queues_vi,
329 .unmap_queues = pm_unmap_queues_vi,
330 .query_status = pm_query_status_vi,
331 .release_mem = pm_release_mem_vi,
332 .map_process_size = sizeof(struct pm4_mes_map_process),
333 .runlist_size = sizeof(struct pm4_mes_runlist),
334 .set_resources_size = sizeof(struct pm4_mes_set_resources),
335 .map_queues_size = sizeof(struct pm4_mes_map_queues),
336 .unmap_queues_size = sizeof(struct pm4_mes_unmap_queues),
337 .query_status_size = sizeof(struct pm4_mes_query_status),
338 .release_mem_size = sizeof(struct pm4_mec_release_mem)
339 };
340