1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 1991 Regents of the University of California.
5 * All rights reserved.
6 * Copyright (c) 1994 John S. Dyson
7 * All rights reserved.
8 * Copyright (c) 1994 David Greenman
9 * All rights reserved.
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
14 * Copyright (c) 2014 Andrew Turner
15 * All rights reserved.
16 * Copyright (c) 2014 The FreeBSD Foundation
17 * All rights reserved.
18 * Copyright (c) 2015-2018 Ruslan Bukin <br@bsdpad.com>
19 * All rights reserved.
20 *
21 * This code is derived from software contributed to Berkeley by
22 * the Systems Programming Group of the University of Utah Computer
23 * Science Department and William Jolitz of UUNET Technologies Inc.
24 *
25 * Portions of this software were developed by Andrew Turner under
26 * sponsorship from The FreeBSD Foundation.
27 *
28 * Portions of this software were developed by SRI International and the
29 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
30 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
31 *
32 * Portions of this software were developed by the University of Cambridge
33 * Computer Laboratory as part of the CTSRD Project, with support from the
34 * UK Higher Education Innovation Fund (HEIF).
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 * 1. Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * 2. Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in the
43 * documentation and/or other materials provided with the distribution.
44 * 3. All advertising materials mentioning features or use of this software
45 * must display the following acknowledgement:
46 * This product includes software developed by the University of
47 * California, Berkeley and its contributors.
48 * 4. Neither the name of the University nor the names of its contributors
49 * may be used to endorse or promote products derived from this software
50 * without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
55 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
62 * SUCH DAMAGE.
63 */
64 /*-
65 * Copyright (c) 2003 Networks Associates Technology, Inc.
66 * All rights reserved.
67 *
68 * This software was developed for the FreeBSD Project by Jake Burkholder,
69 * Safeport Network Services, and Network Associates Laboratories, the
70 * Security Research Division of Network Associates, Inc. under
71 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
72 * CHATS research program.
73 *
74 * Redistribution and use in source and binary forms, with or without
75 * modification, are permitted provided that the following conditions
76 * are met:
77 * 1. Redistributions of source code must retain the above copyright
78 * notice, this list of conditions and the following disclaimer.
79 * 2. Redistributions in binary form must reproduce the above copyright
80 * notice, this list of conditions and the following disclaimer in the
81 * documentation and/or other materials provided with the distribution.
82 *
83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
93 * SUCH DAMAGE.
94 */
95
96 #include <sys/cdefs.h>
97 /*
98 * Manages physical address maps.
99 *
100 * Since the information managed by this module is
101 * also stored by the logical address mapping module,
102 * this module may throw away valid virtual-to-physical
103 * mappings at almost any time. However, invalidations
104 * of virtual-to-physical mappings must be done as
105 * requested.
106 *
107 * In order to cope with hardware architectures which
108 * make virtual-to-physical map invalidates expensive,
109 * this module may delay invalidate or reduced protection
110 * operations until such time as they are actually
111 * necessary. This module is given full information as
112 * to which processors are currently using which maps,
113 * and to when physical maps must be made correct.
114 */
115
116 #include <sys/param.h>
117 #include <sys/systm.h>
118 #include <sys/bitstring.h>
119 #include <sys/bus.h>
120 #include <sys/cpuset.h>
121 #include <sys/kernel.h>
122 #include <sys/ktr.h>
123 #include <sys/lock.h>
124 #include <sys/malloc.h>
125 #include <sys/mman.h>
126 #include <sys/msgbuf.h>
127 #include <sys/mutex.h>
128 #include <sys/physmem.h>
129 #include <sys/proc.h>
130 #include <sys/rwlock.h>
131 #include <sys/sbuf.h>
132 #include <sys/sx.h>
133 #include <sys/vmem.h>
134 #include <sys/vmmeter.h>
135 #include <sys/sched.h>
136 #include <sys/sysctl.h>
137 #include <sys/smp.h>
138
139 #include <vm/vm.h>
140 #include <vm/vm_param.h>
141 #include <vm/vm_kern.h>
142 #include <vm/vm_page.h>
143 #include <vm/vm_map.h>
144 #include <vm/vm_object.h>
145 #include <vm/vm_extern.h>
146 #include <vm/vm_pageout.h>
147 #include <vm/vm_pager.h>
148 #include <vm/vm_phys.h>
149 #include <vm/vm_radix.h>
150 #include <vm/vm_reserv.h>
151 #include <vm/vm_dumpset.h>
152 #include <vm/uma.h>
153
154 #include <machine/machdep.h>
155 #include <machine/md_var.h>
156 #include <machine/pcb.h>
157 #include <machine/sbi.h>
158
159 /*
160 * Boundary values for the page table page index space:
161 *
162 * L3 pages: [0, NUL2E)
163 * L2 pages: [NUL2E, NUL2E + NUL1E)
164 * L1 pages: [NUL2E + NUL1E, NUL2E + NUL1E + NUL0E)
165 *
166 * Note that these ranges are used in both SV39 and SV48 mode. In SV39 mode the
167 * ranges are not fully populated since there are at most Ln_ENTRIES^2 L3 pages
168 * in a set of page tables.
169 */
170 #define NUL0E Ln_ENTRIES
171 #define NUL1E (Ln_ENTRIES * NUL0E)
172 #define NUL2E (Ln_ENTRIES * NUL1E)
173
174 #ifdef PV_STATS
175 #define PV_STAT(x) do { x ; } while (0)
176 #define __pv_stat_used
177 #else
178 #define PV_STAT(x) do { } while (0)
179 #define __pv_stat_used __unused
180 #endif
181
182 #define pmap_l1_pindex(v) (NUL2E + ((v) >> L1_SHIFT))
183 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
184 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
185
186 #define NPV_LIST_LOCKS MAXCPU
187
188 #define PHYS_TO_PV_LIST_LOCK(pa) \
189 (&pv_list_locks[pmap_l2_pindex(pa) % NPV_LIST_LOCKS])
190
191 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
192 struct rwlock **_lockp = (lockp); \
193 struct rwlock *_new_lock; \
194 \
195 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
196 if (_new_lock != *_lockp) { \
197 if (*_lockp != NULL) \
198 rw_wunlock(*_lockp); \
199 *_lockp = _new_lock; \
200 rw_wlock(*_lockp); \
201 } \
202 } while (0)
203
204 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
205 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
206
207 #define RELEASE_PV_LIST_LOCK(lockp) do { \
208 struct rwlock **_lockp = (lockp); \
209 \
210 if (*_lockp != NULL) { \
211 rw_wunlock(*_lockp); \
212 *_lockp = NULL; \
213 } \
214 } while (0)
215
216 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
217 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
218
219 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
220 "VM/pmap parameters");
221
222 /* The list of all the user pmaps */
223 LIST_HEAD(pmaplist, pmap);
224 static struct pmaplist allpmaps = LIST_HEAD_INITIALIZER();
225
226 enum pmap_mode __read_frequently pmap_mode = PMAP_MODE_SV39;
227 SYSCTL_INT(_vm_pmap, OID_AUTO, mode, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
228 &pmap_mode, 0,
229 "translation mode, 0 = SV39, 1 = SV48");
230
231 struct pmap kernel_pmap_store;
232
233 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
234 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
235 vm_offset_t kernel_vm_end = 0;
236
237 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
238 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
239 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
240
241 /* This code assumes all L1 DMAP entries will be used */
242 CTASSERT((DMAP_MIN_ADDRESS & ~L1_OFFSET) == DMAP_MIN_ADDRESS);
243 CTASSERT((DMAP_MAX_ADDRESS & ~L1_OFFSET) == DMAP_MAX_ADDRESS);
244
245 /*
246 * This code assumes that the early DEVMAP is L2_SIZE aligned and is fully
247 * contained within a single L2 entry. The early DTB is mapped immediately
248 * before the devmap L2 entry.
249 */
250 CTASSERT((PMAP_MAPDEV_EARLY_SIZE & L2_OFFSET) == 0);
251 CTASSERT((VM_EARLY_DTB_ADDRESS & L2_OFFSET) == 0);
252 CTASSERT(VM_EARLY_DTB_ADDRESS < (VM_MAX_KERNEL_ADDRESS - PMAP_MAPDEV_EARLY_SIZE));
253
254 static struct rwlock_padalign pvh_global_lock;
255 static struct mtx_padalign allpmaps_lock;
256
257 static int __read_frequently superpages_enabled = 1;
258 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
259 CTLFLAG_RDTUN, &superpages_enabled, 0,
260 "Enable support for transparent superpages");
261
262 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
263 "2MB page mapping counters");
264
265 static u_long pmap_l2_demotions;
266 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
267 &pmap_l2_demotions, 0,
268 "2MB page demotions");
269
270 static u_long pmap_l2_mappings;
271 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, mappings, CTLFLAG_RD,
272 &pmap_l2_mappings, 0,
273 "2MB page mappings");
274
275 static u_long pmap_l2_p_failures;
276 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
277 &pmap_l2_p_failures, 0,
278 "2MB page promotion failures");
279
280 static u_long pmap_l2_promotions;
281 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
282 &pmap_l2_promotions, 0,
283 "2MB page promotions");
284
285 /*
286 * Data for the pv entry allocation mechanism
287 */
288 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
289 static struct mtx pv_chunks_mutex;
290 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
291 static struct md_page *pv_table;
292 static struct md_page pv_dummy;
293
294 extern cpuset_t all_harts;
295
296 /*
297 * Internal flags for pmap_enter()'s helper functions.
298 */
299 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
300 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
301
302 static void free_pv_chunk(struct pv_chunk *pc);
303 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
304 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
305 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
306 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
307 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
308 vm_offset_t va);
309 static bool pmap_demote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va);
310 static bool pmap_demote_l2_locked(pmap_t pmap, pd_entry_t *l2,
311 vm_offset_t va, struct rwlock **lockp);
312 static int pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2,
313 u_int flags, vm_page_t m, struct rwlock **lockp);
314 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
315 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
316 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
317 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
318 static bool pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
319 vm_page_t m, struct rwlock **lockp);
320
321 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
322 struct rwlock **lockp);
323
324 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
325 struct spglist *free);
326 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
327
328 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
329
330 #define pmap_clear(pte) pmap_store(pte, 0)
331 #define pmap_clear_bits(pte, bits) atomic_clear_64(pte, bits)
332 #define pmap_load_store(pte, entry) atomic_swap_64(pte, entry)
333 #define pmap_load_clear(pte) pmap_load_store(pte, 0)
334 #define pmap_load(pte) atomic_load_64(pte)
335 #define pmap_store(pte, entry) atomic_store_64(pte, entry)
336 #define pmap_store_bits(pte, bits) atomic_set_64(pte, bits)
337
338 /********************/
339 /* Inline functions */
340 /********************/
341
342 static __inline void
pagecopy(void * s,void * d)343 pagecopy(void *s, void *d)
344 {
345
346 memcpy(d, s, PAGE_SIZE);
347 }
348
349 static __inline void
pagezero(void * p)350 pagezero(void *p)
351 {
352
353 bzero(p, PAGE_SIZE);
354 }
355
356 #define pmap_l0_index(va) (((va) >> L0_SHIFT) & Ln_ADDR_MASK)
357 #define pmap_l1_index(va) (((va) >> L1_SHIFT) & Ln_ADDR_MASK)
358 #define pmap_l2_index(va) (((va) >> L2_SHIFT) & Ln_ADDR_MASK)
359 #define pmap_l3_index(va) (((va) >> L3_SHIFT) & Ln_ADDR_MASK)
360
361 #define PTE_TO_PHYS(pte) \
362 ((((pte) & ~PTE_HI_MASK) >> PTE_PPN0_S) * PAGE_SIZE)
363 #define L2PTE_TO_PHYS(l2) \
364 ((((l2) & ~PTE_HI_MASK) >> PTE_PPN1_S) << L2_SHIFT)
365 #define PTE_TO_VM_PAGE(pte) PHYS_TO_VM_PAGE(PTE_TO_PHYS(pte))
366
367 static __inline pd_entry_t *
pmap_l0(pmap_t pmap,vm_offset_t va)368 pmap_l0(pmap_t pmap, vm_offset_t va)
369 {
370 KASSERT(pmap_mode != PMAP_MODE_SV39, ("%s: in SV39 mode", __func__));
371 KASSERT(VIRT_IS_VALID(va),
372 ("%s: malformed virtual address %#lx", __func__, va));
373 return (&pmap->pm_top[pmap_l0_index(va)]);
374 }
375
376 static __inline pd_entry_t *
pmap_l0_to_l1(pd_entry_t * l0,vm_offset_t va)377 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
378 {
379 vm_paddr_t phys;
380 pd_entry_t *l1;
381
382 KASSERT(pmap_mode != PMAP_MODE_SV39, ("%s: in SV39 mode", __func__));
383 phys = PTE_TO_PHYS(pmap_load(l0));
384 l1 = (pd_entry_t *)PHYS_TO_DMAP(phys);
385
386 return (&l1[pmap_l1_index(va)]);
387 }
388
389 static __inline pd_entry_t *
pmap_l1(pmap_t pmap,vm_offset_t va)390 pmap_l1(pmap_t pmap, vm_offset_t va)
391 {
392 pd_entry_t *l0;
393
394 KASSERT(VIRT_IS_VALID(va),
395 ("%s: malformed virtual address %#lx", __func__, va));
396 if (pmap_mode == PMAP_MODE_SV39) {
397 return (&pmap->pm_top[pmap_l1_index(va)]);
398 } else {
399 l0 = pmap_l0(pmap, va);
400 if ((pmap_load(l0) & PTE_V) == 0)
401 return (NULL);
402 if ((pmap_load(l0) & PTE_RX) != 0)
403 return (NULL);
404 return (pmap_l0_to_l1(l0, va));
405 }
406 }
407
408 static __inline pd_entry_t *
pmap_l1_to_l2(pd_entry_t * l1,vm_offset_t va)409 pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va)
410 {
411 vm_paddr_t phys;
412 pd_entry_t *l2;
413
414 phys = PTE_TO_PHYS(pmap_load(l1));
415 l2 = (pd_entry_t *)PHYS_TO_DMAP(phys);
416
417 return (&l2[pmap_l2_index(va)]);
418 }
419
420 static __inline pd_entry_t *
pmap_l2(pmap_t pmap,vm_offset_t va)421 pmap_l2(pmap_t pmap, vm_offset_t va)
422 {
423 pd_entry_t *l1;
424
425 l1 = pmap_l1(pmap, va);
426 if (l1 == NULL)
427 return (NULL);
428 if ((pmap_load(l1) & PTE_V) == 0)
429 return (NULL);
430 if ((pmap_load(l1) & PTE_RX) != 0)
431 return (NULL);
432
433 return (pmap_l1_to_l2(l1, va));
434 }
435
436 static __inline pt_entry_t *
pmap_l2_to_l3(pd_entry_t * l2,vm_offset_t va)437 pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va)
438 {
439 vm_paddr_t phys;
440 pt_entry_t *l3;
441
442 phys = PTE_TO_PHYS(pmap_load(l2));
443 l3 = (pd_entry_t *)PHYS_TO_DMAP(phys);
444
445 return (&l3[pmap_l3_index(va)]);
446 }
447
448 static __inline pt_entry_t *
pmap_l3(pmap_t pmap,vm_offset_t va)449 pmap_l3(pmap_t pmap, vm_offset_t va)
450 {
451 pd_entry_t *l2;
452
453 l2 = pmap_l2(pmap, va);
454 if (l2 == NULL)
455 return (NULL);
456 if ((pmap_load(l2) & PTE_V) == 0)
457 return (NULL);
458 if ((pmap_load(l2) & PTE_RX) != 0)
459 return (NULL);
460
461 return (pmap_l2_to_l3(l2, va));
462 }
463
464 static __inline void
pmap_resident_count_inc(pmap_t pmap,int count)465 pmap_resident_count_inc(pmap_t pmap, int count)
466 {
467
468 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
469 pmap->pm_stats.resident_count += count;
470 }
471
472 static __inline void
pmap_resident_count_dec(pmap_t pmap,int count)473 pmap_resident_count_dec(pmap_t pmap, int count)
474 {
475
476 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
477 KASSERT(pmap->pm_stats.resident_count >= count,
478 ("pmap %p resident count underflow %ld %d", pmap,
479 pmap->pm_stats.resident_count, count));
480 pmap->pm_stats.resident_count -= count;
481 }
482
483 static void
pmap_distribute_l1(struct pmap * pmap,vm_pindex_t l1index,pt_entry_t entry)484 pmap_distribute_l1(struct pmap *pmap, vm_pindex_t l1index,
485 pt_entry_t entry)
486 {
487 struct pmap *user_pmap;
488 pd_entry_t *l1;
489
490 /*
491 * Distribute new kernel L1 entry to all the user pmaps. This is only
492 * necessary with three-level paging configured: with four-level paging
493 * the kernel's half of the top-level page table page is static and can
494 * simply be copied at pmap initialization time.
495 */
496 if (pmap != kernel_pmap || pmap_mode != PMAP_MODE_SV39)
497 return;
498
499 mtx_lock(&allpmaps_lock);
500 LIST_FOREACH(user_pmap, &allpmaps, pm_list) {
501 l1 = &user_pmap->pm_top[l1index];
502 pmap_store(l1, entry);
503 }
504 mtx_unlock(&allpmaps_lock);
505 }
506
507 static pt_entry_t *
pmap_early_page_idx(vm_offset_t l1pt,vm_offset_t va,u_int * l1_slot,u_int * l2_slot)508 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
509 u_int *l2_slot)
510 {
511 pt_entry_t *l2;
512 pd_entry_t *l1 __diagused;
513
514 l1 = (pd_entry_t *)l1pt;
515 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
516
517 /* Check locore has used a table L1 map */
518 KASSERT((l1[*l1_slot] & PTE_RX) == 0,
519 ("Invalid bootstrap L1 table"));
520
521 /* Find the address of the L2 table */
522 l2 = (pt_entry_t *)init_pt_va;
523 *l2_slot = pmap_l2_index(va);
524
525 return (l2);
526 }
527
528 static vm_paddr_t
pmap_early_vtophys(vm_offset_t l1pt,vm_offset_t va)529 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
530 {
531 u_int l1_slot, l2_slot;
532 pt_entry_t *l2;
533 vm_paddr_t ret;
534
535 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
536
537 /* Check locore has used L2 superpages */
538 KASSERT((l2[l2_slot] & PTE_RX) != 0,
539 ("Invalid bootstrap L2 table"));
540
541 /* L2 is superpages */
542 ret = L2PTE_TO_PHYS(l2[l2_slot]);
543 ret += (va & L2_OFFSET);
544
545 return (ret);
546 }
547
548 static void
pmap_bootstrap_dmap(vm_offset_t kern_l1,vm_paddr_t min_pa,vm_paddr_t max_pa)549 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa, vm_paddr_t max_pa)
550 {
551 vm_offset_t va;
552 vm_paddr_t pa;
553 pd_entry_t *l1;
554 u_int l1_slot;
555 pt_entry_t entry;
556 pn_t pn;
557
558 pa = dmap_phys_base = min_pa & ~L1_OFFSET;
559 va = DMAP_MIN_ADDRESS;
560 l1 = (pd_entry_t *)kern_l1;
561 l1_slot = pmap_l1_index(DMAP_MIN_ADDRESS);
562
563 for (; va < DMAP_MAX_ADDRESS && pa < max_pa;
564 pa += L1_SIZE, va += L1_SIZE, l1_slot++) {
565 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
566
567 /* superpages */
568 pn = (pa / PAGE_SIZE);
569 entry = PTE_KERN;
570 entry |= (pn << PTE_PPN0_S);
571 pmap_store(&l1[l1_slot], entry);
572 }
573
574 /* Set the upper limit of the DMAP region */
575 dmap_phys_max = pa;
576 dmap_max_addr = va;
577
578 sfence_vma();
579 }
580
581 static vm_offset_t
pmap_bootstrap_l3(vm_offset_t l1pt,vm_offset_t va,vm_offset_t l3_start)582 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
583 {
584 vm_offset_t l3pt;
585 pt_entry_t entry;
586 pd_entry_t *l2;
587 vm_paddr_t pa;
588 u_int l2_slot;
589 pn_t pn;
590
591 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
592
593 l2 = pmap_l2(kernel_pmap, va);
594 l2 = (pd_entry_t *)((uintptr_t)l2 & ~(PAGE_SIZE - 1));
595 l2_slot = pmap_l2_index(va);
596 l3pt = l3_start;
597
598 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
599 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
600
601 pa = pmap_early_vtophys(l1pt, l3pt);
602 pn = (pa / PAGE_SIZE);
603 entry = (PTE_V);
604 entry |= (pn << PTE_PPN0_S);
605 pmap_store(&l2[l2_slot], entry);
606 l3pt += PAGE_SIZE;
607 }
608
609 /* Clean the L2 page table */
610 memset((void *)l3_start, 0, l3pt - l3_start);
611
612 return (l3pt);
613 }
614
615 /*
616 * Bootstrap the system enough to run with virtual memory.
617 */
618 void
pmap_bootstrap(vm_offset_t l1pt,vm_paddr_t kernstart,vm_size_t kernlen)619 pmap_bootstrap(vm_offset_t l1pt, vm_paddr_t kernstart, vm_size_t kernlen)
620 {
621 vm_paddr_t physmap[PHYS_AVAIL_ENTRIES];
622 uint64_t satp;
623 vm_offset_t dpcpu, freemempos, l0pv, msgbufpv;
624 vm_paddr_t l0pa, l1pa, max_pa, min_pa, pa;
625 pd_entry_t *l0p;
626 pt_entry_t *l2p;
627 u_int l1_slot, l2_slot;
628 u_int physmap_idx;
629 int i, mode;
630
631 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
632
633 /* Set this early so we can use the pagetable walking functions */
634 kernel_pmap_store.pm_top = (pd_entry_t *)l1pt;
635 kernel_pmap_store.pm_stage = PM_STAGE1;
636 PMAP_LOCK_INIT(kernel_pmap);
637 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
638 vm_radix_init(&kernel_pmap->pm_root);
639
640 rw_init(&pvh_global_lock, "pmap pv global");
641
642 /*
643 * Set the current CPU as active in the kernel pmap. Secondary cores
644 * will add themselves later in init_secondary(). The SBI firmware
645 * may rely on this mask being precise, so CPU_FILL() is not used.
646 */
647 CPU_SET(PCPU_GET(hart), &kernel_pmap->pm_active);
648
649 /* Assume the address we were loaded to is a valid physical address. */
650 min_pa = max_pa = kernstart;
651
652 physmap_idx = physmem_avail(physmap, nitems(physmap));
653 physmap_idx /= 2;
654
655 /*
656 * Find the minimum physical address. physmap is sorted,
657 * but may contain empty ranges.
658 */
659 for (i = 0; i < physmap_idx * 2; i += 2) {
660 if (physmap[i] == physmap[i + 1])
661 continue;
662 if (physmap[i] <= min_pa)
663 min_pa = physmap[i];
664 if (physmap[i + 1] > max_pa)
665 max_pa = physmap[i + 1];
666 }
667 printf("physmap_idx %u\n", physmap_idx);
668 printf("min_pa %lx\n", min_pa);
669 printf("max_pa %lx\n", max_pa);
670
671 /* Create a direct map region early so we can use it for pa -> va */
672 pmap_bootstrap_dmap(l1pt, min_pa, max_pa);
673
674 /*
675 * Read the page table to find out what is already mapped.
676 * This assumes we have mapped a block of memory from KERNBASE
677 * using a single L1 entry.
678 */
679 (void)pmap_early_page_idx(l1pt, KERNBASE, &l1_slot, &l2_slot);
680
681 /* Sanity check the index, KERNBASE should be the first VA */
682 KASSERT(l2_slot == 0, ("The L2 index is non-zero"));
683
684 freemempos = roundup2(KERNBASE + kernlen, PAGE_SIZE);
685
686 /* Create the l3 tables for the early devmap */
687 freemempos = pmap_bootstrap_l3(l1pt,
688 VM_MAX_KERNEL_ADDRESS - PMAP_MAPDEV_EARLY_SIZE, freemempos);
689
690 /*
691 * Invalidate the mapping we created for the DTB. At this point a copy
692 * has been created, and we no longer need it. We want to avoid the
693 * possibility of an aliased mapping in the future.
694 */
695 l2p = pmap_l2(kernel_pmap, VM_EARLY_DTB_ADDRESS);
696 if ((pmap_load(l2p) & PTE_V) != 0)
697 pmap_clear(l2p);
698
699 sfence_vma();
700
701 #define alloc_pages(var, np) \
702 (var) = freemempos; \
703 freemempos += (np * PAGE_SIZE); \
704 memset((char *)(var), 0, ((np) * PAGE_SIZE));
705
706 mode = 0;
707 TUNABLE_INT_FETCH("vm.pmap.mode", &mode);
708 if (mode == PMAP_MODE_SV48 && (mmu_caps & MMU_SV48) != 0) {
709 /*
710 * Enable SV48 mode: allocate an L0 page and set SV48 mode in
711 * SATP. If the implementation does not provide SV48 mode,
712 * the mode read back from the (WARL) SATP register will be
713 * unchanged, and we continue in SV39 mode.
714 */
715 alloc_pages(l0pv, 1);
716 l0p = (void *)l0pv;
717 l1pa = pmap_early_vtophys(l1pt, l1pt);
718 l0p[pmap_l0_index(KERNBASE)] = PTE_V |
719 ((l1pa >> PAGE_SHIFT) << PTE_PPN0_S);
720
721 l0pa = pmap_early_vtophys(l1pt, l0pv);
722 csr_write(satp, (l0pa >> PAGE_SHIFT) | SATP_MODE_SV48);
723 satp = csr_read(satp);
724 if ((satp & SATP_MODE_M) == SATP_MODE_SV48) {
725 pmap_mode = PMAP_MODE_SV48;
726 kernel_pmap_store.pm_top = l0p;
727 } else {
728 /* Mode didn't change, give the page back. */
729 freemempos -= PAGE_SIZE;
730 }
731 }
732
733 /* Allocate dynamic per-cpu area. */
734 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
735 dpcpu_init((void *)dpcpu, 0);
736
737 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
738 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
739 msgbufp = (void *)msgbufpv;
740
741 virtual_avail = roundup2(freemempos, L2_SIZE);
742 virtual_end = VM_MAX_KERNEL_ADDRESS - PMAP_MAPDEV_EARLY_SIZE;
743 kernel_vm_end = virtual_avail;
744
745 pa = pmap_early_vtophys(l1pt, freemempos);
746
747 physmem_exclude_region(kernstart, pa - kernstart, EXFLAG_NOALLOC);
748 }
749
750 /*
751 * Initialize a vm_page's machine-dependent fields.
752 */
753 void
pmap_page_init(vm_page_t m)754 pmap_page_init(vm_page_t m)
755 {
756
757 TAILQ_INIT(&m->md.pv_list);
758 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
759 }
760
761 /*
762 * Initialize the pmap module.
763 *
764 * Called by vm_mem_init(), to initialize any structures that the pmap
765 * system needs to map virtual memory.
766 */
767 void
pmap_init(void)768 pmap_init(void)
769 {
770 vm_size_t s;
771 int i, pv_npg;
772
773 /*
774 * Initialize the pv chunk and pmap list mutexes.
775 */
776 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
777 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_DEF);
778
779 /*
780 * Initialize the pool of pv list locks.
781 */
782 for (i = 0; i < NPV_LIST_LOCKS; i++)
783 rw_init(&pv_list_locks[i], "pmap pv list");
784
785 /*
786 * Calculate the size of the pv head table for superpages.
787 */
788 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, L2_SIZE);
789
790 /*
791 * Allocate memory for the pv head table for superpages.
792 */
793 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
794 s = round_page(s);
795 pv_table = kmem_malloc(s, M_WAITOK | M_ZERO);
796 for (i = 0; i < pv_npg; i++)
797 TAILQ_INIT(&pv_table[i].pv_list);
798 TAILQ_INIT(&pv_dummy.pv_list);
799
800 if (superpages_enabled)
801 pagesizes[1] = L2_SIZE;
802 }
803
804 #ifdef SMP
805 /*
806 * For SMP, these functions have to use IPIs for coherence.
807 *
808 * In general, the calling thread uses a plain fence to order the
809 * writes to the page tables before invoking an SBI callback to invoke
810 * sfence_vma() on remote CPUs.
811 */
812 static void
pmap_invalidate_page(pmap_t pmap,vm_offset_t va)813 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
814 {
815 cpuset_t mask;
816
817 sched_pin();
818 mask = pmap->pm_active;
819 CPU_CLR(PCPU_GET(hart), &mask);
820 fence();
821 if (!CPU_EMPTY(&mask) && smp_started)
822 sbi_remote_sfence_vma(mask.__bits, va, 1);
823 sfence_vma_page(va);
824 sched_unpin();
825 }
826
827 static void
pmap_invalidate_range(pmap_t pmap,vm_offset_t sva,vm_offset_t eva)828 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
829 {
830 cpuset_t mask;
831
832 sched_pin();
833 mask = pmap->pm_active;
834 CPU_CLR(PCPU_GET(hart), &mask);
835 fence();
836 if (!CPU_EMPTY(&mask) && smp_started)
837 sbi_remote_sfence_vma(mask.__bits, sva, eva - sva + 1);
838
839 /*
840 * Might consider a loop of sfence_vma_page() for a small
841 * number of pages in the future.
842 */
843 sfence_vma();
844 sched_unpin();
845 }
846
847 static void
pmap_invalidate_all(pmap_t pmap)848 pmap_invalidate_all(pmap_t pmap)
849 {
850 cpuset_t mask;
851
852 sched_pin();
853 mask = pmap->pm_active;
854 CPU_CLR(PCPU_GET(hart), &mask);
855
856 /*
857 * XXX: The SBI doc doesn't detail how to specify x0 as the
858 * address to perform a global fence. BBL currently treats
859 * all sfence_vma requests as global however.
860 */
861 fence();
862 if (!CPU_EMPTY(&mask) && smp_started)
863 sbi_remote_sfence_vma(mask.__bits, 0, 0);
864 sfence_vma();
865 sched_unpin();
866 }
867 #else
868 /*
869 * Normal, non-SMP, invalidation functions.
870 * We inline these within pmap.c for speed.
871 */
872 static __inline void
pmap_invalidate_page(pmap_t pmap,vm_offset_t va)873 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
874 {
875
876 sfence_vma_page(va);
877 }
878
879 static __inline void
pmap_invalidate_range(pmap_t pmap,vm_offset_t sva,vm_offset_t eva)880 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
881 {
882
883 /*
884 * Might consider a loop of sfence_vma_page() for a small
885 * number of pages in the future.
886 */
887 sfence_vma();
888 }
889
890 static __inline void
pmap_invalidate_all(pmap_t pmap)891 pmap_invalidate_all(pmap_t pmap)
892 {
893
894 sfence_vma();
895 }
896 #endif
897
898 /*
899 * Routine: pmap_extract
900 * Function:
901 * Extract the physical page address associated
902 * with the given map/virtual_address pair.
903 */
904 vm_paddr_t
pmap_extract(pmap_t pmap,vm_offset_t va)905 pmap_extract(pmap_t pmap, vm_offset_t va)
906 {
907 pd_entry_t *l2p, l2;
908 pt_entry_t *l3p;
909 vm_paddr_t pa;
910
911 pa = 0;
912
913 /*
914 * Start with an L2 lookup, L1 superpages are currently not implemented.
915 */
916 PMAP_LOCK(pmap);
917 l2p = pmap_l2(pmap, va);
918 if (l2p != NULL && ((l2 = pmap_load(l2p)) & PTE_V) != 0) {
919 if ((l2 & PTE_RWX) == 0) {
920 l3p = pmap_l2_to_l3(l2p, va);
921 if (l3p != NULL) {
922 pa = PTE_TO_PHYS(pmap_load(l3p));
923 pa |= (va & L3_OFFSET);
924 }
925 } else {
926 /* L2 is a superpage mapping. */
927 pa = L2PTE_TO_PHYS(l2);
928 pa |= (va & L2_OFFSET);
929 }
930 }
931 PMAP_UNLOCK(pmap);
932 return (pa);
933 }
934
935 /*
936 * Routine: pmap_extract_and_hold
937 * Function:
938 * Atomically extract and hold the physical page
939 * with the given pmap and virtual address pair
940 * if that mapping permits the given protection.
941 */
942 vm_page_t
pmap_extract_and_hold(pmap_t pmap,vm_offset_t va,vm_prot_t prot)943 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
944 {
945 pt_entry_t *l3p, l3;
946 vm_page_t m;
947
948 m = NULL;
949 PMAP_LOCK(pmap);
950 l3p = pmap_l3(pmap, va);
951 if (l3p != NULL && (l3 = pmap_load(l3p)) != 0) {
952 if ((l3 & PTE_W) != 0 || (prot & VM_PROT_WRITE) == 0) {
953 m = PTE_TO_VM_PAGE(l3);
954 if (!vm_page_wire_mapped(m))
955 m = NULL;
956 }
957 }
958 PMAP_UNLOCK(pmap);
959 return (m);
960 }
961
962 /*
963 * Routine: pmap_kextract
964 * Function:
965 * Extract the physical page address associated with the given kernel
966 * virtual address.
967 */
968 vm_paddr_t
pmap_kextract(vm_offset_t va)969 pmap_kextract(vm_offset_t va)
970 {
971 pd_entry_t *l2, l2e;
972 pt_entry_t *l3;
973 vm_paddr_t pa;
974
975 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
976 pa = DMAP_TO_PHYS(va);
977 } else {
978 l2 = pmap_l2(kernel_pmap, va);
979 if (l2 == NULL)
980 panic("pmap_kextract: No l2");
981 l2e = pmap_load(l2);
982 /*
983 * Beware of concurrent promotion and demotion! We must
984 * use l2e rather than loading from l2 multiple times to
985 * ensure we see a consistent state, including the
986 * implicit load in pmap_l2_to_l3. It is, however, safe
987 * to use an old l2e because the L3 page is preserved by
988 * promotion.
989 */
990 if ((l2e & PTE_RX) != 0) {
991 /* superpages */
992 pa = L2PTE_TO_PHYS(l2e);
993 pa |= (va & L2_OFFSET);
994 return (pa);
995 }
996
997 l3 = pmap_l2_to_l3(&l2e, va);
998 if (l3 == NULL)
999 panic("pmap_kextract: No l3...");
1000 pa = PTE_TO_PHYS(pmap_load(l3));
1001 pa |= (va & PAGE_MASK);
1002 }
1003 return (pa);
1004 }
1005
1006 /***************************************************
1007 * Low level mapping routines.....
1008 ***************************************************/
1009
1010 void
pmap_kenter(vm_offset_t sva,vm_size_t size,vm_paddr_t pa,int mode __unused)1011 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode __unused)
1012 {
1013 pt_entry_t entry;
1014 pt_entry_t *l3;
1015 vm_offset_t va;
1016 pn_t pn;
1017
1018 KASSERT((pa & L3_OFFSET) == 0,
1019 ("pmap_kenter_device: Invalid physical address"));
1020 KASSERT((sva & L3_OFFSET) == 0,
1021 ("pmap_kenter_device: Invalid virtual address"));
1022 KASSERT((size & PAGE_MASK) == 0,
1023 ("pmap_kenter_device: Mapping is not page-sized"));
1024
1025 va = sva;
1026 while (size != 0) {
1027 l3 = pmap_l3(kernel_pmap, va);
1028 KASSERT(l3 != NULL, ("Invalid page table, va: 0x%lx", va));
1029
1030 pn = (pa / PAGE_SIZE);
1031 entry = PTE_KERN;
1032 entry |= (pn << PTE_PPN0_S);
1033 pmap_store(l3, entry);
1034
1035 va += PAGE_SIZE;
1036 pa += PAGE_SIZE;
1037 size -= PAGE_SIZE;
1038 }
1039 pmap_invalidate_range(kernel_pmap, sva, va);
1040 }
1041
1042 void
pmap_kenter_device(vm_offset_t sva,vm_size_t size,vm_paddr_t pa)1043 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1044 {
1045 pmap_kenter(sva, size, pa, VM_MEMATTR_DEVICE);
1046 }
1047
1048 /*
1049 * Remove a page from the kernel pagetables.
1050 * Note: not SMP coherent.
1051 */
1052 void
pmap_kremove(vm_offset_t va)1053 pmap_kremove(vm_offset_t va)
1054 {
1055 pt_entry_t *l3;
1056
1057 l3 = pmap_l3(kernel_pmap, va);
1058 KASSERT(l3 != NULL, ("pmap_kremove: Invalid address"));
1059
1060 pmap_clear(l3);
1061 sfence_vma();
1062 }
1063
1064 void
pmap_kremove_device(vm_offset_t sva,vm_size_t size)1065 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1066 {
1067 pt_entry_t *l3;
1068 vm_offset_t va;
1069
1070 KASSERT((sva & L3_OFFSET) == 0,
1071 ("pmap_kremove_device: Invalid virtual address"));
1072 KASSERT((size & PAGE_MASK) == 0,
1073 ("pmap_kremove_device: Mapping is not page-sized"));
1074
1075 va = sva;
1076 while (size != 0) {
1077 l3 = pmap_l3(kernel_pmap, va);
1078 KASSERT(l3 != NULL, ("Invalid page table, va: 0x%lx", va));
1079 pmap_clear(l3);
1080
1081 va += PAGE_SIZE;
1082 size -= PAGE_SIZE;
1083 }
1084
1085 pmap_invalidate_range(kernel_pmap, sva, va);
1086 }
1087
1088 /*
1089 * Used to map a range of physical addresses into kernel
1090 * virtual address space.
1091 *
1092 * The value passed in '*virt' is a suggested virtual address for
1093 * the mapping. Architectures which can support a direct-mapped
1094 * physical to virtual region can return the appropriate address
1095 * within that region, leaving '*virt' unchanged. Other
1096 * architectures should map the pages starting at '*virt' and
1097 * update '*virt' with the first usable address after the mapped
1098 * region.
1099 */
1100 vm_offset_t
pmap_map(vm_offset_t * virt,vm_paddr_t start,vm_paddr_t end,int prot)1101 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1102 {
1103
1104 return PHYS_TO_DMAP(start);
1105 }
1106
1107 /*
1108 * Add a list of wired pages to the kva
1109 * this routine is only used for temporary
1110 * kernel mappings that do not need to have
1111 * page modification or references recorded.
1112 * Note that old mappings are simply written
1113 * over. The page *must* be wired.
1114 * Note: SMP coherent. Uses a ranged shootdown IPI.
1115 */
1116 void
pmap_qenter(vm_offset_t sva,vm_page_t * ma,int count)1117 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1118 {
1119 pt_entry_t *l3, pa;
1120 vm_offset_t va;
1121 vm_page_t m;
1122 pt_entry_t entry;
1123 pn_t pn;
1124 int i;
1125
1126 va = sva;
1127 for (i = 0; i < count; i++) {
1128 m = ma[i];
1129 pa = VM_PAGE_TO_PHYS(m);
1130 pn = (pa / PAGE_SIZE);
1131 l3 = pmap_l3(kernel_pmap, va);
1132
1133 entry = PTE_KERN;
1134 entry |= (pn << PTE_PPN0_S);
1135 pmap_store(l3, entry);
1136
1137 va += L3_SIZE;
1138 }
1139 pmap_invalidate_range(kernel_pmap, sva, va);
1140 }
1141
1142 /*
1143 * This routine tears out page mappings from the
1144 * kernel -- it is meant only for temporary mappings.
1145 * Note: SMP coherent. Uses a ranged shootdown IPI.
1146 */
1147 void
pmap_qremove(vm_offset_t sva,int count)1148 pmap_qremove(vm_offset_t sva, int count)
1149 {
1150 pt_entry_t *l3;
1151 vm_offset_t va;
1152
1153 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1154
1155 for (va = sva; count-- > 0; va += PAGE_SIZE) {
1156 l3 = pmap_l3(kernel_pmap, va);
1157 KASSERT(l3 != NULL, ("pmap_kremove: Invalid address"));
1158 pmap_clear(l3);
1159 }
1160 pmap_invalidate_range(kernel_pmap, sva, va);
1161 }
1162
1163 bool
pmap_ps_enabled(pmap_t pmap __unused)1164 pmap_ps_enabled(pmap_t pmap __unused)
1165 {
1166
1167 return (superpages_enabled);
1168 }
1169
1170 /***************************************************
1171 * Page table page management routines.....
1172 ***************************************************/
1173 /*
1174 * Schedule the specified unused page table page to be freed. Specifically,
1175 * add the page to the specified list of pages that will be released to the
1176 * physical memory manager after the TLB has been updated.
1177 */
1178 static __inline void
pmap_add_delayed_free_list(vm_page_t m,struct spglist * free,bool set_PG_ZERO)1179 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free, bool set_PG_ZERO)
1180 {
1181
1182 if (set_PG_ZERO)
1183 m->flags |= PG_ZERO;
1184 else
1185 m->flags &= ~PG_ZERO;
1186 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1187 }
1188
1189 /*
1190 * Inserts the specified page table page into the specified pmap's collection
1191 * of idle page table pages. Each of a pmap's page table pages is responsible
1192 * for mapping a distinct range of virtual addresses. The pmap's collection is
1193 * ordered by this virtual address range.
1194 *
1195 * If "promoted" is false, then the page table page "mpte" must be zero filled;
1196 * "mpte"'s valid field will be set to 0.
1197 *
1198 * If "promoted" is true and "all_l3e_PTE_A_set" is false, then "mpte" must
1199 * contain valid mappings with identical attributes except for PTE_A;
1200 * "mpte"'s valid field will be set to 1.
1201 *
1202 * If "promoted" and "all_l3e_PTE_A_set" are both true, then "mpte" must contain
1203 * valid mappings with identical attributes including PTE_A; "mpte"'s valid
1204 * field will be set to VM_PAGE_BITS_ALL.
1205 */
1206 static __inline int
pmap_insert_pt_page(pmap_t pmap,vm_page_t mpte,bool promoted,bool all_l3e_PTE_A_set)1207 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted,
1208 bool all_l3e_PTE_A_set)
1209 {
1210
1211 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1212 KASSERT(promoted || !all_l3e_PTE_A_set,
1213 ("a zero-filled PTP can't have PTE_A set in every PTE"));
1214 mpte->valid = promoted ? (all_l3e_PTE_A_set ? VM_PAGE_BITS_ALL : 1) : 0;
1215 return (vm_radix_insert(&pmap->pm_root, mpte));
1216 }
1217
1218 /*
1219 * Removes the page table page mapping the specified virtual address from the
1220 * specified pmap's collection of idle page table pages, and returns it.
1221 * Otherwise, returns NULL if there is no page table page corresponding to the
1222 * specified virtual address.
1223 */
1224 static __inline vm_page_t
pmap_remove_pt_page(pmap_t pmap,vm_offset_t va)1225 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
1226 {
1227
1228 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1229 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
1230 }
1231
1232 /*
1233 * Decrements a page table page's reference count, which is used to record the
1234 * number of valid page table entries within the page. If the reference count
1235 * drops to zero, then the page table page is unmapped. Returns true if the
1236 * page table page was unmapped and false otherwise.
1237 */
1238 static inline bool
pmap_unwire_ptp(pmap_t pmap,vm_offset_t va,vm_page_t m,struct spglist * free)1239 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1240 {
1241 KASSERT(m->ref_count > 0,
1242 ("%s: page %p ref count underflow", __func__, m));
1243
1244 --m->ref_count;
1245 if (m->ref_count == 0) {
1246 _pmap_unwire_ptp(pmap, va, m, free);
1247 return (true);
1248 } else {
1249 return (false);
1250 }
1251 }
1252
1253 static void
_pmap_unwire_ptp(pmap_t pmap,vm_offset_t va,vm_page_t m,struct spglist * free)1254 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1255 {
1256
1257 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1258 if (m->pindex >= NUL2E + NUL1E) {
1259 pd_entry_t *l0;
1260 l0 = pmap_l0(pmap, va);
1261 pmap_clear(l0);
1262 } else if (m->pindex >= NUL2E) {
1263 pd_entry_t *l1;
1264 l1 = pmap_l1(pmap, va);
1265 pmap_clear(l1);
1266 pmap_distribute_l1(pmap, pmap_l1_index(va), 0);
1267 } else {
1268 pd_entry_t *l2;
1269 l2 = pmap_l2(pmap, va);
1270 pmap_clear(l2);
1271 }
1272 pmap_resident_count_dec(pmap, 1);
1273 if (m->pindex < NUL2E) {
1274 pd_entry_t *l1;
1275 vm_page_t pdpg;
1276
1277 l1 = pmap_l1(pmap, va);
1278 pdpg = PTE_TO_VM_PAGE(pmap_load(l1));
1279 pmap_unwire_ptp(pmap, va, pdpg, free);
1280 } else if (m->pindex < NUL2E + NUL1E && pmap_mode != PMAP_MODE_SV39) {
1281 pd_entry_t *l0;
1282 vm_page_t pdpg;
1283
1284 MPASS(pmap_mode != PMAP_MODE_SV39);
1285 l0 = pmap_l0(pmap, va);
1286 pdpg = PTE_TO_VM_PAGE(pmap_load(l0));
1287 pmap_unwire_ptp(pmap, va, pdpg, free);
1288 }
1289 pmap_invalidate_page(pmap, va);
1290
1291 vm_wire_sub(1);
1292
1293 /*
1294 * Put page on a list so that it is released after
1295 * *ALL* TLB shootdown is done
1296 */
1297 pmap_add_delayed_free_list(m, free, true);
1298 }
1299
1300 /*
1301 * After removing a page table entry, this routine is used to
1302 * conditionally free the page, and manage the reference count.
1303 */
1304 static int
pmap_unuse_pt(pmap_t pmap,vm_offset_t va,pd_entry_t ptepde,struct spglist * free)1305 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1306 struct spglist *free)
1307 {
1308 vm_page_t mpte;
1309
1310 if (va >= VM_MAXUSER_ADDRESS)
1311 return (0);
1312 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1313 mpte = PTE_TO_VM_PAGE(ptepde);
1314 return (pmap_unwire_ptp(pmap, va, mpte, free));
1315 }
1316
1317 static uint64_t
pmap_satp_mode(void)1318 pmap_satp_mode(void)
1319 {
1320 return (pmap_mode == PMAP_MODE_SV39 ? SATP_MODE_SV39 : SATP_MODE_SV48);
1321 }
1322
1323 void
pmap_pinit0(pmap_t pmap)1324 pmap_pinit0(pmap_t pmap)
1325 {
1326 PMAP_LOCK_INIT(pmap);
1327 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1328 pmap->pm_stage = PM_STAGE1;
1329 pmap->pm_top = kernel_pmap->pm_top;
1330 pmap->pm_satp = pmap_satp_mode() |
1331 (vtophys(pmap->pm_top) >> PAGE_SHIFT);
1332 CPU_ZERO(&pmap->pm_active);
1333 TAILQ_INIT(&pmap->pm_pvchunk);
1334 vm_radix_init(&pmap->pm_root);
1335 pmap_activate_boot(pmap);
1336 }
1337
1338 int
pmap_pinit_stage(pmap_t pmap,enum pmap_stage stage)1339 pmap_pinit_stage(pmap_t pmap, enum pmap_stage stage)
1340 {
1341 vm_paddr_t topphys;
1342 vm_page_t m;
1343 size_t i;
1344
1345 /*
1346 * Top directory is 4 pages in hypervisor case.
1347 * Current address space layout makes 3 of them unused.
1348 */
1349 if (stage == PM_STAGE1)
1350 m = vm_page_alloc_noobj(VM_ALLOC_WIRED | VM_ALLOC_ZERO |
1351 VM_ALLOC_WAITOK);
1352 else
1353 m = vm_page_alloc_noobj_contig(VM_ALLOC_WIRED | VM_ALLOC_ZERO,
1354 4, 0, ~0ul, L2_SIZE, 0, VM_MEMATTR_DEFAULT);
1355
1356 topphys = VM_PAGE_TO_PHYS(m);
1357 pmap->pm_top = (pd_entry_t *)PHYS_TO_DMAP(topphys);
1358 pmap->pm_satp = pmap_satp_mode() | (topphys >> PAGE_SHIFT);
1359 pmap->pm_stage = stage;
1360
1361 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1362
1363 CPU_ZERO(&pmap->pm_active);
1364
1365 if (stage == PM_STAGE2)
1366 goto finish;
1367
1368 if (pmap_mode == PMAP_MODE_SV39) {
1369 /*
1370 * Copy L1 entries from the kernel pmap. This must be done with
1371 * the allpmaps lock held to avoid races with
1372 * pmap_distribute_l1().
1373 */
1374 mtx_lock(&allpmaps_lock);
1375 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
1376 for (i = pmap_l1_index(VM_MIN_KERNEL_ADDRESS);
1377 i < pmap_l1_index(VM_MAX_KERNEL_ADDRESS); i++)
1378 pmap->pm_top[i] = kernel_pmap->pm_top[i];
1379 for (i = pmap_l1_index(DMAP_MIN_ADDRESS);
1380 i < pmap_l1_index(DMAP_MAX_ADDRESS); i++)
1381 pmap->pm_top[i] = kernel_pmap->pm_top[i];
1382 mtx_unlock(&allpmaps_lock);
1383 } else {
1384 i = pmap_l0_index(VM_MIN_KERNEL_ADDRESS);
1385 pmap->pm_top[i] = kernel_pmap->pm_top[i];
1386 }
1387
1388 finish:
1389 TAILQ_INIT(&pmap->pm_pvchunk);
1390 vm_radix_init(&pmap->pm_root);
1391
1392 return (1);
1393 }
1394
1395 int
pmap_pinit(pmap_t pmap)1396 pmap_pinit(pmap_t pmap)
1397 {
1398
1399 return (pmap_pinit_stage(pmap, PM_STAGE1));
1400 }
1401
1402 /*
1403 * This routine is called if the desired page table page does not exist.
1404 *
1405 * If page table page allocation fails, this routine may sleep before
1406 * returning NULL. It sleeps only if a lock pointer was given.
1407 *
1408 * Note: If a page allocation fails at page table level two or three,
1409 * one or two pages may be held during the wait, only to be released
1410 * afterwards. This conservative approach is easily argued to avoid
1411 * race conditions.
1412 */
1413 static vm_page_t
_pmap_alloc_l3(pmap_t pmap,vm_pindex_t ptepindex,struct rwlock ** lockp)1414 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1415 {
1416 vm_page_t m, pdpg;
1417 pt_entry_t entry;
1418 vm_paddr_t phys;
1419 pn_t pn;
1420
1421 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1422
1423 /*
1424 * Allocate a page table page.
1425 */
1426 m = vm_page_alloc_noobj(VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1427 if (m == NULL) {
1428 if (lockp != NULL) {
1429 RELEASE_PV_LIST_LOCK(lockp);
1430 PMAP_UNLOCK(pmap);
1431 rw_runlock(&pvh_global_lock);
1432 vm_wait(NULL);
1433 rw_rlock(&pvh_global_lock);
1434 PMAP_LOCK(pmap);
1435 }
1436
1437 /*
1438 * Indicate the need to retry. While waiting, the page table
1439 * page may have been allocated.
1440 */
1441 return (NULL);
1442 }
1443 m->pindex = ptepindex;
1444
1445 /*
1446 * Map the pagetable page into the process address space, if
1447 * it isn't already there.
1448 */
1449 pn = VM_PAGE_TO_PHYS(m) >> PAGE_SHIFT;
1450 if (ptepindex >= NUL2E + NUL1E) {
1451 pd_entry_t *l0;
1452 vm_pindex_t l0index;
1453
1454 KASSERT(pmap_mode != PMAP_MODE_SV39,
1455 ("%s: pindex %#lx in SV39 mode", __func__, ptepindex));
1456 KASSERT(ptepindex < NUL2E + NUL1E + NUL0E,
1457 ("%s: pindex %#lx out of range", __func__, ptepindex));
1458
1459 l0index = ptepindex - (NUL2E + NUL1E);
1460 l0 = &pmap->pm_top[l0index];
1461 KASSERT((pmap_load(l0) & PTE_V) == 0,
1462 ("%s: L0 entry %#lx is valid", __func__, pmap_load(l0)));
1463
1464 entry = PTE_V | (pn << PTE_PPN0_S);
1465 pmap_store(l0, entry);
1466 } else if (ptepindex >= NUL2E) {
1467 pd_entry_t *l0, *l1;
1468 vm_pindex_t l0index, l1index;
1469
1470 l1index = ptepindex - NUL2E;
1471 if (pmap_mode == PMAP_MODE_SV39) {
1472 l1 = &pmap->pm_top[l1index];
1473 } else {
1474 l0index = l1index >> Ln_ENTRIES_SHIFT;
1475 l0 = &pmap->pm_top[l0index];
1476 if (pmap_load(l0) == 0) {
1477 /* Recurse to allocate the L1 page. */
1478 if (_pmap_alloc_l3(pmap,
1479 NUL2E + NUL1E + l0index, lockp) == NULL)
1480 goto fail;
1481 phys = PTE_TO_PHYS(pmap_load(l0));
1482 } else {
1483 phys = PTE_TO_PHYS(pmap_load(l0));
1484 pdpg = PHYS_TO_VM_PAGE(phys);
1485 pdpg->ref_count++;
1486 }
1487 l1 = (pd_entry_t *)PHYS_TO_DMAP(phys);
1488 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1489 }
1490 KASSERT((pmap_load(l1) & PTE_V) == 0,
1491 ("%s: L1 entry %#lx is valid", __func__, pmap_load(l1)));
1492
1493 entry = PTE_V | (pn << PTE_PPN0_S);
1494 pmap_store(l1, entry);
1495 pmap_distribute_l1(pmap, l1index, entry);
1496 } else {
1497 vm_pindex_t l0index, l1index;
1498 pd_entry_t *l0, *l1, *l2;
1499
1500 l1index = ptepindex >> (L1_SHIFT - L2_SHIFT);
1501 if (pmap_mode == PMAP_MODE_SV39) {
1502 l1 = &pmap->pm_top[l1index];
1503 if (pmap_load(l1) == 0) {
1504 /* recurse for allocating page dir */
1505 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1506 lockp) == NULL)
1507 goto fail;
1508 } else {
1509 pdpg = PTE_TO_VM_PAGE(pmap_load(l1));
1510 pdpg->ref_count++;
1511 }
1512 } else {
1513 l0index = l1index >> Ln_ENTRIES_SHIFT;
1514 l0 = &pmap->pm_top[l0index];
1515 if (pmap_load(l0) == 0) {
1516 /* Recurse to allocate the L1 entry. */
1517 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1518 lockp) == NULL)
1519 goto fail;
1520 phys = PTE_TO_PHYS(pmap_load(l0));
1521 l1 = (pd_entry_t *)PHYS_TO_DMAP(phys);
1522 l1 = &l1[l1index & Ln_ADDR_MASK];
1523 } else {
1524 phys = PTE_TO_PHYS(pmap_load(l0));
1525 l1 = (pd_entry_t *)PHYS_TO_DMAP(phys);
1526 l1 = &l1[l1index & Ln_ADDR_MASK];
1527 if (pmap_load(l1) == 0) {
1528 /* Recurse to allocate the L2 page. */
1529 if (_pmap_alloc_l3(pmap,
1530 NUL2E + l1index, lockp) == NULL)
1531 goto fail;
1532 } else {
1533 pdpg = PTE_TO_VM_PAGE(pmap_load(l1));
1534 pdpg->ref_count++;
1535 }
1536 }
1537 }
1538
1539 phys = PTE_TO_PHYS(pmap_load(l1));
1540 l2 = (pd_entry_t *)PHYS_TO_DMAP(phys);
1541 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1542 KASSERT((pmap_load(l2) & PTE_V) == 0,
1543 ("%s: L2 entry %#lx is valid", __func__, pmap_load(l2)));
1544
1545 entry = PTE_V | (pn << PTE_PPN0_S);
1546 pmap_store(l2, entry);
1547 }
1548
1549 pmap_resident_count_inc(pmap, 1);
1550
1551 return (m);
1552
1553 fail:
1554 vm_page_unwire_noq(m);
1555 vm_page_free_zero(m);
1556 return (NULL);
1557 }
1558
1559 static vm_page_t
pmap_alloc_l2(pmap_t pmap,vm_offset_t va,struct rwlock ** lockp)1560 pmap_alloc_l2(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1561 {
1562 pd_entry_t *l1;
1563 vm_page_t l2pg;
1564 vm_pindex_t l2pindex;
1565
1566 retry:
1567 l1 = pmap_l1(pmap, va);
1568 if (l1 != NULL && (pmap_load(l1) & PTE_V) != 0) {
1569 KASSERT((pmap_load(l1) & PTE_RWX) == 0,
1570 ("%s: L1 entry %#lx for VA %#lx is a leaf", __func__,
1571 pmap_load(l1), va));
1572 /* Add a reference to the L2 page. */
1573 l2pg = PTE_TO_VM_PAGE(pmap_load(l1));
1574 l2pg->ref_count++;
1575 } else {
1576 /* Allocate a L2 page. */
1577 l2pindex = pmap_l2_pindex(va) >> Ln_ENTRIES_SHIFT;
1578 l2pg = _pmap_alloc_l3(pmap, NUL2E + l2pindex, lockp);
1579 if (l2pg == NULL && lockp != NULL)
1580 goto retry;
1581 }
1582 return (l2pg);
1583 }
1584
1585 static vm_page_t
pmap_alloc_l3(pmap_t pmap,vm_offset_t va,struct rwlock ** lockp)1586 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1587 {
1588 vm_pindex_t ptepindex;
1589 pd_entry_t *l2;
1590 vm_page_t m;
1591
1592 /*
1593 * Calculate pagetable page index
1594 */
1595 ptepindex = pmap_l2_pindex(va);
1596 retry:
1597 /*
1598 * Get the page directory entry
1599 */
1600 l2 = pmap_l2(pmap, va);
1601
1602 /*
1603 * If the page table page is mapped, we just increment the
1604 * hold count, and activate it.
1605 */
1606 if (l2 != NULL && pmap_load(l2) != 0) {
1607 m = PTE_TO_VM_PAGE(pmap_load(l2));
1608 m->ref_count++;
1609 } else {
1610 /*
1611 * Here if the pte page isn't mapped, or if it has been
1612 * deallocated.
1613 */
1614 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
1615 if (m == NULL && lockp != NULL)
1616 goto retry;
1617 }
1618 return (m);
1619 }
1620
1621 /***************************************************
1622 * Pmap allocation/deallocation routines.
1623 ***************************************************/
1624
1625 /*
1626 * Release any resources held by the given physical map.
1627 * Called when a pmap initialized by pmap_pinit is being released.
1628 * Should only be called if the map contains no valid mappings.
1629 */
1630 void
pmap_release(pmap_t pmap)1631 pmap_release(pmap_t pmap)
1632 {
1633 vm_page_t m;
1634 int npages;
1635 int i;
1636
1637 KASSERT(pmap->pm_stats.resident_count == 0,
1638 ("pmap_release: pmap resident count %ld != 0",
1639 pmap->pm_stats.resident_count));
1640 KASSERT(CPU_EMPTY(&pmap->pm_active),
1641 ("releasing active pmap %p", pmap));
1642
1643 if (pmap->pm_stage == PM_STAGE2)
1644 goto finish;
1645
1646 if (pmap_mode == PMAP_MODE_SV39) {
1647 mtx_lock(&allpmaps_lock);
1648 LIST_REMOVE(pmap, pm_list);
1649 mtx_unlock(&allpmaps_lock);
1650 }
1651
1652 finish:
1653 npages = pmap->pm_stage == PM_STAGE2 ? 4 : 1;
1654 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_top));
1655 for (i = 0; i < npages; i++) {
1656 vm_page_unwire_noq(m);
1657 vm_page_free(m);
1658 m++;
1659 }
1660 }
1661
1662 static int
kvm_size(SYSCTL_HANDLER_ARGS)1663 kvm_size(SYSCTL_HANDLER_ARGS)
1664 {
1665 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1666
1667 return sysctl_handle_long(oidp, &ksize, 0, req);
1668 }
1669 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
1670 0, 0, kvm_size, "LU",
1671 "Size of KVM");
1672
1673 static int
kvm_free(SYSCTL_HANDLER_ARGS)1674 kvm_free(SYSCTL_HANDLER_ARGS)
1675 {
1676 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1677
1678 return sysctl_handle_long(oidp, &kfree, 0, req);
1679 }
1680 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
1681 0, 0, kvm_free, "LU",
1682 "Amount of KVM free");
1683
1684 /*
1685 * grow the number of kernel page table entries, if needed
1686 */
1687 void
pmap_growkernel(vm_offset_t addr)1688 pmap_growkernel(vm_offset_t addr)
1689 {
1690 vm_paddr_t paddr;
1691 vm_page_t nkpg;
1692 pd_entry_t *l1, *l2;
1693 pt_entry_t entry;
1694 pn_t pn;
1695
1696 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1697
1698 addr = roundup2(addr, L2_SIZE);
1699 if (addr - 1 >= vm_map_max(kernel_map))
1700 addr = vm_map_max(kernel_map);
1701 while (kernel_vm_end < addr) {
1702 l1 = pmap_l1(kernel_pmap, kernel_vm_end);
1703 if (pmap_load(l1) == 0) {
1704 /* We need a new PDP entry */
1705 nkpg = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT |
1706 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1707 if (nkpg == NULL)
1708 panic("pmap_growkernel: no memory to grow kernel");
1709 nkpg->pindex = kernel_vm_end >> L1_SHIFT;
1710 paddr = VM_PAGE_TO_PHYS(nkpg);
1711
1712 pn = (paddr / PAGE_SIZE);
1713 entry = (PTE_V);
1714 entry |= (pn << PTE_PPN0_S);
1715 pmap_store(l1, entry);
1716 pmap_distribute_l1(kernel_pmap,
1717 pmap_l1_index(kernel_vm_end), entry);
1718 continue; /* try again */
1719 }
1720 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
1721 if ((pmap_load(l2) & PTE_V) != 0 &&
1722 (pmap_load(l2) & PTE_RWX) == 0) {
1723 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1724 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1725 kernel_vm_end = vm_map_max(kernel_map);
1726 break;
1727 }
1728 continue;
1729 }
1730
1731 nkpg = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED |
1732 VM_ALLOC_ZERO);
1733 if (nkpg == NULL)
1734 panic("pmap_growkernel: no memory to grow kernel");
1735 nkpg->pindex = kernel_vm_end >> L2_SHIFT;
1736 paddr = VM_PAGE_TO_PHYS(nkpg);
1737
1738 pn = (paddr / PAGE_SIZE);
1739 entry = (PTE_V);
1740 entry |= (pn << PTE_PPN0_S);
1741 pmap_store(l2, entry);
1742
1743 pmap_invalidate_page(kernel_pmap, kernel_vm_end);
1744
1745 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1746 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1747 kernel_vm_end = vm_map_max(kernel_map);
1748 break;
1749 }
1750 }
1751 }
1752
1753 /***************************************************
1754 * page management routines.
1755 ***************************************************/
1756
1757 static const uint64_t pc_freemask[_NPCM] = {
1758 [0 ... _NPCM - 2] = PC_FREEN,
1759 [_NPCM - 1] = PC_FREEL
1760 };
1761
1762 #if 0
1763 #ifdef PV_STATS
1764 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1765
1766 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1767 "Current number of pv entry chunks");
1768 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1769 "Current number of pv entry chunks allocated");
1770 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1771 "Current number of pv entry chunks frees");
1772 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1773 "Number of times tried to get a chunk page but failed.");
1774
1775 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
1776 static int pv_entry_spare;
1777
1778 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1779 "Current number of pv entry frees");
1780 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1781 "Current number of pv entry allocs");
1782 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1783 "Current number of pv entries");
1784 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1785 "Current number of spare pv entries");
1786 #endif
1787 #endif /* 0 */
1788
1789 /*
1790 * We are in a serious low memory condition. Resort to
1791 * drastic measures to free some pages so we can allocate
1792 * another pv entry chunk.
1793 *
1794 * Returns NULL if PV entries were reclaimed from the specified pmap.
1795 *
1796 * We do not, however, unmap 2mpages because subsequent accesses will
1797 * allocate per-page pv entries until repromotion occurs, thereby
1798 * exacerbating the shortage of free pv entries.
1799 */
1800 static vm_page_t
reclaim_pv_chunk(pmap_t locked_pmap,struct rwlock ** lockp)1801 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
1802 {
1803
1804 panic("RISCVTODO: reclaim_pv_chunk");
1805 }
1806
1807 /*
1808 * free the pv_entry back to the free list
1809 */
1810 static void
free_pv_entry(pmap_t pmap,pv_entry_t pv)1811 free_pv_entry(pmap_t pmap, pv_entry_t pv)
1812 {
1813 struct pv_chunk *pc;
1814 int idx, field, bit;
1815
1816 rw_assert(&pvh_global_lock, RA_LOCKED);
1817 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1818 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
1819 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
1820 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
1821 pc = pv_to_chunk(pv);
1822 idx = pv - &pc->pc_pventry[0];
1823 field = idx / 64;
1824 bit = idx % 64;
1825 pc->pc_map[field] |= 1ul << bit;
1826 if (!pc_is_free(pc)) {
1827 /* 98% of the time, pc is already at the head of the list. */
1828 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
1829 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1830 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1831 }
1832 return;
1833 }
1834 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1835 free_pv_chunk(pc);
1836 }
1837
1838 static void
free_pv_chunk(struct pv_chunk * pc)1839 free_pv_chunk(struct pv_chunk *pc)
1840 {
1841 vm_page_t m;
1842
1843 mtx_lock(&pv_chunks_mutex);
1844 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1845 mtx_unlock(&pv_chunks_mutex);
1846 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
1847 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
1848 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
1849 /* entire chunk is free, return it */
1850 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
1851 dump_drop_page(m->phys_addr);
1852 vm_page_unwire_noq(m);
1853 vm_page_free(m);
1854 }
1855
1856 /*
1857 * Returns a new PV entry, allocating a new PV chunk from the system when
1858 * needed. If this PV chunk allocation fails and a PV list lock pointer was
1859 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
1860 * returned.
1861 *
1862 * The given PV list lock may be released.
1863 */
1864 static pv_entry_t
get_pv_entry(pmap_t pmap,struct rwlock ** lockp)1865 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
1866 {
1867 int bit, field;
1868 pv_entry_t pv;
1869 struct pv_chunk *pc;
1870 vm_page_t m;
1871
1872 rw_assert(&pvh_global_lock, RA_LOCKED);
1873 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1874 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
1875 retry:
1876 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
1877 if (pc != NULL) {
1878 for (field = 0; field < _NPCM; field++) {
1879 if (pc->pc_map[field]) {
1880 bit = ffsl(pc->pc_map[field]) - 1;
1881 break;
1882 }
1883 }
1884 if (field < _NPCM) {
1885 pv = &pc->pc_pventry[field * 64 + bit];
1886 pc->pc_map[field] &= ~(1ul << bit);
1887 /* If this was the last item, move it to tail */
1888 if (pc_is_full(pc)) {
1889 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1890 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
1891 pc_list);
1892 }
1893 PV_STAT(atomic_add_long(&pv_entry_count, 1));
1894 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
1895 return (pv);
1896 }
1897 }
1898 /* No free items, allocate another chunk */
1899 m = vm_page_alloc_noobj(VM_ALLOC_WIRED);
1900 if (m == NULL) {
1901 if (lockp == NULL) {
1902 PV_STAT(pc_chunk_tryfail++);
1903 return (NULL);
1904 }
1905 m = reclaim_pv_chunk(pmap, lockp);
1906 if (m == NULL)
1907 goto retry;
1908 }
1909 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
1910 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
1911 dump_add_page(m->phys_addr);
1912 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
1913 pc->pc_pmap = pmap;
1914 pc->pc_map[0] = PC_FREEN & ~1ul; /* preallocated bit 0 */
1915 pc->pc_map[1] = PC_FREEN;
1916 pc->pc_map[2] = PC_FREEL;
1917 mtx_lock(&pv_chunks_mutex);
1918 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
1919 mtx_unlock(&pv_chunks_mutex);
1920 pv = &pc->pc_pventry[0];
1921 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1922 PV_STAT(atomic_add_long(&pv_entry_count, 1));
1923 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
1924 return (pv);
1925 }
1926
1927 /*
1928 * Ensure that the number of spare PV entries in the specified pmap meets or
1929 * exceeds the given count, "needed".
1930 *
1931 * The given PV list lock may be released.
1932 */
1933 static void
reserve_pv_entries(pmap_t pmap,int needed,struct rwlock ** lockp)1934 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
1935 {
1936 struct pch new_tail;
1937 struct pv_chunk *pc;
1938 vm_page_t m;
1939 int avail, free;
1940 bool reclaimed;
1941
1942 rw_assert(&pvh_global_lock, RA_LOCKED);
1943 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1944 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
1945
1946 /*
1947 * Newly allocated PV chunks must be stored in a private list until
1948 * the required number of PV chunks have been allocated. Otherwise,
1949 * reclaim_pv_chunk() could recycle one of these chunks. In
1950 * contrast, these chunks must be added to the pmap upon allocation.
1951 */
1952 TAILQ_INIT(&new_tail);
1953 retry:
1954 avail = 0;
1955 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
1956 bit_count((bitstr_t *)pc->pc_map, 0,
1957 sizeof(pc->pc_map) * NBBY, &free);
1958 if (free == 0)
1959 break;
1960 avail += free;
1961 if (avail >= needed)
1962 break;
1963 }
1964 for (reclaimed = false; avail < needed; avail += _NPCPV) {
1965 m = vm_page_alloc_noobj(VM_ALLOC_WIRED);
1966 if (m == NULL) {
1967 m = reclaim_pv_chunk(pmap, lockp);
1968 if (m == NULL)
1969 goto retry;
1970 reclaimed = true;
1971 }
1972 /* XXX PV STATS */
1973 #if 0
1974 dump_add_page(m->phys_addr);
1975 #endif
1976 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
1977 pc->pc_pmap = pmap;
1978 pc->pc_map[0] = PC_FREEN;
1979 pc->pc_map[1] = PC_FREEN;
1980 pc->pc_map[2] = PC_FREEL;
1981 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1982 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
1983
1984 /*
1985 * The reclaim might have freed a chunk from the current pmap.
1986 * If that chunk contained available entries, we need to
1987 * re-count the number of available entries.
1988 */
1989 if (reclaimed)
1990 goto retry;
1991 }
1992 if (!TAILQ_EMPTY(&new_tail)) {
1993 mtx_lock(&pv_chunks_mutex);
1994 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
1995 mtx_unlock(&pv_chunks_mutex);
1996 }
1997 }
1998
1999 /*
2000 * First find and then remove the pv entry for the specified pmap and virtual
2001 * address from the specified pv list. Returns the pv entry if found and NULL
2002 * otherwise. This operation can be performed on pv lists for either 4KB or
2003 * 2MB page mappings.
2004 */
2005 static __inline pv_entry_t
pmap_pvh_remove(struct md_page * pvh,pmap_t pmap,vm_offset_t va)2006 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2007 {
2008 pv_entry_t pv;
2009
2010 rw_assert(&pvh_global_lock, RA_LOCKED);
2011 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2012 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2013 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2014 pvh->pv_gen++;
2015 break;
2016 }
2017 }
2018 return (pv);
2019 }
2020
2021 /*
2022 * First find and then destroy the pv entry for the specified pmap and virtual
2023 * address. This operation can be performed on pv lists for either 4KB or 2MB
2024 * page mappings.
2025 */
2026 static void
pmap_pvh_free(struct md_page * pvh,pmap_t pmap,vm_offset_t va)2027 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2028 {
2029 pv_entry_t pv;
2030
2031 pv = pmap_pvh_remove(pvh, pmap, va);
2032
2033 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found for %#lx", va));
2034 free_pv_entry(pmap, pv);
2035 }
2036
2037 /*
2038 * Conditionally create the PV entry for a 4KB page mapping if the required
2039 * memory can be allocated without resorting to reclamation.
2040 */
2041 static bool
pmap_try_insert_pv_entry(pmap_t pmap,vm_offset_t va,vm_page_t m,struct rwlock ** lockp)2042 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2043 struct rwlock **lockp)
2044 {
2045 pv_entry_t pv;
2046
2047 rw_assert(&pvh_global_lock, RA_LOCKED);
2048 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2049 /* Pass NULL instead of the lock pointer to disable reclamation. */
2050 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2051 pv->pv_va = va;
2052 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2053 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2054 m->md.pv_gen++;
2055 return (true);
2056 } else
2057 return (false);
2058 }
2059
2060 /*
2061 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2062 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2063 * entries for each of the 4KB page mappings.
2064 */
2065 static void __unused
pmap_pv_demote_l2(pmap_t pmap,vm_offset_t va,vm_paddr_t pa,struct rwlock ** lockp)2066 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2067 struct rwlock **lockp)
2068 {
2069 struct md_page *pvh;
2070 struct pv_chunk *pc;
2071 pv_entry_t pv;
2072 vm_page_t m;
2073 vm_offset_t va_last;
2074 int bit, field;
2075
2076 rw_assert(&pvh_global_lock, RA_LOCKED);
2077 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2078 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2079
2080 /*
2081 * Transfer the 2mpage's pv entry for this mapping to the first
2082 * page's pv list. Once this transfer begins, the pv list lock
2083 * must not be released until the last pv entry is reinstantiated.
2084 */
2085 pvh = pa_to_pvh(pa);
2086 va &= ~L2_OFFSET;
2087 pv = pmap_pvh_remove(pvh, pmap, va);
2088 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2089 m = PHYS_TO_VM_PAGE(pa);
2090 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2091 m->md.pv_gen++;
2092 /* Instantiate the remaining 511 pv entries. */
2093 va_last = va + L2_SIZE - PAGE_SIZE;
2094 for (;;) {
2095 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2096 KASSERT(!pc_is_full(pc), ("pmap_pv_demote_l2: missing spare"));
2097 for (field = 0; field < _NPCM; field++) {
2098 while (pc->pc_map[field] != 0) {
2099 bit = ffsl(pc->pc_map[field]) - 1;
2100 pc->pc_map[field] &= ~(1ul << bit);
2101 pv = &pc->pc_pventry[field * 64 + bit];
2102 va += PAGE_SIZE;
2103 pv->pv_va = va;
2104 m++;
2105 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2106 ("pmap_pv_demote_l2: page %p is not managed", m));
2107 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2108 m->md.pv_gen++;
2109 if (va == va_last)
2110 goto out;
2111 }
2112 }
2113 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2114 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2115 }
2116 out:
2117 if (pc_is_free(pc)) {
2118 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2119 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2120 }
2121 /* XXX PV stats */
2122 }
2123
2124 #if VM_NRESERVLEVEL > 0
2125 static void
pmap_pv_promote_l2(pmap_t pmap,vm_offset_t va,vm_paddr_t pa,struct rwlock ** lockp)2126 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2127 struct rwlock **lockp)
2128 {
2129 struct md_page *pvh;
2130 pv_entry_t pv;
2131 vm_page_t m;
2132 vm_offset_t va_last;
2133
2134 rw_assert(&pvh_global_lock, RA_LOCKED);
2135 KASSERT((pa & L2_OFFSET) == 0,
2136 ("pmap_pv_promote_l2: misaligned pa %#lx", pa));
2137
2138 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2139
2140 m = PHYS_TO_VM_PAGE(pa);
2141 va = va & ~L2_OFFSET;
2142 pv = pmap_pvh_remove(&m->md, pmap, va);
2143 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv for %#lx not found", va));
2144 pvh = pa_to_pvh(pa);
2145 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2146 pvh->pv_gen++;
2147
2148 va_last = va + L2_SIZE - PAGE_SIZE;
2149 do {
2150 m++;
2151 va += PAGE_SIZE;
2152 pmap_pvh_free(&m->md, pmap, va);
2153 } while (va < va_last);
2154 }
2155 #endif /* VM_NRESERVLEVEL > 0 */
2156
2157 /*
2158 * Create the PV entry for a 2MB page mapping. Always returns true unless the
2159 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
2160 * false if the PV entry cannot be allocated without resorting to reclamation.
2161 */
2162 static bool
pmap_pv_insert_l2(pmap_t pmap,vm_offset_t va,pd_entry_t l2e,u_int flags,struct rwlock ** lockp)2163 pmap_pv_insert_l2(pmap_t pmap, vm_offset_t va, pd_entry_t l2e, u_int flags,
2164 struct rwlock **lockp)
2165 {
2166 struct md_page *pvh;
2167 pv_entry_t pv;
2168 vm_paddr_t pa;
2169
2170 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2171 /* Pass NULL instead of the lock pointer to disable reclamation. */
2172 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
2173 NULL : lockp)) == NULL)
2174 return (false);
2175 pv->pv_va = va;
2176 pa = PTE_TO_PHYS(l2e);
2177 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2178 pvh = pa_to_pvh(pa);
2179 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2180 pvh->pv_gen++;
2181 return (true);
2182 }
2183
2184 static void
pmap_remove_kernel_l2(pmap_t pmap,pt_entry_t * l2,vm_offset_t va)2185 pmap_remove_kernel_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
2186 {
2187 pt_entry_t newl2, oldl2 __diagused;
2188 vm_page_t ml3;
2189 vm_paddr_t ml3pa;
2190
2191 KASSERT(!VIRT_IN_DMAP(va), ("removing direct mapping of %#lx", va));
2192 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
2193 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2194
2195 ml3 = pmap_remove_pt_page(pmap, va);
2196 if (ml3 == NULL)
2197 panic("pmap_remove_kernel_l2: Missing pt page");
2198
2199 ml3pa = VM_PAGE_TO_PHYS(ml3);
2200 newl2 = ml3pa | PTE_V;
2201
2202 /*
2203 * If this page table page was unmapped by a promotion, then it
2204 * contains valid mappings. Zero it to invalidate those mappings.
2205 */
2206 if (vm_page_any_valid(ml3))
2207 pagezero((void *)PHYS_TO_DMAP(ml3pa));
2208
2209 /*
2210 * Demote the mapping.
2211 */
2212 oldl2 = pmap_load_store(l2, newl2);
2213 KASSERT(oldl2 == 0, ("%s: found existing mapping at %p: %#lx",
2214 __func__, l2, oldl2));
2215 }
2216
2217 /*
2218 * pmap_remove_l2: Do the things to unmap a level 2 superpage.
2219 */
2220 static int
pmap_remove_l2(pmap_t pmap,pt_entry_t * l2,vm_offset_t sva,pd_entry_t l1e,struct spglist * free,struct rwlock ** lockp)2221 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
2222 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
2223 {
2224 struct md_page *pvh;
2225 pt_entry_t oldl2;
2226 vm_offset_t eva, va;
2227 vm_page_t m, ml3;
2228
2229 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2230 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
2231 oldl2 = pmap_load_clear(l2);
2232 KASSERT((oldl2 & PTE_RWX) != 0,
2233 ("pmap_remove_l2: L2e %lx is not a superpage mapping", oldl2));
2234
2235 /*
2236 * The sfence.vma documentation states that it is sufficient to specify
2237 * a single address within a superpage mapping. However, since we do
2238 * not perform any invalidation upon promotion, TLBs may still be
2239 * caching 4KB mappings within the superpage, so we must invalidate the
2240 * entire range.
2241 */
2242 pmap_invalidate_range(pmap, sva, sva + L2_SIZE);
2243 if ((oldl2 & PTE_SW_WIRED) != 0)
2244 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
2245 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
2246 if ((oldl2 & PTE_SW_MANAGED) != 0) {
2247 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, PTE_TO_PHYS(oldl2));
2248 pvh = pa_to_pvh(PTE_TO_PHYS(oldl2));
2249 pmap_pvh_free(pvh, pmap, sva);
2250 eva = sva + L2_SIZE;
2251 for (va = sva, m = PTE_TO_VM_PAGE(oldl2);
2252 va < eva; va += PAGE_SIZE, m++) {
2253 if ((oldl2 & PTE_D) != 0)
2254 vm_page_dirty(m);
2255 if ((oldl2 & PTE_A) != 0)
2256 vm_page_aflag_set(m, PGA_REFERENCED);
2257 if (TAILQ_EMPTY(&m->md.pv_list) &&
2258 TAILQ_EMPTY(&pvh->pv_list))
2259 vm_page_aflag_clear(m, PGA_WRITEABLE);
2260 }
2261 }
2262 if (pmap == kernel_pmap) {
2263 pmap_remove_kernel_l2(pmap, l2, sva);
2264 } else {
2265 ml3 = pmap_remove_pt_page(pmap, sva);
2266 if (ml3 != NULL) {
2267 KASSERT(vm_page_any_valid(ml3),
2268 ("pmap_remove_l2: l3 page not promoted"));
2269 pmap_resident_count_dec(pmap, 1);
2270 KASSERT(ml3->ref_count == Ln_ENTRIES,
2271 ("pmap_remove_l2: l3 page ref count error"));
2272 ml3->ref_count = 1;
2273 vm_page_unwire_noq(ml3);
2274 pmap_add_delayed_free_list(ml3, free, false);
2275 }
2276 }
2277 return (pmap_unuse_pt(pmap, sva, l1e, free));
2278 }
2279
2280 /*
2281 * pmap_remove_l3: do the things to unmap a page in a process
2282 */
2283 static int
pmap_remove_l3(pmap_t pmap,pt_entry_t * l3,vm_offset_t va,pd_entry_t l2e,struct spglist * free,struct rwlock ** lockp)2284 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
2285 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
2286 {
2287 struct md_page *pvh;
2288 pt_entry_t old_l3;
2289 vm_page_t m;
2290
2291 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2292 old_l3 = pmap_load_clear(l3);
2293 pmap_invalidate_page(pmap, va);
2294 if (old_l3 & PTE_SW_WIRED)
2295 pmap->pm_stats.wired_count -= 1;
2296 pmap_resident_count_dec(pmap, 1);
2297 if (old_l3 & PTE_SW_MANAGED) {
2298 m = PTE_TO_VM_PAGE(old_l3);
2299 if ((old_l3 & PTE_D) != 0)
2300 vm_page_dirty(m);
2301 if (old_l3 & PTE_A)
2302 vm_page_aflag_set(m, PGA_REFERENCED);
2303 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2304 pmap_pvh_free(&m->md, pmap, va);
2305 if (TAILQ_EMPTY(&m->md.pv_list) &&
2306 (m->flags & PG_FICTITIOUS) == 0) {
2307 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2308 if (TAILQ_EMPTY(&pvh->pv_list))
2309 vm_page_aflag_clear(m, PGA_WRITEABLE);
2310 }
2311 }
2312
2313 return (pmap_unuse_pt(pmap, va, l2e, free));
2314 }
2315
2316 /*
2317 * Remove the given range of addresses from the specified map.
2318 *
2319 * It is assumed that the start and end are properly
2320 * rounded to the page size.
2321 */
2322 void
pmap_remove(pmap_t pmap,vm_offset_t sva,vm_offset_t eva)2323 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2324 {
2325 struct spglist free;
2326 struct rwlock *lock;
2327 vm_offset_t va, va_next;
2328 pd_entry_t *l0, *l1, *l2, l2e;
2329 pt_entry_t *l3;
2330
2331 /*
2332 * Perform an unsynchronized read. This is, however, safe.
2333 */
2334 if (pmap->pm_stats.resident_count == 0)
2335 return;
2336
2337 SLIST_INIT(&free);
2338
2339 rw_rlock(&pvh_global_lock);
2340 PMAP_LOCK(pmap);
2341
2342 lock = NULL;
2343 for (; sva < eva; sva = va_next) {
2344 if (pmap->pm_stats.resident_count == 0)
2345 break;
2346
2347 if (pmap_mode == PMAP_MODE_SV48) {
2348 l0 = pmap_l0(pmap, sva);
2349 if (pmap_load(l0) == 0) {
2350 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2351 if (va_next < sva)
2352 va_next = eva;
2353 continue;
2354 }
2355 l1 = pmap_l0_to_l1(l0, sva);
2356 } else {
2357 l1 = pmap_l1(pmap, sva);
2358 }
2359
2360 if (pmap_load(l1) == 0) {
2361 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2362 if (va_next < sva)
2363 va_next = eva;
2364 continue;
2365 }
2366
2367 /*
2368 * Calculate index for next page table.
2369 */
2370 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2371 if (va_next < sva)
2372 va_next = eva;
2373
2374 l2 = pmap_l1_to_l2(l1, sva);
2375 if (l2 == NULL)
2376 continue;
2377 if ((l2e = pmap_load(l2)) == 0)
2378 continue;
2379 if ((l2e & PTE_RWX) != 0) {
2380 if (sva + L2_SIZE == va_next && eva >= va_next) {
2381 (void)pmap_remove_l2(pmap, l2, sva,
2382 pmap_load(l1), &free, &lock);
2383 continue;
2384 } else if (!pmap_demote_l2_locked(pmap, l2, sva,
2385 &lock)) {
2386 /*
2387 * The large page mapping was destroyed.
2388 */
2389 continue;
2390 }
2391 l2e = pmap_load(l2);
2392 }
2393
2394 /*
2395 * Limit our scan to either the end of the va represented
2396 * by the current page table page, or to the end of the
2397 * range being removed.
2398 */
2399 if (va_next > eva)
2400 va_next = eva;
2401
2402 va = va_next;
2403 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
2404 sva += L3_SIZE) {
2405 if (pmap_load(l3) == 0) {
2406 if (va != va_next) {
2407 pmap_invalidate_range(pmap, va, sva);
2408 va = va_next;
2409 }
2410 continue;
2411 }
2412 if (va == va_next)
2413 va = sva;
2414 if (pmap_remove_l3(pmap, l3, sva, l2e, &free, &lock)) {
2415 sva += L3_SIZE;
2416 break;
2417 }
2418 }
2419 if (va != va_next)
2420 pmap_invalidate_range(pmap, va, sva);
2421 }
2422 if (lock != NULL)
2423 rw_wunlock(lock);
2424 rw_runlock(&pvh_global_lock);
2425 PMAP_UNLOCK(pmap);
2426 vm_page_free_pages_toq(&free, false);
2427 }
2428
2429 /*
2430 * Routine: pmap_remove_all
2431 * Function:
2432 * Removes this physical page from
2433 * all physical maps in which it resides.
2434 * Reflects back modify bits to the pager.
2435 *
2436 * Notes:
2437 * Original versions of this routine were very
2438 * inefficient because they iteratively called
2439 * pmap_remove (slow...)
2440 */
2441
2442 void
pmap_remove_all(vm_page_t m)2443 pmap_remove_all(vm_page_t m)
2444 {
2445 struct spglist free;
2446 struct md_page *pvh;
2447 pmap_t pmap;
2448 pt_entry_t *l3, l3e;
2449 pd_entry_t *l2, l2e __diagused;
2450 pv_entry_t pv;
2451 vm_offset_t va;
2452
2453 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2454 ("pmap_remove_all: page %p is not managed", m));
2455 SLIST_INIT(&free);
2456 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
2457 pa_to_pvh(VM_PAGE_TO_PHYS(m));
2458
2459 rw_wlock(&pvh_global_lock);
2460 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2461 pmap = PV_PMAP(pv);
2462 PMAP_LOCK(pmap);
2463 va = pv->pv_va;
2464 l2 = pmap_l2(pmap, va);
2465 (void)pmap_demote_l2(pmap, l2, va);
2466 PMAP_UNLOCK(pmap);
2467 }
2468 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2469 pmap = PV_PMAP(pv);
2470 PMAP_LOCK(pmap);
2471 pmap_resident_count_dec(pmap, 1);
2472 l2 = pmap_l2(pmap, pv->pv_va);
2473 KASSERT(l2 != NULL, ("pmap_remove_all: no l2 table found"));
2474 l2e = pmap_load(l2);
2475
2476 KASSERT((l2e & PTE_RX) == 0,
2477 ("pmap_remove_all: found a superpage in %p's pv list", m));
2478
2479 l3 = pmap_l2_to_l3(l2, pv->pv_va);
2480 l3e = pmap_load_clear(l3);
2481 pmap_invalidate_page(pmap, pv->pv_va);
2482 if (l3e & PTE_SW_WIRED)
2483 pmap->pm_stats.wired_count--;
2484 if ((l3e & PTE_A) != 0)
2485 vm_page_aflag_set(m, PGA_REFERENCED);
2486
2487 /*
2488 * Update the vm_page_t clean and reference bits.
2489 */
2490 if ((l3e & PTE_D) != 0)
2491 vm_page_dirty(m);
2492 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(l2), &free);
2493 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2494 m->md.pv_gen++;
2495 free_pv_entry(pmap, pv);
2496 PMAP_UNLOCK(pmap);
2497 }
2498 vm_page_aflag_clear(m, PGA_WRITEABLE);
2499 rw_wunlock(&pvh_global_lock);
2500 vm_page_free_pages_toq(&free, false);
2501 }
2502
2503 /*
2504 * Set the physical protection on the
2505 * specified range of this map as requested.
2506 */
2507 void
pmap_protect(pmap_t pmap,vm_offset_t sva,vm_offset_t eva,vm_prot_t prot)2508 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2509 {
2510 pd_entry_t *l0, *l1, *l2, l2e;
2511 pt_entry_t *l3, l3e, mask;
2512 vm_page_t m, mt;
2513 vm_offset_t va_next;
2514 bool anychanged, pv_lists_locked;
2515
2516 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2517 pmap_remove(pmap, sva, eva);
2518 return;
2519 }
2520
2521 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
2522 (VM_PROT_WRITE | VM_PROT_EXECUTE))
2523 return;
2524
2525 anychanged = false;
2526 pv_lists_locked = false;
2527 mask = 0;
2528 if ((prot & VM_PROT_WRITE) == 0)
2529 mask |= PTE_W | PTE_D;
2530 if ((prot & VM_PROT_EXECUTE) == 0)
2531 mask |= PTE_X;
2532 resume:
2533 PMAP_LOCK(pmap);
2534 for (; sva < eva; sva = va_next) {
2535 if (pmap_mode == PMAP_MODE_SV48) {
2536 l0 = pmap_l0(pmap, sva);
2537 if (pmap_load(l0) == 0) {
2538 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2539 if (va_next < sva)
2540 va_next = eva;
2541 continue;
2542 }
2543 l1 = pmap_l0_to_l1(l0, sva);
2544 } else {
2545 l1 = pmap_l1(pmap, sva);
2546 }
2547
2548 if (pmap_load(l1) == 0) {
2549 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2550 if (va_next < sva)
2551 va_next = eva;
2552 continue;
2553 }
2554
2555 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2556 if (va_next < sva)
2557 va_next = eva;
2558
2559 l2 = pmap_l1_to_l2(l1, sva);
2560 if (l2 == NULL || (l2e = pmap_load(l2)) == 0)
2561 continue;
2562 if ((l2e & PTE_RWX) != 0) {
2563 if (sva + L2_SIZE == va_next && eva >= va_next) {
2564 retryl2:
2565 if ((prot & VM_PROT_WRITE) == 0 &&
2566 (l2e & (PTE_SW_MANAGED | PTE_D)) ==
2567 (PTE_SW_MANAGED | PTE_D)) {
2568 m = PTE_TO_VM_PAGE(l2e);
2569 for (mt = m; mt < &m[Ln_ENTRIES]; mt++)
2570 vm_page_dirty(mt);
2571 }
2572 if (!atomic_fcmpset_long(l2, &l2e, l2e & ~mask))
2573 goto retryl2;
2574 anychanged = true;
2575 continue;
2576 } else {
2577 if (!pv_lists_locked) {
2578 pv_lists_locked = true;
2579 if (!rw_try_rlock(&pvh_global_lock)) {
2580 if (anychanged)
2581 pmap_invalidate_all(
2582 pmap);
2583 PMAP_UNLOCK(pmap);
2584 rw_rlock(&pvh_global_lock);
2585 goto resume;
2586 }
2587 }
2588 if (!pmap_demote_l2(pmap, l2, sva)) {
2589 /*
2590 * The large page mapping was destroyed.
2591 */
2592 continue;
2593 }
2594 }
2595 }
2596
2597 if (va_next > eva)
2598 va_next = eva;
2599
2600 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
2601 sva += L3_SIZE) {
2602 l3e = pmap_load(l3);
2603 retryl3:
2604 if ((l3e & PTE_V) == 0)
2605 continue;
2606 if ((prot & VM_PROT_WRITE) == 0 &&
2607 (l3e & (PTE_SW_MANAGED | PTE_D)) ==
2608 (PTE_SW_MANAGED | PTE_D)) {
2609 m = PTE_TO_VM_PAGE(l3e);
2610 vm_page_dirty(m);
2611 }
2612 if (!atomic_fcmpset_long(l3, &l3e, l3e & ~mask))
2613 goto retryl3;
2614 anychanged = true;
2615 }
2616 }
2617 if (anychanged)
2618 pmap_invalidate_all(pmap);
2619 if (pv_lists_locked)
2620 rw_runlock(&pvh_global_lock);
2621 PMAP_UNLOCK(pmap);
2622 }
2623
2624 int
pmap_fault(pmap_t pmap,vm_offset_t va,vm_prot_t ftype)2625 pmap_fault(pmap_t pmap, vm_offset_t va, vm_prot_t ftype)
2626 {
2627 pd_entry_t *l2, l2e;
2628 pt_entry_t bits, *pte, oldpte;
2629 int rv;
2630
2631 KASSERT(VIRT_IS_VALID(va), ("pmap_fault: invalid va %#lx", va));
2632
2633 rv = 0;
2634 PMAP_LOCK(pmap);
2635 l2 = pmap_l2(pmap, va);
2636 if (l2 == NULL || ((l2e = pmap_load(l2)) & PTE_V) == 0)
2637 goto done;
2638 if ((l2e & PTE_RWX) == 0) {
2639 pte = pmap_l2_to_l3(l2, va);
2640 if (pte == NULL || ((oldpte = pmap_load(pte)) & PTE_V) == 0)
2641 goto done;
2642 } else {
2643 pte = l2;
2644 oldpte = l2e;
2645 }
2646
2647 if ((pmap != kernel_pmap && (oldpte & PTE_U) == 0) ||
2648 (ftype == VM_PROT_WRITE && (oldpte & PTE_W) == 0) ||
2649 (ftype == VM_PROT_EXECUTE && (oldpte & PTE_X) == 0) ||
2650 (ftype == VM_PROT_READ && (oldpte & PTE_R) == 0))
2651 goto done;
2652
2653 bits = PTE_A;
2654 if (ftype == VM_PROT_WRITE)
2655 bits |= PTE_D;
2656
2657 /*
2658 * Spurious faults can occur if the implementation caches invalid
2659 * entries in the TLB, or if simultaneous accesses on multiple CPUs
2660 * race with each other.
2661 */
2662 if ((oldpte & bits) != bits)
2663 pmap_store_bits(pte, bits);
2664 sfence_vma();
2665 rv = 1;
2666 done:
2667 PMAP_UNLOCK(pmap);
2668 return (rv);
2669 }
2670
2671 static bool
pmap_demote_l2(pmap_t pmap,pd_entry_t * l2,vm_offset_t va)2672 pmap_demote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va)
2673 {
2674 struct rwlock *lock;
2675 bool rv;
2676
2677 lock = NULL;
2678 rv = pmap_demote_l2_locked(pmap, l2, va, &lock);
2679 if (lock != NULL)
2680 rw_wunlock(lock);
2681 return (rv);
2682 }
2683
2684 /*
2685 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
2686 * mapping is invalidated.
2687 */
2688 static bool
pmap_demote_l2_locked(pmap_t pmap,pd_entry_t * l2,vm_offset_t va,struct rwlock ** lockp)2689 pmap_demote_l2_locked(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
2690 struct rwlock **lockp)
2691 {
2692 struct spglist free;
2693 vm_page_t mpte;
2694 pd_entry_t newl2, oldl2;
2695 pt_entry_t *firstl3, newl3;
2696 vm_paddr_t mptepa;
2697 int i;
2698
2699 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2700
2701 oldl2 = pmap_load(l2);
2702 KASSERT((oldl2 & PTE_RWX) != 0,
2703 ("pmap_demote_l2_locked: oldl2 is not a leaf entry"));
2704 if ((oldl2 & PTE_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
2705 NULL) {
2706 KASSERT((oldl2 & PTE_SW_WIRED) == 0,
2707 ("pmap_demote_l2_locked: page table page for a wired mapping is missing"));
2708 if ((oldl2 & PTE_A) == 0 || (mpte = vm_page_alloc_noobj(
2709 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : 0) |
2710 VM_ALLOC_WIRED)) == NULL) {
2711 SLIST_INIT(&free);
2712 (void)pmap_remove_l2(pmap, l2, va & ~L2_OFFSET,
2713 pmap_load(pmap_l1(pmap, va)), &free, lockp);
2714 vm_page_free_pages_toq(&free, true);
2715 CTR2(KTR_PMAP, "pmap_demote_l2_locked: "
2716 "failure for va %#lx in pmap %p", va, pmap);
2717 return (false);
2718 }
2719 mpte->pindex = pmap_l2_pindex(va);
2720 if (va < VM_MAXUSER_ADDRESS) {
2721 mpte->ref_count = Ln_ENTRIES;
2722 pmap_resident_count_inc(pmap, 1);
2723 }
2724 }
2725 mptepa = VM_PAGE_TO_PHYS(mpte);
2726 firstl3 = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
2727 newl2 = ((mptepa / PAGE_SIZE) << PTE_PPN0_S) | PTE_V;
2728 KASSERT((oldl2 & PTE_A) != 0,
2729 ("pmap_demote_l2_locked: oldl2 is missing PTE_A"));
2730 KASSERT((oldl2 & (PTE_D | PTE_W)) != PTE_W,
2731 ("pmap_demote_l2_locked: oldl2 is missing PTE_D"));
2732 newl3 = oldl2;
2733
2734 /*
2735 * If the page table page is not leftover from an earlier promotion,
2736 * initialize it.
2737 */
2738 if (!vm_page_all_valid(mpte)) {
2739 for (i = 0; i < Ln_ENTRIES; i++)
2740 pmap_store(firstl3 + i, newl3 + (i << PTE_PPN0_S));
2741 }
2742 KASSERT(PTE_TO_PHYS(pmap_load(firstl3)) == PTE_TO_PHYS(newl3),
2743 ("pmap_demote_l2_locked: firstl3 and newl3 map different physical "
2744 "addresses"));
2745
2746 /*
2747 * If the mapping has changed attributes, update the PTEs.
2748 */
2749 if ((pmap_load(firstl3) & PTE_PROMOTE) != (newl3 & PTE_PROMOTE))
2750 for (i = 0; i < Ln_ENTRIES; i++)
2751 pmap_store(firstl3 + i, newl3 + (i << PTE_PPN0_S));
2752
2753 /*
2754 * The spare PV entries must be reserved prior to demoting the
2755 * mapping, that is, prior to changing the L2 entry. Otherwise, the
2756 * state of the L2 entry and the PV lists will be inconsistent, which
2757 * can result in reclaim_pv_chunk() attempting to remove a PV entry from
2758 * the wrong PV list and pmap_pv_demote_l2() failing to find the
2759 * expected PV entry for the 2MB page mapping that is being demoted.
2760 */
2761 if ((oldl2 & PTE_SW_MANAGED) != 0)
2762 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
2763
2764 /*
2765 * Demote the mapping.
2766 */
2767 pmap_store(l2, newl2);
2768
2769 /*
2770 * Demote the PV entry.
2771 */
2772 if ((oldl2 & PTE_SW_MANAGED) != 0)
2773 pmap_pv_demote_l2(pmap, va, PTE_TO_PHYS(oldl2), lockp);
2774
2775 atomic_add_long(&pmap_l2_demotions, 1);
2776 CTR2(KTR_PMAP, "pmap_demote_l2_locked: success for va %#lx in pmap %p",
2777 va, pmap);
2778 return (true);
2779 }
2780
2781 #if VM_NRESERVLEVEL > 0
2782 static bool
pmap_promote_l2(pmap_t pmap,pd_entry_t * l2,vm_offset_t va,vm_page_t ml3,struct rwlock ** lockp)2783 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va, vm_page_t ml3,
2784 struct rwlock **lockp)
2785 {
2786 pt_entry_t all_l3e_PTE_A, *firstl3, firstl3e, *l3, l3e;
2787 vm_paddr_t pa;
2788
2789 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2790 if (!pmap_ps_enabled(pmap))
2791 return (false);
2792
2793 KASSERT((pmap_load(l2) & PTE_RWX) == 0,
2794 ("pmap_promote_l2: invalid l2 entry %p", l2));
2795
2796 /*
2797 * Examine the first L3E in the specified PTP. Abort if this L3E is
2798 * ineligible for promotion or does not map the first 4KB physical page
2799 * within a 2MB page.
2800 */
2801 firstl3 = (pt_entry_t *)PHYS_TO_DMAP(PTE_TO_PHYS(pmap_load(l2)));
2802 firstl3e = pmap_load(firstl3);
2803 pa = PTE_TO_PHYS(firstl3e);
2804 if ((pa & L2_OFFSET) != 0) {
2805 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx pmap %p",
2806 va, pmap);
2807 atomic_add_long(&pmap_l2_p_failures, 1);
2808 return (false);
2809 }
2810
2811 /*
2812 * Downgrade a clean, writable mapping to read-only to ensure that the
2813 * hardware does not set PTE_D while we are comparing PTEs.
2814 *
2815 * Upon a write access to a clean mapping, the implementation will
2816 * either atomically check protections and set PTE_D, or raise a page
2817 * fault. In the latter case, the pmap lock provides atomicity. Thus,
2818 * we do not issue an sfence.vma here and instead rely on pmap_fault()
2819 * to do so lazily.
2820 */
2821 while ((firstl3e & (PTE_W | PTE_D)) == PTE_W) {
2822 if (atomic_fcmpset_64(firstl3, &firstl3e, firstl3e & ~PTE_W)) {
2823 firstl3e &= ~PTE_W;
2824 break;
2825 }
2826 }
2827
2828 /*
2829 * Examine each of the other PTEs in the specified PTP. Abort if this
2830 * PTE maps an unexpected 4KB physical page or does not have identical
2831 * characteristics to the first PTE.
2832 */
2833 all_l3e_PTE_A = firstl3e & PTE_A;
2834 pa += L2_SIZE - PAGE_SIZE;
2835 for (l3 = firstl3 + Ln_ENTRIES - 1; l3 > firstl3; l3--) {
2836 l3e = pmap_load(l3);
2837 if (PTE_TO_PHYS(l3e) != pa) {
2838 CTR2(KTR_PMAP,
2839 "pmap_promote_l2: failure for va %#lx pmap %p",
2840 va, pmap);
2841 atomic_add_long(&pmap_l2_p_failures, 1);
2842 return (false);
2843 }
2844 while ((l3e & (PTE_W | PTE_D)) == PTE_W) {
2845 if (atomic_fcmpset_64(l3, &l3e, l3e & ~PTE_W)) {
2846 l3e &= ~PTE_W;
2847 break;
2848 }
2849 }
2850 if ((l3e & PTE_PROMOTE) != (firstl3e & PTE_PROMOTE)) {
2851 CTR2(KTR_PMAP,
2852 "pmap_promote_l2: failure for va %#lx pmap %p",
2853 va, pmap);
2854 atomic_add_long(&pmap_l2_p_failures, 1);
2855 return (false);
2856 }
2857 all_l3e_PTE_A &= l3e;
2858 pa -= PAGE_SIZE;
2859 }
2860
2861 /*
2862 * Unless all PTEs have PTE_A set, clear it from the superpage
2863 * mapping, so that promotions triggered by speculative mappings,
2864 * such as pmap_enter_quick(), don't automatically mark the
2865 * underlying pages as referenced.
2866 */
2867 firstl3e &= ~PTE_A | all_l3e_PTE_A;
2868
2869 /*
2870 * Save the page table page in its current state until the L2
2871 * mapping the superpage is demoted by pmap_demote_l2() or
2872 * destroyed by pmap_remove_l3().
2873 */
2874 if (ml3 == NULL)
2875 ml3 = PTE_TO_VM_PAGE(pmap_load(l2));
2876 KASSERT(ml3->pindex == pmap_l2_pindex(va),
2877 ("pmap_promote_l2: page table page's pindex is wrong"));
2878 if (pmap_insert_pt_page(pmap, ml3, true, all_l3e_PTE_A != 0)) {
2879 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx pmap %p",
2880 va, pmap);
2881 atomic_add_long(&pmap_l2_p_failures, 1);
2882 return (false);
2883 }
2884
2885 if ((firstl3e & PTE_SW_MANAGED) != 0)
2886 pmap_pv_promote_l2(pmap, va, PTE_TO_PHYS(firstl3e), lockp);
2887
2888 pmap_store(l2, firstl3e);
2889
2890 atomic_add_long(&pmap_l2_promotions, 1);
2891 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
2892 pmap);
2893 return (true);
2894 }
2895 #endif
2896
2897 /*
2898 * Insert the given physical page (p) at
2899 * the specified virtual address (v) in the
2900 * target physical map with the protection requested.
2901 *
2902 * If specified, the page will be wired down, meaning
2903 * that the related pte can not be reclaimed.
2904 *
2905 * NB: This is the only routine which MAY NOT lazy-evaluate
2906 * or lose information. That is, this routine must actually
2907 * insert this page into the given map NOW.
2908 */
2909 int
pmap_enter(pmap_t pmap,vm_offset_t va,vm_page_t m,vm_prot_t prot,u_int flags,int8_t psind)2910 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
2911 u_int flags, int8_t psind)
2912 {
2913 struct rwlock *lock;
2914 pd_entry_t *l2, l2e;
2915 pt_entry_t new_l3, orig_l3;
2916 pt_entry_t *l3;
2917 pv_entry_t pv;
2918 vm_paddr_t opa, pa;
2919 vm_page_t mpte, om;
2920 pn_t pn;
2921 int rv;
2922 bool nosleep;
2923
2924 va = trunc_page(va);
2925 if ((m->oflags & VPO_UNMANAGED) == 0)
2926 VM_PAGE_OBJECT_BUSY_ASSERT(m);
2927 pa = VM_PAGE_TO_PHYS(m);
2928 pn = (pa / PAGE_SIZE);
2929
2930 new_l3 = PTE_V | PTE_R | PTE_A;
2931 if (prot & VM_PROT_EXECUTE)
2932 new_l3 |= PTE_X;
2933 if (flags & VM_PROT_WRITE)
2934 new_l3 |= PTE_D;
2935 if (prot & VM_PROT_WRITE)
2936 new_l3 |= PTE_W;
2937 if (va < VM_MAX_USER_ADDRESS)
2938 new_l3 |= PTE_U;
2939
2940 new_l3 |= (pn << PTE_PPN0_S);
2941 if ((flags & PMAP_ENTER_WIRED) != 0)
2942 new_l3 |= PTE_SW_WIRED;
2943
2944 /*
2945 * Set modified bit gratuitously for writeable mappings if
2946 * the page is unmanaged. We do not want to take a fault
2947 * to do the dirty bit accounting for these mappings.
2948 */
2949 if ((m->oflags & VPO_UNMANAGED) != 0) {
2950 if (prot & VM_PROT_WRITE)
2951 new_l3 |= PTE_D;
2952 } else
2953 new_l3 |= PTE_SW_MANAGED;
2954
2955 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
2956
2957 lock = NULL;
2958 mpte = NULL;
2959 rw_rlock(&pvh_global_lock);
2960 PMAP_LOCK(pmap);
2961 if (psind == 1) {
2962 /* Assert the required virtual and physical alignment. */
2963 KASSERT((va & L2_OFFSET) == 0,
2964 ("pmap_enter: va %#lx unaligned", va));
2965 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
2966 rv = pmap_enter_l2(pmap, va, new_l3, flags, m, &lock);
2967 goto out;
2968 }
2969
2970 l2 = pmap_l2(pmap, va);
2971 if (l2 != NULL && ((l2e = pmap_load(l2)) & PTE_V) != 0 &&
2972 ((l2e & PTE_RWX) == 0 || pmap_demote_l2_locked(pmap, l2,
2973 va, &lock))) {
2974 l3 = pmap_l2_to_l3(l2, va);
2975 if (va < VM_MAXUSER_ADDRESS) {
2976 mpte = PTE_TO_VM_PAGE(pmap_load(l2));
2977 mpte->ref_count++;
2978 }
2979 } else if (va < VM_MAXUSER_ADDRESS) {
2980 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
2981 mpte = pmap_alloc_l3(pmap, va, nosleep ? NULL : &lock);
2982 if (mpte == NULL && nosleep) {
2983 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
2984 if (lock != NULL)
2985 rw_wunlock(lock);
2986 rw_runlock(&pvh_global_lock);
2987 PMAP_UNLOCK(pmap);
2988 return (KERN_RESOURCE_SHORTAGE);
2989 }
2990 l3 = pmap_l3(pmap, va);
2991 } else {
2992 panic("pmap_enter: missing L3 table for kernel va %#lx", va);
2993 }
2994
2995 orig_l3 = pmap_load(l3);
2996 opa = PTE_TO_PHYS(orig_l3);
2997 pv = NULL;
2998
2999 /*
3000 * Is the specified virtual address already mapped?
3001 */
3002 if ((orig_l3 & PTE_V) != 0) {
3003 /*
3004 * Wiring change, just update stats. We don't worry about
3005 * wiring PT pages as they remain resident as long as there
3006 * are valid mappings in them. Hence, if a user page is wired,
3007 * the PT page will be also.
3008 */
3009 if ((flags & PMAP_ENTER_WIRED) != 0 &&
3010 (orig_l3 & PTE_SW_WIRED) == 0)
3011 pmap->pm_stats.wired_count++;
3012 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
3013 (orig_l3 & PTE_SW_WIRED) != 0)
3014 pmap->pm_stats.wired_count--;
3015
3016 /*
3017 * Remove the extra PT page reference.
3018 */
3019 if (mpte != NULL) {
3020 mpte->ref_count--;
3021 KASSERT(mpte->ref_count > 0,
3022 ("pmap_enter: missing reference to page table page,"
3023 " va: 0x%lx", va));
3024 }
3025
3026 /*
3027 * Has the physical page changed?
3028 */
3029 if (opa == pa) {
3030 /*
3031 * No, might be a protection or wiring change.
3032 */
3033 if ((orig_l3 & PTE_SW_MANAGED) != 0 &&
3034 (new_l3 & PTE_W) != 0)
3035 vm_page_aflag_set(m, PGA_WRITEABLE);
3036 goto validate;
3037 }
3038
3039 /*
3040 * The physical page has changed. Temporarily invalidate
3041 * the mapping. This ensures that all threads sharing the
3042 * pmap keep a consistent view of the mapping, which is
3043 * necessary for the correct handling of COW faults. It
3044 * also permits reuse of the old mapping's PV entry,
3045 * avoiding an allocation.
3046 *
3047 * For consistency, handle unmanaged mappings the same way.
3048 */
3049 orig_l3 = pmap_load_clear(l3);
3050 KASSERT(PTE_TO_PHYS(orig_l3) == opa,
3051 ("pmap_enter: unexpected pa update for %#lx", va));
3052 if ((orig_l3 & PTE_SW_MANAGED) != 0) {
3053 om = PHYS_TO_VM_PAGE(opa);
3054
3055 /*
3056 * The pmap lock is sufficient to synchronize with
3057 * concurrent calls to pmap_page_test_mappings() and
3058 * pmap_ts_referenced().
3059 */
3060 if ((orig_l3 & PTE_D) != 0)
3061 vm_page_dirty(om);
3062 if ((orig_l3 & PTE_A) != 0)
3063 vm_page_aflag_set(om, PGA_REFERENCED);
3064 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
3065 pv = pmap_pvh_remove(&om->md, pmap, va);
3066 KASSERT(pv != NULL,
3067 ("pmap_enter: no PV entry for %#lx", va));
3068 if ((new_l3 & PTE_SW_MANAGED) == 0)
3069 free_pv_entry(pmap, pv);
3070 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
3071 TAILQ_EMPTY(&om->md.pv_list) &&
3072 ((om->flags & PG_FICTITIOUS) != 0 ||
3073 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3074 vm_page_aflag_clear(om, PGA_WRITEABLE);
3075 }
3076 pmap_invalidate_page(pmap, va);
3077 orig_l3 = 0;
3078 } else {
3079 /*
3080 * Increment the counters.
3081 */
3082 if ((new_l3 & PTE_SW_WIRED) != 0)
3083 pmap->pm_stats.wired_count++;
3084 pmap_resident_count_inc(pmap, 1);
3085 }
3086 /*
3087 * Enter on the PV list if part of our managed memory.
3088 */
3089 if ((new_l3 & PTE_SW_MANAGED) != 0) {
3090 if (pv == NULL) {
3091 pv = get_pv_entry(pmap, &lock);
3092 pv->pv_va = va;
3093 }
3094 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
3095 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3096 m->md.pv_gen++;
3097 if ((new_l3 & PTE_W) != 0)
3098 vm_page_aflag_set(m, PGA_WRITEABLE);
3099 }
3100
3101 validate:
3102 /*
3103 * Sync the i-cache on all harts before updating the PTE
3104 * if the new PTE is executable.
3105 */
3106 if (prot & VM_PROT_EXECUTE)
3107 pmap_sync_icache(pmap, va, PAGE_SIZE);
3108
3109 /*
3110 * Update the L3 entry.
3111 */
3112 if (orig_l3 != 0) {
3113 orig_l3 = pmap_load_store(l3, new_l3);
3114 pmap_invalidate_page(pmap, va);
3115 KASSERT(PTE_TO_PHYS(orig_l3) == pa,
3116 ("pmap_enter: invalid update"));
3117 if ((orig_l3 & (PTE_D | PTE_SW_MANAGED)) ==
3118 (PTE_D | PTE_SW_MANAGED))
3119 vm_page_dirty(m);
3120 } else {
3121 pmap_store(l3, new_l3);
3122 }
3123
3124 #if VM_NRESERVLEVEL > 0
3125 if (mpte != NULL && mpte->ref_count == Ln_ENTRIES &&
3126 (m->flags & PG_FICTITIOUS) == 0 &&
3127 vm_reserv_level_iffullpop(m) == 0)
3128 (void)pmap_promote_l2(pmap, l2, va, mpte, &lock);
3129 #endif
3130
3131 rv = KERN_SUCCESS;
3132 out:
3133 if (lock != NULL)
3134 rw_wunlock(lock);
3135 rw_runlock(&pvh_global_lock);
3136 PMAP_UNLOCK(pmap);
3137 return (rv);
3138 }
3139
3140 /*
3141 * Release a page table page reference after a failed attempt to create a
3142 * mapping.
3143 */
3144 static void
pmap_abort_ptp(pmap_t pmap,vm_offset_t va,vm_page_t l2pg)3145 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t l2pg)
3146 {
3147 struct spglist free;
3148
3149 SLIST_INIT(&free);
3150 if (pmap_unwire_ptp(pmap, va, l2pg, &free)) {
3151 /*
3152 * Although "va" is not mapped, paging-structure
3153 * caches could nonetheless have entries that
3154 * refer to the freed page table pages.
3155 * Invalidate those entries.
3156 */
3157 pmap_invalidate_page(pmap, va);
3158 vm_page_free_pages_toq(&free, true);
3159 }
3160 }
3161
3162 /*
3163 * Tries to create a read- and/or execute-only 2MB page mapping. Returns
3164 * KERN_SUCCESS if the mapping was created. Otherwise, returns an error
3165 * value. See pmap_enter_l2() for the possible error values when "no sleep",
3166 * "no replace", and "no reclaim" are specified.
3167 */
3168 static int
pmap_enter_2mpage(pmap_t pmap,vm_offset_t va,vm_page_t m,vm_prot_t prot,struct rwlock ** lockp)3169 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3170 struct rwlock **lockp)
3171 {
3172 pd_entry_t new_l2;
3173 pn_t pn;
3174
3175 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3176
3177 pn = VM_PAGE_TO_PHYS(m) / PAGE_SIZE;
3178 new_l2 = (pd_entry_t)((pn << PTE_PPN0_S) | PTE_R | PTE_V);
3179 if ((m->oflags & VPO_UNMANAGED) == 0)
3180 new_l2 |= PTE_SW_MANAGED;
3181 if ((prot & VM_PROT_EXECUTE) != 0)
3182 new_l2 |= PTE_X;
3183 if (va < VM_MAXUSER_ADDRESS)
3184 new_l2 |= PTE_U;
3185 return (pmap_enter_l2(pmap, va, new_l2, PMAP_ENTER_NOSLEEP |
3186 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp));
3187 }
3188
3189 /*
3190 * Returns true if every page table entry in the specified page table is
3191 * zero.
3192 */
3193 static bool
pmap_every_pte_zero(vm_paddr_t pa)3194 pmap_every_pte_zero(vm_paddr_t pa)
3195 {
3196 pt_entry_t *pt_end, *pte;
3197
3198 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
3199 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
3200 for (pt_end = pte + Ln_ENTRIES; pte < pt_end; pte++) {
3201 if (*pte != 0)
3202 return (false);
3203 }
3204 return (true);
3205 }
3206
3207 /*
3208 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
3209 * the mapping was created, and one of KERN_FAILURE, KERN_NO_SPACE, or
3210 * KERN_RESOURCE_SHORTAGE otherwise. Returns KERN_FAILURE if
3211 * PMAP_ENTER_NOREPLACE was specified and a 4KB page mapping already exists
3212 * within the 2MB virtual address range starting at the specified virtual
3213 * address. Returns KERN_NO_SPACE if PMAP_ENTER_NOREPLACE was specified and a
3214 * 2MB page mapping already exists at the specified virtual address. Returns
3215 * KERN_RESOURCE_SHORTAGE if either (1) PMAP_ENTER_NOSLEEP was specified and a
3216 * page table page allocation failed or (2) PMAP_ENTER_NORECLAIM was specified
3217 * and a PV entry allocation failed.
3218 *
3219 * The parameter "m" is only used when creating a managed, writeable mapping.
3220 */
3221 static int
pmap_enter_l2(pmap_t pmap,vm_offset_t va,pd_entry_t new_l2,u_int flags,vm_page_t m,struct rwlock ** lockp)3222 pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, u_int flags,
3223 vm_page_t m, struct rwlock **lockp)
3224 {
3225 struct spglist free;
3226 pd_entry_t *l2, *l3, oldl2;
3227 vm_offset_t sva;
3228 vm_page_t l2pg, mt;
3229 vm_page_t uwptpg;
3230
3231 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3232
3233 if ((l2pg = pmap_alloc_l2(pmap, va, (flags & PMAP_ENTER_NOSLEEP) != 0 ?
3234 NULL : lockp)) == NULL) {
3235 CTR2(KTR_PMAP, "pmap_enter_l2: failed to allocate PT page"
3236 " for va %#lx in pmap %p", va, pmap);
3237 return (KERN_RESOURCE_SHORTAGE);
3238 }
3239
3240 l2 = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(l2pg));
3241 l2 = &l2[pmap_l2_index(va)];
3242 if ((oldl2 = pmap_load(l2)) != 0) {
3243 KASSERT(l2pg->ref_count > 1,
3244 ("pmap_enter_l2: l2pg's ref count is too low"));
3245 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
3246 if ((oldl2 & PTE_RWX) != 0) {
3247 l2pg->ref_count--;
3248 CTR2(KTR_PMAP,
3249 "pmap_enter_l2: no space for va %#lx"
3250 " in pmap %p", va, pmap);
3251 return (KERN_NO_SPACE);
3252 } else if (va < VM_MAXUSER_ADDRESS ||
3253 !pmap_every_pte_zero(L2PTE_TO_PHYS(oldl2))) {
3254 l2pg->ref_count--;
3255 CTR2(KTR_PMAP, "pmap_enter_l2:"
3256 " failed to replace existing mapping"
3257 " for va %#lx in pmap %p", va, pmap);
3258 return (KERN_FAILURE);
3259 }
3260 }
3261 SLIST_INIT(&free);
3262 if ((oldl2 & PTE_RWX) != 0)
3263 (void)pmap_remove_l2(pmap, l2, va,
3264 pmap_load(pmap_l1(pmap, va)), &free, lockp);
3265 else
3266 for (sva = va; sva < va + L2_SIZE; sva += PAGE_SIZE) {
3267 l3 = pmap_l2_to_l3(l2, sva);
3268 if ((pmap_load(l3) & PTE_V) != 0 &&
3269 pmap_remove_l3(pmap, l3, sva, oldl2, &free,
3270 lockp) != 0)
3271 break;
3272 }
3273 vm_page_free_pages_toq(&free, true);
3274 if (va >= VM_MAXUSER_ADDRESS) {
3275 /*
3276 * Both pmap_remove_l2() and pmap_remove_l3() will
3277 * leave the kernel page table page zero filled.
3278 */
3279 mt = PTE_TO_VM_PAGE(pmap_load(l2));
3280 if (pmap_insert_pt_page(pmap, mt, false, false))
3281 panic("pmap_enter_l2: trie insert failed");
3282 } else
3283 KASSERT(pmap_load(l2) == 0,
3284 ("pmap_enter_l2: non-zero L2 entry %p", l2));
3285 }
3286
3287 /*
3288 * Allocate leaf ptpage for wired userspace pages.
3289 */
3290 uwptpg = NULL;
3291 if ((new_l2 & PTE_SW_WIRED) != 0 && pmap != kernel_pmap) {
3292 uwptpg = vm_page_alloc_noobj(VM_ALLOC_WIRED);
3293 if (uwptpg == NULL) {
3294 pmap_abort_ptp(pmap, va, l2pg);
3295 return (KERN_RESOURCE_SHORTAGE);
3296 }
3297 uwptpg->pindex = pmap_l2_pindex(va);
3298 if (pmap_insert_pt_page(pmap, uwptpg, true, false)) {
3299 vm_page_unwire_noq(uwptpg);
3300 vm_page_free(uwptpg);
3301 pmap_abort_ptp(pmap, va, l2pg);
3302 return (KERN_RESOURCE_SHORTAGE);
3303 }
3304 pmap_resident_count_inc(pmap, 1);
3305 uwptpg->ref_count = Ln_ENTRIES;
3306 }
3307 if ((new_l2 & PTE_SW_MANAGED) != 0) {
3308 /*
3309 * Abort this mapping if its PV entry could not be created.
3310 */
3311 if (!pmap_pv_insert_l2(pmap, va, new_l2, flags, lockp)) {
3312 pmap_abort_ptp(pmap, va, l2pg);
3313 if (uwptpg != NULL) {
3314 mt = pmap_remove_pt_page(pmap, va);
3315 KASSERT(mt == uwptpg,
3316 ("removed pt page %p, expected %p", mt,
3317 uwptpg));
3318 pmap_resident_count_dec(pmap, 1);
3319 uwptpg->ref_count = 1;
3320 vm_page_unwire_noq(uwptpg);
3321 vm_page_free(uwptpg);
3322 }
3323 CTR2(KTR_PMAP,
3324 "pmap_enter_l2: failed to create PV entry"
3325 " for va %#lx in pmap %p", va, pmap);
3326 return (KERN_RESOURCE_SHORTAGE);
3327 }
3328 if ((new_l2 & PTE_W) != 0)
3329 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3330 vm_page_aflag_set(mt, PGA_WRITEABLE);
3331 }
3332
3333 /*
3334 * Increment counters.
3335 */
3336 if ((new_l2 & PTE_SW_WIRED) != 0)
3337 pmap->pm_stats.wired_count += L2_SIZE / PAGE_SIZE;
3338 pmap->pm_stats.resident_count += L2_SIZE / PAGE_SIZE;
3339
3340 /*
3341 * Map the superpage.
3342 */
3343 pmap_store(l2, new_l2);
3344
3345 atomic_add_long(&pmap_l2_mappings, 1);
3346 CTR2(KTR_PMAP, "pmap_enter_l2: success for va %#lx in pmap %p",
3347 va, pmap);
3348
3349 return (KERN_SUCCESS);
3350 }
3351
3352 /*
3353 * Maps a sequence of resident pages belonging to the same object.
3354 * The sequence begins with the given page m_start. This page is
3355 * mapped at the given virtual address start. Each subsequent page is
3356 * mapped at a virtual address that is offset from start by the same
3357 * amount as the page is offset from m_start within the object. The
3358 * last page in the sequence is the page with the largest offset from
3359 * m_start that can be mapped at a virtual address less than the given
3360 * virtual address end. Not every virtual page between start and end
3361 * is mapped; only those for which a resident page exists with the
3362 * corresponding offset from m_start are mapped.
3363 */
3364 void
pmap_enter_object(pmap_t pmap,vm_offset_t start,vm_offset_t end,vm_page_t m_start,vm_prot_t prot)3365 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3366 vm_page_t m_start, vm_prot_t prot)
3367 {
3368 struct rwlock *lock;
3369 vm_offset_t va;
3370 vm_page_t m, mpte;
3371 vm_pindex_t diff, psize;
3372 int rv;
3373
3374 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3375
3376 psize = atop(end - start);
3377 mpte = NULL;
3378 m = m_start;
3379 lock = NULL;
3380 rw_rlock(&pvh_global_lock);
3381 PMAP_LOCK(pmap);
3382 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3383 va = start + ptoa(diff);
3384 if ((va & L2_OFFSET) == 0 && va + L2_SIZE <= end &&
3385 m->psind == 1 && pmap_ps_enabled(pmap) &&
3386 ((rv = pmap_enter_2mpage(pmap, va, m, prot, &lock)) ==
3387 KERN_SUCCESS || rv == KERN_NO_SPACE))
3388 m = &m[L2_SIZE / PAGE_SIZE - 1];
3389 else
3390 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte,
3391 &lock);
3392 m = TAILQ_NEXT(m, listq);
3393 }
3394 if (lock != NULL)
3395 rw_wunlock(lock);
3396 rw_runlock(&pvh_global_lock);
3397 PMAP_UNLOCK(pmap);
3398 }
3399
3400 /*
3401 * this code makes some *MAJOR* assumptions:
3402 * 1. Current pmap & pmap exists.
3403 * 2. Not wired.
3404 * 3. Read access.
3405 * 4. No page table pages.
3406 * but is *MUCH* faster than pmap_enter...
3407 */
3408
3409 void
pmap_enter_quick(pmap_t pmap,vm_offset_t va,vm_page_t m,vm_prot_t prot)3410 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3411 {
3412 struct rwlock *lock;
3413
3414 lock = NULL;
3415 rw_rlock(&pvh_global_lock);
3416 PMAP_LOCK(pmap);
3417 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
3418 if (lock != NULL)
3419 rw_wunlock(lock);
3420 rw_runlock(&pvh_global_lock);
3421 PMAP_UNLOCK(pmap);
3422 }
3423
3424 static vm_page_t
pmap_enter_quick_locked(pmap_t pmap,vm_offset_t va,vm_page_t m,vm_prot_t prot,vm_page_t mpte,struct rwlock ** lockp)3425 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3426 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
3427 {
3428 struct spglist free;
3429 pd_entry_t *l2;
3430 pt_entry_t *l3, newl3;
3431
3432 KASSERT(!VA_IS_CLEANMAP(va) ||
3433 (m->oflags & VPO_UNMANAGED) != 0,
3434 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3435 rw_assert(&pvh_global_lock, RA_LOCKED);
3436 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3437 l2 = NULL;
3438
3439 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
3440 /*
3441 * In the case that a page table page is not
3442 * resident, we are creating it here.
3443 */
3444 if (va < VM_MAXUSER_ADDRESS) {
3445 vm_pindex_t l2pindex;
3446
3447 /*
3448 * Calculate pagetable page index
3449 */
3450 l2pindex = pmap_l2_pindex(va);
3451 if (mpte && (mpte->pindex == l2pindex)) {
3452 mpte->ref_count++;
3453 } else {
3454 /*
3455 * Get the l2 entry
3456 */
3457 l2 = pmap_l2(pmap, va);
3458
3459 /*
3460 * If the page table page is mapped, we just increment
3461 * the hold count, and activate it. Otherwise, we
3462 * attempt to allocate a page table page. If this
3463 * attempt fails, we don't retry. Instead, we give up.
3464 */
3465 if (l2 != NULL && pmap_load(l2) != 0) {
3466 if ((pmap_load(l2) & PTE_RWX) != 0)
3467 return (NULL);
3468 mpte = PTE_TO_VM_PAGE(pmap_load(l2));
3469 mpte->ref_count++;
3470 } else {
3471 /*
3472 * Pass NULL instead of the PV list lock
3473 * pointer, because we don't intend to sleep.
3474 */
3475 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
3476 if (mpte == NULL)
3477 return (mpte);
3478 }
3479 }
3480 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
3481 l3 = &l3[pmap_l3_index(va)];
3482 } else {
3483 mpte = NULL;
3484 l3 = pmap_l3(kernel_pmap, va);
3485 }
3486 if (l3 == NULL)
3487 panic("pmap_enter_quick_locked: No l3");
3488 if (pmap_load(l3) != 0) {
3489 if (mpte != NULL)
3490 mpte->ref_count--;
3491 return (NULL);
3492 }
3493
3494 /*
3495 * Enter on the PV list if part of our managed memory.
3496 */
3497 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3498 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
3499 if (mpte != NULL) {
3500 SLIST_INIT(&free);
3501 if (pmap_unwire_ptp(pmap, va, mpte, &free))
3502 vm_page_free_pages_toq(&free, false);
3503 }
3504 return (NULL);
3505 }
3506
3507 /*
3508 * Increment counters
3509 */
3510 pmap_resident_count_inc(pmap, 1);
3511
3512 newl3 = ((VM_PAGE_TO_PHYS(m) / PAGE_SIZE) << PTE_PPN0_S) |
3513 PTE_V | PTE_R;
3514 if ((prot & VM_PROT_EXECUTE) != 0)
3515 newl3 |= PTE_X;
3516 if ((m->oflags & VPO_UNMANAGED) == 0)
3517 newl3 |= PTE_SW_MANAGED;
3518 if (va < VM_MAX_USER_ADDRESS)
3519 newl3 |= PTE_U;
3520
3521 /*
3522 * Sync the i-cache on all harts before updating the PTE
3523 * if the new PTE is executable.
3524 */
3525 if (prot & VM_PROT_EXECUTE)
3526 pmap_sync_icache(pmap, va, PAGE_SIZE);
3527
3528 pmap_store(l3, newl3);
3529
3530 #if VM_NRESERVLEVEL > 0
3531 /*
3532 * If both the PTP and the reservation are fully populated, then attempt
3533 * promotion.
3534 */
3535 if ((prot & VM_PROT_NO_PROMOTE) == 0 &&
3536 (mpte == NULL || mpte->ref_count == Ln_ENTRIES) &&
3537 (m->flags & PG_FICTITIOUS) == 0 &&
3538 vm_reserv_level_iffullpop(m) == 0) {
3539 if (l2 == NULL)
3540 l2 = pmap_l2(pmap, va);
3541
3542 /*
3543 * If promotion succeeds, then the next call to this function
3544 * should not be given the unmapped PTP as a hint.
3545 */
3546 if (pmap_promote_l2(pmap, l2, va, mpte, lockp))
3547 mpte = NULL;
3548 }
3549 #endif
3550
3551 return (mpte);
3552 }
3553
3554 /*
3555 * This code maps large physical mmap regions into the
3556 * processor address space. Note that some shortcuts
3557 * are taken, but the code works.
3558 */
3559 void
pmap_object_init_pt(pmap_t pmap,vm_offset_t addr,vm_object_t object,vm_pindex_t pindex,vm_size_t size)3560 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3561 vm_pindex_t pindex, vm_size_t size)
3562 {
3563
3564 VM_OBJECT_ASSERT_WLOCKED(object);
3565 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3566 ("pmap_object_init_pt: non-device object"));
3567 }
3568
3569 /*
3570 * Clear the wired attribute from the mappings for the specified range of
3571 * addresses in the given pmap. Every valid mapping within that range
3572 * must have the wired attribute set. In contrast, invalid mappings
3573 * cannot have the wired attribute set, so they are ignored.
3574 *
3575 * The wired attribute of the page table entry is not a hardware feature,
3576 * so there is no need to invalidate any TLB entries.
3577 */
3578 void
pmap_unwire(pmap_t pmap,vm_offset_t sva,vm_offset_t eva)3579 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3580 {
3581 vm_offset_t va_next;
3582 pd_entry_t *l0, *l1, *l2, l2e;
3583 pt_entry_t *l3, l3e;
3584 bool pv_lists_locked;
3585
3586 pv_lists_locked = false;
3587 retry:
3588 PMAP_LOCK(pmap);
3589 for (; sva < eva; sva = va_next) {
3590 if (pmap_mode == PMAP_MODE_SV48) {
3591 l0 = pmap_l0(pmap, sva);
3592 if (pmap_load(l0) == 0) {
3593 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3594 if (va_next < sva)
3595 va_next = eva;
3596 continue;
3597 }
3598 l1 = pmap_l0_to_l1(l0, sva);
3599 } else {
3600 l1 = pmap_l1(pmap, sva);
3601 }
3602
3603 if (pmap_load(l1) == 0) {
3604 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3605 if (va_next < sva)
3606 va_next = eva;
3607 continue;
3608 }
3609
3610 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3611 if (va_next < sva)
3612 va_next = eva;
3613
3614 l2 = pmap_l1_to_l2(l1, sva);
3615 if ((l2e = pmap_load(l2)) == 0)
3616 continue;
3617 if ((l2e & PTE_RWX) != 0) {
3618 if (sva + L2_SIZE == va_next && eva >= va_next) {
3619 if ((l2e & PTE_SW_WIRED) == 0)
3620 panic("pmap_unwire: l2 %#jx is missing "
3621 "PTE_SW_WIRED", (uintmax_t)l2e);
3622 pmap_clear_bits(l2, PTE_SW_WIRED);
3623 continue;
3624 } else {
3625 if (!pv_lists_locked) {
3626 pv_lists_locked = true;
3627 if (!rw_try_rlock(&pvh_global_lock)) {
3628 PMAP_UNLOCK(pmap);
3629 rw_rlock(&pvh_global_lock);
3630 /* Repeat sva. */
3631 goto retry;
3632 }
3633 }
3634 if (!pmap_demote_l2(pmap, l2, sva))
3635 panic("pmap_unwire: demotion failed");
3636 }
3637 }
3638
3639 if (va_next > eva)
3640 va_next = eva;
3641 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
3642 sva += L3_SIZE) {
3643 if ((l3e = pmap_load(l3)) == 0)
3644 continue;
3645 if ((l3e & PTE_SW_WIRED) == 0)
3646 panic("pmap_unwire: l3 %#jx is missing "
3647 "PTE_SW_WIRED", (uintmax_t)l3e);
3648
3649 /*
3650 * PG_W must be cleared atomically. Although the pmap
3651 * lock synchronizes access to PG_W, another processor
3652 * could be setting PG_M and/or PG_A concurrently.
3653 */
3654 pmap_clear_bits(l3, PTE_SW_WIRED);
3655 pmap->pm_stats.wired_count--;
3656 }
3657 }
3658 if (pv_lists_locked)
3659 rw_runlock(&pvh_global_lock);
3660 PMAP_UNLOCK(pmap);
3661 }
3662
3663 /*
3664 * Copy the range specified by src_addr/len
3665 * from the source map to the range dst_addr/len
3666 * in the destination map.
3667 *
3668 * This routine is only advisory and need not do anything.
3669 */
3670
3671 void
pmap_copy(pmap_t dst_pmap,pmap_t src_pmap,vm_offset_t dst_addr,vm_size_t len,vm_offset_t src_addr)3672 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
3673 vm_offset_t src_addr)
3674 {
3675
3676 }
3677
3678 /*
3679 * pmap_zero_page zeros the specified hardware page by mapping
3680 * the page into KVM and using bzero to clear its contents.
3681 */
3682 void
pmap_zero_page(vm_page_t m)3683 pmap_zero_page(vm_page_t m)
3684 {
3685 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3686
3687 pagezero((void *)va);
3688 }
3689
3690 /*
3691 * pmap_zero_page_area zeros the specified hardware page by mapping
3692 * the page into KVM and using bzero to clear its contents.
3693 *
3694 * off and size may not cover an area beyond a single hardware page.
3695 */
3696 void
pmap_zero_page_area(vm_page_t m,int off,int size)3697 pmap_zero_page_area(vm_page_t m, int off, int size)
3698 {
3699 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3700
3701 if (off == 0 && size == PAGE_SIZE)
3702 pagezero((void *)va);
3703 else
3704 bzero((char *)va + off, size);
3705 }
3706
3707 /*
3708 * pmap_copy_page copies the specified (machine independent)
3709 * page by mapping the page into virtual memory and using
3710 * bcopy to copy the page, one machine dependent page at a
3711 * time.
3712 */
3713 void
pmap_copy_page(vm_page_t msrc,vm_page_t mdst)3714 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
3715 {
3716 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
3717 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
3718
3719 pagecopy((void *)src, (void *)dst);
3720 }
3721
3722 int unmapped_buf_allowed = 1;
3723
3724 void
pmap_copy_pages(vm_page_t ma[],vm_offset_t a_offset,vm_page_t mb[],vm_offset_t b_offset,int xfersize)3725 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
3726 vm_offset_t b_offset, int xfersize)
3727 {
3728 void *a_cp, *b_cp;
3729 vm_page_t m_a, m_b;
3730 vm_paddr_t p_a, p_b;
3731 vm_offset_t a_pg_offset, b_pg_offset;
3732 int cnt;
3733
3734 while (xfersize > 0) {
3735 a_pg_offset = a_offset & PAGE_MASK;
3736 m_a = ma[a_offset >> PAGE_SHIFT];
3737 p_a = m_a->phys_addr;
3738 b_pg_offset = b_offset & PAGE_MASK;
3739 m_b = mb[b_offset >> PAGE_SHIFT];
3740 p_b = m_b->phys_addr;
3741 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
3742 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
3743 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
3744 panic("!DMAP a %lx", p_a);
3745 } else {
3746 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
3747 }
3748 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
3749 panic("!DMAP b %lx", p_b);
3750 } else {
3751 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
3752 }
3753 bcopy(a_cp, b_cp, cnt);
3754 a_offset += cnt;
3755 b_offset += cnt;
3756 xfersize -= cnt;
3757 }
3758 }
3759
3760 vm_offset_t
pmap_quick_enter_page(vm_page_t m)3761 pmap_quick_enter_page(vm_page_t m)
3762 {
3763
3764 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
3765 }
3766
3767 void
pmap_quick_remove_page(vm_offset_t addr)3768 pmap_quick_remove_page(vm_offset_t addr)
3769 {
3770 }
3771
3772 /*
3773 * Returns true if the pmap's pv is one of the first
3774 * 16 pvs linked to from this page. This count may
3775 * be changed upwards or downwards in the future; it
3776 * is only necessary that true be returned for a small
3777 * subset of pmaps for proper page aging.
3778 */
3779 bool
pmap_page_exists_quick(pmap_t pmap,vm_page_t m)3780 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
3781 {
3782 struct md_page *pvh;
3783 struct rwlock *lock;
3784 pv_entry_t pv;
3785 int loops = 0;
3786 bool rv;
3787
3788 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3789 ("pmap_page_exists_quick: page %p is not managed", m));
3790 rv = false;
3791 rw_rlock(&pvh_global_lock);
3792 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3793 rw_rlock(lock);
3794 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3795 if (PV_PMAP(pv) == pmap) {
3796 rv = true;
3797 break;
3798 }
3799 loops++;
3800 if (loops >= 16)
3801 break;
3802 }
3803 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
3804 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3805 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3806 if (PV_PMAP(pv) == pmap) {
3807 rv = true;
3808 break;
3809 }
3810 loops++;
3811 if (loops >= 16)
3812 break;
3813 }
3814 }
3815 rw_runlock(lock);
3816 rw_runlock(&pvh_global_lock);
3817 return (rv);
3818 }
3819
3820 /*
3821 * pmap_page_wired_mappings:
3822 *
3823 * Return the number of managed mappings to the given physical page
3824 * that are wired.
3825 */
3826 int
pmap_page_wired_mappings(vm_page_t m)3827 pmap_page_wired_mappings(vm_page_t m)
3828 {
3829 struct md_page *pvh;
3830 struct rwlock *lock;
3831 pmap_t pmap;
3832 pd_entry_t *l2;
3833 pt_entry_t *l3;
3834 pv_entry_t pv;
3835 int count, md_gen, pvh_gen;
3836
3837 if ((m->oflags & VPO_UNMANAGED) != 0)
3838 return (0);
3839 rw_rlock(&pvh_global_lock);
3840 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3841 rw_rlock(lock);
3842 restart:
3843 count = 0;
3844 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3845 pmap = PV_PMAP(pv);
3846 if (!PMAP_TRYLOCK(pmap)) {
3847 md_gen = m->md.pv_gen;
3848 rw_runlock(lock);
3849 PMAP_LOCK(pmap);
3850 rw_rlock(lock);
3851 if (md_gen != m->md.pv_gen) {
3852 PMAP_UNLOCK(pmap);
3853 goto restart;
3854 }
3855 }
3856 l2 = pmap_l2(pmap, pv->pv_va);
3857 KASSERT((pmap_load(l2) & PTE_RWX) == 0,
3858 ("%s: found a 2mpage in page %p's pv list", __func__, m));
3859 l3 = pmap_l2_to_l3(l2, pv->pv_va);
3860 if ((pmap_load(l3) & PTE_SW_WIRED) != 0)
3861 count++;
3862 PMAP_UNLOCK(pmap);
3863 }
3864 if ((m->flags & PG_FICTITIOUS) == 0) {
3865 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3866 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3867 pmap = PV_PMAP(pv);
3868 if (!PMAP_TRYLOCK(pmap)) {
3869 md_gen = m->md.pv_gen;
3870 pvh_gen = pvh->pv_gen;
3871 rw_runlock(lock);
3872 PMAP_LOCK(pmap);
3873 rw_rlock(lock);
3874 if (md_gen != m->md.pv_gen ||
3875 pvh_gen != pvh->pv_gen) {
3876 PMAP_UNLOCK(pmap);
3877 goto restart;
3878 }
3879 }
3880 l2 = pmap_l2(pmap, pv->pv_va);
3881 if ((pmap_load(l2) & PTE_SW_WIRED) != 0)
3882 count++;
3883 PMAP_UNLOCK(pmap);
3884 }
3885 }
3886 rw_runlock(lock);
3887 rw_runlock(&pvh_global_lock);
3888 return (count);
3889 }
3890
3891 /*
3892 * Returns true if the given page is mapped individually or as part of
3893 * a 2mpage. Otherwise, returns false.
3894 */
3895 bool
pmap_page_is_mapped(vm_page_t m)3896 pmap_page_is_mapped(vm_page_t m)
3897 {
3898 struct rwlock *lock;
3899 bool rv;
3900
3901 if ((m->oflags & VPO_UNMANAGED) != 0)
3902 return (false);
3903 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3904 rw_rlock(lock);
3905 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
3906 ((m->flags & PG_FICTITIOUS) == 0 &&
3907 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
3908 rw_runlock(lock);
3909 return (rv);
3910 }
3911
3912 static void
pmap_remove_pages_pv(pmap_t pmap,vm_page_t m,pv_entry_t pv,struct spglist * free,bool superpage)3913 pmap_remove_pages_pv(pmap_t pmap, vm_page_t m, pv_entry_t pv,
3914 struct spglist *free, bool superpage)
3915 {
3916 struct md_page *pvh;
3917 vm_page_t mpte, mt;
3918
3919 if (superpage) {
3920 pmap_resident_count_dec(pmap, Ln_ENTRIES);
3921 pvh = pa_to_pvh(m->phys_addr);
3922 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3923 pvh->pv_gen++;
3924 if (TAILQ_EMPTY(&pvh->pv_list)) {
3925 for (mt = m; mt < &m[Ln_ENTRIES]; mt++)
3926 if (TAILQ_EMPTY(&mt->md.pv_list) &&
3927 (mt->a.flags & PGA_WRITEABLE) != 0)
3928 vm_page_aflag_clear(mt, PGA_WRITEABLE);
3929 }
3930 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
3931 if (mpte != NULL) {
3932 KASSERT(vm_page_any_valid(mpte),
3933 ("pmap_remove_pages: pte page not promoted"));
3934 pmap_resident_count_dec(pmap, 1);
3935 KASSERT(mpte->ref_count == Ln_ENTRIES,
3936 ("pmap_remove_pages: pte page ref count error"));
3937 mpte->ref_count = 0;
3938 pmap_add_delayed_free_list(mpte, free, false);
3939 }
3940 } else {
3941 pmap_resident_count_dec(pmap, 1);
3942 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3943 m->md.pv_gen++;
3944 if (TAILQ_EMPTY(&m->md.pv_list) &&
3945 (m->a.flags & PGA_WRITEABLE) != 0) {
3946 pvh = pa_to_pvh(m->phys_addr);
3947 if (TAILQ_EMPTY(&pvh->pv_list))
3948 vm_page_aflag_clear(m, PGA_WRITEABLE);
3949 }
3950 }
3951 }
3952
3953 /*
3954 * Destroy all managed, non-wired mappings in the given user-space
3955 * pmap. This pmap cannot be active on any processor besides the
3956 * caller.
3957 *
3958 * This function cannot be applied to the kernel pmap. Moreover, it
3959 * is not intended for general use. It is only to be used during
3960 * process termination. Consequently, it can be implemented in ways
3961 * that make it faster than pmap_remove(). First, it can more quickly
3962 * destroy mappings by iterating over the pmap's collection of PV
3963 * entries, rather than searching the page table. Second, it doesn't
3964 * have to test and clear the page table entries atomically, because
3965 * no processor is currently accessing the user address space. In
3966 * particular, a page table entry's dirty bit won't change state once
3967 * this function starts.
3968 */
3969 void
pmap_remove_pages(pmap_t pmap)3970 pmap_remove_pages(pmap_t pmap)
3971 {
3972 struct spglist free;
3973 pd_entry_t ptepde;
3974 pt_entry_t *pte, tpte;
3975 vm_page_t m, mt;
3976 pv_entry_t pv;
3977 struct pv_chunk *pc, *npc;
3978 struct rwlock *lock;
3979 int64_t bit;
3980 uint64_t inuse, bitmask;
3981 int allfree, field, freed __pv_stat_used, idx;
3982 bool superpage;
3983
3984 lock = NULL;
3985
3986 SLIST_INIT(&free);
3987 rw_rlock(&pvh_global_lock);
3988 PMAP_LOCK(pmap);
3989 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
3990 allfree = 1;
3991 freed = 0;
3992 for (field = 0; field < _NPCM; field++) {
3993 inuse = ~pc->pc_map[field] & pc_freemask[field];
3994 while (inuse != 0) {
3995 bit = ffsl(inuse) - 1;
3996 bitmask = 1UL << bit;
3997 idx = field * 64 + bit;
3998 pv = &pc->pc_pventry[idx];
3999 inuse &= ~bitmask;
4000
4001 pte = pmap_l1(pmap, pv->pv_va);
4002 ptepde = pmap_load(pte);
4003 pte = pmap_l1_to_l2(pte, pv->pv_va);
4004 tpte = pmap_load(pte);
4005
4006 KASSERT((tpte & PTE_V) != 0,
4007 ("L2 PTE is invalid... bogus PV entry? "
4008 "va=%#lx, pte=%#lx", pv->pv_va, tpte));
4009 if ((tpte & PTE_RWX) != 0) {
4010 superpage = true;
4011 } else {
4012 ptepde = tpte;
4013 pte = pmap_l2_to_l3(pte, pv->pv_va);
4014 tpte = pmap_load(pte);
4015 superpage = false;
4016 }
4017
4018 /*
4019 * We cannot remove wired pages from a
4020 * process' mapping at this time.
4021 */
4022 if (tpte & PTE_SW_WIRED) {
4023 allfree = 0;
4024 continue;
4025 }
4026
4027 m = PTE_TO_VM_PAGE(tpte);
4028 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4029 m < &vm_page_array[vm_page_array_size],
4030 ("pmap_remove_pages: bad pte %#jx",
4031 (uintmax_t)tpte));
4032
4033 pmap_clear(pte);
4034
4035 /*
4036 * Update the vm_page_t clean/reference bits.
4037 */
4038 if ((tpte & (PTE_D | PTE_W)) ==
4039 (PTE_D | PTE_W)) {
4040 if (superpage)
4041 for (mt = m;
4042 mt < &m[Ln_ENTRIES]; mt++)
4043 vm_page_dirty(mt);
4044 else
4045 vm_page_dirty(m);
4046 }
4047
4048 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
4049
4050 /* Mark free */
4051 pc->pc_map[field] |= bitmask;
4052
4053 pmap_remove_pages_pv(pmap, m, pv, &free,
4054 superpage);
4055 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
4056 freed++;
4057 }
4058 }
4059 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4060 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4061 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4062 if (allfree) {
4063 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4064 free_pv_chunk(pc);
4065 }
4066 }
4067 if (lock != NULL)
4068 rw_wunlock(lock);
4069 pmap_invalidate_all(pmap);
4070 rw_runlock(&pvh_global_lock);
4071 PMAP_UNLOCK(pmap);
4072 vm_page_free_pages_toq(&free, false);
4073 }
4074
4075 static bool
pmap_page_test_mappings(vm_page_t m,bool accessed,bool modified)4076 pmap_page_test_mappings(vm_page_t m, bool accessed, bool modified)
4077 {
4078 struct md_page *pvh;
4079 struct rwlock *lock;
4080 pd_entry_t *l2;
4081 pt_entry_t *l3, mask;
4082 pv_entry_t pv;
4083 pmap_t pmap;
4084 int md_gen, pvh_gen;
4085 bool rv;
4086
4087 mask = 0;
4088 if (modified)
4089 mask |= PTE_D;
4090 if (accessed)
4091 mask |= PTE_A;
4092
4093 rv = false;
4094 rw_rlock(&pvh_global_lock);
4095 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4096 rw_rlock(lock);
4097 restart:
4098 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4099 pmap = PV_PMAP(pv);
4100 if (!PMAP_TRYLOCK(pmap)) {
4101 md_gen = m->md.pv_gen;
4102 rw_runlock(lock);
4103 PMAP_LOCK(pmap);
4104 rw_rlock(lock);
4105 if (md_gen != m->md.pv_gen) {
4106 PMAP_UNLOCK(pmap);
4107 goto restart;
4108 }
4109 }
4110 l2 = pmap_l2(pmap, pv->pv_va);
4111 KASSERT((pmap_load(l2) & PTE_RWX) == 0,
4112 ("%s: found a 2mpage in page %p's pv list", __func__, m));
4113 l3 = pmap_l2_to_l3(l2, pv->pv_va);
4114 rv = (pmap_load(l3) & mask) == mask;
4115 PMAP_UNLOCK(pmap);
4116 if (rv)
4117 goto out;
4118 }
4119 if ((m->flags & PG_FICTITIOUS) == 0) {
4120 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4121 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4122 pmap = PV_PMAP(pv);
4123 if (!PMAP_TRYLOCK(pmap)) {
4124 md_gen = m->md.pv_gen;
4125 pvh_gen = pvh->pv_gen;
4126 rw_runlock(lock);
4127 PMAP_LOCK(pmap);
4128 rw_rlock(lock);
4129 if (md_gen != m->md.pv_gen ||
4130 pvh_gen != pvh->pv_gen) {
4131 PMAP_UNLOCK(pmap);
4132 goto restart;
4133 }
4134 }
4135 l2 = pmap_l2(pmap, pv->pv_va);
4136 rv = (pmap_load(l2) & mask) == mask;
4137 PMAP_UNLOCK(pmap);
4138 if (rv)
4139 goto out;
4140 }
4141 }
4142 out:
4143 rw_runlock(lock);
4144 rw_runlock(&pvh_global_lock);
4145 return (rv);
4146 }
4147
4148 /*
4149 * pmap_is_modified:
4150 *
4151 * Return whether or not the specified physical page was modified
4152 * in any physical maps.
4153 */
4154 bool
pmap_is_modified(vm_page_t m)4155 pmap_is_modified(vm_page_t m)
4156 {
4157
4158 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4159 ("pmap_is_modified: page %p is not managed", m));
4160
4161 /*
4162 * If the page is not busied then this check is racy.
4163 */
4164 if (!pmap_page_is_write_mapped(m))
4165 return (false);
4166 return (pmap_page_test_mappings(m, false, true));
4167 }
4168
4169 /*
4170 * pmap_is_prefaultable:
4171 *
4172 * Return whether or not the specified virtual address is eligible
4173 * for prefault.
4174 */
4175 bool
pmap_is_prefaultable(pmap_t pmap,vm_offset_t addr)4176 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4177 {
4178 pt_entry_t *l3;
4179 bool rv;
4180
4181 /*
4182 * Return true if and only if the L3 entry for the specified virtual
4183 * address is allocated but invalid.
4184 */
4185 rv = false;
4186 PMAP_LOCK(pmap);
4187 l3 = pmap_l3(pmap, addr);
4188 if (l3 != NULL && pmap_load(l3) == 0) {
4189 rv = true;
4190 }
4191 PMAP_UNLOCK(pmap);
4192 return (rv);
4193 }
4194
4195 /*
4196 * pmap_is_referenced:
4197 *
4198 * Return whether or not the specified physical page was referenced
4199 * in any physical maps.
4200 */
4201 bool
pmap_is_referenced(vm_page_t m)4202 pmap_is_referenced(vm_page_t m)
4203 {
4204
4205 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4206 ("pmap_is_referenced: page %p is not managed", m));
4207 return (pmap_page_test_mappings(m, true, false));
4208 }
4209
4210 /*
4211 * Clear the write and modified bits in each of the given page's mappings.
4212 */
4213 void
pmap_remove_write(vm_page_t m)4214 pmap_remove_write(vm_page_t m)
4215 {
4216 struct md_page *pvh;
4217 struct rwlock *lock;
4218 pmap_t pmap;
4219 pd_entry_t *l2;
4220 pt_entry_t *l3, oldl3, newl3;
4221 pv_entry_t next_pv, pv;
4222 vm_offset_t va;
4223 int md_gen, pvh_gen;
4224
4225 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4226 ("pmap_remove_write: page %p is not managed", m));
4227 vm_page_assert_busied(m);
4228
4229 if (!pmap_page_is_write_mapped(m))
4230 return;
4231 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4232 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4233 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4234 rw_rlock(&pvh_global_lock);
4235 retry_pv_loop:
4236 rw_wlock(lock);
4237 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4238 pmap = PV_PMAP(pv);
4239 if (!PMAP_TRYLOCK(pmap)) {
4240 pvh_gen = pvh->pv_gen;
4241 rw_wunlock(lock);
4242 PMAP_LOCK(pmap);
4243 rw_wlock(lock);
4244 if (pvh_gen != pvh->pv_gen) {
4245 PMAP_UNLOCK(pmap);
4246 rw_wunlock(lock);
4247 goto retry_pv_loop;
4248 }
4249 }
4250 va = pv->pv_va;
4251 l2 = pmap_l2(pmap, va);
4252 if ((pmap_load(l2) & PTE_W) != 0)
4253 (void)pmap_demote_l2_locked(pmap, l2, va, &lock);
4254 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4255 ("inconsistent pv lock %p %p for page %p",
4256 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4257 PMAP_UNLOCK(pmap);
4258 }
4259 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4260 pmap = PV_PMAP(pv);
4261 if (!PMAP_TRYLOCK(pmap)) {
4262 pvh_gen = pvh->pv_gen;
4263 md_gen = m->md.pv_gen;
4264 rw_wunlock(lock);
4265 PMAP_LOCK(pmap);
4266 rw_wlock(lock);
4267 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4268 PMAP_UNLOCK(pmap);
4269 rw_wunlock(lock);
4270 goto retry_pv_loop;
4271 }
4272 }
4273 l2 = pmap_l2(pmap, pv->pv_va);
4274 KASSERT((pmap_load(l2) & PTE_RWX) == 0,
4275 ("%s: found a 2mpage in page %p's pv list", __func__, m));
4276 l3 = pmap_l2_to_l3(l2, pv->pv_va);
4277 oldl3 = pmap_load(l3);
4278 retry:
4279 if ((oldl3 & PTE_W) != 0) {
4280 newl3 = oldl3 & ~(PTE_D | PTE_W);
4281 if (!atomic_fcmpset_long(l3, &oldl3, newl3))
4282 goto retry;
4283 if ((oldl3 & PTE_D) != 0)
4284 vm_page_dirty(m);
4285 pmap_invalidate_page(pmap, pv->pv_va);
4286 }
4287 PMAP_UNLOCK(pmap);
4288 }
4289 rw_wunlock(lock);
4290 vm_page_aflag_clear(m, PGA_WRITEABLE);
4291 rw_runlock(&pvh_global_lock);
4292 }
4293
4294 /*
4295 * pmap_ts_referenced:
4296 *
4297 * Return a count of reference bits for a page, clearing those bits.
4298 * It is not necessary for every reference bit to be cleared, but it
4299 * is necessary that 0 only be returned when there are truly no
4300 * reference bits set.
4301 *
4302 * As an optimization, update the page's dirty field if a modified bit is
4303 * found while counting reference bits. This opportunistic update can be
4304 * performed at low cost and can eliminate the need for some future calls
4305 * to pmap_is_modified(). However, since this function stops after
4306 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4307 * dirty pages. Those dirty pages will only be detected by a future call
4308 * to pmap_is_modified().
4309 */
4310 int
pmap_ts_referenced(vm_page_t m)4311 pmap_ts_referenced(vm_page_t m)
4312 {
4313 struct spglist free;
4314 struct md_page *pvh;
4315 struct rwlock *lock;
4316 pv_entry_t pv, pvf;
4317 pmap_t pmap;
4318 pd_entry_t *l2, l2e;
4319 pt_entry_t *l3, l3e;
4320 vm_paddr_t pa;
4321 vm_offset_t va;
4322 int cleared, md_gen, not_cleared, pvh_gen;
4323
4324 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4325 ("pmap_ts_referenced: page %p is not managed", m));
4326 SLIST_INIT(&free);
4327 cleared = 0;
4328 pa = VM_PAGE_TO_PHYS(m);
4329 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
4330
4331 lock = PHYS_TO_PV_LIST_LOCK(pa);
4332 rw_rlock(&pvh_global_lock);
4333 rw_wlock(lock);
4334 retry:
4335 not_cleared = 0;
4336 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4337 goto small_mappings;
4338 pv = pvf;
4339 do {
4340 pmap = PV_PMAP(pv);
4341 if (!PMAP_TRYLOCK(pmap)) {
4342 pvh_gen = pvh->pv_gen;
4343 rw_wunlock(lock);
4344 PMAP_LOCK(pmap);
4345 rw_wlock(lock);
4346 if (pvh_gen != pvh->pv_gen) {
4347 PMAP_UNLOCK(pmap);
4348 goto retry;
4349 }
4350 }
4351 va = pv->pv_va;
4352 l2 = pmap_l2(pmap, va);
4353 l2e = pmap_load(l2);
4354 if ((l2e & (PTE_W | PTE_D)) == (PTE_W | PTE_D)) {
4355 /*
4356 * Although l2e is mapping a 2MB page, because
4357 * this function is called at a 4KB page granularity,
4358 * we only update the 4KB page under test.
4359 */
4360 vm_page_dirty(m);
4361 }
4362 if ((l2e & PTE_A) != 0) {
4363 /*
4364 * Since this reference bit is shared by 512 4KB
4365 * pages, it should not be cleared every time it is
4366 * tested. Apply a simple "hash" function on the
4367 * physical page number, the virtual superpage number,
4368 * and the pmap address to select one 4KB page out of
4369 * the 512 on which testing the reference bit will
4370 * result in clearing that reference bit. This
4371 * function is designed to avoid the selection of the
4372 * same 4KB page for every 2MB page mapping.
4373 *
4374 * On demotion, a mapping that hasn't been referenced
4375 * is simply destroyed. To avoid the possibility of a
4376 * subsequent page fault on a demoted wired mapping,
4377 * always leave its reference bit set. Moreover,
4378 * since the superpage is wired, the current state of
4379 * its reference bit won't affect page replacement.
4380 */
4381 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^
4382 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
4383 (l2e & PTE_SW_WIRED) == 0) {
4384 pmap_clear_bits(l2, PTE_A);
4385 pmap_invalidate_page(pmap, va);
4386 cleared++;
4387 } else
4388 not_cleared++;
4389 }
4390 PMAP_UNLOCK(pmap);
4391 /* Rotate the PV list if it has more than one entry. */
4392 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4393 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4394 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4395 pvh->pv_gen++;
4396 }
4397 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
4398 goto out;
4399 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4400 small_mappings:
4401 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4402 goto out;
4403 pv = pvf;
4404 do {
4405 pmap = PV_PMAP(pv);
4406 if (!PMAP_TRYLOCK(pmap)) {
4407 pvh_gen = pvh->pv_gen;
4408 md_gen = m->md.pv_gen;
4409 rw_wunlock(lock);
4410 PMAP_LOCK(pmap);
4411 rw_wlock(lock);
4412 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4413 PMAP_UNLOCK(pmap);
4414 goto retry;
4415 }
4416 }
4417 l2 = pmap_l2(pmap, pv->pv_va);
4418
4419 KASSERT((pmap_load(l2) & PTE_RX) == 0,
4420 ("pmap_ts_referenced: found an invalid l2 table"));
4421
4422 l3 = pmap_l2_to_l3(l2, pv->pv_va);
4423 l3e = pmap_load(l3);
4424 if ((l3e & PTE_D) != 0)
4425 vm_page_dirty(m);
4426 if ((l3e & PTE_A) != 0) {
4427 if ((l3e & PTE_SW_WIRED) == 0) {
4428 /*
4429 * Wired pages cannot be paged out so
4430 * doing accessed bit emulation for
4431 * them is wasted effort. We do the
4432 * hard work for unwired pages only.
4433 */
4434 pmap_clear_bits(l3, PTE_A);
4435 pmap_invalidate_page(pmap, pv->pv_va);
4436 cleared++;
4437 } else
4438 not_cleared++;
4439 }
4440 PMAP_UNLOCK(pmap);
4441 /* Rotate the PV list if it has more than one entry. */
4442 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4443 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4444 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4445 m->md.pv_gen++;
4446 }
4447 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
4448 not_cleared < PMAP_TS_REFERENCED_MAX);
4449 out:
4450 rw_wunlock(lock);
4451 rw_runlock(&pvh_global_lock);
4452 vm_page_free_pages_toq(&free, false);
4453 return (cleared + not_cleared);
4454 }
4455
4456 /*
4457 * Apply the given advice to the specified range of addresses within the
4458 * given pmap. Depending on the advice, clear the referenced and/or
4459 * modified flags in each mapping and set the mapped page's dirty field.
4460 */
4461 void
pmap_advise(pmap_t pmap,vm_offset_t sva,vm_offset_t eva,int advice)4462 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4463 {
4464 }
4465
4466 /*
4467 * Clear the modify bits on the specified physical page.
4468 */
4469 void
pmap_clear_modify(vm_page_t m)4470 pmap_clear_modify(vm_page_t m)
4471 {
4472 struct md_page *pvh;
4473 struct rwlock *lock;
4474 pmap_t pmap;
4475 pv_entry_t next_pv, pv;
4476 pd_entry_t *l2, oldl2;
4477 pt_entry_t *l3;
4478 vm_offset_t va;
4479 int md_gen, pvh_gen;
4480
4481 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4482 ("pmap_clear_modify: page %p is not managed", m));
4483 vm_page_assert_busied(m);
4484
4485 if (!pmap_page_is_write_mapped(m))
4486 return;
4487
4488 /*
4489 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
4490 * If the object containing the page is locked and the page is not
4491 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
4492 */
4493 if ((m->a.flags & PGA_WRITEABLE) == 0)
4494 return;
4495 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
4496 pa_to_pvh(VM_PAGE_TO_PHYS(m));
4497 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
4498 rw_rlock(&pvh_global_lock);
4499 rw_wlock(lock);
4500 restart:
4501 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4502 pmap = PV_PMAP(pv);
4503 if (!PMAP_TRYLOCK(pmap)) {
4504 pvh_gen = pvh->pv_gen;
4505 rw_wunlock(lock);
4506 PMAP_LOCK(pmap);
4507 rw_wlock(lock);
4508 if (pvh_gen != pvh->pv_gen) {
4509 PMAP_UNLOCK(pmap);
4510 goto restart;
4511 }
4512 }
4513 va = pv->pv_va;
4514 l2 = pmap_l2(pmap, va);
4515 oldl2 = pmap_load(l2);
4516 /* If oldl2 has PTE_W set, then it also has PTE_D set. */
4517 if ((oldl2 & PTE_W) != 0 &&
4518 pmap_demote_l2_locked(pmap, l2, va, &lock) &&
4519 (oldl2 & PTE_SW_WIRED) == 0) {
4520 /*
4521 * Write protect the mapping to a single page so that
4522 * a subsequent write access may repromote.
4523 */
4524 va += VM_PAGE_TO_PHYS(m) - PTE_TO_PHYS(oldl2);
4525 l3 = pmap_l2_to_l3(l2, va);
4526 pmap_clear_bits(l3, PTE_D | PTE_W);
4527 vm_page_dirty(m);
4528 pmap_invalidate_page(pmap, va);
4529 }
4530 PMAP_UNLOCK(pmap);
4531 }
4532 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4533 pmap = PV_PMAP(pv);
4534 if (!PMAP_TRYLOCK(pmap)) {
4535 md_gen = m->md.pv_gen;
4536 pvh_gen = pvh->pv_gen;
4537 rw_wunlock(lock);
4538 PMAP_LOCK(pmap);
4539 rw_wlock(lock);
4540 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4541 PMAP_UNLOCK(pmap);
4542 goto restart;
4543 }
4544 }
4545 l2 = pmap_l2(pmap, pv->pv_va);
4546 KASSERT((pmap_load(l2) & PTE_RWX) == 0,
4547 ("%s: found a 2mpage in page %p's pv list", __func__, m));
4548 l3 = pmap_l2_to_l3(l2, pv->pv_va);
4549 if ((pmap_load(l3) & (PTE_D | PTE_W)) == (PTE_D | PTE_W)) {
4550 pmap_clear_bits(l3, PTE_D | PTE_W);
4551 pmap_invalidate_page(pmap, pv->pv_va);
4552 }
4553 PMAP_UNLOCK(pmap);
4554 }
4555 rw_wunlock(lock);
4556 rw_runlock(&pvh_global_lock);
4557 }
4558
4559 void *
pmap_mapbios(vm_paddr_t pa,vm_size_t size)4560 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
4561 {
4562
4563 return ((void *)PHYS_TO_DMAP(pa));
4564 }
4565
4566 void
pmap_unmapbios(void * p,vm_size_t size)4567 pmap_unmapbios(void *p, vm_size_t size)
4568 {
4569 }
4570
4571 /*
4572 * Sets the memory attribute for the specified page.
4573 */
4574 void
pmap_page_set_memattr(vm_page_t m,vm_memattr_t ma)4575 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
4576 {
4577
4578 m->md.pv_memattr = ma;
4579
4580 /*
4581 * If "m" is a normal page, update its direct mapping. This update
4582 * can be relied upon to perform any cache operations that are
4583 * required for data coherence.
4584 */
4585 if ((m->flags & PG_FICTITIOUS) == 0 &&
4586 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
4587 m->md.pv_memattr) != 0)
4588 panic("memory attribute change on the direct map failed");
4589 }
4590
4591 /*
4592 * Changes the specified virtual address range's memory type to that given by
4593 * the parameter "mode". The specified virtual address range must be
4594 * completely contained within either the direct map or the kernel map.
4595 *
4596 * Returns zero if the change completed successfully, and either EINVAL or
4597 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
4598 * of the virtual address range was not mapped, and ENOMEM is returned if
4599 * there was insufficient memory available to complete the change. In the
4600 * latter case, the memory type may have been changed on some part of the
4601 * virtual address range.
4602 */
4603 int
pmap_change_attr(vm_offset_t va,vm_size_t size,int mode)4604 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
4605 {
4606 int error;
4607
4608 PMAP_LOCK(kernel_pmap);
4609 error = pmap_change_attr_locked(va, size, mode);
4610 PMAP_UNLOCK(kernel_pmap);
4611 return (error);
4612 }
4613
4614 static int
pmap_change_attr_locked(vm_offset_t va,vm_size_t size,int mode)4615 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
4616 {
4617 vm_offset_t base, offset, tmpva;
4618 pd_entry_t *l1, l1e;
4619 pd_entry_t *l2, l2e;
4620 pt_entry_t *l3, l3e;
4621
4622 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
4623 base = trunc_page(va);
4624 offset = va & PAGE_MASK;
4625 size = round_page(offset + size);
4626
4627 if (!VIRT_IN_DMAP(base) &&
4628 !(base >= VM_MIN_KERNEL_ADDRESS && base < VM_MAX_KERNEL_ADDRESS))
4629 return (EINVAL);
4630
4631 for (tmpva = base; tmpva < base + size; ) {
4632 l1 = pmap_l1(kernel_pmap, tmpva);
4633 if (l1 == NULL || ((l1e = pmap_load(l1)) & PTE_V) == 0)
4634 return (EINVAL);
4635 if ((l1e & PTE_RWX) != 0) {
4636 /*
4637 * TODO: Demote if attributes don't match and there
4638 * isn't an L1 page left in the range, and update the
4639 * L1 entry if the attributes don't match but there is
4640 * an L1 page left in the range, once we support the
4641 * upcoming Svpbmt extension.
4642 */
4643 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
4644 continue;
4645 }
4646 l2 = pmap_l1_to_l2(l1, tmpva);
4647 if (l2 == NULL || ((l2e = pmap_load(l2)) & PTE_V) == 0)
4648 return (EINVAL);
4649 if ((l2e & PTE_RWX) != 0) {
4650 /*
4651 * TODO: Demote if attributes don't match and there
4652 * isn't an L2 page left in the range, and update the
4653 * L2 entry if the attributes don't match but there is
4654 * an L2 page left in the range, once we support the
4655 * upcoming Svpbmt extension.
4656 */
4657 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
4658 continue;
4659 }
4660 l3 = pmap_l2_to_l3(l2, tmpva);
4661 if (l3 == NULL || ((l3e = pmap_load(l3)) & PTE_V) == 0)
4662 return (EINVAL);
4663 /*
4664 * TODO: Update the L3 entry if the attributes don't match once
4665 * we support the upcoming Svpbmt extension.
4666 */
4667 tmpva += PAGE_SIZE;
4668 }
4669
4670 return (0);
4671 }
4672
4673 /*
4674 * Perform the pmap work for mincore(2). If the page is not both referenced and
4675 * modified by this pmap, returns its physical address so that the caller can
4676 * find other mappings.
4677 */
4678 int
pmap_mincore(pmap_t pmap,vm_offset_t addr,vm_paddr_t * pap)4679 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
4680 {
4681 pt_entry_t *l2, *l3, tpte;
4682 vm_paddr_t pa;
4683 int val;
4684 bool managed;
4685
4686 PMAP_LOCK(pmap);
4687 l2 = pmap_l2(pmap, addr);
4688 if (l2 != NULL && ((tpte = pmap_load(l2)) & PTE_V) != 0) {
4689 if ((tpte & PTE_RWX) != 0) {
4690 pa = PTE_TO_PHYS(tpte) | (addr & L2_OFFSET);
4691 val = MINCORE_INCORE | MINCORE_PSIND(1);
4692 } else {
4693 l3 = pmap_l2_to_l3(l2, addr);
4694 tpte = pmap_load(l3);
4695 if ((tpte & PTE_V) == 0) {
4696 PMAP_UNLOCK(pmap);
4697 return (0);
4698 }
4699 pa = PTE_TO_PHYS(tpte) | (addr & L3_OFFSET);
4700 val = MINCORE_INCORE;
4701 }
4702
4703 if ((tpte & PTE_D) != 0)
4704 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4705 if ((tpte & PTE_A) != 0)
4706 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4707 managed = (tpte & PTE_SW_MANAGED) == PTE_SW_MANAGED;
4708 } else {
4709 managed = false;
4710 val = 0;
4711 }
4712 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
4713 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
4714 *pap = pa;
4715 }
4716 PMAP_UNLOCK(pmap);
4717 return (val);
4718 }
4719
4720 void
pmap_activate_sw(struct thread * td)4721 pmap_activate_sw(struct thread *td)
4722 {
4723 pmap_t oldpmap, pmap;
4724 u_int hart;
4725
4726 oldpmap = PCPU_GET(curpmap);
4727 pmap = vmspace_pmap(td->td_proc->p_vmspace);
4728 if (pmap == oldpmap)
4729 return;
4730 csr_write(satp, pmap->pm_satp);
4731
4732 hart = PCPU_GET(hart);
4733 #ifdef SMP
4734 CPU_SET_ATOMIC(hart, &pmap->pm_active);
4735 CPU_CLR_ATOMIC(hart, &oldpmap->pm_active);
4736 #else
4737 CPU_SET(hart, &pmap->pm_active);
4738 CPU_CLR(hart, &oldpmap->pm_active);
4739 #endif
4740 PCPU_SET(curpmap, pmap);
4741
4742 sfence_vma();
4743 }
4744
4745 void
pmap_activate(struct thread * td)4746 pmap_activate(struct thread *td)
4747 {
4748
4749 critical_enter();
4750 pmap_activate_sw(td);
4751 critical_exit();
4752 }
4753
4754 void
pmap_activate_boot(pmap_t pmap)4755 pmap_activate_boot(pmap_t pmap)
4756 {
4757 u_int hart;
4758
4759 hart = PCPU_GET(hart);
4760 #ifdef SMP
4761 CPU_SET_ATOMIC(hart, &pmap->pm_active);
4762 #else
4763 CPU_SET(hart, &pmap->pm_active);
4764 #endif
4765 PCPU_SET(curpmap, pmap);
4766 }
4767
4768 void
pmap_active_cpus(pmap_t pmap,cpuset_t * res)4769 pmap_active_cpus(pmap_t pmap, cpuset_t *res)
4770 {
4771 *res = pmap->pm_active;
4772 }
4773
4774 void
pmap_sync_icache(pmap_t pmap,vm_offset_t va,vm_size_t sz)4775 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
4776 {
4777 cpuset_t mask;
4778
4779 /*
4780 * From the RISC-V User-Level ISA V2.2:
4781 *
4782 * "To make a store to instruction memory visible to all
4783 * RISC-V harts, the writing hart has to execute a data FENCE
4784 * before requesting that all remote RISC-V harts execute a
4785 * FENCE.I."
4786 *
4787 * However, this is slightly misleading; we still need to
4788 * perform a FENCE.I for the local hart, as FENCE does nothing
4789 * for its icache. FENCE.I alone is also sufficient for the
4790 * local hart.
4791 */
4792 sched_pin();
4793 mask = all_harts;
4794 CPU_CLR(PCPU_GET(hart), &mask);
4795 fence_i();
4796 if (!CPU_EMPTY(&mask) && smp_started) {
4797 fence();
4798 sbi_remote_fence_i(mask.__bits);
4799 }
4800 sched_unpin();
4801 }
4802
4803 /*
4804 * Increase the starting virtual address of the given mapping if a
4805 * different alignment might result in more superpage mappings.
4806 */
4807 void
pmap_align_superpage(vm_object_t object,vm_ooffset_t offset,vm_offset_t * addr,vm_size_t size)4808 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
4809 vm_offset_t *addr, vm_size_t size)
4810 {
4811 vm_offset_t superpage_offset;
4812
4813 if (size < L2_SIZE)
4814 return;
4815 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
4816 offset += ptoa(object->pg_color);
4817 superpage_offset = offset & L2_OFFSET;
4818 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
4819 (*addr & L2_OFFSET) == superpage_offset)
4820 return;
4821 if ((*addr & L2_OFFSET) < superpage_offset)
4822 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
4823 else
4824 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
4825 }
4826
4827 /**
4828 * Get the kernel virtual address of a set of physical pages. If there are
4829 * physical addresses not covered by the DMAP perform a transient mapping
4830 * that will be removed when calling pmap_unmap_io_transient.
4831 *
4832 * \param page The pages the caller wishes to obtain the virtual
4833 * address on the kernel memory map.
4834 * \param vaddr On return contains the kernel virtual memory address
4835 * of the pages passed in the page parameter.
4836 * \param count Number of pages passed in.
4837 * \param can_fault true if the thread using the mapped pages can take
4838 * page faults, false otherwise.
4839 *
4840 * \returns true if the caller must call pmap_unmap_io_transient when
4841 * finished or false otherwise.
4842 *
4843 */
4844 bool
pmap_map_io_transient(vm_page_t page[],vm_offset_t vaddr[],int count,bool can_fault)4845 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
4846 bool can_fault)
4847 {
4848 vm_paddr_t paddr;
4849 bool needs_mapping;
4850 int error __diagused, i;
4851
4852 /*
4853 * Allocate any KVA space that we need, this is done in a separate
4854 * loop to prevent calling vmem_alloc while pinned.
4855 */
4856 needs_mapping = false;
4857 for (i = 0; i < count; i++) {
4858 paddr = VM_PAGE_TO_PHYS(page[i]);
4859 if (__predict_false(paddr >= DMAP_MAX_PHYSADDR)) {
4860 error = vmem_alloc(kernel_arena, PAGE_SIZE,
4861 M_BESTFIT | M_WAITOK, &vaddr[i]);
4862 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
4863 needs_mapping = true;
4864 } else {
4865 vaddr[i] = PHYS_TO_DMAP(paddr);
4866 }
4867 }
4868
4869 /* Exit early if everything is covered by the DMAP */
4870 if (!needs_mapping)
4871 return (false);
4872
4873 if (!can_fault)
4874 sched_pin();
4875 for (i = 0; i < count; i++) {
4876 paddr = VM_PAGE_TO_PHYS(page[i]);
4877 if (paddr >= DMAP_MAX_PHYSADDR) {
4878 panic(
4879 "pmap_map_io_transient: TODO: Map out of DMAP data");
4880 }
4881 }
4882
4883 return (needs_mapping);
4884 }
4885
4886 void
pmap_unmap_io_transient(vm_page_t page[],vm_offset_t vaddr[],int count,bool can_fault)4887 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
4888 bool can_fault)
4889 {
4890 vm_paddr_t paddr;
4891 int i;
4892
4893 if (!can_fault)
4894 sched_unpin();
4895 for (i = 0; i < count; i++) {
4896 paddr = VM_PAGE_TO_PHYS(page[i]);
4897 if (paddr >= DMAP_MAX_PHYSADDR) {
4898 panic("RISCVTODO: pmap_unmap_io_transient: Unmap data");
4899 }
4900 }
4901 }
4902
4903 bool
pmap_is_valid_memattr(pmap_t pmap __unused,vm_memattr_t mode)4904 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
4905 {
4906
4907 return (mode >= VM_MEMATTR_DEVICE && mode <= VM_MEMATTR_WRITE_BACK);
4908 }
4909
4910 bool
pmap_get_tables(pmap_t pmap,vm_offset_t va,pd_entry_t ** l1,pd_entry_t ** l2,pt_entry_t ** l3)4911 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l1, pd_entry_t **l2,
4912 pt_entry_t **l3)
4913 {
4914 pd_entry_t *l1p, *l2p;
4915
4916 /* Get l1 directory entry. */
4917 l1p = pmap_l1(pmap, va);
4918 *l1 = l1p;
4919
4920 if (l1p == NULL || (pmap_load(l1p) & PTE_V) == 0)
4921 return (false);
4922
4923 if ((pmap_load(l1p) & PTE_RX) != 0) {
4924 *l2 = NULL;
4925 *l3 = NULL;
4926 return (true);
4927 }
4928
4929 /* Get l2 directory entry. */
4930 l2p = pmap_l1_to_l2(l1p, va);
4931 *l2 = l2p;
4932
4933 if (l2p == NULL || (pmap_load(l2p) & PTE_V) == 0)
4934 return (false);
4935
4936 if ((pmap_load(l2p) & PTE_RX) != 0) {
4937 *l3 = NULL;
4938 return (true);
4939 }
4940
4941 /* Get l3 page table entry. */
4942 *l3 = pmap_l2_to_l3(l2p, va);
4943
4944 return (true);
4945 }
4946
4947 /*
4948 * Track a range of the kernel's virtual address space that is contiguous
4949 * in various mapping attributes.
4950 */
4951 struct pmap_kernel_map_range {
4952 vm_offset_t sva;
4953 pt_entry_t attrs;
4954 int l3pages;
4955 int l2pages;
4956 int l1pages;
4957 };
4958
4959 static void
sysctl_kmaps_dump(struct sbuf * sb,struct pmap_kernel_map_range * range,vm_offset_t eva)4960 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
4961 vm_offset_t eva)
4962 {
4963
4964 if (eva <= range->sva)
4965 return;
4966
4967 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c %d %d %d\n",
4968 range->sva, eva,
4969 (range->attrs & PTE_W) == PTE_W ? 'w' : '-',
4970 (range->attrs & PTE_X) == PTE_X ? 'x' : '-',
4971 (range->attrs & PTE_U) == PTE_U ? 'u' : 's',
4972 (range->attrs & PTE_G) == PTE_G ? 'g' : '-',
4973 range->l1pages, range->l2pages, range->l3pages);
4974
4975 /* Reset to sentinel value. */
4976 range->sva = 0xfffffffffffffffful;
4977 }
4978
4979 /*
4980 * Determine whether the attributes specified by a page table entry match those
4981 * being tracked by the current range.
4982 */
4983 static bool
sysctl_kmaps_match(struct pmap_kernel_map_range * range,pt_entry_t attrs)4984 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
4985 {
4986
4987 return (range->attrs == attrs);
4988 }
4989
4990 static void
sysctl_kmaps_reinit(struct pmap_kernel_map_range * range,vm_offset_t va,pt_entry_t attrs)4991 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
4992 pt_entry_t attrs)
4993 {
4994
4995 memset(range, 0, sizeof(*range));
4996 range->sva = va;
4997 range->attrs = attrs;
4998 }
4999
5000 /*
5001 * Given a leaf PTE, derive the mapping's attributes. If they do not match
5002 * those of the current run, dump the address range and its attributes, and
5003 * begin a new run.
5004 */
5005 static void
sysctl_kmaps_check(struct sbuf * sb,struct pmap_kernel_map_range * range,vm_offset_t va,pd_entry_t l1e,pd_entry_t l2e,pt_entry_t l3e)5006 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
5007 vm_offset_t va, pd_entry_t l1e, pd_entry_t l2e, pt_entry_t l3e)
5008 {
5009 pt_entry_t attrs;
5010
5011 /* The PTE global bit is inherited by lower levels. */
5012 attrs = l1e & PTE_G;
5013 if ((l1e & PTE_RWX) != 0)
5014 attrs |= l1e & (PTE_RWX | PTE_U);
5015 else if (l2e != 0)
5016 attrs |= l2e & PTE_G;
5017 if ((l2e & PTE_RWX) != 0)
5018 attrs |= l2e & (PTE_RWX | PTE_U);
5019 else if (l3e != 0)
5020 attrs |= l3e & (PTE_RWX | PTE_U | PTE_G);
5021
5022 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
5023 sysctl_kmaps_dump(sb, range, va);
5024 sysctl_kmaps_reinit(range, va, attrs);
5025 }
5026 }
5027
5028 static int
sysctl_kmaps(SYSCTL_HANDLER_ARGS)5029 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
5030 {
5031 struct pmap_kernel_map_range range;
5032 struct sbuf sbuf, *sb;
5033 pd_entry_t *l1, l1e, *l2, l2e;
5034 pt_entry_t *l3, l3e;
5035 vm_offset_t sva;
5036 vm_paddr_t pa;
5037 int error, i, j, k;
5038
5039 error = sysctl_wire_old_buffer(req, 0);
5040 if (error != 0)
5041 return (error);
5042 sb = &sbuf;
5043 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
5044
5045 /* Sentinel value. */
5046 range.sva = 0xfffffffffffffffful;
5047
5048 /*
5049 * Iterate over the kernel page tables without holding the kernel pmap
5050 * lock. Kernel page table pages are never freed, so at worst we will
5051 * observe inconsistencies in the output.
5052 */
5053 sva = VM_MIN_KERNEL_ADDRESS;
5054 for (i = pmap_l1_index(sva); i < Ln_ENTRIES; i++) {
5055 if (i == pmap_l1_index(DMAP_MIN_ADDRESS))
5056 sbuf_printf(sb, "\nDirect map:\n");
5057 else if (i == pmap_l1_index(VM_MIN_KERNEL_ADDRESS))
5058 sbuf_printf(sb, "\nKernel map:\n");
5059
5060 l1 = pmap_l1(kernel_pmap, sva);
5061 l1e = pmap_load(l1);
5062 if ((l1e & PTE_V) == 0) {
5063 sysctl_kmaps_dump(sb, &range, sva);
5064 sva += L1_SIZE;
5065 continue;
5066 }
5067 if ((l1e & PTE_RWX) != 0) {
5068 sysctl_kmaps_check(sb, &range, sva, l1e, 0, 0);
5069 range.l1pages++;
5070 sva += L1_SIZE;
5071 continue;
5072 }
5073 pa = PTE_TO_PHYS(l1e);
5074 l2 = (pd_entry_t *)PHYS_TO_DMAP(pa);
5075
5076 for (j = pmap_l2_index(sva); j < Ln_ENTRIES; j++) {
5077 l2e = l2[j];
5078 if ((l2e & PTE_V) == 0) {
5079 sysctl_kmaps_dump(sb, &range, sva);
5080 sva += L2_SIZE;
5081 continue;
5082 }
5083 if ((l2e & PTE_RWX) != 0) {
5084 sysctl_kmaps_check(sb, &range, sva, l1e, l2e, 0);
5085 range.l2pages++;
5086 sva += L2_SIZE;
5087 continue;
5088 }
5089 pa = PTE_TO_PHYS(l2e);
5090 l3 = (pd_entry_t *)PHYS_TO_DMAP(pa);
5091
5092 for (k = pmap_l3_index(sva); k < Ln_ENTRIES; k++,
5093 sva += L3_SIZE) {
5094 l3e = l3[k];
5095 if ((l3e & PTE_V) == 0) {
5096 sysctl_kmaps_dump(sb, &range, sva);
5097 continue;
5098 }
5099 sysctl_kmaps_check(sb, &range, sva,
5100 l1e, l2e, l3e);
5101 range.l3pages++;
5102 }
5103 }
5104 }
5105
5106 error = sbuf_finish(sb);
5107 sbuf_delete(sb);
5108 return (error);
5109 }
5110 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
5111 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE | CTLFLAG_SKIP,
5112 NULL, 0, sysctl_kmaps, "A",
5113 "Dump kernel address layout");
5114