1 /*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
5 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
6 * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
7 * Copyright (C) 2007 Carl-Daniel Hailfinger
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19 /*
20 * Contains the board specific flash enables.
21 */
22
23 #include <strings.h>
24 #include <string.h>
25 #include <stdlib.h>
26 #include "flash.h"
27 #include "programmer.h"
28 #include "hwaccess.h"
29
30 #if defined(__i386__) || defined(__x86_64__)
31 /*
32 * Helper functions for many Winbond Super I/Os of the W836xx range.
33 */
34 /* Enter extended functions */
w836xx_ext_enter(uint16_t port)35 void w836xx_ext_enter(uint16_t port)
36 {
37 OUTB(0x87, port);
38 OUTB(0x87, port);
39 }
40
41 /* Leave extended functions */
w836xx_ext_leave(uint16_t port)42 void w836xx_ext_leave(uint16_t port)
43 {
44 OUTB(0xAA, port);
45 }
46
47 /* Generic Super I/O helper functions */
sio_read(uint16_t port,uint8_t reg)48 uint8_t sio_read(uint16_t port, uint8_t reg)
49 {
50 OUTB(reg, port);
51 return INB(port + 1);
52 }
53
sio_write(uint16_t port,uint8_t reg,uint8_t data)54 void sio_write(uint16_t port, uint8_t reg, uint8_t data)
55 {
56 OUTB(reg, port);
57 OUTB(data, port + 1);
58 }
59
sio_mask(uint16_t port,uint8_t reg,uint8_t data,uint8_t mask)60 void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
61 {
62 uint8_t tmp;
63
64 OUTB(reg, port);
65 tmp = INB(port + 1) & ~mask;
66 OUTB(tmp | (data & mask), port + 1);
67 }
68
69 /* Winbond W83697 documentation indicates that the index register has to be written for each access. */
sio_mask_alzheimer(uint16_t port,uint8_t reg,uint8_t data,uint8_t mask)70 static void sio_mask_alzheimer(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
71 {
72 uint8_t tmp;
73
74 OUTB(reg, port);
75 tmp = INB(port + 1) & ~mask;
76 OUTB(reg, port);
77 OUTB(tmp | (data & mask), port + 1);
78 }
79
80 /* Not used yet. */
81 #if 0
82 static int enable_flash_decode_superio(void)
83 {
84 int ret;
85 uint8_t tmp;
86
87 switch (superio.vendor) {
88 case SUPERIO_VENDOR_NONE:
89 ret = -1;
90 break;
91 case SUPERIO_VENDOR_ITE:
92 enter_conf_mode_ite(superio.port);
93 /* Enable flash mapping. Works for most old ITE style Super I/O. */
94 tmp = sio_read(superio.port, 0x24);
95 tmp |= 0xfc;
96 sio_write(superio.port, 0x24, tmp);
97 exit_conf_mode_ite(superio.port);
98 ret = 0;
99 break;
100 default:
101 msg_pdbg("Unhandled Super I/O type!\n");
102 ret = -1;
103 break;
104 }
105 return ret;
106 }
107 #endif
108
109 /*
110 * SMSC FDC37B787: Raise GPIO50
111 */
fdc37b787_gpio50_raise(uint16_t port)112 static int fdc37b787_gpio50_raise(uint16_t port)
113 {
114 uint8_t id, val;
115
116 OUTB(0x55, port); /* enter conf mode */
117 id = sio_read(port, 0x20);
118 if (id != 0x44) {
119 msg_perr("\nERROR: FDC37B787: Wrong ID 0x%02X.\n", id);
120 OUTB(0xAA, port); /* leave conf mode */
121 return -1;
122 }
123
124 sio_write(port, 0x07, 0x08); /* Select Aux I/O subdevice */
125
126 val = sio_read(port, 0xC8); /* GP50 */
127 if ((val & 0x1B) != 0x10) /* output, no invert, GPIO */
128 {
129 msg_perr("\nERROR: GPIO50 mode 0x%02X unexpected.\n", val);
130 OUTB(0xAA, port);
131 return -1;
132 }
133
134 sio_mask(port, 0xF9, 0x01, 0x01);
135
136 OUTB(0xAA, port); /* Leave conf mode */
137 return 0;
138 }
139
140 /*
141 * Suited for:
142 * - Nokia IP530: Intel 440BX + PIIX4 + FDC37B787
143 */
fdc37b787_gpio50_raise_3f0(void)144 static int fdc37b787_gpio50_raise_3f0(void)
145 {
146 return fdc37b787_gpio50_raise(0x3f0);
147 }
148
149 struct winbond_mux {
150 uint8_t reg; /* 0 if the corresponding pin is not muxed */
151 uint8_t data; /* reg/data/mask may be directly ... */
152 uint8_t mask; /* ... passed to sio_mask */
153 };
154
155 struct winbond_port {
156 const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */
157 uint8_t ldn; /* LDN this GPIO register is located in */
158 uint8_t enable_bit; /* bit in 0x30 of that LDN to enable
159 the GPIO port */
160 uint8_t base; /* base register in that LDN for the port */
161 };
162
163 struct winbond_chip {
164 uint8_t device_id; /* reg 0x20 of the expected w83626x */
165 uint8_t gpio_port_count;
166 const struct winbond_port *port;
167 };
168
169
170 #define UNIMPLEMENTED_PORT {NULL, 0, 0, 0}
171
172 enum winbond_id {
173 WINBOND_W83627HF_ID = 0x52,
174 WINBOND_W83627EHF_ID = 0x88,
175 WINBOND_W83627THF_ID = 0x82,
176 WINBOND_W83697HF_ID = 0x60,
177 };
178
179 static const struct winbond_mux w83627hf_port2_mux[8] = {
180 {0x2A, 0x01, 0x01}, /* or MIDI */
181 {0x2B, 0x80, 0x80}, /* or SPI */
182 {0x2B, 0x40, 0x40}, /* or SPI */
183 {0x2B, 0x20, 0x20}, /* or power LED */
184 {0x2B, 0x10, 0x10}, /* or watchdog */
185 {0x2B, 0x08, 0x08}, /* or infra red */
186 {0x2B, 0x04, 0x04}, /* or infra red */
187 {0x2B, 0x03, 0x03} /* or IRQ1 input */
188 };
189
190 static const struct winbond_port w83627hf[3] = {
191 UNIMPLEMENTED_PORT,
192 {w83627hf_port2_mux, 0x08, 0, 0xF0},
193 UNIMPLEMENTED_PORT,
194 };
195
196 static const struct winbond_mux w83627ehf_port2_mux[8] = {
197 {0x29, 0x06, 0x02}, /* or MIDI */
198 {0x29, 0x06, 0x02},
199 {0x24, 0x02, 0x00}, /* or SPI ROM interface */
200 {0x24, 0x02, 0x00},
201 {0x2A, 0x01, 0x01}, /* or keyboard/mouse interface */
202 {0x2A, 0x01, 0x01},
203 {0x2A, 0x01, 0x01},
204 {0x2A, 0x01, 0x01},
205 };
206
207 static const struct winbond_port w83627ehf[6] = {
208 UNIMPLEMENTED_PORT,
209 {w83627ehf_port2_mux, 0x09, 0, 0xE3},
210 UNIMPLEMENTED_PORT,
211 UNIMPLEMENTED_PORT,
212 UNIMPLEMENTED_PORT,
213 UNIMPLEMENTED_PORT,
214 };
215
216 static const struct winbond_mux w83627thf_port4_mux[8] = {
217 {0x2D, 0x01, 0x01}, /* or watchdog or VID level strap */
218 {0x2D, 0x02, 0x02}, /* or resume reset */
219 {0x2D, 0x04, 0x04}, /* or S3 input */
220 {0x2D, 0x08, 0x08}, /* or PSON# */
221 {0x2D, 0x10, 0x10}, /* or PWROK */
222 {0x2D, 0x20, 0x20}, /* or suspend LED */
223 {0x2D, 0x40, 0x40}, /* or panel switch input */
224 {0x2D, 0x80, 0x80}, /* or panel switch output */
225 };
226
227 static const struct winbond_port w83627thf[5] = {
228 UNIMPLEMENTED_PORT, /* GPIO1 */
229 UNIMPLEMENTED_PORT, /* GPIO2 */
230 UNIMPLEMENTED_PORT, /* GPIO3 */
231 {w83627thf_port4_mux, 0x09, 1, 0xF4},
232 UNIMPLEMENTED_PORT, /* GPIO5 */
233 };
234
235 static const struct winbond_chip winbond_chips[] = {
236 {WINBOND_W83627HF_ID, ARRAY_SIZE(w83627hf), w83627hf },
237 {WINBOND_W83627EHF_ID, ARRAY_SIZE(w83627ehf), w83627ehf},
238 {WINBOND_W83627THF_ID, ARRAY_SIZE(w83627thf), w83627thf},
239 };
240
241 #define WINBOND_SUPERIO_PORT1 0x2e
242 #define WINBOND_SUPERIO_PORT2 0x4e
243
244 /* We don't really care about the hardware monitor, but it offers better (more specific) device ID info than
245 * the simple device ID in the normal configuration registers.
246 * Note: This function expects to be called while the Super I/O is in config mode.
247 */
w836xx_deviceid_hwmon(uint16_t sio_port)248 static uint8_t w836xx_deviceid_hwmon(uint16_t sio_port)
249 {
250 uint16_t hwmport;
251 uint16_t hwm_vendorid;
252 uint8_t hwm_deviceid;
253
254 sio_write(sio_port, 0x07, 0x0b); /* Select LDN 0xb (HWM). */
255 if ((sio_read(sio_port, 0x30) & (1 << 0)) != (1 << 0)) {
256 msg_pinfo("W836xx hardware monitor disabled or does not exist.\n");
257 return 0;
258 }
259 /* Get HWM base address (stored in LDN 0xb, index 0x60/0x61). */
260 hwmport = sio_read(sio_port, 0x60) << 8;
261 hwmport |= sio_read(sio_port, 0x61);
262 /* HWM address register = HWM base address + 5. */
263 hwmport += 5;
264 msg_pdbg2("W836xx Hardware Monitor at port %04x\n", hwmport);
265 /* FIXME: This busy check should happen before each HWM access. */
266 if (INB(hwmport) & 0x80) {
267 msg_pinfo("W836xx hardware monitor busy, ignoring it.\n");
268 return 0;
269 }
270 /* Set HBACS=1. */
271 sio_mask_alzheimer(hwmport, 0x4e, 0x80, 0x80);
272 /* Read upper byte of vendor ID. */
273 hwm_vendorid = sio_read(hwmport, 0x4f) << 8;
274 /* Set HBACS=0. */
275 sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x80);
276 /* Read lower byte of vendor ID. */
277 hwm_vendorid |= sio_read(hwmport, 0x4f);
278 if (hwm_vendorid != 0x5ca3) {
279 msg_pinfo("W836xx hardware monitor vendor ID weirdness: expected 0x5ca3, got %04x\n",
280 hwm_vendorid);
281 return 0;
282 }
283 /* Set Bank=0. */
284 sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x07);
285 /* Read "chip" ID. We call this one the device ID. */
286 hwm_deviceid = sio_read(hwmport, 0x58);
287 return hwm_deviceid;
288 }
289
probe_superio_winbond(void)290 void probe_superio_winbond(void)
291 {
292 struct superio s = {0};
293 uint16_t winbond_ports[] = {WINBOND_SUPERIO_PORT1, WINBOND_SUPERIO_PORT2, 0};
294 uint16_t *i = winbond_ports;
295 uint8_t model;
296 uint8_t tmp;
297
298 s.vendor = SUPERIO_VENDOR_WINBOND;
299 for (; *i; i++) {
300 s.port = *i;
301 /* If we're already in Super I/O config more, the W836xx enter sequence won't hurt. */
302 w836xx_ext_enter(s.port);
303 model = sio_read(s.port, 0x20);
304 /* No response, no point leaving the config mode. */
305 if (model == 0xff)
306 continue;
307 /* Try to leave config mode. If the ID register is still readable, it's not a Winbond chip. */
308 w836xx_ext_leave(s.port);
309 if (model == sio_read(s.port, 0x20)) {
310 msg_pdbg("W836xx enter config mode worked or we were already in config mode. W836xx "
311 "leave config mode had no effect.\n");
312 if (model == 0x87) {
313 /* ITE IT8707F and IT8710F are special: They need the W837xx enter sequence,
314 * but they want the ITE exit sequence. Handle them here.
315 */
316 tmp = sio_read(s.port, 0x21);
317 switch (tmp) {
318 case 0x07:
319 case 0x10:
320 s.vendor = SUPERIO_VENDOR_ITE;
321 s.model = (0x87 << 8) | tmp ;
322 msg_pdbg("Found ITE Super I/O, ID 0x%04hx on port "
323 "0x%x\n", s.model, s.port);
324 register_superio(s);
325 /* Exit ITE config mode. */
326 exit_conf_mode_ite(s.port);
327 /* Restore vendor for next loop iteration. */
328 s.vendor = SUPERIO_VENDOR_WINBOND;
329 continue;
330 }
331 }
332 msg_pdbg("Active config mode, unknown reg 0x20 ID: %02x.\n", model);
333 continue;
334 }
335 /* The Super I/O reacts to W836xx enter and exit config mode, it's probably Winbond. */
336 w836xx_ext_enter(s.port);
337 s.model = sio_read(s.port, 0x20);
338 switch (s.model) {
339 case WINBOND_W83627HF_ID:
340 case WINBOND_W83627EHF_ID:
341 case WINBOND_W83627THF_ID:
342 msg_pdbg("Found Winbond Super I/O, id 0x%02hx\n", s.model);
343 register_superio(s);
344 break;
345 case WINBOND_W83697HF_ID:
346 /* This code is extremely paranoid. */
347 tmp = sio_read(s.port, 0x26) & 0x40;
348 if (((tmp == 0x00) && (s.port != WINBOND_SUPERIO_PORT1)) ||
349 ((tmp == 0x40) && (s.port != WINBOND_SUPERIO_PORT2))) {
350 msg_pdbg("Winbond Super I/O probe weirdness: Port mismatch for ID "
351 "0x%02x at port 0x%04x\n", s.model, s.port);
352 break;
353 }
354 tmp = w836xx_deviceid_hwmon(s.port);
355 /* FIXME: This might be too paranoid... */
356 if (!tmp) {
357 msg_pdbg("Probably not a Winbond Super I/O\n");
358 break;
359 }
360 if (tmp != s.model) {
361 msg_pinfo("W83 series hardware monitor device ID weirdness: expected 0x%02x, "
362 "got 0x%02x\n", WINBOND_W83697HF_ID, tmp);
363 break;
364 }
365 msg_pinfo("Found Winbond Super I/O, id 0x%02hx\n", s.model);
366 register_superio(s);
367 break;
368 }
369 w836xx_ext_leave(s.port);
370 }
371 return;
372 }
373
winbond_superio_chipdef(void)374 static const struct winbond_chip *winbond_superio_chipdef(void)
375 {
376 int i;
377 unsigned int j;
378
379 for (i = 0; i < superio_count; i++) {
380 if (superios[i].vendor != SUPERIO_VENDOR_WINBOND)
381 continue;
382 for (j = 0; j < ARRAY_SIZE(winbond_chips); j++)
383 if (winbond_chips[j].device_id == superios[i].model)
384 return &winbond_chips[j];
385 }
386 return NULL;
387 }
388
389 /*
390 * The chipid parameter goes away as soon as we have Super I/O matching in the
391 * board enable table. The call to winbond_superio_detect() goes away as
392 * soon as we have generic Super I/O detection code.
393 */
winbond_gpio_set(uint16_t base,enum winbond_id chipid,int pin,int raise)394 static int winbond_gpio_set(uint16_t base, enum winbond_id chipid,
395 int pin, int raise)
396 {
397 const struct winbond_chip *chip = NULL;
398 const struct winbond_port *gpio;
399 int port = pin / 10;
400 int bit = pin % 10;
401
402 chip = winbond_superio_chipdef();
403 if (!chip) {
404 msg_perr("\nERROR: No supported Winbond Super I/O found\n");
405 return -1;
406 }
407 if (chip->device_id != chipid) {
408 msg_perr("\nERROR: Found Winbond chip with ID 0x%x, "
409 "expected %x\n", chip->device_id, chipid);
410 return -1;
411 }
412 if (bit >= 8 || port == 0 || port > chip->gpio_port_count) {
413 msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n",
414 pin);
415 return -1;
416 }
417
418 gpio = &chip->port[port - 1];
419
420 if (gpio->ldn == 0) {
421 msg_perr("\nERROR: GPIO%d is not supported yet on this"
422 " winbond chip\n", port);
423 return -1;
424 }
425
426 w836xx_ext_enter(base);
427
428 /* Select logical device. */
429 sio_write(base, 0x07, gpio->ldn);
430
431 /* Activate logical device. */
432 sio_mask(base, 0x30, 1 << gpio->enable_bit, 1 << gpio->enable_bit);
433
434 /* Select GPIO function of that pin. */
435 if (gpio->mux && gpio->mux[bit].reg)
436 sio_mask(base, gpio->mux[bit].reg,
437 gpio->mux[bit].data, gpio->mux[bit].mask);
438
439 sio_mask(base, gpio->base + 0, 0, 1 << bit); /* Make pin output */
440 sio_mask(base, gpio->base + 2, 0, 1 << bit); /* Clear inversion */
441 sio_mask(base, gpio->base + 1, raise << bit, 1 << bit);
442
443 w836xx_ext_leave(base);
444
445 return 0;
446 }
447
448 /*
449 * Winbond W83627HF: Raise GPIO24.
450 *
451 * Suited for:
452 * - Agami Aruma
453 * - IWILL DK8-HTX
454 */
w83627hf_gpio24_raise_2e(void)455 static int w83627hf_gpio24_raise_2e(void)
456 {
457 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 24, 1);
458 }
459
460 /*
461 * Winbond W83627HF: Raise GPIO25.
462 *
463 * Suited for:
464 * - MSI MS-6577
465 */
w83627hf_gpio25_raise_2e(void)466 static int w83627hf_gpio25_raise_2e(void)
467 {
468 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 25, 1);
469 }
470
471 /*
472 * Winbond W83627EHF: Raise GPIO22.
473 *
474 * Suited for:
475 * - ASUS A8N-VM CSM: AMD Socket 939 + GeForce 6150 (C51) + MCP51
476 */
w83627ehf_gpio22_raise_2e(void)477 static int w83627ehf_gpio22_raise_2e(void)
478 {
479 return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 22, 1);
480 }
481
482 /*
483 * Winbond W83627THF: Raise GPIO 44.
484 *
485 * Suited for:
486 * - MSI K8T Neo2-F V2.0
487 */
w83627thf_gpio44_raise_2e(void)488 static int w83627thf_gpio44_raise_2e(void)
489 {
490 return winbond_gpio_set(0x2e, WINBOND_W83627THF_ID, 44, 1);
491 }
492
493 /*
494 * Winbond W83627THF: Raise GPIO 44.
495 *
496 * Suited for:
497 * - MSI K8N Neo3
498 */
w83627thf_gpio44_raise_4e(void)499 static int w83627thf_gpio44_raise_4e(void)
500 {
501 return winbond_gpio_set(0x4e, WINBOND_W83627THF_ID, 44, 1);
502 }
503
504 /*
505 * Enable MEMW# and set ROM size to max.
506 * Supported chips: W83L517D, W83697HF/F/HG, W83697SF/UF/UG
507 */
w836xx_memw_enable(uint16_t port)508 static void w836xx_memw_enable(uint16_t port)
509 {
510 w836xx_ext_enter(port);
511 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
512 /* Enable MEMW# and set ROM size select to max. (4M). */
513 sio_mask(port, 0x24, 0x28, 0x28);
514 }
515 w836xx_ext_leave(port);
516 }
517
518 /**
519 * Enable MEMW# and set ROM size to max.
520 * Supported chips:
521 * W83697HF/F/HG, W83697SF/UF/UG
522 */
w83697xx_memw_enable(uint16_t port)523 static void w83697xx_memw_enable(uint16_t port)
524 {
525 w836xx_ext_enter(port);
526 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
527 if((sio_read(port, 0x2A) & 0xF0) == 0xF0) {
528
529 /* CR24 Bits 7 & 2 must be set to 0 enable the flash ROM */
530 /* address segments 000E0000h ~ 000FFFFFh on W83697SF/UF/UG */
531 /* These bits are reserved on W83697HF/F/HG */
532 /* Shouldn't be needed though. */
533
534 /* CR28 Bit3 must be set to 1 to enable flash access to */
535 /* FFE80000h ~ FFEFFFFFh on W83697SF/UF/UG. */
536 /* This bit is reserved on W83697HF/F/HG which default to 0 */
537 sio_mask(port, 0x28, 0x08, 0x08);
538
539 /* Enable MEMW# and set ROM size select to max. (4M)*/
540 sio_mask(port, 0x24, 0x28, 0x38);
541
542 } else {
543 msg_pwarn("Warning: Flash interface in use by GPIO!\n");
544 }
545 } else {
546 msg_pinfo("BIOS ROM is disabled\n");
547 }
548 w836xx_ext_leave(port);
549 }
550
551 /*
552 * Suited for:
553 * - Biostar M7VIQ: VIA KM266 + VT8235
554 */
w83697xx_memw_enable_2e(void)555 static int w83697xx_memw_enable_2e(void)
556 {
557 w83697xx_memw_enable(0x2E);
558
559 return 0;
560 }
561
562
563 /*
564 * Suited for:
565 * - DFI AD77: VIA KT400 + VT8235 + W83697HF
566 * - EPoX EP-8K5A2: VIA KT333 + VT8235
567 * - Albatron PM266A Pro: VIA P4M266A + VT8235
568 * - Shuttle AK31 (all versions): VIA KT266 + VT8233
569 * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
570 * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237
571 * - MSI KM4M-V and KM4AM-V: VIA KM400/KM400A + VT8237
572 * - MSI MS-6561 (745 Ultra): SiS 745 + W83697HF
573 * - MSI MS-6787 (P4MAM-V/P4MAM-L): VIA P4M266 + VT8235
574 * - ASRock K7S41: SiS 741 + SiS 963 + W83697HF
575 * - ASRock K7S41GX: SiS 741GX + SiS 963L + W83697HF
576 */
w836xx_memw_enable_2e(void)577 static int w836xx_memw_enable_2e(void)
578 {
579 w836xx_memw_enable(0x2E);
580
581 return 0;
582 }
583
584 /*
585 * Suited for:
586 * - Termtek TK-3370 (rev. 2.5b)
587 */
w836xx_memw_enable_4e(void)588 static int w836xx_memw_enable_4e(void)
589 {
590 w836xx_memw_enable(0x4E);
591
592 return 0;
593 }
594
595 /*
596 * Suited for all boards with ITE IT8705F.
597 * The SIS950 Super I/O probably requires a similar flash write enable.
598 */
it8705f_write_enable(uint8_t port)599 int it8705f_write_enable(uint8_t port)
600 {
601 uint8_t tmp;
602 int ret = 0;
603
604 if (!(internal_buses_supported & BUS_PARALLEL))
605 return 1;
606
607 enter_conf_mode_ite(port);
608 tmp = sio_read(port, 0x24);
609 /* Check if at least one flash segment is enabled. */
610 if (tmp & 0xf0) {
611 /* The IT8705F will respond to LPC cycles and translate them. */
612 internal_buses_supported &= BUS_PARALLEL;
613 /* Flash ROM I/F Writes Enable */
614 tmp |= 0x04;
615 msg_pdbg("Enabling IT8705F flash ROM interface write.\n");
616 if (tmp & 0x02) {
617 /* The data sheet contradicts itself about max size. */
618 max_rom_decode.parallel = 1024 * 1024;
619 msg_pinfo("IT8705F with very unusual settings.\n"
620 "Please send the output of \"flashrom -V -p internal\" to flashrom@flashrom.org\n"
621 "with \"IT8705: your board name: flashrom -V\" as the subject to help us finish\n"
622 "support for your Super I/O. Thanks.\n");
623 ret = 1;
624 } else if (tmp & 0x08) {
625 max_rom_decode.parallel = 512 * 1024;
626 } else {
627 max_rom_decode.parallel = 256 * 1024;
628 }
629 /* Safety checks. The data sheet is unclear here: Segments 1+3
630 * overlap, no segment seems to cover top - 1MB to top - 512kB.
631 * We assume that certain combinations make no sense.
632 */
633 if (((tmp & 0x02) && !(tmp & 0x08)) || /* 1 MB en, 512 kB dis */
634 (!(tmp & 0x10)) || /* 128 kB dis */
635 (!(tmp & 0x40))) { /* 256/512 kB dis */
636 msg_perr("Inconsistent IT8705F decode size!\n");
637 ret = 1;
638 }
639 if (sio_read(port, 0x25) != 0) {
640 msg_perr("IT8705F flash data pins disabled!\n");
641 ret = 1;
642 }
643 if (sio_read(port, 0x26) != 0) {
644 msg_perr("IT8705F flash address pins 0-7 disabled!\n");
645 ret = 1;
646 }
647 if (sio_read(port, 0x27) != 0) {
648 msg_perr("IT8705F flash address pins 8-15 disabled!\n");
649 ret = 1;
650 }
651 if ((sio_read(port, 0x29) & 0x10) != 0) {
652 msg_perr("IT8705F flash write enable pin disabled!\n");
653 ret = 1;
654 }
655 if ((sio_read(port, 0x29) & 0x08) != 0) {
656 msg_perr("IT8705F flash chip select pin disabled!\n");
657 ret = 1;
658 }
659 if ((sio_read(port, 0x29) & 0x04) != 0) {
660 msg_perr("IT8705F flash read strobe pin disabled!\n");
661 ret = 1;
662 }
663 if ((sio_read(port, 0x29) & 0x03) != 0) {
664 msg_perr("IT8705F flash address pins 16-17 disabled!\n");
665 /* Not really an error if you use flash chips smaller
666 * than 256 kByte, but such a configuration is unlikely.
667 */
668 ret = 1;
669 }
670 msg_pdbg("Maximum IT8705F parallel flash decode size is %u.\n",
671 max_rom_decode.parallel);
672 if (ret) {
673 msg_pinfo("Not enabling IT8705F flash write.\n");
674 } else {
675 sio_write(port, 0x24, tmp);
676 }
677 } else {
678 msg_pdbg("No IT8705F flash segment enabled.\n");
679 ret = 0;
680 }
681 exit_conf_mode_ite(port);
682
683 return ret;
684 }
685
686 /*
687 * The ITE IT8707F is a custom chip made by ITE exclusively for ASUS.
688 * It uses the Winbond command sequence to enter extended configuration
689 * mode and the ITE sequence to exit.
690 *
691 * Registers seems similar to the ones on ITE IT8710F.
692 */
it8707f_write_enable(uint8_t port)693 static int it8707f_write_enable(uint8_t port)
694 {
695 uint8_t tmp;
696
697 w836xx_ext_enter(port);
698
699 /* Set bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A rw */
700 tmp = sio_read(port, 0x23);
701 tmp |= (1 << 3);
702 sio_write(port, 0x23, tmp);
703
704 /* Set bit 2 (FLASH_WE) and bit 3 (FLASH_IF_EN) of reg 0x24 */
705 tmp = sio_read(port, 0x24);
706 tmp |= (1 << 2) | (1 << 3);
707 sio_write(port, 0x24, tmp);
708
709 /* Clear bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A ro */
710 tmp = sio_read(port, 0x23);
711 tmp &= ~(1 << 3);
712 sio_write(port, 0x23, tmp);
713
714 exit_conf_mode_ite(port);
715
716 return 0;
717 }
718
719 /*
720 * Suited for:
721 * - ASUS P4SC-E: SiS 651 + 962 + ITE IT8707F
722 */
it8707f_write_enable_2e(void)723 static int it8707f_write_enable_2e(void)
724 {
725 return it8707f_write_enable(0x2e);
726 }
727
728 #define PC87360_ID 0xE1
729 #define PC87364_ID 0xE4
730
pc8736x_gpio_set(uint8_t chipid,uint8_t gpio,int raise)731 static int pc8736x_gpio_set(uint8_t chipid, uint8_t gpio, int raise)
732 {
733 static const int bankbase[] = {0, 4, 8, 10, 12};
734 int gpio_bank = gpio / 8;
735 int gpio_pin = gpio % 8;
736 uint16_t baseport;
737 uint8_t id, val;
738
739 if (gpio_bank > 4) {
740 msg_perr("PC8736x: Invalid GPIO %d\n", gpio);
741 return -1;
742 }
743
744 id = sio_read(0x2E, 0x20);
745 if (id != chipid) {
746 msg_perr("PC8736x: unexpected ID %02x (expected %02x)\n",
747 id, chipid);
748 return -1;
749 }
750
751 sio_write(0x2E, 0x07, 0x07); /* Select GPIO device. */
752 baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
753 if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) {
754 msg_perr("PC87360: invalid GPIO base address %04x\n",
755 baseport);
756 return -1;
757 }
758 sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device. */
759 sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin);
760 sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output. */
761
762 val = INB(baseport + bankbase[gpio_bank]);
763 if (raise)
764 val |= 1 << gpio_pin;
765 else
766 val &= ~(1 << gpio_pin);
767 OUTB(val, baseport + bankbase[gpio_bank]);
768
769 return 0;
770 }
771
772 /*
773 * VIA VT823x: Set one of the GPIO pins.
774 */
via_vt823x_gpio_set(uint8_t gpio,int raise)775 static int via_vt823x_gpio_set(uint8_t gpio, int raise)
776 {
777 struct pci_dev *dev;
778 uint16_t base;
779 uint8_t val, bit, offset;
780
781 dev = pci_dev_find_vendorclass(0x1106, 0x0601);
782 switch (dev->device_id) {
783 case 0x3177: /* VT8235 */
784 case 0x3227: /* VT8237/VT8237R */
785 case 0x3337: /* VT8237A */
786 break;
787 default:
788 msg_perr("\nERROR: VT823x ISA bridge not found.\n");
789 return -1;
790 }
791
792 if ((gpio >= 12) && (gpio <= 15)) {
793 /* GPIO12-15 -> output */
794 val = pci_read_byte(dev, 0xE4);
795 val |= 0x10;
796 pci_write_byte(dev, 0xE4, val);
797 } else if (gpio == 9) {
798 /* GPIO9 -> Output */
799 val = pci_read_byte(dev, 0xE4);
800 val |= 0x20;
801 pci_write_byte(dev, 0xE4, val);
802 } else if (gpio == 5) {
803 val = pci_read_byte(dev, 0xE4);
804 val |= 0x01;
805 pci_write_byte(dev, 0xE4, val);
806 } else {
807 msg_perr("\nERROR: "
808 "VT823x GPIO%02d is not implemented.\n", gpio);
809 return -1;
810 }
811
812 /* We need the I/O Base Address for this board's flash enable. */
813 base = pci_read_word(dev, 0x88) & 0xff80;
814
815 offset = 0x4C + gpio / 8;
816 bit = 0x01 << (gpio % 8);
817
818 val = INB(base + offset);
819 if (raise)
820 val |= bit;
821 else
822 val &= ~bit;
823 OUTB(val, base + offset);
824
825 return 0;
826 }
827
828 /*
829 * Suited for:
830 * - ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F
831 */
via_vt823x_gpio5_raise(void)832 static int via_vt823x_gpio5_raise(void)
833 {
834 /* On M2V-MX: GPO5 is connected to WP# and TBL#. */
835 return via_vt823x_gpio_set(5, 1);
836 }
837
838 /*
839 * Suited for:
840 * - VIA EPIA EK & N & NL
841 */
via_vt823x_gpio9_raise(void)842 static int via_vt823x_gpio9_raise(void)
843 {
844 return via_vt823x_gpio_set(9, 1);
845 }
846
847 /*
848 * Suited for:
849 * - VIA EPIA M and MII (and maybe other CLE266 based EPIAs)
850 *
851 * We don't need to do this for EPIA M when using coreboot, GPIO15 is never
852 * lowered there.
853 */
via_vt823x_gpio15_raise(void)854 static int via_vt823x_gpio15_raise(void)
855 {
856 return via_vt823x_gpio_set(15, 1);
857 }
858
859 /*
860 * Winbond W83697HF Super I/O + VIA VT8235 southbridge
861 *
862 * Suited for:
863 * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
864 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
865 */
board_msi_kt4v(void)866 static int board_msi_kt4v(void)
867 {
868 int ret;
869
870 ret = via_vt823x_gpio_set(12, 1);
871 w836xx_memw_enable(0x2E);
872
873 return ret;
874 }
875
876 /*
877 * Suited for:
878 * - ASUS P5A
879 *
880 * This is rather nasty code, but there's no way to do this cleanly.
881 * We're basically talking to some unknown device on SMBus, my guess
882 * is that it is the Winbond W83781D that lives near the DIP BIOS.
883 */
board_asus_p5a(void)884 static int board_asus_p5a(void)
885 {
886 uint8_t tmp;
887 int i;
888
889 #define ASUSP5A_LOOP 5000
890
891 OUTB(0x00, 0xE807);
892 OUTB(0xEF, 0xE803);
893
894 OUTB(0xFF, 0xE800);
895
896 for (i = 0; i < ASUSP5A_LOOP; i++) {
897 OUTB(0xE1, 0xFF);
898 if (INB(0xE800) & 0x04)
899 break;
900 }
901
902 if (i == ASUSP5A_LOOP) {
903 msg_perr("Unable to contact device.\n");
904 return -1;
905 }
906
907 OUTB(0x20, 0xE801);
908 OUTB(0x20, 0xE1);
909
910 OUTB(0xFF, 0xE802);
911
912 for (i = 0; i < ASUSP5A_LOOP; i++) {
913 tmp = INB(0xE800);
914 if (tmp & 0x70)
915 break;
916 }
917
918 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
919 msg_perr("Failed to read device.\n");
920 return -1;
921 }
922
923 tmp = INB(0xE804);
924 tmp &= ~0x02;
925
926 OUTB(0x00, 0xE807);
927 OUTB(0xEE, 0xE803);
928
929 OUTB(tmp, 0xE804);
930
931 OUTB(0xFF, 0xE800);
932 OUTB(0xE1, 0xFF);
933
934 OUTB(0x20, 0xE801);
935 OUTB(0x20, 0xE1);
936
937 OUTB(0xFF, 0xE802);
938
939 for (i = 0; i < ASUSP5A_LOOP; i++) {
940 tmp = INB(0xE800);
941 if (tmp & 0x70)
942 break;
943 }
944
945 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
946 msg_perr("Failed to write to device.\n");
947 return -1;
948 }
949
950 return 0;
951 }
952
953 /*
954 * Set GPIO lines in the Broadcom HT-1000 southbridge.
955 *
956 * It's not a Super I/O but it uses the same index/data port method.
957 */
board_hp_dl145_g3_enable(void)958 static int board_hp_dl145_g3_enable(void)
959 {
960 /* GPIO 0 reg from PM regs */
961 /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
962 sio_mask(0xcd6, 0x44, 0x24, 0x24);
963
964 return 0;
965 }
966
967 /*
968 * Set GPIO lines in the Broadcom HT-1000 southbridge.
969 *
970 * It's not a Super I/O but it uses the same index/data port method.
971 */
board_hp_dl165_g6_enable(void)972 static int board_hp_dl165_g6_enable(void)
973 {
974 /* Variant of DL145, with slightly different pin placement. */
975 sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */
976 sio_mask(0xcd6, 0x46, 0x04, 0x04); /* WP# */
977
978 return 0;
979 }
980
board_ibm_x3455(void)981 static int board_ibm_x3455(void)
982 {
983 /* Raise GPIO13. */
984 sio_mask(0xcd6, 0x45, 0x20, 0x20);
985
986 return 0;
987 }
988
989 /*
990 * Suited for:
991 * - Elitegroup GeForce6100SM-M: NVIDIA MCP61 + ITE IT8726F
992 */
board_ecs_geforce6100sm_m(void)993 static int board_ecs_geforce6100sm_m(void)
994 {
995 struct pci_dev *dev;
996 uint32_t tmp;
997
998 dev = pci_dev_find(0x10DE, 0x03EB); /* NVIDIA MCP61 SMBus. */
999 if (!dev) {
1000 msg_perr("\nERROR: NVIDIA MCP61 SMBus not found.\n");
1001 return -1;
1002 }
1003
1004 tmp = pci_read_byte(dev, 0xE0);
1005 tmp &= ~(1 << 3);
1006 pci_write_byte(dev, 0xE0, tmp);
1007
1008 return 0;
1009 }
1010
1011 /*
1012 * Very similar to AMD 8111 IO Hub.
1013 */
nvidia_mcp_gpio_set(int gpio,int raise)1014 static int nvidia_mcp_gpio_set(int gpio, int raise)
1015 {
1016 struct pci_dev *dev;
1017 uint16_t base, devclass;
1018 uint8_t tmp;
1019
1020 if ((gpio < 0) || (gpio >= 0x40)) {
1021 msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio);
1022 return -1;
1023 }
1024
1025 /* Check for the ISA bridge first. */
1026 dev = pci_dev_find_vendorclass(0x10DE, 0x0601);
1027 switch (dev->device_id) {
1028 case 0x0030: /* CK804 */
1029 case 0x0050: /* MCP04 */
1030 case 0x0060: /* MCP2 */
1031 case 0x00E0: /* CK8 */
1032 break;
1033 case 0x0260: /* MCP51 */
1034 case 0x0261: /* MCP51 */
1035 case 0x0360: /* MCP55 */
1036 case 0x0364: /* MCP55 */
1037 /* find SMBus controller on *this* southbridge */
1038 /* The infamous Tyan S2915-E has two south bridges; they are
1039 easily told apart from each other by the class of the
1040 LPC bridge, but have the same SMBus bridge IDs */
1041 if (dev->func != 0) {
1042 msg_perr("MCP LPC bridge at unexpected function"
1043 " number %d\n", dev->func);
1044 return -1;
1045 }
1046
1047 #if !defined(OLD_PCI_GET_DEV)
1048 dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1);
1049 #else
1050 /* pciutils/libpci before version 2.2 is too old to support
1051 * PCI domains. Such old machines usually don't have domains
1052 * besides domain 0, so this is not a problem.
1053 */
1054 dev = pci_get_dev(pacc, dev->bus, dev->dev, 1);
1055 #endif
1056 if (!dev) {
1057 msg_perr("MCP SMBus controller could not be found\n");
1058 return -1;
1059 }
1060 devclass = pci_read_word(dev, PCI_CLASS_DEVICE);
1061 if (devclass != 0x0C05) {
1062 msg_perr("Unexpected device class %04x for SMBus"
1063 " controller\n", devclass);
1064 return -1;
1065 }
1066 break;
1067 default:
1068 msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n");
1069 return -1;
1070 }
1071
1072 base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
1073 base += 0xC0;
1074
1075 tmp = INB(base + gpio);
1076 tmp &= ~0x0F; /* null lower nibble */
1077 tmp |= 0x04; /* gpio -> output. */
1078 if (raise)
1079 tmp |= 0x01;
1080 OUTB(tmp, base + gpio);
1081
1082 return 0;
1083 }
1084
1085 /*
1086 * Suited for:
1087 * - ASUS A8M2N-LA (HP OEM "NodusM3-GL8E"): NVIDIA MCP51
1088 * - ASUS A8N-LA (HP OEM "Nagami-GL8E"): NVIDIA MCP51
1089 * - ASUS M2NBP-VM CSM: NVIDIA MCP51
1090 */
nvidia_mcp_gpio0_raise(void)1091 static int nvidia_mcp_gpio0_raise(void)
1092 {
1093 return nvidia_mcp_gpio_set(0x00, 1);
1094 }
1095
1096 /*
1097 * Suited for:
1098 * - abit KN8 Ultra: NVIDIA CK804
1099 * - abit KN9 Ultra: NVIDIA MCP55
1100 */
nvidia_mcp_gpio2_lower(void)1101 static int nvidia_mcp_gpio2_lower(void)
1102 {
1103 return nvidia_mcp_gpio_set(0x02, 0);
1104 }
1105
1106 /*
1107 * Suited for:
1108 * - Foxconn 6150K8MD-8EKRSH: Socket 939 + NVIDIA MCP51
1109 * - MSI K8N Neo4(-F/-FI/-FX/Platinum): NVIDIA CK804
1110 * - MSI K8NGM2-L: NVIDIA MCP51
1111 * - MSI K9N SLI: NVIDIA MCP55
1112 */
nvidia_mcp_gpio2_raise(void)1113 static int nvidia_mcp_gpio2_raise(void)
1114 {
1115 return nvidia_mcp_gpio_set(0x02, 1);
1116 }
1117
1118 /*
1119 * Suited for:
1120 * - EPoX EP-8NPA7I: Socket 754 + NVIDIA nForce4 4X
1121 */
nvidia_mcp_gpio4_raise(void)1122 static int nvidia_mcp_gpio4_raise(void)
1123 {
1124 return nvidia_mcp_gpio_set(0x04, 1);
1125 }
1126
1127 /*
1128 * Suited for:
1129 * - HP xw9400 (Tyan S2915-E OEM): Dual(!) NVIDIA MCP55
1130 *
1131 * Notes: a) There are two MCP55 chips, so also two SMBus bridges on that
1132 * board. We can't tell the SMBus logical devices apart, but we
1133 * can tell the LPC bridge functions apart.
1134 * We need to choose the SMBus bridge next to the LPC bridge with
1135 * ID 0x364 and the "LPC bridge" class.
1136 * b) #TBL is hardwired on that board to a pull-down. It can be
1137 * overridden by connecting the two solder points next to F2.
1138 */
nvidia_mcp_gpio5_raise(void)1139 static int nvidia_mcp_gpio5_raise(void)
1140 {
1141 return nvidia_mcp_gpio_set(0x05, 1);
1142 }
1143
1144 /*
1145 * Suited for:
1146 * - abit NF7-S: NVIDIA CK804
1147 */
nvidia_mcp_gpio8_raise(void)1148 static int nvidia_mcp_gpio8_raise(void)
1149 {
1150 return nvidia_mcp_gpio_set(0x08, 1);
1151 }
1152
1153 /*
1154 * Suited for:
1155 * - GIGABYTE GA-K8NS Pro-939: Socket 939 + NVIDIA nForce3 + CK8
1156 * - Probably other versions of the GA-K8NS
1157 */
nvidia_mcp_gpio0a_raise(void)1158 static int nvidia_mcp_gpio0a_raise(void)
1159 {
1160 return nvidia_mcp_gpio_set(0x0a, 1);
1161 }
1162
1163 /*
1164 * Suited for:
1165 * - MSI K8N Neo Platinum: Socket 754 + nForce3 Ultra + CK8
1166 * - MSI K8N Neo2 Platinum: Socket 939 + nForce3 Ultra + CK8
1167 */
nvidia_mcp_gpio0c_raise(void)1168 static int nvidia_mcp_gpio0c_raise(void)
1169 {
1170 return nvidia_mcp_gpio_set(0x0c, 1);
1171 }
1172
1173 /*
1174 * Suited for:
1175 * - abit NF-M2 nView: Socket AM2 + NVIDIA MCP51
1176 */
nvidia_mcp_gpio4_lower(void)1177 static int nvidia_mcp_gpio4_lower(void)
1178 {
1179 return nvidia_mcp_gpio_set(0x04, 0);
1180 }
1181
1182 /*
1183 * Suited for:
1184 * - ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04
1185 */
nvidia_mcp_gpio10_raise(void)1186 static int nvidia_mcp_gpio10_raise(void)
1187 {
1188 return nvidia_mcp_gpio_set(0x10, 1);
1189 }
1190
1191 /*
1192 * Suited for:
1193 * - GIGABYTE GA-K8N-SLI: AMD socket 939 + NVIDIA CK804 + ITE IT8712F
1194 */
nvidia_mcp_gpio21_raise(void)1195 static int nvidia_mcp_gpio21_raise(void)
1196 {
1197 return nvidia_mcp_gpio_set(0x21, 0x01);
1198 }
1199
1200 /*
1201 * Suited for:
1202 * - EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2
1203 */
nvidia_mcp_gpio31_raise(void)1204 static int nvidia_mcp_gpio31_raise(void)
1205 {
1206 return nvidia_mcp_gpio_set(0x31, 0x01);
1207 }
1208
1209 /*
1210 * Suited for:
1211 * - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51
1212 * - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51
1213 */
nvidia_mcp_gpio3b_raise(void)1214 static int nvidia_mcp_gpio3b_raise(void)
1215 {
1216 return nvidia_mcp_gpio_set(0x3b, 1);
1217 }
1218
1219 /*
1220 * Suited for:
1221 * - Sun Ultra 40 M2: Dual Socket F (1207) + MCP55
1222 */
board_sun_ultra_40_m2(void)1223 static int board_sun_ultra_40_m2(void)
1224 {
1225 int ret;
1226 uint8_t reg;
1227 uint16_t base;
1228 struct pci_dev *dev;
1229
1230 ret = nvidia_mcp_gpio4_lower();
1231 if (ret)
1232 return ret;
1233
1234 dev = pci_dev_find(0x10de, 0x0364); /* NVIDIA MCP55 LPC bridge */
1235 if (!dev) {
1236 msg_perr("\nERROR: NVIDIA MCP55 LPC bridge not found.\n");
1237 return -1;
1238 }
1239
1240 base = pci_read_word(dev, 0xb4); /* some IO BAR? */
1241 if (!base)
1242 return -1;
1243
1244 reg = INB(base + 0x4b);
1245 reg |= 0x10;
1246 OUTB(reg, base + 0x4b);
1247
1248 return 0;
1249 }
1250
1251 /*
1252 * Suited for:
1253 * - Artec Group DBE61 and DBE62
1254 */
board_artecgroup_dbe6x(void)1255 static int board_artecgroup_dbe6x(void)
1256 {
1257 #define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015
1258 #define DBE6x_PRI_BOOT_LOC_SHIFT 2
1259 #define DBE6x_BOOT_OP_LATCHED_SHIFT 8
1260 #define DBE6x_SEC_BOOT_LOC_SHIFT 10
1261 #define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT)
1262 #define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT)
1263 #define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT)
1264 #define DBE6x_BOOT_LOC_FLASH 2
1265 #define DBE6x_BOOT_LOC_FWHUB 3
1266
1267 msr_t msr;
1268 unsigned long boot_loc;
1269
1270 /* Geode only has a single core */
1271 if (setup_cpu_msr(0))
1272 return -1;
1273
1274 msr = rdmsr(DBE6x_MSR_DIVIL_BALL_OPTS);
1275
1276 if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) ==
1277 (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))
1278 boot_loc = DBE6x_BOOT_LOC_FWHUB;
1279 else
1280 boot_loc = DBE6x_BOOT_LOC_FLASH;
1281
1282 msr.lo &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
1283 msr.lo |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
1284 (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
1285
1286 wrmsr(DBE6x_MSR_DIVIL_BALL_OPTS, msr);
1287
1288 cleanup_cpu_msr();
1289
1290 return 0;
1291 }
1292
1293 /*
1294 * Suited for:
1295 * - ASUS A8AE-LE (Codename AmberineM; used in Compaq Presario 061)
1296 * Datasheet(s) used:
1297 * - AMD document 43009 "AMD SB700/710/750 Register Reference Guide" rev. 1.00
1298 */
amd_sbxxx_gpio9_raise(void)1299 static int amd_sbxxx_gpio9_raise(void)
1300 {
1301 struct pci_dev *dev;
1302 uint32_t reg;
1303
1304 dev = pci_dev_find(0x1002, 0x4372); /* AMD SMBus controller */
1305 if (!dev) {
1306 msg_perr("\nERROR: AMD SMBus Controller (0x4372) not found.\n");
1307 return -1;
1308 }
1309
1310 reg = pci_read_long(dev, 0xA8); /* GPIO_12_to_4_Cntrl CI_Reg: A8h-ABh */
1311 /* enable output (0: enable, 1: tristate):
1312 GPIO9 output enable is at bit 5 in 0xA9 */
1313 reg &= ~((uint32_t)1<<(8+5));
1314 /* raise:
1315 GPIO9 output register is at bit 5 in 0xA8 */
1316 reg |= (1<<5);
1317 pci_write_long(dev, 0xA8, reg);
1318
1319 return 0;
1320 }
1321
1322 /*
1323 * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}.
1324 */
intel_piix4_gpo_set(unsigned int gpo,int raise)1325 static int intel_piix4_gpo_set(unsigned int gpo, int raise)
1326 {
1327 unsigned int gpo_byte, gpo_bit;
1328 struct pci_dev *dev;
1329 uint32_t tmp, base;
1330
1331 /* GPO{0,8,27,28,30} are always available. */
1332 static const uint32_t nonmuxed_gpos = 0x58000101;
1333
1334 static const struct {unsigned int reg, mask, value; } piix4_gpo[] = {
1335 {0},
1336 {0xB0, 0x0001, 0x0000}, /* GPO1... */
1337 {0xB0, 0x0001, 0x0000},
1338 {0xB0, 0x0001, 0x0000},
1339 {0xB0, 0x0001, 0x0000},
1340 {0xB0, 0x0001, 0x0000},
1341 {0xB0, 0x0001, 0x0000},
1342 {0xB0, 0x0001, 0x0000}, /* ...GPO7: GENCFG bit 0 */
1343 {0},
1344 {0xB0, 0x0100, 0x0000}, /* GPO9: GENCFG bit 8 */
1345 {0xB0, 0x0200, 0x0000}, /* GPO10: GENCFG bit 9 */
1346 {0xB0, 0x0400, 0x0000}, /* GPO11: GENCFG bit 10 */
1347 {0x4E, 0x0100, 0x0000}, /* GPO12... */
1348 {0x4E, 0x0100, 0x0000},
1349 {0x4E, 0x0100, 0x0000}, /* ...GPO14: XBCS bit 8 */
1350 {0xB2, 0x0002, 0x0002}, /* GPO15... */
1351 {0xB2, 0x0002, 0x0002}, /* ...GPO16: GENCFG bit 17 */
1352 {0xB2, 0x0004, 0x0004}, /* GPO17: GENCFG bit 18 */
1353 {0xB2, 0x0008, 0x0008}, /* GPO18: GENCFG bit 19 */
1354 {0xB2, 0x0010, 0x0010}, /* GPO19: GENCFG bit 20 */
1355 {0xB2, 0x0020, 0x0020}, /* GPO20: GENCFG bit 21 */
1356 {0xB2, 0x0040, 0x0040}, /* GPO21: GENCFG bit 22 */
1357 {0xB2, 0x1000, 0x1000}, /* GPO22... */
1358 {0xB2, 0x1000, 0x1000}, /* ...GPO23: GENCFG bit 28 */
1359 {0xB2, 0x2000, 0x2000}, /* GPO24: GENCFG bit 29 */
1360 {0xB2, 0x4000, 0x4000}, /* GPO25: GENCFG bit 30 */
1361 {0xB2, 0x8000, 0x8000}, /* GPO26: GENCFG bit 31 */
1362 {0},
1363 {0},
1364 {0x4E, 0x0100, 0x0000}, /* ...GPO29: XBCS bit 8 */
1365 {0}
1366 };
1367
1368 dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */
1369 if (!dev) {
1370 msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n");
1371 return -1;
1372 }
1373
1374 /* Sanity check. */
1375 if (gpo > 30) {
1376 msg_perr("\nERROR: Intel PIIX4 has no GPO%d.\n", gpo);
1377 return -1;
1378 }
1379
1380 if ((((1 << gpo) & nonmuxed_gpos) == 0) &&
1381 ((pci_read_word(dev, piix4_gpo[gpo].reg) & piix4_gpo[gpo].mask) !=
1382 piix4_gpo[gpo].value)) {
1383 msg_perr("\nERROR: PIIX4 GPO%d not programmed for output.\n", gpo);
1384 return -1;
1385 }
1386
1387 dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */
1388 if (!dev) {
1389 msg_perr("\nERROR: Intel PIIX4 PM not found.\n");
1390 return -1;
1391 }
1392
1393 /* PM IO base */
1394 base = pci_read_long(dev, 0x40) & 0x0000FFC0;
1395
1396 gpo_byte = gpo >> 3;
1397 gpo_bit = gpo & 7;
1398 tmp = INB(base + 0x34 + gpo_byte); /* GPO register */
1399 if (raise)
1400 tmp |= 0x01 << gpo_bit;
1401 else
1402 tmp &= ~(0x01 << gpo_bit);
1403 OUTB(tmp, base + 0x34 + gpo_byte);
1404
1405 return 0;
1406 }
1407
1408 /*
1409 * Suited for:
1410 * - ASUS OPLX-M
1411 * - ASUS P2B-N
1412 */
intel_piix4_gpo18_lower(void)1413 static int intel_piix4_gpo18_lower(void)
1414 {
1415 return intel_piix4_gpo_set(18, 0);
1416 }
1417
1418 /*
1419 * Suited for:
1420 * - MSI MS-6163 v2 (MS-6163 Pro): Intel 440BX + PIIX4E + Winbond W83977EF
1421 */
intel_piix4_gpo14_raise(void)1422 static int intel_piix4_gpo14_raise(void)
1423 {
1424 return intel_piix4_gpo_set(14, 1);
1425 }
1426
1427 /*
1428 * Suited for:
1429 * - EPoX EP-BX3
1430 */
intel_piix4_gpo22_raise(void)1431 static int intel_piix4_gpo22_raise(void)
1432 {
1433 return intel_piix4_gpo_set(22, 1);
1434 }
1435
1436 /*
1437 * Suited for:
1438 * - abit BM6
1439 */
intel_piix4_gpo26_lower(void)1440 static int intel_piix4_gpo26_lower(void)
1441 {
1442 return intel_piix4_gpo_set(26, 0);
1443 }
1444
1445 /*
1446 * Suited for:
1447 * - Intel SE440BX-2
1448 */
intel_piix4_gpo27_lower(void)1449 static int intel_piix4_gpo27_lower(void)
1450 {
1451 return intel_piix4_gpo_set(27, 0);
1452 }
1453
1454 /*
1455 * Suited for:
1456 * - Dell OptiPlex GX1
1457 */
intel_piix4_gpo30_lower(void)1458 static int intel_piix4_gpo30_lower(void)
1459 {
1460 return intel_piix4_gpo_set(30, 0);
1461 }
1462
1463 /*
1464 * Set a GPIO line on a given Intel ICH LPC controller.
1465 */
intel_ich_gpio_set(int gpio,int raise)1466 static int intel_ich_gpio_set(int gpio, int raise)
1467 {
1468 /* Table mapping the different Intel ICH LPC chipsets. */
1469 static struct {
1470 uint16_t id;
1471 uint8_t base_reg;
1472 uint32_t bank0;
1473 uint32_t bank1;
1474 uint32_t bank2;
1475 } intel_ich_gpio_table[] = {
1476 {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */
1477 {0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */
1478 {0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */
1479 {0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */
1480 {0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */
1481 {0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */
1482 {0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */
1483 {0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */
1484 {0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */
1485 {0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */
1486 {0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */
1487 {0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */
1488 {0x27B0, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GDH (ICH7 DH) */
1489 {0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */
1490 {0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */
1491 {0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */
1492 {0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */
1493 {0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */
1494 {0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */
1495 {0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */
1496 {0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */
1497 {0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */
1498 {0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */
1499 {0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */
1500 {0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */
1501 {0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */
1502 {0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */
1503 {0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */
1504 {0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */
1505 {0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */
1506 {0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */
1507 {0, 0, 0, 0, 0} /* end marker */
1508 };
1509
1510 struct pci_dev *dev;
1511 uint16_t base;
1512 uint32_t tmp;
1513 int i, allowed;
1514
1515 /* First, look for a known LPC bridge */
1516 for (dev = pacc->devices; dev; dev = dev->next) {
1517 uint16_t device_class;
1518 /* libpci before version 2.2.4 does not store class info. */
1519 device_class = pci_read_word(dev, PCI_CLASS_DEVICE);
1520 if ((dev->vendor_id == 0x8086) &&
1521 (device_class == 0x0601)) { /* ISA bridge */
1522 /* Is this device in our list? */
1523 for (i = 0; intel_ich_gpio_table[i].id; i++)
1524 if (dev->device_id == intel_ich_gpio_table[i].id)
1525 break;
1526
1527 if (intel_ich_gpio_table[i].id)
1528 break;
1529 }
1530 }
1531
1532 if (!dev) {
1533 msg_perr("\nERROR: No known Intel LPC bridge found.\n");
1534 return -1;
1535 }
1536
1537 /*
1538 * According to the datasheets, all Intel ICHs have the GPIO bar 5:1
1539 * strapped to zero. From some mobile ICH9 version on, this becomes
1540 * 6:1. The mask below catches all.
1541 */
1542 base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0;
1543
1544 /* Check whether the line is allowed. */
1545 if (gpio < 32)
1546 allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01;
1547 else if (gpio < 64)
1548 allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01;
1549 else
1550 allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01;
1551
1552 if (!allowed) {
1553 msg_perr("\nERROR: This Intel LPC bridge does not allow"
1554 " setting GPIO%02d\n", gpio);
1555 return -1;
1556 }
1557
1558 msg_pdbg("\nIntel ICH LPC bridge: %sing GPIO%02d.\n",
1559 raise ? "Rais" : "Dropp", gpio);
1560
1561 if (gpio < 32) {
1562 /* Set line to GPIO. */
1563 tmp = INL(base);
1564 /* ICH/ICH0 multiplexes 27/28 on the line set. */
1565 if ((gpio == 28) &&
1566 ((dev->device_id == 0x2410) || (dev->device_id == 0x2420)))
1567 tmp |= 1 << 27;
1568 else
1569 tmp |= 1 << gpio;
1570 OUTL(tmp, base);
1571
1572 /* As soon as we are talking to ICH8 and above, this register
1573 decides whether we can set the gpio or not. */
1574 if (dev->device_id > 0x2800) {
1575 tmp = INL(base);
1576 if (!(tmp & (1 << gpio))) {
1577 msg_perr("\nERROR: This Intel LPC bridge"
1578 " does not allow setting GPIO%02d\n",
1579 gpio);
1580 return -1;
1581 }
1582 }
1583
1584 /* Set GPIO to OUTPUT. */
1585 tmp = INL(base + 0x04);
1586 tmp &= ~(1 << gpio);
1587 OUTL(tmp, base + 0x04);
1588
1589 /* Raise GPIO line. */
1590 tmp = INL(base + 0x0C);
1591 if (raise)
1592 tmp |= 1 << gpio;
1593 else
1594 tmp &= ~(1 << gpio);
1595 OUTL(tmp, base + 0x0C);
1596 } else if (gpio < 64) {
1597 gpio -= 32;
1598
1599 /* Set line to GPIO. */
1600 tmp = INL(base + 0x30);
1601 tmp |= 1 << gpio;
1602 OUTL(tmp, base + 0x30);
1603
1604 /* As soon as we are talking to ICH8 and above, this register
1605 decides whether we can set the gpio or not. */
1606 if (dev->device_id > 0x2800) {
1607 tmp = INL(base + 30);
1608 if (!(tmp & (1 << gpio))) {
1609 msg_perr("\nERROR: This Intel LPC bridge"
1610 " does not allow setting GPIO%02d\n",
1611 gpio + 32);
1612 return -1;
1613 }
1614 }
1615
1616 /* Set GPIO to OUTPUT. */
1617 tmp = INL(base + 0x34);
1618 tmp &= ~(1 << gpio);
1619 OUTL(tmp, base + 0x34);
1620
1621 /* Raise GPIO line. */
1622 tmp = INL(base + 0x38);
1623 if (raise)
1624 tmp |= 1 << gpio;
1625 else
1626 tmp &= ~(1 << gpio);
1627 OUTL(tmp, base + 0x38);
1628 } else {
1629 gpio -= 64;
1630
1631 /* Set line to GPIO. */
1632 tmp = INL(base + 0x40);
1633 tmp |= 1 << gpio;
1634 OUTL(tmp, base + 0x40);
1635
1636 tmp = INL(base + 40);
1637 if (!(tmp & (1 << gpio))) {
1638 msg_perr("\nERROR: This Intel LPC bridge does "
1639 "not allow setting GPIO%02d\n", gpio + 64);
1640 return -1;
1641 }
1642
1643 /* Set GPIO to OUTPUT. */
1644 tmp = INL(base + 0x44);
1645 tmp &= ~(1 << gpio);
1646 OUTL(tmp, base + 0x44);
1647
1648 /* Raise GPIO line. */
1649 tmp = INL(base + 0x48);
1650 if (raise)
1651 tmp |= 1 << gpio;
1652 else
1653 tmp &= ~(1 << gpio);
1654 OUTL(tmp, base + 0x48);
1655 }
1656
1657 return 0;
1658 }
1659
1660 /*
1661 * Suited for:
1662 * - abit IP35: Intel P35 + ICH9R
1663 * - abit IP35 Pro: Intel P35 + ICH9R
1664 * - ASUS P5LD2
1665 * - ASUS P5LD2-MQ
1666 * - ASUS P5LD2-VM
1667 * - ASUS P5LD2-VM DH
1668 */
intel_ich_gpio16_raise(void)1669 static int intel_ich_gpio16_raise(void)
1670 {
1671 return intel_ich_gpio_set(16, 1);
1672 }
1673
1674 /*
1675 * Suited for:
1676 * - HP Puffer2-UL8E (ASUS PTGD-LA OEM): LGA775 + 915 + ICH6
1677 */
intel_ich_gpio18_raise(void)1678 static int intel_ich_gpio18_raise(void)
1679 {
1680 return intel_ich_gpio_set(18, 1);
1681 }
1682
1683 /*
1684 * Suited for:
1685 * - MSI MS-7046: LGA775 + 915P + ICH6
1686 */
intel_ich_gpio19_raise(void)1687 static int intel_ich_gpio19_raise(void)
1688 {
1689 return intel_ich_gpio_set(19, 1);
1690 }
1691
1692 /*
1693 * Suited for:
1694 * - ASUS P5BV-R: LGA775 + 3200 + ICH7
1695 * - AOpen i965GMt-LA: Intel Socket479 + 965GM + ICH8M
1696 */
intel_ich_gpio20_raise(void)1697 static int intel_ich_gpio20_raise(void)
1698 {
1699 return intel_ich_gpio_set(20, 1);
1700 }
1701
1702 /*
1703 * Suited for:
1704 * - ASUS CUSL2-C: Intel socket370 + 815 + ICH2
1705 * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2
1706 * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5
1707 * - ASUS P4P800: Intel socket478 + 865PE + ICH5R
1708 * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R
1709 * - ASUS P4P800-VM: Intel socket478 + 865PE + ICH5R
1710 * - ASUS P4P800-X: Intel socket478 + 865PE + ICH5R
1711 * - ASUS P4P800SE: Intel socket478 + 865PE + ICH5R
1712 * - ASUS P5GD1 Pro: Intel LGA 775 + 915P + ICH6R
1713 * - ASUS P5GD2 Premium: Intel LGA775 + 915G + ICH6R
1714 * - ASUS P5GDC Deluxe: Intel socket775 + 915P + ICH6R
1715 * - ASUS P5PE-VM: Intel LGA775 + 865G + ICH5
1716 * - ASUS TUSL2-C: Intel socket370 + 815 + ICH2
1717 * - Samsung Polaris 32: socket478 + 865P + ICH5
1718 */
intel_ich_gpio21_raise(void)1719 static int intel_ich_gpio21_raise(void)
1720 {
1721 return intel_ich_gpio_set(21, 1);
1722 }
1723
1724 /*
1725 * Suited for:
1726 * - ASUS P4B266: socket478 + Intel 845D + ICH2
1727 * - ASUS P4B533-E: socket478 + 845E + ICH4
1728 * - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2
1729 * - TriGem Anaheim-3: socket370 + Intel 810 + ICH
1730 */
intel_ich_gpio22_raise(void)1731 static int intel_ich_gpio22_raise(void)
1732 {
1733 return intel_ich_gpio_set(22, 1);
1734 }
1735
1736 /*
1737 * Suited for:
1738 * - ASUS A8Jm (laptop): Intel 945 + ICH7
1739 * - ASUS P5LP-LE used in ...
1740 * - HP Media Center m7270.fr Desktop PC as "Lithium-UL8E"
1741 * - Epson Endeavor MT7700
1742 */
intel_ich_gpio34_raise(void)1743 static int intel_ich_gpio34_raise(void)
1744 {
1745 return intel_ich_gpio_set(34, 1);
1746 }
1747
1748 /*
1749 * Suited for:
1750 * - AOpen i945GMx-VFX: Intel 945GM + ICH7-M used in ...
1751 * - FSC ESPRIMO Q5010 (SMBIOS: D2544-B1)
1752 */
intel_ich_gpio38_raise(void)1753 static int intel_ich_gpio38_raise(void)
1754 {
1755 return intel_ich_gpio_set(38, 1);
1756 }
1757
1758 /*
1759 * Suited for:
1760 * - ASUS M6Ne (laptop): socket 479M (guessed) + Intel 855PM + ICH4-M
1761 */
intel_ich_gpio43_raise(void)1762 static int intel_ich_gpio43_raise(void)
1763 {
1764 return intel_ich_gpio_set(43, 1);
1765 }
1766
1767 /*
1768 * Suited for:
1769 * - HP Vectra VL400: 815 + ICH + PC87360
1770 */
board_hp_vl400(void)1771 static int board_hp_vl400(void)
1772 {
1773 int ret;
1774 ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */
1775 if (!ret)
1776 ret = pc8736x_gpio_set(PC87360_ID, 0x09, 1); /* #WP ? */
1777 if (!ret)
1778 ret = pc8736x_gpio_set(PC87360_ID, 0x27, 1); /* #TBL */
1779 return ret;
1780 }
1781
1782 /*
1783 * Suited for:
1784 * - HP e-Vectra P2706T: 810E + ICH + PC87364
1785 */
board_hp_p2706t(void)1786 static int board_hp_p2706t(void)
1787 {
1788 int ret;
1789 ret = pc8736x_gpio_set(PC87364_ID, 0x25, 1);
1790 if (!ret)
1791 ret = pc8736x_gpio_set(PC87364_ID, 0x26, 1);
1792 return ret;
1793 }
1794
1795 /*
1796 * Suited for:
1797 * - Dell PowerEdge 1850: Intel PPGA604 + E7520 + ICH5R
1798 * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R
1799 * - ASRock 775i65G: Intel LGA 775 + 865G + ICH5
1800 * - MSI MS-6391 (845 Pro4): Intel Socket478 + 845 + ICH2
1801 */
intel_ich_gpio23_raise(void)1802 static int intel_ich_gpio23_raise(void)
1803 {
1804 return intel_ich_gpio_set(23, 1);
1805 }
1806
1807 /*
1808 * Suited for:
1809 * - GIGABYTE GA-6IEM: Intel Socket370 + i815 + ICH2
1810 * - GIGABYTE GA-8IRML: Intel Socket478 + i845 + ICH2
1811 */
intel_ich_gpio25_raise(void)1812 static int intel_ich_gpio25_raise(void)
1813 {
1814 return intel_ich_gpio_set(25, 1);
1815 }
1816
1817 /*
1818 * Suited for:
1819 * - IBASE MB899: i945GM + ICH7
1820 */
intel_ich_gpio26_raise(void)1821 static int intel_ich_gpio26_raise(void)
1822 {
1823 return intel_ich_gpio_set(26, 1);
1824 }
1825
1826 /*
1827 * Suited for:
1828 * - ASUS DSAN-DX
1829 * - P4SD-LA (HP OEM): i865 + ICH5
1830 * - GIGABYTE GA-8IP775: 865P + ICH5
1831 * - GIGABYTE GA-8PE667 Ultra 2: socket 478 + i845PE + ICH4
1832 * - MSI MS-6788-40 (aka 848P Neo-V)
1833 */
intel_ich_gpio32_raise(void)1834 static int intel_ich_gpio32_raise(void)
1835 {
1836 return intel_ich_gpio_set(32, 1);
1837 }
1838
1839 /*
1840 * Suited for:
1841 * - AOpen i975Xa-YDG: i975X + ICH7 + W83627EHF
1842 */
board_aopen_i975xa_ydg(void)1843 static int board_aopen_i975xa_ydg(void)
1844 {
1845 int ret;
1846
1847 /* Vendor BIOS ends up in LDN6... maybe the board enable is wrong,
1848 * or perhaps it's not needed at all?
1849 * The regs it tries to touch are 0xF0, 0xF1, 0xF2 which means if it
1850 * were in the right LDN, it would have to be GPIO1 or GPIO3.
1851 */
1852 /*
1853 ret = winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, x, 0)
1854 if (!ret)
1855 */
1856 ret = intel_ich_gpio_set(33, 1);
1857
1858 return ret;
1859 }
1860
1861 /*
1862 * Suited for:
1863 * - Acorp 6A815EPD: socket 370 + intel 815 + ICH2
1864 */
board_acorp_6a815epd(void)1865 static int board_acorp_6a815epd(void)
1866 {
1867 int ret;
1868
1869 /* Lower Blocks Lock -- pin 7 of PLCC32 */
1870 ret = intel_ich_gpio_set(22, 1);
1871 if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */
1872 ret = intel_ich_gpio_set(23, 1);
1873
1874 return ret;
1875 }
1876
1877 /*
1878 * Suited for:
1879 * - Kontron 986LCD-M: Socket478 + 915GM + ICH7R
1880 */
board_kontron_986lcd_m(void)1881 static int board_kontron_986lcd_m(void)
1882 {
1883 int ret;
1884
1885 ret = intel_ich_gpio_set(34, 1); /* #TBL */
1886 if (!ret)
1887 ret = intel_ich_gpio_set(35, 1); /* #WP */
1888
1889 return ret;
1890 }
1891
1892 /*
1893 * Suited for:
1894 * - Soyo SY-7VCA: Pro133A + VT82C686
1895 */
via_apollo_gpo_set(int gpio,int raise)1896 static int via_apollo_gpo_set(int gpio, int raise)
1897 {
1898 struct pci_dev *dev;
1899 uint32_t base, tmp;
1900
1901 /* VT82C686 power management */
1902 dev = pci_dev_find(0x1106, 0x3057);
1903 if (!dev) {
1904 msg_perr("\nERROR: VT82C686 PM device not found.\n");
1905 return -1;
1906 }
1907
1908 msg_pdbg("\nVIA Apollo ACPI: %sing GPIO%02d.\n",
1909 raise ? "Rais" : "Dropp", gpio);
1910
1911 /* Select GPO function on multiplexed pins. */
1912 tmp = pci_read_byte(dev, 0x54);
1913 switch (gpio) {
1914 case 0:
1915 tmp &= ~0x03;
1916 break;
1917 case 1:
1918 tmp |= 0x04;
1919 break;
1920 case 2:
1921 tmp |= 0x08;
1922 break;
1923 case 3:
1924 tmp |= 0x10;
1925 break;
1926 }
1927 pci_write_byte(dev, 0x54, tmp);
1928
1929 /* PM IO base */
1930 base = pci_read_long(dev, 0x48) & 0x0000FF00;
1931
1932 /* Drop GPO0 */
1933 tmp = INL(base + 0x4C);
1934 if (raise)
1935 tmp |= 1U << gpio;
1936 else
1937 tmp &= ~(1U << gpio);
1938 OUTL(tmp, base + 0x4C);
1939
1940 return 0;
1941 }
1942
1943 /*
1944 * Suited for:
1945 * - abit VT6X4: Pro133x + VT82C686A
1946 * - abit VA6: Pro133x + VT82C686A
1947 */
via_apollo_gpo4_lower(void)1948 static int via_apollo_gpo4_lower(void)
1949 {
1950 return via_apollo_gpo_set(4, 0);
1951 }
1952
1953 /*
1954 * Suited for:
1955 * - Soyo SY-7VCA: Pro133A + VT82C686
1956 */
via_apollo_gpo0_lower(void)1957 static int via_apollo_gpo0_lower(void)
1958 {
1959 return via_apollo_gpo_set(0, 0);
1960 }
1961
1962 /*
1963 * Enable some GPIO pin on SiS southbridge and enables SIO flash writes.
1964 *
1965 * Suited for:
1966 * - MSI 651M-L: SiS651 / SiS962
1967 * - GIGABYTE GA-8SIMLFS 2.0
1968 * - GIGABYTE GA-8SIMLH
1969 */
sis_gpio0_raise_and_w836xx_memw(void)1970 static int sis_gpio0_raise_and_w836xx_memw(void)
1971 {
1972 struct pci_dev *dev;
1973 uint16_t base, temp;
1974
1975 dev = pci_dev_find(0x1039, 0x0962);
1976 if (!dev) {
1977 msg_perr("Expected south bridge not found\n");
1978 return 1;
1979 }
1980
1981 base = pci_read_word(dev, 0x74);
1982 temp = INW(base + 0x68);
1983 temp &= ~(1 << 0); /* Make pin output? */
1984 OUTW(temp, base + 0x68);
1985
1986 temp = INW(base + 0x64);
1987 temp |= (1 << 0); /* Raise output? */
1988 OUTW(temp, base + 0x64);
1989
1990 w836xx_memw_enable(0x2E);
1991
1992 return 0;
1993 }
1994
1995 /*
1996 * Find the runtime registers of an SMSC Super I/O, after verifying its
1997 * chip ID.
1998 *
1999 * Returns the base port of the runtime register block, or 0 on error.
2000 */
smsc_find_runtime(uint16_t sio_port,uint16_t chip_id,uint8_t logical_device)2001 static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id,
2002 uint8_t logical_device)
2003 {
2004 uint16_t rt_port = 0;
2005
2006 /* Verify the chip ID. */
2007 OUTB(0x55, sio_port); /* Enable configuration. */
2008 if (sio_read(sio_port, 0x20) != chip_id) {
2009 msg_perr("\nERROR: SMSC Super I/O not found.\n");
2010 goto out;
2011 }
2012
2013 /* If the runtime block is active, get its address. */
2014 sio_write(sio_port, 0x07, logical_device);
2015 if (sio_read(sio_port, 0x30) & 1) {
2016 rt_port = (sio_read(sio_port, 0x60) << 8)
2017 | sio_read(sio_port, 0x61);
2018 }
2019
2020 if (rt_port == 0) {
2021 msg_perr("\nERROR: "
2022 "Super I/O runtime interface not available.\n");
2023 }
2024 out:
2025 OUTB(0xaa, sio_port); /* Disable configuration. */
2026 return rt_port;
2027 }
2028
2029 /*
2030 * Disable write protection on the Mitac 6513WU. WP# on the FWH is
2031 * connected to GP30 on the Super I/O, and TBL# is always high.
2032 */
board_mitac_6513wu(void)2033 static int board_mitac_6513wu(void)
2034 {
2035 struct pci_dev *dev;
2036 uint16_t rt_port;
2037 uint8_t val;
2038
2039 dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */
2040 if (!dev) {
2041 msg_perr("\nERROR: Intel 82801AA ISA bridge not found.\n");
2042 return -1;
2043 }
2044
2045 rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa);
2046 if (rt_port == 0)
2047 return -1;
2048
2049 /* Configure the GPIO pin. */
2050 val = INB(rt_port + 0x33); /* GP30 config */
2051 val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */
2052 OUTB(val, rt_port + 0x33);
2053
2054 /* Disable write protection. */
2055 val = INB(rt_port + 0x4d); /* GP3 values */
2056 val |= 0x01; /* Set GP30 high. */
2057 OUTB(val, rt_port + 0x4d);
2058
2059 return 0;
2060 }
2061
2062 /*
2063 * Suited for:
2064 * - abit AV8: Socket939 + K8T800Pro + VT8237
2065 */
board_abit_av8(void)2066 static int board_abit_av8(void)
2067 {
2068 uint8_t val;
2069
2070 /* Raise GPO pins GP22 & GP23 */
2071 val = INB(0x404E);
2072 val |= 0xC0;
2073 OUTB(val, 0x404E);
2074
2075 return 0;
2076 }
2077
2078 /*
2079 * Suited for:
2080 * - ASUS A7V333: VIA KT333 + VT8233A + IT8703F
2081 * - ASUS A7V8X: VIA KT400 + VT8235 + IT8703F
2082 */
it8703f_gpio51_raise(void)2083 static int it8703f_gpio51_raise(void)
2084 {
2085 uint16_t id, base;
2086 uint8_t tmp;
2087
2088 /* Find the IT8703F. */
2089 w836xx_ext_enter(0x2E);
2090 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
2091 w836xx_ext_leave(0x2E);
2092
2093 if (id != 0x8701) {
2094 msg_perr("\nERROR: IT8703F Super I/O not found.\n");
2095 return -1;
2096 }
2097
2098 /* Get the GP567 I/O base. */
2099 w836xx_ext_enter(0x2E);
2100 sio_write(0x2E, 0x07, 0x0C);
2101 base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
2102 w836xx_ext_leave(0x2E);
2103
2104 if (!base) {
2105 msg_perr("\nERROR: Failed to read IT8703F Super I/O GPIO"
2106 " Base.\n");
2107 return -1;
2108 }
2109
2110 /* Raise GP51. */
2111 tmp = INB(base);
2112 tmp |= 0x02;
2113 OUTB(tmp, base);
2114
2115 return 0;
2116 }
2117
2118 /*
2119 * General routine for raising/dropping GPIO lines on the ITE IT87xx.
2120 */
it87_gpio_set(unsigned int gpio,int raise)2121 static int it87_gpio_set(unsigned int gpio, int raise)
2122 {
2123 int allowed, sio;
2124 unsigned int port;
2125 uint16_t base, sioport;
2126 uint8_t tmp;
2127
2128 /* IT87 GPIO configuration table */
2129 static const struct it87cfg {
2130 uint16_t id;
2131 uint8_t base_reg;
2132 uint32_t bank0;
2133 uint32_t bank1;
2134 uint32_t bank2;
2135 } it87_gpio_table[] = {
2136 {0x8712, 0x62, 0xCFF3FC00, 0x00FCFF3F, 0},
2137 {0x8718, 0x62, 0xCFF37C00, 0xF3FCDF3F, 0x0000000F},
2138 {0, 0, 0, 0, 0} /* end marker */
2139 };
2140 const struct it87cfg *cfg = NULL;
2141
2142 /* Find the Super I/O in the probed list */
2143 for (sio = 0; sio < superio_count; sio++) {
2144 int i;
2145 if (superios[sio].vendor != SUPERIO_VENDOR_ITE)
2146 continue;
2147
2148 /* Is this device in our list? */
2149 for (i = 0; it87_gpio_table[i].id; i++)
2150 if (superios[sio].model == it87_gpio_table[i].id) {
2151 cfg = &it87_gpio_table[i];
2152 goto found;
2153 }
2154 }
2155
2156 if (cfg == NULL) {
2157 msg_perr("\nERROR: No IT87 Super I/O GPIO configuration "
2158 "found.\n");
2159 return -1;
2160 }
2161
2162 found:
2163 /* Check whether the gpio is allowed. */
2164 if (gpio < 32)
2165 allowed = (cfg->bank0 >> gpio) & 0x01;
2166 else if (gpio < 64)
2167 allowed = (cfg->bank1 >> (gpio - 32)) & 0x01;
2168 else if (gpio < 96)
2169 allowed = (cfg->bank2 >> (gpio - 64)) & 0x01;
2170 else
2171 allowed = 0;
2172
2173 if (!allowed) {
2174 msg_perr("\nERROR: IT%02X does not allow setting GPIO%02u.\n",
2175 cfg->id, gpio);
2176 return -1;
2177 }
2178
2179 /* Read the Simple I/O Base Address Register */
2180 sioport = superios[sio].port;
2181 enter_conf_mode_ite(sioport);
2182 sio_write(sioport, 0x07, 0x07);
2183 base = (sio_read(sioport, cfg->base_reg) << 8) |
2184 sio_read(sioport, cfg->base_reg + 1);
2185 exit_conf_mode_ite(sioport);
2186
2187 if (!base) {
2188 msg_perr("\nERROR: Failed to read IT87 Super I/O GPIO Base.\n");
2189 return -1;
2190 }
2191
2192 msg_pdbg("Using IT87 GPIO base 0x%04x\n", base);
2193
2194 port = gpio / 10 - 1;
2195 gpio %= 10;
2196
2197 /* set GPIO. */
2198 tmp = INB(base + port);
2199 if (raise)
2200 tmp |= 1 << gpio;
2201 else
2202 tmp &= ~(1 << gpio);
2203 OUTB(tmp, base + port);
2204
2205 return 0;
2206 }
2207
2208 /*
2209 * Suited for:
2210 * - ASUS A7N8X-VM/400: NVIDIA nForce2 IGP2 + IT8712F
2211 */
it8712f_gpio12_raise(void)2212 static int it8712f_gpio12_raise(void)
2213 {
2214 return it87_gpio_set(12, 1);
2215 }
2216
2217 /*
2218 * Suited for:
2219 * - ASUS A7V600-X: VIA KT600 + VT8237 + IT8712F
2220 * - ASUS A7V8X-X: VIA KT400 + VT8235 + IT8712F
2221 */
it8712f_gpio31_raise(void)2222 static int it8712f_gpio31_raise(void)
2223 {
2224 return it87_gpio_set(32, 1);
2225 }
2226
2227 /*
2228 * Suited for:
2229 * - ASUS P5N-D: NVIDIA MCP51 + IT8718F
2230 * - ASUS P5N-E SLI: NVIDIA MCP51 + IT8718F
2231 */
it8718f_gpio63_raise(void)2232 static int it8718f_gpio63_raise(void)
2233 {
2234 return it87_gpio_set(63, 1);
2235 }
2236
2237 /*
2238 * Suited for all boards with ambiguous DMI chassis information, which should be
2239 * whitelisted because they are known to work:
2240 * - ASRock IMB-A180(-H)
2241 * - Intel D945GCNL
2242 * - MSC Q7 Tunnel Creek Module (Q7-TCTC)
2243 */
p2_not_a_laptop(void)2244 static int p2_not_a_laptop(void)
2245 {
2246 /* label this board as not a laptop */
2247 is_laptop = 0;
2248 msg_pdbg("Laptop detection overridden by P2 board enable.\n");
2249 return 0;
2250 }
2251
2252 /*
2253 * Suited for all laptops, which are known to *not* have interfering embedded controllers.
2254 */
p2_whitelist_laptop(void)2255 static int p2_whitelist_laptop(void)
2256 {
2257 is_laptop = 1;
2258 laptop_ok = 1;
2259 msg_pdbg("Whitelisted laptop detected.\n");
2260 return 0;
2261 }
2262
2263 #endif
2264
2265 /*
2266 * Below is the list of boards which need a special "board enable" code in
2267 * flashrom before their ROM chip can be accessed/written to.
2268 *
2269 * NOTE: Please add boards that _don't_ need such enables or don't work yet
2270 * to the respective tables in print.c. Thanks!
2271 *
2272 * We use 2 sets of PCI IDs here, you're free to choose which is which. This
2273 * is to provide a very high degree of certainty when matching a board on
2274 * the basis of subsystem/card IDs. As not every vendor handles
2275 * subsystem/card IDs in a sane manner.
2276 *
2277 * Keep the second set NULLed if it should be ignored. Keep the subsystem IDs
2278 * and the dmi identifier NULLed if they don't identify the board fully to disable autodetection.
2279 * But please take care to provide an as complete set of pci ids as possible;
2280 * autodetection is the preferred behaviour and we would like to make sure that
2281 * matches are unique.
2282 *
2283 * If PCI IDs are not sufficient for board matching, the match can be further
2284 * constrained by a string that has to be present in the DMI database for
2285 * the baseboard or the system entry. The pattern is matched by case sensitive
2286 * substring match, unless it is anchored to the beginning (with a ^ in front)
2287 * or the end (with a $ at the end). Both anchors may be specified at the
2288 * same time to match the full field.
2289 *
2290 * When a board is matched through DMI, the first and second main PCI IDs
2291 * and the first subsystem PCI ID have to match as well. If you specify the
2292 * first subsystem ID as 0x0:0x0, the DMI matching code expects that the
2293 * subsystem ID of that device is indeed zero.
2294 *
2295 * The coreboot ids are used two fold. When running with a coreboot firmware,
2296 * the ids uniquely matches the coreboot board identification string. When a
2297 * legacy bios is installed and when autodetection is not possible, these ids
2298 * can be used to identify the board through the -p internal:mainboard=
2299 * programmer parameter.
2300 *
2301 * When a board is identified through its coreboot ids (in both cases), the
2302 * main pci ids are still required to match, as a safeguard.
2303 */
2304
2305 /* Please keep this list alphabetically ordered by vendor/board name. */
2306 const struct board_match board_matches[] = {
2307
2308 /* first pci-id set [4], second pci-id set [4], dmi identifier, coreboot id [2], phase, vendor name, board name max_rom_... OK? flash enable */
2309 #if defined(__i386__) || defined(__x86_64__)
2310 {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, P3, "abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise},
2311 {0x1106, 0x0282, 0x147B, 0x1415, 0x1106, 0x3227, 0x147B, 0x1415, "^AV8 ", NULL, NULL, P3, "abit", "AV8", 0, OK, board_abit_av8},
2312 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, NULL /* "^I440BX-W977$" */, "abit", "bf6", P3, "abit", "BF6", 0, OK, intel_piix4_gpo26_lower},
2313 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^i440BX-W977 (BM6)$", NULL, NULL, P3, "abit", "BM6", 0, OK, intel_piix4_gpo26_lower},
2314 {0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, P3, "abit", "IC7", 0, NT, intel_ich_gpio23_raise},
2315 {0x8086, 0x2930, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, P3, "abit", "IP35", 0, OK, intel_ich_gpio16_raise},
2316 {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, P3, "abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise},
2317 {0x10de, 0x0050, 0x147b, 0x1c1a, 0x10de, 0x0052, 0x147b, 0x1c1a, NULL, NULL, NULL, P3, "abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower},
2318 {0x10de, 0x0369, 0x147b, 0x1c20, 0x10de, 0x0360, 0x147b, 0x1c20, "^KN9(NF-MCP55 series)$", NULL, NULL, P3, "abit", "KN9 Ultra", 0, OK, nvidia_mcp_gpio2_lower},
2319 {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, P3, "abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise},
2320 {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0260, 0x147b, 0x1c26, NULL, NULL, NULL, P3, "abit", "NF-M2 nView", 0, OK, nvidia_mcp_gpio4_lower},
2321 {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, "(VA6)$", NULL, NULL, P3, "abit", "VA6", 0, OK, via_apollo_gpo4_lower},
2322 {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", P3, "abit", "VT6X4", 0, OK, via_apollo_gpo4_lower},
2323 {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, P3, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd},
2324 {0x1022, 0x746B, 0, 0, 0x1022, 0x7460, 0, 0, NULL, "AGAMI", "ARUMA", P3, "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e},
2325 {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, P3, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e},
2326 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", P3, "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x},
2327 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", P3, "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x},
2328 {0x8086, 0x27b9, 0xa0a0, 0x0632, 0x8086, 0x27da, 0xa0a0, 0x0632, NULL, NULL, NULL, P3, "AOpen", "i945GMx-VFX", 0, OK, intel_ich_gpio38_raise},
2329 {0x8086, 0x2a00, 0xa0a0, 0x063e, 0x8086, 0x2815, 0xa0a0, 0x063e, NULL, NULL, NULL, P3, "AOpen", "i965GMt-LA", 0, OK, intel_ich_gpio20_raise},
2330 {0x8086, 0x277c, 0xa0a0, 0x060b, 0x8086, 0x27da, 0xa0a0, 0x060b, NULL, NULL, NULL, P3, "AOpen", "i975Xa-YDG", 0, OK, board_aopen_i975xa_ydg},
2331 {0x8086, 0x27A0, 0x8086, 0x7270, 0x8086, 0x27B9, 0x8086, 0x7270, "^iMac5,2$", NULL, NULL, P2, "Apple", "iMac5,2", 0, OK, p2_whitelist_laptop},
2332 {0x8086, 0x27A0, 0x8086, 0x7270, 0x8086, 0x27B9, 0x8086, 0x7270, "^MacBook2,1$", NULL, NULL, P2, "Apple", "MacBook2,1", 0, OK, p2_whitelist_laptop},
2333 {0x8086, 0x27b8, 0x1849, 0x27b8, 0x8086, 0x27da, 0x1849, 0x27da, "^ConRoeXFire-eSATA2", NULL, NULL, P3, "ASRock", "ConRoeXFire-eSATA2", 0, OK, intel_ich_gpio16_raise},
2334 {0x1022, 0x1536, 0x1849, 0x1536, 0x1022, 0x780e, 0x1849, 0x780e, "^Kabini CRB$", NULL, NULL, P2, "ASRock", "IMB-A180(-H)", 0, OK, p2_not_a_laptop},
2335 {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, P3, "ASRock", "K7S41", 0, OK, w836xx_memw_enable_2e},
2336 {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41GX$", NULL, NULL, P3, "ASRock", "K7S41GX", 0, OK, w836xx_memw_enable_2e},
2337 {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, P3, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise},
2338 {0x8086, 0x2570, 0x1849, 0x2570, 0x8086, 0x24d3, 0x1849, 0x24d0, NULL, NULL, NULL, P3, "ASRock", "775i65G", 0, OK, intel_ich_gpio23_raise},
2339 {0x10DE, 0x0060, 0x1043, 0x80AD, 0x10DE, 0x01E0, 0x1043, 0x80C0, NULL, NULL, NULL, P3, "ASUS", "A7N8X-VM/400", 0, OK, it8712f_gpio12_raise},
2340 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, P3, "ASUS", "A7V600-X", 0, OK, it8712f_gpio31_raise},
2341 {0x1106, 0x3177, 0x1043, 0x80F9, 0x1106, 0x3205, 0x1043, 0x80F9, NULL, NULL, NULL, P3, "ASUS", "A7V8X-MX", 0, OK, w836xx_memw_enable_2e},
2342 {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, P3, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e},
2343 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V8X", 0, OK, it8703f_gpio51_raise},
2344 {0x1106, 0x3099, 0x1043, 0x807F, 0x1106, 0x3147, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V333", 0, OK, it8703f_gpio51_raise},
2345 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, P3, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio31_raise},
2346 {0x1002, 0x4372, 0x103c, 0x2a26, 0x1002, 0x4377, 0x103c, 0x2a26, NULL, NULL, NULL, P3, "ASUS", "A8AE-LE", 0, OK, amd_sbxxx_gpio9_raise},
2347 {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, P3, "ASUS", "A8Jm", 0, NT, intel_ich_gpio34_raise},
2348 {0x10DE, 0x0260, 0x103C, 0x2A34, 0x10DE, 0x0264, 0x103C, 0x2A34, "NODUSM3", NULL, NULL, P3, "ASUS", "A8M2N-LA (NodusM3-GL8E)", 0, OK, nvidia_mcp_gpio0_raise},
2349 {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI2L", NULL, NULL, P3, "ASUS", "A8N-LA (Nagami-GL8E)", 0, OK, nvidia_mcp_gpio0_raise},
2350 {0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, P3, "ASUS", "A8N-VM CSM", 0, OK, w83627ehf_gpio22_raise_2e},
2351 {0x8086, 0x65c0, 0x1043, 0x8301, 0x8086, 0x2916, 0x1043, 0x82a6, "^DSAN-DX$", NULL, NULL, P3, "ASUS", "DSAN-DX", 0, NT, intel_ich_gpio32_raise},
2352 {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, P3, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise},
2353 {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, P3, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise},
2354 {0x8086, 0x24cc, 0, 0, 0x8086, 0x24c3, 0x1043, 0x1869, "^M6Ne$", NULL, NULL, P3, "ASUS", "M6Ne", 0, NT, intel_ich_gpio43_raise},
2355 {0x8086, 0x7180, 0, 0, 0x8086, 0x7110, 0, 0, "^OPLX-M$", NULL, NULL, P3, "ASUS", "OPLX-M", 0, NT, intel_piix4_gpo18_lower},
2356 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^P2B-N$", NULL, NULL, P3, "ASUS", "P2B-N", 0, OK, intel_piix4_gpo18_lower},
2357 {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, P3, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise},
2358 {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, P3, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise},
2359 {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, P3, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise},
2360 {0x8086, 0x2560, 0x103C, 0x2A00, 0x8086, 0x24C3, 0x103C, 0x2A01, "^Guppy", NULL, NULL, P3, "ASUS", "P4GV-LA (Guppy)", 0, OK, intel_ich_gpio21_raise},
2361 {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, P3, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
2362 {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D5, 0x1043, 0x80F3, NULL, NULL, NULL, P3, "ASUS", "P4P800", 0, NT, intel_ich_gpio21_raise},
2363 {0x8086, 0x2570, 0x1043, 0x80f2, 0x8086, 0x24d3, 0x1043, 0x80a6, "^P4P800-E$", NULL, NULL, P3, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
2364 {0x8086, 0x2570, 0x1043, 0x80a5, 0x8086, 0x24d3, 0x1043, 0x80a6, "^P4P800-VM$", NULL, NULL, P3, "ASUS", "P4P800-VM", 0, OK, intel_ich_gpio21_raise},
2365 {0x8086, 0x2570, 0x1043, 0x80f2, 0x8086, 0x24d3, 0x1043, 0x80a6, "^P4P800-X$", NULL, NULL, P3, "ASUS", "P4P800-X", 0, OK, intel_ich_gpio21_raise},
2366 {0x8086, 0x2570, 0x1043, 0x80f2, 0x8086, 0x24d3, 0, 0, "^P4P800SE$", NULL, NULL, P3, "ASUS", "P4P800SE", 0, OK, intel_ich_gpio21_raise},
2367 {0x8086, 0x2570, 0x1043, 0x80b2, 0x8086, 0x24c3, 0x1043, 0x8089, "^P4PE-X/TE$",NULL, NULL, P3, "ASUS", "P4PE-X/TE", 0, NT, intel_ich_gpio21_raise},
2368 {0x1039, 0x0651, 0x1043, 0x8081, 0x1039, 0x0962, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4SC-E", 0, OK, it8707f_write_enable_2e},
2369 {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, P3, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise},
2370 {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x5513, 0x1043, 0x8087, NULL, NULL, NULL, P3, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e},
2371 {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", P3, "ASUS", "P5A", 0, OK, board_asus_p5a},
2372 {0x8086, 0x27b8, 0x1043, 0x819e, 0x8086, 0x29f0, 0x1043, 0x82a5, "^P5BV-R$", NULL, NULL, P3, "ASUS", "P5BV-R", 0, OK, intel_ich_gpio20_raise},
2373 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, "^P5GD1 PRO$", NULL, NULL, P3, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise},
2374 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, "^P5GD1-VM$", NULL, NULL, P3, "ASUS", "P5GD1-VM/S", 0, OK, intel_ich_gpio21_raise},
2375 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, P3, "ASUS", "P5GD1(-VM)", 0, NT, intel_ich_gpio21_raise},
2376 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GD2-Premium$", NULL, NULL, P3, "ASUS", "P5GD2 Premium", 0, OK, intel_ich_gpio21_raise},
2377 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x81a6, "^P5GD2-X$", NULL, NULL, P3, "ASUS", "P5GD2-X", 0, OK, intel_ich_gpio21_raise},
2378 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GDC-V$", NULL, NULL, P3, "ASUS", "P5GDC-V Deluxe", 0, OK, intel_ich_gpio21_raise},
2379 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GDC$", NULL, NULL, P3, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise},
2380 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GD2/C variants", 0, NT, intel_ich_gpio21_raise},
2381 {0x8086, 0x27b8, 0x103c, 0x2a22, 0x8086, 0x2770, 0x103c, 0x2a22, "^LITHIUM$", NULL, NULL, P3, "ASUS", "P5LP-LE (Lithium-UL8E)",0, OK, intel_ich_gpio34_raise},
2382 {0x8086, 0x27b8, 0x1043, 0x2a22, 0x8086, 0x2770, 0x1043, 0x2a22, "^P5LP-LE$", NULL, NULL, P3, "ASUS", "P5LP-LE (Epson OEM)", 0, OK, intel_ich_gpio34_raise},
2383 {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, OK, intel_ich_gpio16_raise},
2384 {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b0, 0x1043, 0x8179, "^P5LD2-MQ$", NULL, NULL, P3, "ASUS", "P5LD2-MQ", 0, OK, intel_ich_gpio16_raise},
2385 {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2-VM$", NULL, NULL, P3, "ASUS", "P5LD2-VM", 0, OK, intel_ich_gpio16_raise},
2386 {0x8086, 0x27b0, 0x1043, 0x8179, 0x8086, 0x2770, 0x1043, 0x817a, "^P5LD2-VM DH$", NULL, NULL, P3, "ASUS", "P5LD2-VM DH", 0, OK, intel_ich_gpio16_raise},
2387 {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, P3, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise},
2388 {0x10DE, 0x0260, 0x1043, 0x81BC, 0x10DE, 0x026C, 0x1043, 0x829E, "^P5N-D$", NULL, NULL, P3, "ASUS", "P5N-D", 0, OK, it8718f_gpio63_raise},
2389 {0x10DE, 0x0260, 0x1043, 0x81BC, 0x10DE, 0x026C, 0x1043, 0x8249, "^P5N-E SLI$",NULL, NULL, P3, "ASUS", "P5N-E SLI", 0, NT, it8718f_gpio63_raise},
2390 {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, P3, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise},
2391 {0x8086, 0x2443, 0x1043, 0x8027, 0x8086, 0x1130, 0x1043, 0x8027, "^CUSL2-C", NULL, NULL, P3, "ASUS", "CUSL2-C", 0, OK, intel_ich_gpio21_raise},
2392 {0x8086, 0x2443, 0x1043, 0x8027, 0x8086, 0x1130, 0x1043, 0x8027, "^TUSL2-C", NULL, NULL, P3, "ASUS", "TUSL2-C", 0, NT, intel_ich_gpio21_raise},
2393 {0x1022, 0x780E, 0x1043, 0x1437, 0x1022, 0x780B, 0x1043, 0x1437, "^U38N$", NULL, NULL, P2, "ASUS", "U38N", 0, OK, p2_whitelist_laptop},
2394 {0x1106, 0x3059, 0x1106, 0x4161, 0x1106, 0x3065, 0x1106, 0x0102, NULL, NULL, NULL, P3, "Bcom/Clientron", "WinNET P680", 0, OK, w836xx_memw_enable_2e},
2395 {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3116, 0x1106, 0x3116, "^KM266-8235$", "biostar", "m7viq", P3, "Biostar", "M7VIQ", 0, NT, w83697xx_memw_enable_2e},
2396 {0x8086, 0x283e, 0x1028, 0x01f9, 0x8086, 0x2a01, 0, 0, "^Latitude D630", NULL, NULL, P2, "Dell", "Latitude D630", 0, OK, p2_whitelist_laptop},
2397 {0x10b7, 0x9055, 0x1028, 0x0082, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Dell", "OptiPlex GX1", 0, OK, intel_piix4_gpo30_lower},
2398 {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, P3, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise},
2399 {0x1106, 0x3189, 0x1106, 0x3189, 0x1106, 0x3177, 0x1106, 0x3177, "^AD77", "dfi", "ad77", P3, "DFI", "AD77", 0, NT, w836xx_memw_enable_2e},
2400 {0x1039, 0x6325, 0x1019, 0x0f05, 0x1039, 0x0016, 0, 0, NULL, NULL, NULL, P2, "Elitegroup", "A928", 0, OK, p2_whitelist_laptop},
2401 {0x10de, 0x03ea, 0x1019, 0x2602, 0x10de, 0x03e0, 0x1019, 0x2602, NULL, NULL, NULL, P3, "Elitegroup", "GeForce6100SM-M", 0, OK, board_ecs_geforce6100sm_m},
2402 {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, P3, "Elitegroup", "K7VTA3", 256, OK, NULL},
2403 {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, P3, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e},
2404 {0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, "8NPA7I", NULL, NULL, P3, "EPoX", "EP-8NPA7I", 0, OK, nvidia_mcp_gpio4_raise},
2405 {0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, "9NPA7I", NULL, NULL, P3, "EPoX", "EP-9NPA7I", 0, OK, nvidia_mcp_gpio4_raise},
2406 {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, P3, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise},
2407 {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", P3, "EPoX", "EP-BX3", 0, NT, intel_piix4_gpo22_raise},
2408 {0x10de, 0x02f0, 0x105b, 0x0d01, 0x10de, 0x0264, 0x105b, 0x0d01, NULL, NULL, NULL, P3, "Foxconn", "6150K8MD-8EKRSH", 0, NT, nvidia_mcp_gpio2_raise},
2409 {0x8086, 0x2A40, 0x1734, 0x1148, 0x8086, 0x2930, 0x1734, 0x1148, "^XY680", NULL, NULL, P2, "Fujitsu", "Amilo Xi 3650", 0, OK, p2_whitelist_laptop},
2410 {0x8086, 0x2443, 0x8086, 0x2442, 0x8086, 0x1130, 0x8086, 0x1130, "^6IEM ", NULL, NULL, P3, "GIGABYTE", "GA-6IEM", 0, NT, intel_ich_gpio25_raise},
2411 {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-7ZM", 512, OK, NULL},
2412 {0x8086, 0x2570, 0x1458, 0x2570, 0x8086, 0x24d0, 0, 0, "^8IP775/-G$",NULL, NULL, P3, "GIGABYTE", "GA-8IP775", 0, OK, intel_ich_gpio32_raise},
2413 {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise},
2414 {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise},
2415 {0x1039, 0x0650, 0x1039, 0x0650, 0x1039, 0x7012, 0x1458, 0xA002, "^GA-8SIMLFS20$", NULL, NULL, P3, "GIGABYTE", "GA-8SIMLFS 2.0", 0, OK, sis_gpio0_raise_and_w836xx_memw},
2416 {0x1039, 0x0651, 0x1039, 0x0651, 0x1039, 0x7002, 0x1458, 0x5004, "^GA-8SIMLH$",NULL, NULL, P3, "GIGABYTE", "GA-8SIMLH", 0, OK, sis_gpio0_raise_and_w836xx_memw},
2417 {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise},
2418 {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise},
2419 {0x10DE, 0x00E4, 0x1458, 0x0C11, 0x10DE, 0x00E0, 0x1458, 0x0C11, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8NS", 0, OK, nvidia_mcp_gpio0a_raise},
2420 {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise},
2421 {0x8086, 0x2415, 0x103c, 0x1250, 0x10b7, 0x9200, 0x103c, 0x1247, NULL, NULL, NULL, P3, "HP", "e-Vectra P2706T", 0, OK, board_hp_p2706t},
2422 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", P3, "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable},
2423 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", P3, "HP", "ProLiant DL165 G6", 0, OK, board_hp_dl165_g6_enable},
2424 {0x8086, 0x2580, 0x103c, 0x2a08, 0x8086, 0x2640, 0x103c, 0x2a0a, NULL, NULL, NULL, P3, "HP", "Puffer2-UL8E", 0, OK, intel_ich_gpio18_raise},
2425 {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, P3, "HP", "Vectra VL400", 0, OK, board_hp_vl400},
2426 {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, P3, "HP", "Vectra VL420 SFF", 0, OK, intel_ich_gpio22_raise},
2427 {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, "hp", "xw9400", P3, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise},
2428 {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", P3, "IBASE", "MB899", 0, OK, intel_ich_gpio26_raise},
2429 {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, P3, "IBM", "x3455", 0, OK, board_ibm_x3455},
2430 {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, P3, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi},
2431 {0x8086, 0x27b8, 0x8086, 0xd606, 0x8086, 0x2770, 0x8086, 0xd606, "^D945GCNL$", NULL, NULL, P2, "Intel", "D945GCNL", 0, OK, p2_not_a_laptop},
2432 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, P3, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower},
2433 {0x1022, 0x7468, 0, 0, 0x1022, 0x7460, 0, 0, NULL, "iwill", "dk8_htx", P3, "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e},
2434 {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", P3, "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m},
2435 {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad R400", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad R400", 0, OK, p2_whitelist_laptop},
2436 {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad T400", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T400", 0, OK, p2_whitelist_laptop},
2437 {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad T500", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T500", 0, OK, p2_whitelist_laptop},
2438 {0x8086, 0x1E22, 0x17AA, 0x21F6, 0x8086, 0x1E55, 0x17AA, 0x21F6, "^ThinkPad T530", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T530", 0, OK, p2_whitelist_laptop},
2439 {0x8086, 0x27a0, 0x17aa, 0x2015, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T60", 0, OK, p2_whitelist_laptop},
2440 {0x8086, 0x27a0, 0x17aa, 0x2017, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T60(s)", 0, OK, p2_whitelist_laptop},
2441 {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad W500", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad W500", 0, OK, p2_whitelist_laptop},
2442 {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad X200", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X200", 0, OK, p2_whitelist_laptop},
2443 {0x8086, 0x3B07, 0x17AA, 0x2166, 0x8086, 0x3B30, 0x17AA, 0x2167, "^ThinkPad X201", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X201", 0, OK, p2_whitelist_laptop},
2444 {0x8086, 0x1C22, 0x17AA, 0x21DB, 0x8086, 0x1C4F, 0x17AA, 0x21DB, NULL, "lenovo", "x220", P2, "IBM/Lenovo", "ThinkPad X220", 0, OK, p2_whitelist_laptop},
2445 {0x8086, 0x1E22, 0x17AA, 0x21FA, 0x8086, 0x1E55, 0x17AA, 0x21FA, "^ThinkPad X230", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X230", 0, OK, p2_whitelist_laptop},
2446 {0x8086, 0x27A0, 0x17AA, 0x2017, 0x8086, 0x27B9, 0x17AA, 0x2009, "^ThinkPad X60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X60(s)", 0, OK, p2_whitelist_laptop},
2447 {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^Taurinus X200", "Libiquity", "Taurinus X200", P2, "Libiquity", "ThinkPad X200", 0, OK, p2_whitelist_laptop},
2448 {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, P3, "Mitac", "6513WU", 0, OK, board_mitac_6513wu},
2449 {0x8086, 0x8186, 0x8086, 0x8186, 0x8086, 0x8800, 0, 0, "^MSC Vertriebs GmbH$", NULL, NULL, P2, "MSC", "Q7-TCTC", 0, OK, p2_not_a_laptop},
2450 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^MS-6163 (i440BX)$", NULL, NULL, P3, "MSI", "MS-6163 (MS-6163 Pro)", 0, OK, intel_piix4_gpo14_raise},
2451 {0x8086, 0x244b, 0x1462, 0x3910, 0x8086, 0x2442, 0x1462, 0x3910, NULL, NULL, NULL, P3, "MSI", "MS-6391 (845 Pro4)", 0, OK, intel_ich_gpio23_raise},
2452 {0x1039, 0x0745, 0, 0, 0x1039, 0x0018, 0, 0, "^MS-6561", NULL, NULL, P3, "MSI", "MS-6561 (745 Ultra)", 0, OK, w836xx_memw_enable_2e},
2453 {0x8086, 0x2560, 0x1462, 0x5770, 0x8086, 0x24C3, 0x1462, 0x5770, NULL, NULL, NULL, P3, "MSI", "MS-6577 (Xenon)", 0, OK, w83627hf_gpio25_raise_2e},
2454 {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, P3, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v},
2455 {0x1106, 0x0282, 0x1106, 0x0282, 0x1106, 0x3227, 0x1106, 0x3227, "^MS-7094$", NULL, NULL, P3, "MSI", "MS-7094 (K8T Neo2-F V2.0)", 0, OK, w83627thf_gpio44_raise_2e},
2456 {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, P3, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v},
2457 {0x1106, 0x3148, 0 , 0 , 0x1106, 0x3177, 0 , 0 , NULL, "msi", "ms6787", P3, "MSI", "MS-6787 (P4MAM-V/P4MAM-L)", 0, OK, w836xx_memw_enable_2e},
2458 {0x8086, 0x24d3, 0x1462, 0x7880, 0x8086, 0x2570, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-6788-040 (848P NeoV)", 0, OK, intel_ich_gpio32_raise},
2459 {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, P3, "MSI", "MS-7005 (651M-L)", 0, OK, sis_gpio0_raise_and_w836xx_memw},
2460 {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, P3, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, OK, nvidia_mcp_gpio0c_raise},
2461 {0x10DE, 0x00E0, 0x1462, 0x0300, 0x10DE, 0x00E1, 0x1462, 0x0300, NULL, NULL, NULL, P3, "MSI", "MS-7030 (K8N Neo Platinum)", 0, OK, nvidia_mcp_gpio0c_raise},
2462 {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, P3, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise},
2463 {0x1106, 0x3149, 0x1462, 0x7061, 0x1106, 0x3227, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-7061 (KM4M-V/KM4AM-V)", 0, OK, w836xx_memw_enable_2e},
2464 {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, P3, "MSI", "MS-7125 (K8N Neo4(-F/-FI/-FX/Platinum))", 0, OK, nvidia_mcp_gpio2_raise},
2465 {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", P3, "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio44_raise_4e},
2466 {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, P3, "MSI", "MS-7207 (K8NGM2-L)", 0, NT, nvidia_mcp_gpio2_raise},
2467 {0x10DE, 0x0360, 0x1462, 0x7250, 0x10DE, 0x0368, 0x1462, 0x7250, NULL, NULL, NULL, P3, "MSI", "MS-7250 (K9N SLI)", 0, OK, nvidia_mcp_gpio2_raise},
2468 {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0},
2469 {0x8086, 0x3B30, 0x1025, 0x0379, 0x8086, 0x3B09, 0x1025, 0x0379, "^EasyNote LM85$", NULL, NULL, P2, "Packard Bell","EasyNote LM85", 0, OK, p2_whitelist_laptop},
2470 {0x8086, 0x0154, 0x8086, 0x0154, 0x8086, 0x1e55, 0x8086, 0x1e55, "RV11$", "Roda", "Lizard RV11", P2, "Roda", "RV11", 0, OK, p2_whitelist_laptop},
2471 {0x8086, 0x24d3, 0x144d, 0xb025, 0x8086, 0x1050, 0x144d, 0xb025, NULL, NULL, NULL, P3, "Samsung", "Polaris 32", 0, OK, intel_ich_gpio21_raise},
2472 {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", P3, "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e},
2473 {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, P3, "Shuttle", "AK38N", 256, OK, NULL},
2474 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, P3, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower},
2475 {0x10de, 0x0364, 0x108e, 0x6676, 0x10de, 0x0369, 0x108e, 0x6676, "^Sun Ultra 40 M2", NULL, NULL, P3, "Sun", "Ultra 40 M2", 0, OK, board_sun_ultra_40_m2},
2476 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, P3, "Tekram", "P6Pro-A5", 256, OK, NULL},
2477 {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, P3, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e},
2478 {0x8086, 0x7120, 0x109f, 0x3157, 0x8086, 0x2410, 0, 0, NULL, NULL, NULL, P3, "TriGem", "Anaheim-3", 0, OK, intel_ich_gpio22_raise},
2479 {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, P3, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e},
2480 {0x1106, 0x0259, 0x1106, 0xAA07, 0x1106, 0x3227, 0x1106, 0xAA07, NULL, NULL, NULL, P3, "VIA", "EPIA EK", 0, NT, via_vt823x_gpio9_raise},
2481 {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, P3, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise},
2482 {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, P3, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise},
2483 #endif
2484 { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, P3, NULL, NULL, 0, NT, NULL}, /* end marker */
2485 };
2486
selfcheck_board_enables(void)2487 int selfcheck_board_enables(void)
2488 {
2489 if (board_matches[ARRAY_SIZE(board_matches) - 1].vendor_name != NULL) {
2490 msg_gerr("Board enables table miscompilation!\n");
2491 return 1;
2492 }
2493
2494 int ret = 0;
2495 unsigned int i;
2496 for (i = 0; i + 1 < ARRAY_SIZE(board_matches); i++) {
2497 const struct board_match *b = &board_matches[i];
2498 if (b->vendor_name == NULL || b->board_name == NULL) {
2499 msg_gerr("ERROR: Board enable #%d does not define a vendor and board name.\n"
2500 "Please report a bug at flashrom@flashrom.org\n", i);
2501 ret = 1;
2502 continue;
2503 }
2504 if ((b->first_vendor == 0 || b->first_device == 0 ||
2505 b->second_vendor == 0 || b->second_device == 0) ||
2506 ((b->lb_vendor == NULL) ^ (b->lb_part == NULL)) ||
2507 (b->max_rom_decode_parallel == 0 && b->enable == NULL)) {
2508 msg_gerr("ERROR: Board enable for %s %s is misdefined.\n"
2509 "Please report a bug at flashrom@flashrom.org\n",
2510 b->vendor_name, b->board_name);
2511 ret = 1;
2512 }
2513 }
2514 return ret;
2515 }
2516
2517 /* Parse the <vendor>:<board> string specified by the user as part of -p internal:mainboard=<vendor>:<board>.
2518 * Parameters vendor and model will be overwritten. Returns 0 on success.
2519 * Note: strtok modifies the original string, so we work on a copy and allocate memory for the results.
2520 */
board_parse_parameter(const char * boardstring,char ** vendor,char ** model)2521 int board_parse_parameter(const char *boardstring, char **vendor, char **model)
2522 {
2523 /* strtok may modify the original string. */
2524 char *tempstr = strdup(boardstring);
2525 char *tempstr2 = NULL;
2526 strtok(tempstr, ":");
2527 tempstr2 = strtok(NULL, ":");
2528 if (tempstr == NULL || tempstr2 == NULL) {
2529 free(tempstr);
2530 msg_pinfo("Please supply the board vendor and model name with the "
2531 "-p internal:mainboard=<vendor>:<model> option.\n");
2532 return 1;
2533 }
2534 *vendor = strdup(tempstr);
2535 *model = strdup(tempstr2);
2536 msg_pspew("-p internal:mainboard: vendor=\"%s\", model=\"%s\"\n", tempstr, tempstr2);
2537 free(tempstr);
2538 return 0;
2539 }
2540
2541 /*
2542 * Match boards on vendor and model name.
2543 * The string parameters can come either from the coreboot table or the command line (i.e. the user).
2544 * The boolean needs to be set accordingly to compare them to the right entries of the board enables table.
2545 * Require main PCI IDs to match too as extra safety.
2546 * Parameters vendor and model must be non-NULL!
2547 */
board_match_name(const char * vendor,const char * model,bool cb)2548 static const struct board_match *board_match_name(const char *vendor, const char *model, bool cb)
2549 {
2550 const struct board_match *board = board_matches;
2551 const struct board_match *partmatch = NULL;
2552
2553 for (; board->vendor_name; board++) {
2554 const char *cur_vendor = cb ? board->lb_vendor : board->vendor_name;
2555 const char *cur_model = cb ? board->lb_part : board->board_name;
2556
2557 if (!cur_vendor || strcasecmp(cur_vendor, vendor))
2558 continue;
2559
2560 if (!cur_model || strcasecmp(cur_model, model))
2561 continue;
2562
2563 if (!pci_dev_find(board->first_vendor, board->first_device)) {
2564 msg_pdbg("Odd. Board name \"%s\":\"%s\" matches, but first PCI device %04x:%04x "
2565 "doesn't.\n", vendor, model, board->first_vendor, board->first_device);
2566 continue;
2567 }
2568
2569 if (!pci_dev_find(board->second_vendor, board->second_device)) {
2570 msg_pdbg("Odd. Board name \"%s\":\"%s\" matches, but second PCI device %04x:%04x "
2571 "doesn't.\n", vendor, model, board->second_vendor, board->second_device);
2572 continue;
2573 }
2574
2575 if (partmatch) {
2576 /* More than one entry has a matching name. */
2577 msg_perr("Board name \"%s\":\"%s\" and PCI IDs matched more than one board enable "
2578 "entry. Please report a bug at flashrom@flashrom.org\n", vendor, model);
2579 return NULL;
2580 }
2581 partmatch = board;
2582 }
2583
2584 if (partmatch)
2585 return partmatch;
2586
2587 return NULL;
2588 }
2589
2590 /*
2591 * Match boards on PCI IDs and subsystem IDs.
2592 * Second set of IDs can be either main+subsystem IDs, main IDs or no IDs.
2593 */
board_match_pci_ids(enum board_match_phase phase)2594 static const struct board_match *board_match_pci_ids(enum board_match_phase phase)
2595 {
2596 const struct board_match *board = board_matches;
2597
2598 for (; board->vendor_name; board++) {
2599 if ((!board->first_card_vendor || !board->first_card_device) &&
2600 !board->dmi_pattern)
2601 continue;
2602 if (board->phase != phase)
2603 continue;
2604
2605 if (!pci_card_find(board->first_vendor, board->first_device,
2606 board->first_card_vendor,
2607 board->first_card_device))
2608 continue;
2609
2610 if (board->second_vendor) {
2611 if (board->second_card_vendor) {
2612 if (!pci_card_find(board->second_vendor,
2613 board->second_device,
2614 board->second_card_vendor,
2615 board->second_card_device))
2616 continue;
2617 } else {
2618 if (!pci_dev_find(board->second_vendor,
2619 board->second_device))
2620 continue;
2621 }
2622 }
2623
2624 #if defined(__i386__) || defined(__x86_64__)
2625 if (board->dmi_pattern) {
2626 if (!has_dmi_support) {
2627 msg_pwarn("Warning: Can't autodetect %s %s, DMI info unavailable.\n",
2628 board->vendor_name, board->board_name);
2629 msg_pinfo("Please supply the board vendor and model name with the "
2630 "-p internal:mainboard=<vendor>:<model> option.\n");
2631 continue;
2632 } else {
2633 if (!dmi_match(board->dmi_pattern))
2634 continue;
2635 }
2636 }
2637 #endif // defined(__i386__) || defined(__x86_64__)
2638 return board;
2639 }
2640
2641 return NULL;
2642 }
2643
board_enable_safetycheck(const struct board_match * board)2644 static int board_enable_safetycheck(const struct board_match *board)
2645 {
2646 if (!board)
2647 return 1;
2648
2649 if (board->status == OK)
2650 return 0;
2651
2652 if (!force_boardenable) {
2653 msg_pwarn("Warning: The mainboard-specific code for %s %s has not been tested,\n"
2654 "and thus will not be executed by default. Depending on your hardware,\n"
2655 "erasing, writing or even probing can fail without running this code.\n\n"
2656 "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n"
2657 "\"internal programmer\") for details.\n", board->vendor_name, board->board_name);
2658 return 1;
2659 }
2660 msg_pwarn("NOTE: Running an untested board enable procedure.\n"
2661 "Please report success/failure to flashrom@flashrom.org.\n");
2662 return 0;
2663 }
2664
2665 /* FIXME: Should this be identical to board_flash_enable? */
board_handle_phase(enum board_match_phase phase)2666 static int board_handle_phase(enum board_match_phase phase)
2667 {
2668 const struct board_match *board = NULL;
2669
2670 board = board_match_pci_ids(phase);
2671
2672 if (!board)
2673 return 0;
2674
2675 if (board_enable_safetycheck(board))
2676 return 0;
2677
2678 if (!board->enable) {
2679 /* Not sure if there is a valid case for this. */
2680 msg_perr("Board match found, but nothing to do?\n");
2681 return 0;
2682 }
2683
2684 return board->enable();
2685 }
2686
board_handle_before_superio(void)2687 void board_handle_before_superio(void)
2688 {
2689 board_handle_phase(P1);
2690 }
2691
board_handle_before_laptop(void)2692 void board_handle_before_laptop(void)
2693 {
2694 board_handle_phase(P2);
2695 }
2696
board_flash_enable(const char * vendor,const char * model,const char * cb_vendor,const char * cb_model)2697 int board_flash_enable(const char *vendor, const char *model, const char *cb_vendor, const char *cb_model)
2698 {
2699 const struct board_match *board = NULL;
2700 int ret = 0;
2701
2702 if (vendor != NULL && model != NULL) {
2703 board = board_match_name(vendor, model, false);
2704 if (!board) { /* If a board was given by the user it has to match, else we abort here. */
2705 msg_perr("No suitable board enable found for vendor=\"%s\", model=\"%s\".\n",
2706 vendor, model);
2707 return 1;
2708 }
2709 }
2710 if (board == NULL && cb_vendor != NULL && cb_model != NULL) {
2711 board = board_match_name(cb_vendor, cb_model, true);
2712 if (!board) { /* Failure is an option here, because many cb boards don't require an enable. */
2713 msg_pdbg2("No board enable found matching coreboot IDs vendor=\"%s\", model=\"%s\".\n",
2714 cb_vendor, cb_model);
2715 }
2716 }
2717 if (board == NULL) {
2718 board = board_match_pci_ids(P3);
2719 if (!board) /* i.e. there is just no board enable available for this board */
2720 return 0;
2721 }
2722
2723 if (board_enable_safetycheck(board))
2724 return 1;
2725
2726 /* limit the maximum size of the parallel bus */
2727 if (board->max_rom_decode_parallel)
2728 max_rom_decode.parallel = board->max_rom_decode_parallel * 1024;
2729
2730 if (board->enable != NULL) {
2731 msg_pinfo("Enabling full flash access for board \"%s %s\"... ",
2732 board->vendor_name, board->board_name);
2733
2734 ret = board->enable();
2735 if (ret)
2736 msg_pinfo("FAILED!\n");
2737 else
2738 msg_pinfo("OK.\n");
2739 }
2740
2741 return ret;
2742 }
2743