1 //////////////////////////////////////////////////////////////////////////////// 2 // 3 // The University of Illinois/NCSA 4 // Open Source License (NCSA) 5 // 6 // Copyright (c) 2014-2015, Advanced Micro Devices, Inc. All rights reserved. 7 // 8 // Developed by: 9 // 10 // AMD Research and AMD HSA Software Development 11 // 12 // Advanced Micro Devices, Inc. 13 // 14 // www.amd.com 15 // 16 // Permission is hereby granted, free of charge, to any person obtaining a copy 17 // of this software and associated documentation files (the "Software"), to 18 // deal with the Software without restriction, including without limitation 19 // the rights to use, copy, modify, merge, publish, distribute, sublicense, 20 // and/or sell copies of the Software, and to permit persons to whom the 21 // Software is furnished to do so, subject to the following conditions: 22 // 23 // - Redistributions of source code must retain the above copyright notice, 24 // this list of conditions and the following disclaimers. 25 // - Redistributions in binary form must reproduce the above copyright 26 // notice, this list of conditions and the following disclaimers in 27 // the documentation and/or other materials provided with the distribution. 28 // - Neither the names of Advanced Micro Devices, Inc, 29 // nor the names of its contributors may be used to endorse or promote 30 // products derived from this Software without specific prior written 31 // permission. 32 // 33 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 34 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 35 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 36 // THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 37 // OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 38 // ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 39 // DEALINGS WITH THE SOFTWARE. 40 // 41 //////////////////////////////////////////////////////////////////////////////// 42 43 #ifndef AMD_HSA_ELF_H 44 #define AMD_HSA_ELF_H 45 46 #include "amd_hsa_common.h" 47 48 // ELF Header Enumeration Values. 49 #define EM_AMDGPU 224 50 #define ELFOSABI_AMDGPU_HSA 64 51 #define ELFABIVERSION_AMDGPU_HSA 0 52 #define EF_AMDGPU_XNACK 0x00000001 53 #define EF_AMDGPU_TRAP_HANDLER 0x00000002 54 55 // FIXME: We really need to start thinking about separating legacy code out, 56 // it is getting messy. 57 #define EF_AMDGPU_XNACK_LC 0x100 58 59 // ELF Section Header Flag Enumeration Values. 60 #define SHF_AMDGPU_HSA_GLOBAL (0x00100000 & SHF_MASKOS) 61 #define SHF_AMDGPU_HSA_READONLY (0x00200000 & SHF_MASKOS) 62 #define SHF_AMDGPU_HSA_CODE (0x00400000 & SHF_MASKOS) 63 #define SHF_AMDGPU_HSA_AGENT (0x00800000 & SHF_MASKOS) 64 65 // 66 typedef enum { 67 AMDGPU_HSA_SEGMENT_GLOBAL_PROGRAM = 0, 68 AMDGPU_HSA_SEGMENT_GLOBAL_AGENT = 1, 69 AMDGPU_HSA_SEGMENT_READONLY_AGENT = 2, 70 AMDGPU_HSA_SEGMENT_CODE_AGENT = 3, 71 AMDGPU_HSA_SEGMENT_LAST, 72 } amdgpu_hsa_elf_segment_t; 73 74 // ELF Program Header Type Enumeration Values. 75 #define PT_AMDGPU_HSA_LOAD_GLOBAL_PROGRAM (PT_LOOS + AMDGPU_HSA_SEGMENT_GLOBAL_PROGRAM) 76 #define PT_AMDGPU_HSA_LOAD_GLOBAL_AGENT (PT_LOOS + AMDGPU_HSA_SEGMENT_GLOBAL_AGENT) 77 #define PT_AMDGPU_HSA_LOAD_READONLY_AGENT (PT_LOOS + AMDGPU_HSA_SEGMENT_READONLY_AGENT) 78 #define PT_AMDGPU_HSA_LOAD_CODE_AGENT (PT_LOOS + AMDGPU_HSA_SEGMENT_CODE_AGENT) 79 80 // ELF Symbol Type Enumeration Values. 81 #define STT_AMDGPU_HSA_KERNEL (STT_LOOS + 0) 82 #define STT_AMDGPU_HSA_INDIRECT_FUNCTION (STT_LOOS + 1) 83 #define STT_AMDGPU_HSA_METADATA (STT_LOOS + 2) 84 85 // ELF Symbol Binding Enumeration Values. 86 #define STB_AMDGPU_HSA_EXTERNAL (STB_LOOS + 0) 87 88 // ELF Symbol Other Information Creation/Retrieval. 89 #define ELF64_ST_AMDGPU_ALLOCATION(o) (((o) >> 2) & 0x3) 90 #define ELF64_ST_AMDGPU_FLAGS(o) ((o) >> 4) 91 #define ELF64_ST_AMDGPU_OTHER(f, a, v) (((f) << 4) + (((a) & 0x3) << 2) + ((v) & 0x3)) 92 93 typedef enum { 94 AMDGPU_HSA_SYMBOL_ALLOCATION_DEFAULT = 0, 95 AMDGPU_HSA_SYMBOL_ALLOCATION_GLOBAL_PROGRAM = 1, 96 AMDGPU_HSA_SYMBOL_ALLOCATION_GLOBAL_AGENT = 2, 97 AMDGPU_HSA_SYMBOL_ALLOCATION_READONLY_AGENT = 3, 98 AMDGPU_HSA_SYMBOL_ALLOCATION_LAST, 99 } amdgpu_hsa_symbol_allocation_t; 100 101 // ELF Symbol Allocation Enumeration Values. 102 #define STA_AMDGPU_HSA_DEFAULT AMDGPU_HSA_SYMBOL_ALLOCATION_DEFAULT 103 #define STA_AMDGPU_HSA_GLOBAL_PROGRAM AMDGPU_HSA_SYMBOL_ALLOCATION_GLOBAL_PROGRAM 104 #define STA_AMDGPU_HSA_GLOBAL_AGENT AMDGPU_HSA_SYMBOL_ALLOCATION_GLOBAL_AGENT 105 #define STA_AMDGPU_HSA_READONLY_AGENT AMDGPU_HSA_SYMBOL_ALLOCATION_READONLY_AGENT 106 107 typedef enum { 108 AMDGPU_HSA_SYMBOL_FLAG_DEFAULT = 0, 109 AMDGPU_HSA_SYMBOL_FLAG_CONST = 1, 110 AMDGPU_HSA_SYMBOL_FLAG_LAST, 111 } amdgpu_hsa_symbol_flag_t; 112 113 // ELF Symbol Flag Enumeration Values. 114 #define STF_AMDGPU_HSA_CONST AMDGPU_HSA_SYMBOL_FLAG_CONST 115 116 // AMD GPU Relocation Type Enumeration Values. 117 #define R_AMDGPU_NONE 0 118 #define R_AMDGPU_32_LOW 1 119 #define R_AMDGPU_32_HIGH 2 120 #define R_AMDGPU_64 3 121 #define R_AMDGPU_INIT_SAMPLER 4 122 #define R_AMDGPU_INIT_IMAGE 5 123 #define R_AMDGPU_RELATIVE64 13 124 125 // AMD GPU Note Type Enumeration Values. 126 #define NT_AMDGPU_HSA_CODE_OBJECT_VERSION 1 127 #define NT_AMDGPU_HSA_HSAIL 2 128 #define NT_AMDGPU_HSA_ISA 3 129 #define NT_AMDGPU_HSA_PRODUCER 4 130 #define NT_AMDGPU_HSA_PRODUCER_OPTIONS 5 131 #define NT_AMDGPU_HSA_EXTENSION 6 132 #define NT_AMDGPU_HSA_HLDEBUG_DEBUG 101 133 #define NT_AMDGPU_HSA_HLDEBUG_TARGET 102 134 135 // AMD GPU Metadata Kind Enumeration Values. 136 typedef uint16_t amdgpu_hsa_metadata_kind16_t; 137 typedef enum { 138 AMDGPU_HSA_METADATA_KIND_NONE = 0, 139 AMDGPU_HSA_METADATA_KIND_INIT_SAMP = 1, 140 AMDGPU_HSA_METADATA_KIND_INIT_ROIMG = 2, 141 AMDGPU_HSA_METADATA_KIND_INIT_WOIMG = 3, 142 AMDGPU_HSA_METADATA_KIND_INIT_RWIMG = 4 143 } amdgpu_hsa_metadata_kind_t; 144 145 // AMD GPU Sampler Coordinate Normalization Enumeration Values. 146 typedef uint8_t amdgpu_hsa_sampler_coord8_t; 147 typedef enum { 148 AMDGPU_HSA_SAMPLER_COORD_UNNORMALIZED = 0, 149 AMDGPU_HSA_SAMPLER_COORD_NORMALIZED = 1 150 } amdgpu_hsa_sampler_coord_t; 151 152 // AMD GPU Sampler Filter Enumeration Values. 153 typedef uint8_t amdgpu_hsa_sampler_filter8_t; 154 typedef enum { 155 AMDGPU_HSA_SAMPLER_FILTER_NEAREST = 0, 156 AMDGPU_HSA_SAMPLER_FILTER_LINEAR = 1 157 } amdgpu_hsa_sampler_filter_t; 158 159 // AMD GPU Sampler Addressing Enumeration Values. 160 typedef uint8_t amdgpu_hsa_sampler_addressing8_t; 161 typedef enum { 162 AMDGPU_HSA_SAMPLER_ADDRESSING_UNDEFINED = 0, 163 AMDGPU_HSA_SAMPLER_ADDRESSING_CLAMP_TO_EDGE = 1, 164 AMDGPU_HSA_SAMPLER_ADDRESSING_CLAMP_TO_BORDER = 2, 165 AMDGPU_HSA_SAMPLER_ADDRESSING_REPEAT = 3, 166 AMDGPU_HSA_SAMPLER_ADDRESSING_MIRRORED_REPEAT = 4 167 } amdgpu_hsa_sampler_addressing_t; 168 169 // AMD GPU Sampler Descriptor. 170 typedef struct amdgpu_hsa_sampler_descriptor_s { 171 uint16_t size; 172 amdgpu_hsa_metadata_kind16_t kind; 173 amdgpu_hsa_sampler_coord8_t coord; 174 amdgpu_hsa_sampler_filter8_t filter; 175 amdgpu_hsa_sampler_addressing8_t addressing; 176 uint8_t reserved1; 177 } amdgpu_hsa_sampler_descriptor_t; 178 179 // AMD GPU Image Geometry Enumeration Values. 180 typedef uint8_t amdgpu_hsa_image_geometry8_t; 181 typedef enum { 182 AMDGPU_HSA_IMAGE_GEOMETRY_1D = 0, 183 AMDGPU_HSA_IMAGE_GEOMETRY_2D = 1, 184 AMDGPU_HSA_IMAGE_GEOMETRY_3D = 2, 185 AMDGPU_HSA_IMAGE_GEOMETRY_1DA = 3, 186 AMDGPU_HSA_IMAGE_GEOMETRY_2DA = 4, 187 AMDGPU_HSA_IMAGE_GEOMETRY_1DB = 5, 188 AMDGPU_HSA_IMAGE_GEOMETRY_2DDEPTH = 6, 189 AMDGPU_HSA_IMAGE_GEOMETRY_2DADEPTH = 7 190 } amdgpu_hsa_image_geometry_t; 191 192 // AMD GPU Image Channel Order Enumeration Values. 193 typedef uint8_t amdgpu_hsa_image_channel_order8_t; 194 typedef enum { 195 AMDGPU_HSA_IMAGE_CHANNEL_ORDER_A = 0, 196 AMDGPU_HSA_IMAGE_CHANNEL_ORDER_R = 1, 197 AMDGPU_HSA_IMAGE_CHANNEL_ORDER_RX = 2, 198 AMDGPU_HSA_IMAGE_CHANNEL_ORDER_RG = 3, 199 AMDGPU_HSA_IMAGE_CHANNEL_ORDER_RGX = 4, 200 AMDGPU_HSA_IMAGE_CHANNEL_ORDER_RA = 5, 201 AMDGPU_HSA_IMAGE_CHANNEL_ORDER_RGB = 6, 202 AMDGPU_HSA_IMAGE_CHANNEL_ORDER_RGBX = 7, 203 AMDGPU_HSA_IMAGE_CHANNEL_ORDER_RGBA = 8, 204 AMDGPU_HSA_IMAGE_CHANNEL_ORDER_BGRA = 9, 205 AMDGPU_HSA_IMAGE_CHANNEL_ORDER_ARGB = 10, 206 AMDGPU_HSA_IMAGE_CHANNEL_ORDER_ABGR = 11, 207 AMDGPU_HSA_IMAGE_CHANNEL_ORDER_SRGB = 12, 208 AMDGPU_HSA_IMAGE_CHANNEL_ORDER_SRGBX = 13, 209 AMDGPU_HSA_IMAGE_CHANNEL_ORDER_SRGBA = 14, 210 AMDGPU_HSA_IMAGE_CHANNEL_ORDER_SBGRA = 15, 211 AMDGPU_HSA_IMAGE_CHANNEL_ORDER_INTENSITY = 16, 212 AMDGPU_HSA_IMAGE_CHANNEL_ORDER_LUMINANCE = 17, 213 AMDGPU_HSA_IMAGE_CHANNEL_ORDER_DEPTH = 18, 214 AMDGPU_HSA_IMAGE_CHANNEL_ORDER_DEPTH_STENCIL = 19 215 } amdgpu_hsa_image_channel_order_t; 216 217 // AMD GPU Image Channel Type Enumeration Values. 218 typedef uint8_t amdgpu_hsa_image_channel_type8_t; 219 typedef enum { 220 AMDGPU_HSA_IMAGE_CHANNEL_TYPE_SNORM_INT8 = 0, 221 AMDGPU_HSA_IMAGE_CHANNEL_TYPE_SNORM_INT16 = 1, 222 AMDGPU_HSA_IMAGE_CHANNEL_TYPE_UNORM_INT8 = 2, 223 AMDGPU_HSA_IMAGE_CHANNEL_TYPE_UNORM_INT16 = 3, 224 AMDGPU_HSA_IMAGE_CHANNEL_TYPE_UNORM_INT24 = 4, 225 AMDGPU_HSA_IMAGE_CHANNEL_TYPE_SHORT_555 = 5, 226 AMDGPU_HSA_IMAGE_CHANNEL_TYPE_SHORT_565 = 6, 227 AMDGPU_HSA_IMAGE_CHANNEL_TYPE_INT_101010 = 7, 228 AMDGPU_HSA_IMAGE_CHANNEL_TYPE_SIGNED_INT8 = 8, 229 AMDGPU_HSA_IMAGE_CHANNEL_TYPE_SIGNED_INT16 = 9, 230 AMDGPU_HSA_IMAGE_CHANNEL_TYPE_SIGNED_INT32 = 10, 231 AMDGPU_HSA_IMAGE_CHANNEL_TYPE_UNSIGNED_INT8 = 11, 232 AMDGPU_HSA_IMAGE_CHANNEL_TYPE_UNSIGNED_INT16 = 12, 233 AMDGPU_HSA_IMAGE_CHANNEL_TYPE_UNSIGNED_INT32 = 13, 234 AMDGPU_HSA_IMAGE_CHANNEL_TYPE_HALF_FLOAT = 14, 235 AMDGPU_HSA_IMAGE_CHANNEL_TYPE_FLOAT = 15 236 } amdgpu_hsa_image_channel_type_t; 237 238 // AMD GPU Image Descriptor. 239 typedef struct amdgpu_hsa_image_descriptor_s { 240 uint16_t size; 241 amdgpu_hsa_metadata_kind16_t kind; 242 amdgpu_hsa_image_geometry8_t geometry; 243 amdgpu_hsa_image_channel_order8_t channel_order; 244 amdgpu_hsa_image_channel_type8_t channel_type; 245 uint8_t reserved1; 246 uint64_t width; 247 uint64_t height; 248 uint64_t depth; 249 uint64_t array; 250 } amdgpu_hsa_image_descriptor_t; 251 252 typedef struct amdgpu_hsa_note_code_object_version_s { 253 uint32_t major_version; 254 uint32_t minor_version; 255 } amdgpu_hsa_note_code_object_version_t; 256 257 typedef struct amdgpu_hsa_note_hsail_s { 258 uint32_t hsail_major_version; 259 uint32_t hsail_minor_version; 260 uint8_t profile; 261 uint8_t machine_model; 262 uint8_t default_float_round; 263 } amdgpu_hsa_note_hsail_t; 264 265 typedef struct amdgpu_hsa_note_isa_s { 266 uint16_t vendor_name_size; 267 uint16_t architecture_name_size; 268 uint32_t major; 269 uint32_t minor; 270 uint32_t stepping; 271 char vendor_and_architecture_name[1]; 272 } amdgpu_hsa_note_isa_t; 273 274 typedef struct amdgpu_hsa_note_producer_s { 275 uint16_t producer_name_size; 276 uint16_t reserved; 277 uint32_t producer_major_version; 278 uint32_t producer_minor_version; 279 char producer_name[1]; 280 } amdgpu_hsa_note_producer_t; 281 282 typedef struct amdgpu_hsa_note_producer_options_s { 283 uint16_t producer_options_size; 284 char producer_options[1]; 285 } amdgpu_hsa_note_producer_options_t; 286 287 typedef enum { 288 AMDGPU_HSA_RODATA_GLOBAL_PROGRAM = 0, 289 AMDGPU_HSA_RODATA_GLOBAL_AGENT, 290 AMDGPU_HSA_RODATA_READONLY_AGENT, 291 AMDGPU_HSA_DATA_GLOBAL_PROGRAM, 292 AMDGPU_HSA_DATA_GLOBAL_AGENT, 293 AMDGPU_HSA_DATA_READONLY_AGENT, 294 AMDGPU_HSA_BSS_GLOBAL_PROGRAM, 295 AMDGPU_HSA_BSS_GLOBAL_AGENT, 296 AMDGPU_HSA_BSS_READONLY_AGENT, 297 AMDGPU_HSA_SECTION_LAST, 298 } amdgpu_hsa_elf_section_t; 299 300 #endif // AMD_HSA_ELF_H 301