1 /* $NetBSD: radeon_r100.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $ */
2
3 /*
4 * Copyright 2008 Advanced Micro Devices, Inc.
5 * Copyright 2008 Red Hat Inc.
6 * Copyright 2009 Jerome Glisse.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
24 * OTHER DEALINGS IN THE SOFTWARE.
25 *
26 * Authors: Dave Airlie
27 * Alex Deucher
28 * Jerome Glisse
29 */
30
31 #include <sys/cdefs.h>
32 __KERNEL_RCSID(0, "$NetBSD: radeon_r100.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $");
33
34 #include <linux/firmware.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/seq_file.h>
38 #include <linux/slab.h>
39
40 #include <drm/drm_debugfs.h>
41 #include <drm/drm_device.h>
42 #include <drm/drm_file.h>
43 #include <drm/drm_fourcc.h>
44 #include <drm/drm_vblank.h>
45 #include <drm/radeon_drm.h>
46
47 #include "atom.h"
48 #include "r100_reg_safe.h"
49 #include "r100d.h"
50 #include "radeon.h"
51 #include "radeon_asic.h"
52 #include "radeon_reg.h"
53 #include "rn50_reg_safe.h"
54 #include "rs100d.h"
55 #include "rv200d.h"
56 #include "rv250d.h"
57
58 /* Firmware Names */
59 #define FIRMWARE_R100 "radeon/R100_cp.bin"
60 #define FIRMWARE_R200 "radeon/R200_cp.bin"
61 #define FIRMWARE_R300 "radeon/R300_cp.bin"
62 #define FIRMWARE_R420 "radeon/R420_cp.bin"
63 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
64 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
65 #define FIRMWARE_R520 "radeon/R520_cp.bin"
66
67 MODULE_FIRMWARE(FIRMWARE_R100);
68 MODULE_FIRMWARE(FIRMWARE_R200);
69 MODULE_FIRMWARE(FIRMWARE_R300);
70 MODULE_FIRMWARE(FIRMWARE_R420);
71 MODULE_FIRMWARE(FIRMWARE_RS690);
72 MODULE_FIRMWARE(FIRMWARE_RS600);
73 MODULE_FIRMWARE(FIRMWARE_R520);
74
75 #include "r100_track.h"
76
77 /* This files gather functions specifics to:
78 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
79 * and others in some cases.
80 */
81
r100_is_in_vblank(struct radeon_device * rdev,int crtc)82 static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
83 {
84 if (crtc == 0) {
85 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
86 return true;
87 else
88 return false;
89 } else {
90 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
91 return true;
92 else
93 return false;
94 }
95 }
96
r100_is_counter_moving(struct radeon_device * rdev,int crtc)97 static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
98 {
99 u32 vline1, vline2;
100
101 if (crtc == 0) {
102 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
103 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
104 } else {
105 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
106 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
107 }
108 if (vline1 != vline2)
109 return true;
110 else
111 return false;
112 }
113
114 /**
115 * r100_wait_for_vblank - vblank wait asic callback.
116 *
117 * @rdev: radeon_device pointer
118 * @crtc: crtc to wait for vblank on
119 *
120 * Wait for vblank on the requested crtc (r1xx-r4xx).
121 */
r100_wait_for_vblank(struct radeon_device * rdev,int crtc)122 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
123 {
124 unsigned i = 0;
125
126 if (crtc >= rdev->num_crtc)
127 return;
128
129 if (crtc == 0) {
130 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
131 return;
132 } else {
133 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
134 return;
135 }
136
137 /* depending on when we hit vblank, we may be close to active; if so,
138 * wait for another frame.
139 */
140 while (r100_is_in_vblank(rdev, crtc)) {
141 if (i++ % 100 == 0) {
142 if (!r100_is_counter_moving(rdev, crtc))
143 break;
144 }
145 }
146
147 while (!r100_is_in_vblank(rdev, crtc)) {
148 if (i++ % 100 == 0) {
149 if (!r100_is_counter_moving(rdev, crtc))
150 break;
151 }
152 }
153 }
154
155 /**
156 * r100_page_flip - pageflip callback.
157 *
158 * @rdev: radeon_device pointer
159 * @crtc_id: crtc to cleanup pageflip on
160 * @crtc_base: new address of the crtc (GPU MC address)
161 *
162 * Does the actual pageflip (r1xx-r4xx).
163 * During vblank we take the crtc lock and wait for the update_pending
164 * bit to go high, when it does, we release the lock, and allow the
165 * double buffered update to take place.
166 */
r100_page_flip(struct radeon_device * rdev,int crtc_id,u64 crtc_base,bool async)167 void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)
168 {
169 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
170 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
171 int i;
172
173 /* Lock the graphics update lock */
174 /* update the scanout addresses */
175 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
176
177 /* Wait for update_pending to go high. */
178 for (i = 0; i < rdev->usec_timeout; i++) {
179 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
180 break;
181 udelay(1);
182 }
183 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
184
185 /* Unlock the lock, so double-buffering can take place inside vblank */
186 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
187 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
188
189 }
190
191 /**
192 * r100_page_flip_pending - check if page flip is still pending
193 *
194 * @rdev: radeon_device pointer
195 * @crtc_id: crtc to check
196 *
197 * Check if the last pagefilp is still pending (r1xx-r4xx).
198 * Returns the current update pending status.
199 */
r100_page_flip_pending(struct radeon_device * rdev,int crtc_id)200 bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id)
201 {
202 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
203
204 /* Return current update_pending status: */
205 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) &
206 RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET);
207 }
208
209 /**
210 * r100_pm_get_dynpm_state - look up dynpm power state callback.
211 *
212 * @rdev: radeon_device pointer
213 *
214 * Look up the optimal power state based on the
215 * current state of the GPU (r1xx-r5xx).
216 * Used for dynpm only.
217 */
r100_pm_get_dynpm_state(struct radeon_device * rdev)218 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
219 {
220 int i;
221 rdev->pm.dynpm_can_upclock = true;
222 rdev->pm.dynpm_can_downclock = true;
223
224 switch (rdev->pm.dynpm_planned_action) {
225 case DYNPM_ACTION_MINIMUM:
226 rdev->pm.requested_power_state_index = 0;
227 rdev->pm.dynpm_can_downclock = false;
228 break;
229 case DYNPM_ACTION_DOWNCLOCK:
230 if (rdev->pm.current_power_state_index == 0) {
231 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
232 rdev->pm.dynpm_can_downclock = false;
233 } else {
234 if (rdev->pm.active_crtc_count > 1) {
235 for (i = 0; i < rdev->pm.num_power_states; i++) {
236 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
237 continue;
238 else if (i >= rdev->pm.current_power_state_index) {
239 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
240 break;
241 } else {
242 rdev->pm.requested_power_state_index = i;
243 break;
244 }
245 }
246 } else
247 rdev->pm.requested_power_state_index =
248 rdev->pm.current_power_state_index - 1;
249 }
250 /* don't use the power state if crtcs are active and no display flag is set */
251 if ((rdev->pm.active_crtc_count > 0) &&
252 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
253 RADEON_PM_MODE_NO_DISPLAY)) {
254 rdev->pm.requested_power_state_index++;
255 }
256 break;
257 case DYNPM_ACTION_UPCLOCK:
258 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
259 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
260 rdev->pm.dynpm_can_upclock = false;
261 } else {
262 if (rdev->pm.active_crtc_count > 1) {
263 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
264 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
265 continue;
266 else if (i <= rdev->pm.current_power_state_index) {
267 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
268 break;
269 } else {
270 rdev->pm.requested_power_state_index = i;
271 break;
272 }
273 }
274 } else
275 rdev->pm.requested_power_state_index =
276 rdev->pm.current_power_state_index + 1;
277 }
278 break;
279 case DYNPM_ACTION_DEFAULT:
280 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
281 rdev->pm.dynpm_can_upclock = false;
282 break;
283 case DYNPM_ACTION_NONE:
284 default:
285 DRM_ERROR("Requested mode for not defined action\n");
286 return;
287 }
288 /* only one clock mode per power state */
289 rdev->pm.requested_clock_mode_index = 0;
290
291 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
292 rdev->pm.power_state[rdev->pm.requested_power_state_index].
293 clock_info[rdev->pm.requested_clock_mode_index].sclk,
294 rdev->pm.power_state[rdev->pm.requested_power_state_index].
295 clock_info[rdev->pm.requested_clock_mode_index].mclk,
296 rdev->pm.power_state[rdev->pm.requested_power_state_index].
297 pcie_lanes);
298 }
299
300 /**
301 * r100_pm_init_profile - Initialize power profiles callback.
302 *
303 * @rdev: radeon_device pointer
304 *
305 * Initialize the power states used in profile mode
306 * (r1xx-r3xx).
307 * Used for profile mode only.
308 */
r100_pm_init_profile(struct radeon_device * rdev)309 void r100_pm_init_profile(struct radeon_device *rdev)
310 {
311 /* default */
312 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
313 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
314 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
315 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
316 /* low sh */
317 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
320 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
321 /* mid sh */
322 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
325 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
326 /* high sh */
327 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
328 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
329 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
330 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
331 /* low mh */
332 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
333 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
334 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
335 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
336 /* mid mh */
337 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
338 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
339 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
340 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
341 /* high mh */
342 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
343 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
344 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
345 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
346 }
347
348 /**
349 * r100_pm_misc - set additional pm hw parameters callback.
350 *
351 * @rdev: radeon_device pointer
352 *
353 * Set non-clock parameters associated with a power state
354 * (voltage, pcie lanes, etc.) (r1xx-r4xx).
355 */
r100_pm_misc(struct radeon_device * rdev)356 void r100_pm_misc(struct radeon_device *rdev)
357 {
358 int requested_index = rdev->pm.requested_power_state_index;
359 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
360 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
361 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
362
363 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
364 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
365 tmp = RREG32(voltage->gpio.reg);
366 if (voltage->active_high)
367 tmp |= voltage->gpio.mask;
368 else
369 tmp &= ~(voltage->gpio.mask);
370 WREG32(voltage->gpio.reg, tmp);
371 if (voltage->delay)
372 udelay(voltage->delay);
373 } else {
374 tmp = RREG32(voltage->gpio.reg);
375 if (voltage->active_high)
376 tmp &= ~voltage->gpio.mask;
377 else
378 tmp |= voltage->gpio.mask;
379 WREG32(voltage->gpio.reg, tmp);
380 if (voltage->delay)
381 udelay(voltage->delay);
382 }
383 }
384
385 sclk_cntl = RREG32_PLL(SCLK_CNTL);
386 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
387 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
388 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
389 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
390 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
391 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
392 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
393 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
394 else
395 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
396 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
397 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
398 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
399 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
400 } else
401 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
402
403 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
404 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
405 if (voltage->delay) {
406 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
407 switch (voltage->delay) {
408 case 33:
409 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
410 break;
411 case 66:
412 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
413 break;
414 case 99:
415 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
416 break;
417 case 132:
418 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
419 break;
420 }
421 } else
422 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
423 } else
424 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
425
426 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
427 sclk_cntl &= ~FORCE_HDP;
428 else
429 sclk_cntl |= FORCE_HDP;
430
431 WREG32_PLL(SCLK_CNTL, sclk_cntl);
432 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
433 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
434
435 /* set pcie lanes */
436 if ((rdev->flags & RADEON_IS_PCIE) &&
437 !(rdev->flags & RADEON_IS_IGP) &&
438 rdev->asic->pm.set_pcie_lanes &&
439 (ps->pcie_lanes !=
440 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
441 radeon_set_pcie_lanes(rdev,
442 ps->pcie_lanes);
443 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
444 }
445 }
446
447 /**
448 * r100_pm_prepare - pre-power state change callback.
449 *
450 * @rdev: radeon_device pointer
451 *
452 * Prepare for a power state change (r1xx-r4xx).
453 */
r100_pm_prepare(struct radeon_device * rdev)454 void r100_pm_prepare(struct radeon_device *rdev)
455 {
456 struct drm_device *ddev = rdev->ddev;
457 struct drm_crtc *crtc;
458 struct radeon_crtc *radeon_crtc;
459 u32 tmp;
460
461 /* disable any active CRTCs */
462 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
463 radeon_crtc = to_radeon_crtc(crtc);
464 if (radeon_crtc->enabled) {
465 if (radeon_crtc->crtc_id) {
466 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
467 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
468 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
469 } else {
470 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
471 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
472 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
473 }
474 }
475 }
476 }
477
478 /**
479 * r100_pm_finish - post-power state change callback.
480 *
481 * @rdev: radeon_device pointer
482 *
483 * Clean up after a power state change (r1xx-r4xx).
484 */
r100_pm_finish(struct radeon_device * rdev)485 void r100_pm_finish(struct radeon_device *rdev)
486 {
487 struct drm_device *ddev = rdev->ddev;
488 struct drm_crtc *crtc;
489 struct radeon_crtc *radeon_crtc;
490 u32 tmp;
491
492 /* enable any active CRTCs */
493 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
494 radeon_crtc = to_radeon_crtc(crtc);
495 if (radeon_crtc->enabled) {
496 if (radeon_crtc->crtc_id) {
497 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
498 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
499 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
500 } else {
501 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
502 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
503 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
504 }
505 }
506 }
507 }
508
509 /**
510 * r100_gui_idle - gui idle callback.
511 *
512 * @rdev: radeon_device pointer
513 *
514 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
515 * Returns true if idle, false if not.
516 */
r100_gui_idle(struct radeon_device * rdev)517 bool r100_gui_idle(struct radeon_device *rdev)
518 {
519 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
520 return false;
521 else
522 return true;
523 }
524
525 /* hpd for digital panel detect/disconnect */
526 /**
527 * r100_hpd_sense - hpd sense callback.
528 *
529 * @rdev: radeon_device pointer
530 * @hpd: hpd (hotplug detect) pin
531 *
532 * Checks if a digital monitor is connected (r1xx-r4xx).
533 * Returns true if connected, false if not connected.
534 */
r100_hpd_sense(struct radeon_device * rdev,enum radeon_hpd_id hpd)535 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
536 {
537 bool connected = false;
538
539 switch (hpd) {
540 case RADEON_HPD_1:
541 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
542 connected = true;
543 break;
544 case RADEON_HPD_2:
545 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
546 connected = true;
547 break;
548 default:
549 break;
550 }
551 return connected;
552 }
553
554 /**
555 * r100_hpd_set_polarity - hpd set polarity callback.
556 *
557 * @rdev: radeon_device pointer
558 * @hpd: hpd (hotplug detect) pin
559 *
560 * Set the polarity of the hpd pin (r1xx-r4xx).
561 */
r100_hpd_set_polarity(struct radeon_device * rdev,enum radeon_hpd_id hpd)562 void r100_hpd_set_polarity(struct radeon_device *rdev,
563 enum radeon_hpd_id hpd)
564 {
565 u32 tmp;
566 bool connected = r100_hpd_sense(rdev, hpd);
567
568 switch (hpd) {
569 case RADEON_HPD_1:
570 tmp = RREG32(RADEON_FP_GEN_CNTL);
571 if (connected)
572 tmp &= ~RADEON_FP_DETECT_INT_POL;
573 else
574 tmp |= RADEON_FP_DETECT_INT_POL;
575 WREG32(RADEON_FP_GEN_CNTL, tmp);
576 break;
577 case RADEON_HPD_2:
578 tmp = RREG32(RADEON_FP2_GEN_CNTL);
579 if (connected)
580 tmp &= ~RADEON_FP2_DETECT_INT_POL;
581 else
582 tmp |= RADEON_FP2_DETECT_INT_POL;
583 WREG32(RADEON_FP2_GEN_CNTL, tmp);
584 break;
585 default:
586 break;
587 }
588 }
589
590 /**
591 * r100_hpd_init - hpd setup callback.
592 *
593 * @rdev: radeon_device pointer
594 *
595 * Setup the hpd pins used by the card (r1xx-r4xx).
596 * Set the polarity, and enable the hpd interrupts.
597 */
r100_hpd_init(struct radeon_device * rdev)598 void r100_hpd_init(struct radeon_device *rdev)
599 {
600 struct drm_device *dev = rdev->ddev;
601 struct drm_connector *connector;
602 unsigned enable = 0;
603
604 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
605 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
606 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
607 enable |= 1 << radeon_connector->hpd.hpd;
608 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
609 }
610 radeon_irq_kms_enable_hpd(rdev, enable);
611 }
612
613 /**
614 * r100_hpd_fini - hpd tear down callback.
615 *
616 * @rdev: radeon_device pointer
617 *
618 * Tear down the hpd pins used by the card (r1xx-r4xx).
619 * Disable the hpd interrupts.
620 */
r100_hpd_fini(struct radeon_device * rdev)621 void r100_hpd_fini(struct radeon_device *rdev)
622 {
623 struct drm_device *dev = rdev->ddev;
624 struct drm_connector *connector;
625 unsigned disable = 0;
626
627 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
628 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
629 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
630 disable |= 1 << radeon_connector->hpd.hpd;
631 }
632 radeon_irq_kms_disable_hpd(rdev, disable);
633 }
634
635 /*
636 * PCI GART
637 */
r100_pci_gart_tlb_flush(struct radeon_device * rdev)638 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
639 {
640 /* TODO: can we do somethings here ? */
641 /* It seems hw only cache one entry so we should discard this
642 * entry otherwise if first GPU GART read hit this entry it
643 * could end up in wrong address. */
644 }
645
r100_pci_gart_init(struct radeon_device * rdev)646 int r100_pci_gart_init(struct radeon_device *rdev)
647 {
648 int r;
649
650 if (rdev->gart.ptr) {
651 WARN(1, "R100 PCI GART already initialized\n");
652 return 0;
653 }
654 /* Initialize common gart structure */
655 r = radeon_gart_init(rdev);
656 if (r)
657 return r;
658 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
659 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
660 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
661 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
662 return radeon_gart_table_ram_alloc(rdev);
663 }
664
r100_pci_gart_enable(struct radeon_device * rdev)665 int r100_pci_gart_enable(struct radeon_device *rdev)
666 {
667 uint32_t tmp;
668
669 /* discard memory request outside of configured range */
670 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
671 WREG32(RADEON_AIC_CNTL, tmp);
672 /* set address range for PCI address translate */
673 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
674 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
675 /* set PCI GART page-table base address */
676 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
677 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
678 WREG32(RADEON_AIC_CNTL, tmp);
679 r100_pci_gart_tlb_flush(rdev);
680 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
681 (unsigned)(rdev->mc.gtt_size >> 20),
682 (unsigned long long)rdev->gart.table_addr);
683 rdev->gart.ready = true;
684 return 0;
685 }
686
r100_pci_gart_disable(struct radeon_device * rdev)687 void r100_pci_gart_disable(struct radeon_device *rdev)
688 {
689 uint32_t tmp;
690
691 /* discard memory request outside of configured range */
692 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
693 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
694 WREG32(RADEON_AIC_LO_ADDR, 0);
695 WREG32(RADEON_AIC_HI_ADDR, 0);
696 }
697
r100_pci_gart_get_page_entry(uint64_t addr,uint32_t flags)698 uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags)
699 {
700 return addr;
701 }
702
r100_pci_gart_set_page(struct radeon_device * rdev,unsigned i,uint64_t entry)703 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
704 uint64_t entry)
705 {
706 u32 *gtt = rdev->gart.ptr;
707 gtt[i] = cpu_to_le32(lower_32_bits(entry));
708 }
709
r100_pci_gart_fini(struct radeon_device * rdev)710 void r100_pci_gart_fini(struct radeon_device *rdev)
711 {
712 radeon_gart_fini(rdev);
713 r100_pci_gart_disable(rdev);
714 radeon_gart_table_ram_free(rdev);
715 }
716
r100_irq_set(struct radeon_device * rdev)717 int r100_irq_set(struct radeon_device *rdev)
718 {
719 uint32_t tmp = 0;
720
721 if (!rdev->irq.installed) {
722 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
723 WREG32(R_000040_GEN_INT_CNTL, 0);
724 return -EINVAL;
725 }
726 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
727 tmp |= RADEON_SW_INT_ENABLE;
728 }
729 if (rdev->irq.crtc_vblank_int[0] ||
730 atomic_read(&rdev->irq.pflip[0])) {
731 tmp |= RADEON_CRTC_VBLANK_MASK;
732 }
733 if (rdev->irq.crtc_vblank_int[1] ||
734 atomic_read(&rdev->irq.pflip[1])) {
735 tmp |= RADEON_CRTC2_VBLANK_MASK;
736 }
737 if (rdev->irq.hpd[0]) {
738 tmp |= RADEON_FP_DETECT_MASK;
739 }
740 if (rdev->irq.hpd[1]) {
741 tmp |= RADEON_FP2_DETECT_MASK;
742 }
743 WREG32(RADEON_GEN_INT_CNTL, tmp);
744
745 /* read back to post the write */
746 RREG32(RADEON_GEN_INT_CNTL);
747
748 return 0;
749 }
750
r100_irq_disable(struct radeon_device * rdev)751 void r100_irq_disable(struct radeon_device *rdev)
752 {
753 u32 tmp;
754
755 WREG32(R_000040_GEN_INT_CNTL, 0);
756 /* Wait and acknowledge irq */
757 mdelay(1);
758 tmp = RREG32(R_000044_GEN_INT_STATUS);
759 WREG32(R_000044_GEN_INT_STATUS, tmp);
760 }
761
r100_irq_ack(struct radeon_device * rdev)762 static uint32_t r100_irq_ack(struct radeon_device *rdev)
763 {
764 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
765 uint32_t irq_mask = RADEON_SW_INT_TEST |
766 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
767 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
768
769 if (irqs) {
770 WREG32(RADEON_GEN_INT_STATUS, irqs);
771 }
772 return irqs & irq_mask;
773 }
774
r100_irq_process(struct radeon_device * rdev)775 int r100_irq_process(struct radeon_device *rdev)
776 {
777 uint32_t status, msi_rearm;
778 bool queue_hotplug = false;
779
780 status = r100_irq_ack(rdev);
781 if (!status) {
782 return IRQ_NONE;
783 }
784 if (rdev->shutdown) {
785 return IRQ_NONE;
786 }
787 while (status) {
788 /* SW interrupt */
789 if (status & RADEON_SW_INT_TEST) {
790 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
791 }
792 /* Vertical blank interrupts */
793 if (status & RADEON_CRTC_VBLANK_STAT) {
794 if (rdev->irq.crtc_vblank_int[0]) {
795 drm_handle_vblank(rdev->ddev, 0);
796 #ifdef __NetBSD__
797 spin_lock(&rdev->irq.vblank_lock);
798 rdev->pm.vblank_sync = true;
799 DRM_SPIN_WAKEUP_ONE(&rdev->irq.vblank_queue, &rdev->irq.vblank_lock);
800 spin_unlock(&rdev->irq.vblank_lock);
801 #else
802 rdev->pm.vblank_sync = true;
803 wake_up(&rdev->irq.vblank_queue);
804 #endif
805 }
806 if (atomic_read(&rdev->irq.pflip[0]))
807 radeon_crtc_handle_vblank(rdev, 0);
808 }
809 if (status & RADEON_CRTC2_VBLANK_STAT) {
810 if (rdev->irq.crtc_vblank_int[1]) {
811 drm_handle_vblank(rdev->ddev, 1);
812 #ifdef __NetBSD__
813 spin_lock(&rdev->irq.vblank_lock);
814 rdev->pm.vblank_sync = true;
815 DRM_SPIN_WAKEUP_ONE(&rdev->irq.vblank_queue, &rdev->irq.vblank_lock);
816 spin_unlock(&rdev->irq.vblank_lock);
817 #else
818 rdev->pm.vblank_sync = true;
819 wake_up(&rdev->irq.vblank_queue);
820 #endif
821 }
822 if (atomic_read(&rdev->irq.pflip[1]))
823 radeon_crtc_handle_vblank(rdev, 1);
824 }
825 if (status & RADEON_FP_DETECT_STAT) {
826 queue_hotplug = true;
827 DRM_DEBUG("HPD1\n");
828 }
829 if (status & RADEON_FP2_DETECT_STAT) {
830 queue_hotplug = true;
831 DRM_DEBUG("HPD2\n");
832 }
833 status = r100_irq_ack(rdev);
834 }
835 if (queue_hotplug)
836 schedule_delayed_work(&rdev->hotplug_work, 0);
837 if (rdev->msi_enabled) {
838 switch (rdev->family) {
839 case CHIP_RS400:
840 case CHIP_RS480:
841 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
842 WREG32(RADEON_AIC_CNTL, msi_rearm);
843 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
844 break;
845 default:
846 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
847 break;
848 }
849 }
850 return IRQ_HANDLED;
851 }
852
r100_get_vblank_counter(struct radeon_device * rdev,int crtc)853 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
854 {
855 if (crtc == 0)
856 return RREG32(RADEON_CRTC_CRNT_FRAME);
857 else
858 return RREG32(RADEON_CRTC2_CRNT_FRAME);
859 }
860
861 /**
862 * r100_ring_hdp_flush - flush Host Data Path via the ring buffer
863 * rdev: radeon device structure
864 * ring: ring buffer struct for emitting packets
865 */
r100_ring_hdp_flush(struct radeon_device * rdev,struct radeon_ring * ring)866 static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
867 {
868 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
869 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
870 RADEON_HDP_READ_BUFFER_INVALIDATE);
871 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
872 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
873 }
874
875 /* Who ever call radeon_fence_emit should call ring_lock and ask
876 * for enough space (today caller are ib schedule and buffer move) */
r100_fence_ring_emit(struct radeon_device * rdev,struct radeon_fence * fence)877 void r100_fence_ring_emit(struct radeon_device *rdev,
878 struct radeon_fence *fence)
879 {
880 struct radeon_ring *ring = &rdev->ring[fence->ring];
881
882 /* We have to make sure that caches are flushed before
883 * CPU might read something from VRAM. */
884 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
885 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
886 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
887 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
888 /* Wait until IDLE & CLEAN */
889 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
890 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
891 r100_ring_hdp_flush(rdev, ring);
892 /* Emit fence sequence & fire IRQ */
893 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
894 radeon_ring_write(ring, fence->seq);
895 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
896 radeon_ring_write(ring, RADEON_SW_INT_FIRE);
897 }
898
r100_semaphore_ring_emit(struct radeon_device * rdev,struct radeon_ring * ring,struct radeon_semaphore * semaphore,bool emit_wait)899 bool r100_semaphore_ring_emit(struct radeon_device *rdev,
900 struct radeon_ring *ring,
901 struct radeon_semaphore *semaphore,
902 bool emit_wait)
903 {
904 /* Unused on older asics, since we don't have semaphores or multiple rings */
905 BUG();
906 return false;
907 }
908
r100_copy_blit(struct radeon_device * rdev,uint64_t src_offset,uint64_t dst_offset,unsigned num_gpu_pages,struct dma_resv * resv)909 struct radeon_fence *r100_copy_blit(struct radeon_device *rdev,
910 uint64_t src_offset,
911 uint64_t dst_offset,
912 unsigned num_gpu_pages,
913 struct dma_resv *resv)
914 {
915 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
916 struct radeon_fence *fence;
917 uint32_t cur_pages;
918 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
919 uint32_t pitch;
920 uint32_t stride_pixels;
921 unsigned ndw;
922 int num_loops;
923 int r = 0;
924
925 /* radeon limited to 16k stride */
926 stride_bytes &= 0x3fff;
927 /* radeon pitch is /64 */
928 pitch = stride_bytes / 64;
929 stride_pixels = stride_bytes / 4;
930 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
931
932 /* Ask for enough room for blit + flush + fence */
933 ndw = 64 + (10 * num_loops);
934 r = radeon_ring_lock(rdev, ring, ndw);
935 if (r) {
936 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
937 return ERR_PTR(-EINVAL);
938 }
939 while (num_gpu_pages > 0) {
940 cur_pages = num_gpu_pages;
941 if (cur_pages > 8191) {
942 cur_pages = 8191;
943 }
944 num_gpu_pages -= cur_pages;
945
946 /* pages are in Y direction - height
947 page width in X direction - width */
948 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
949 radeon_ring_write(ring,
950 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
951 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
952 RADEON_GMC_SRC_CLIPPING |
953 RADEON_GMC_DST_CLIPPING |
954 RADEON_GMC_BRUSH_NONE |
955 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
956 RADEON_GMC_SRC_DATATYPE_COLOR |
957 RADEON_ROP3_S |
958 RADEON_DP_SRC_SOURCE_MEMORY |
959 RADEON_GMC_CLR_CMP_CNTL_DIS |
960 RADEON_GMC_WR_MSK_DIS);
961 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
962 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
963 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
964 radeon_ring_write(ring, 0);
965 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
966 radeon_ring_write(ring, num_gpu_pages);
967 radeon_ring_write(ring, num_gpu_pages);
968 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
969 }
970 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
971 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
972 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
973 radeon_ring_write(ring,
974 RADEON_WAIT_2D_IDLECLEAN |
975 RADEON_WAIT_HOST_IDLECLEAN |
976 RADEON_WAIT_DMA_GUI_IDLE);
977 r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
978 if (r) {
979 radeon_ring_unlock_undo(rdev, ring);
980 return ERR_PTR(r);
981 }
982 radeon_ring_unlock_commit(rdev, ring, false);
983 return fence;
984 }
985
r100_cp_wait_for_idle(struct radeon_device * rdev)986 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
987 {
988 unsigned i;
989 u32 tmp;
990
991 for (i = 0; i < rdev->usec_timeout; i++) {
992 tmp = RREG32(R_000E40_RBBM_STATUS);
993 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
994 return 0;
995 }
996 udelay(1);
997 }
998 return -1;
999 }
1000
r100_ring_start(struct radeon_device * rdev,struct radeon_ring * ring)1001 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
1002 {
1003 int r;
1004
1005 r = radeon_ring_lock(rdev, ring, 2);
1006 if (r) {
1007 return;
1008 }
1009 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
1010 radeon_ring_write(ring,
1011 RADEON_ISYNC_ANY2D_IDLE3D |
1012 RADEON_ISYNC_ANY3D_IDLE2D |
1013 RADEON_ISYNC_WAIT_IDLEGUI |
1014 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
1015 radeon_ring_unlock_commit(rdev, ring, false);
1016 }
1017
1018
1019 /* Load the microcode for the CP */
r100_cp_init_microcode(struct radeon_device * rdev)1020 static int r100_cp_init_microcode(struct radeon_device *rdev)
1021 {
1022 const char *fw_name = NULL;
1023 int err;
1024
1025 DRM_DEBUG_KMS("\n");
1026
1027 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
1028 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
1029 (rdev->family == CHIP_RS200)) {
1030 DRM_INFO("Loading R100 Microcode\n");
1031 fw_name = FIRMWARE_R100;
1032 } else if ((rdev->family == CHIP_R200) ||
1033 (rdev->family == CHIP_RV250) ||
1034 (rdev->family == CHIP_RV280) ||
1035 (rdev->family == CHIP_RS300)) {
1036 DRM_INFO("Loading R200 Microcode\n");
1037 fw_name = FIRMWARE_R200;
1038 } else if ((rdev->family == CHIP_R300) ||
1039 (rdev->family == CHIP_R350) ||
1040 (rdev->family == CHIP_RV350) ||
1041 (rdev->family == CHIP_RV380) ||
1042 (rdev->family == CHIP_RS400) ||
1043 (rdev->family == CHIP_RS480)) {
1044 DRM_INFO("Loading R300 Microcode\n");
1045 fw_name = FIRMWARE_R300;
1046 } else if ((rdev->family == CHIP_R420) ||
1047 (rdev->family == CHIP_R423) ||
1048 (rdev->family == CHIP_RV410)) {
1049 DRM_INFO("Loading R400 Microcode\n");
1050 fw_name = FIRMWARE_R420;
1051 } else if ((rdev->family == CHIP_RS690) ||
1052 (rdev->family == CHIP_RS740)) {
1053 DRM_INFO("Loading RS690/RS740 Microcode\n");
1054 fw_name = FIRMWARE_RS690;
1055 } else if (rdev->family == CHIP_RS600) {
1056 DRM_INFO("Loading RS600 Microcode\n");
1057 fw_name = FIRMWARE_RS600;
1058 } else if ((rdev->family == CHIP_RV515) ||
1059 (rdev->family == CHIP_R520) ||
1060 (rdev->family == CHIP_RV530) ||
1061 (rdev->family == CHIP_R580) ||
1062 (rdev->family == CHIP_RV560) ||
1063 (rdev->family == CHIP_RV570)) {
1064 DRM_INFO("Loading R500 Microcode\n");
1065 fw_name = FIRMWARE_R520;
1066 }
1067
1068 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1069 if (err) {
1070 pr_err("radeon_cp: Failed to load firmware \"%s\"\n", fw_name);
1071 } else if (rdev->me_fw->size % 8) {
1072 pr_err("radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1073 rdev->me_fw->size, fw_name);
1074 err = -EINVAL;
1075 release_firmware(rdev->me_fw);
1076 rdev->me_fw = NULL;
1077 }
1078 return err;
1079 }
1080
r100_gfx_get_rptr(struct radeon_device * rdev,struct radeon_ring * ring)1081 u32 r100_gfx_get_rptr(struct radeon_device *rdev,
1082 struct radeon_ring *ring)
1083 {
1084 u32 rptr;
1085
1086 if (rdev->wb.enabled)
1087 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
1088 else
1089 rptr = RREG32(RADEON_CP_RB_RPTR);
1090
1091 return rptr;
1092 }
1093
r100_gfx_get_wptr(struct radeon_device * rdev,struct radeon_ring * ring)1094 u32 r100_gfx_get_wptr(struct radeon_device *rdev,
1095 struct radeon_ring *ring)
1096 {
1097 return RREG32(RADEON_CP_RB_WPTR);
1098 }
1099
r100_gfx_set_wptr(struct radeon_device * rdev,struct radeon_ring * ring)1100 void r100_gfx_set_wptr(struct radeon_device *rdev,
1101 struct radeon_ring *ring)
1102 {
1103 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1104 (void)RREG32(RADEON_CP_RB_WPTR);
1105 }
1106
r100_cp_load_microcode(struct radeon_device * rdev)1107 static void r100_cp_load_microcode(struct radeon_device *rdev)
1108 {
1109 const __be32 *fw_data;
1110 int i, size;
1111
1112 if (r100_gui_wait_for_idle(rdev)) {
1113 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
1114 }
1115
1116 if (rdev->me_fw) {
1117 size = rdev->me_fw->size / 4;
1118 fw_data = (const __be32 *)rdev->me_fw->data;
1119 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1120 for (i = 0; i < size; i += 2) {
1121 WREG32(RADEON_CP_ME_RAM_DATAH,
1122 be32_to_cpup(&fw_data[i]));
1123 WREG32(RADEON_CP_ME_RAM_DATAL,
1124 be32_to_cpup(&fw_data[i + 1]));
1125 }
1126 }
1127 }
1128
r100_cp_init(struct radeon_device * rdev,unsigned ring_size)1129 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1130 {
1131 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1132 unsigned rb_bufsz;
1133 unsigned rb_blksz;
1134 unsigned max_fetch;
1135 unsigned pre_write_timer;
1136 unsigned pre_write_limit;
1137 unsigned indirect2_start;
1138 unsigned indirect1_start;
1139 uint32_t tmp;
1140 int r;
1141
1142 if (r100_debugfs_cp_init(rdev)) {
1143 DRM_ERROR("Failed to register debugfs file for CP !\n");
1144 }
1145 if (!rdev->me_fw) {
1146 r = r100_cp_init_microcode(rdev);
1147 if (r) {
1148 DRM_ERROR("Failed to load firmware!\n");
1149 return r;
1150 }
1151 }
1152
1153 /* Align ring size */
1154 rb_bufsz = order_base_2(ring_size / 8);
1155 ring_size = (1 << (rb_bufsz + 1)) * 4;
1156 r100_cp_load_microcode(rdev);
1157 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1158 RADEON_CP_PACKET2);
1159 if (r) {
1160 return r;
1161 }
1162 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1163 * the rptr copy in system ram */
1164 rb_blksz = 9;
1165 /* cp will read 128bytes at a time (4 dwords) */
1166 max_fetch = 1;
1167 ring->align_mask = 16 - 1;
1168 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1169 pre_write_timer = 64;
1170 /* Force CP_RB_WPTR write if written more than one time before the
1171 * delay expire
1172 */
1173 pre_write_limit = 0;
1174 /* Setup the cp cache like this (cache size is 96 dwords) :
1175 * RING 0 to 15
1176 * INDIRECT1 16 to 79
1177 * INDIRECT2 80 to 95
1178 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1179 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1180 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1181 * Idea being that most of the gpu cmd will be through indirect1 buffer
1182 * so it gets the bigger cache.
1183 */
1184 indirect2_start = 80;
1185 indirect1_start = 16;
1186 /* cp setup */
1187 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1188 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1189 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1190 REG_SET(RADEON_MAX_FETCH, max_fetch));
1191 #ifdef __BIG_ENDIAN
1192 tmp |= RADEON_BUF_SWAP_32BIT;
1193 #endif
1194 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1195
1196 /* Set ring address */
1197 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1198 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1199 /* Force read & write ptr to 0 */
1200 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1201 WREG32(RADEON_CP_RB_RPTR_WR, 0);
1202 ring->wptr = 0;
1203 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1204
1205 /* set the wb address whether it's enabled or not */
1206 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1207 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1208 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1209
1210 if (rdev->wb.enabled)
1211 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1212 else {
1213 tmp |= RADEON_RB_NO_UPDATE;
1214 WREG32(R_000770_SCRATCH_UMSK, 0);
1215 }
1216
1217 WREG32(RADEON_CP_RB_CNTL, tmp);
1218 udelay(10);
1219 /* Set cp mode to bus mastering & enable cp*/
1220 WREG32(RADEON_CP_CSQ_MODE,
1221 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1222 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1223 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1224 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1225 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1226
1227 /* at this point everything should be setup correctly to enable master */
1228 pci_set_master(rdev->pdev);
1229
1230 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1231 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1232 if (r) {
1233 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1234 return r;
1235 }
1236 ring->ready = true;
1237 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1238
1239 if (!ring->rptr_save_reg /* not resuming from suspend */
1240 && radeon_ring_supports_scratch_reg(rdev, ring)) {
1241 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1242 if (r) {
1243 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
1244 ring->rptr_save_reg = 0;
1245 }
1246 }
1247 return 0;
1248 }
1249
r100_cp_fini(struct radeon_device * rdev)1250 void r100_cp_fini(struct radeon_device *rdev)
1251 {
1252 if (r100_cp_wait_for_idle(rdev)) {
1253 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1254 }
1255 /* Disable ring */
1256 r100_cp_disable(rdev);
1257 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
1258 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1259 DRM_INFO("radeon: cp finalized\n");
1260 }
1261
r100_cp_disable(struct radeon_device * rdev)1262 void r100_cp_disable(struct radeon_device *rdev)
1263 {
1264 /* Disable ring */
1265 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1266 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1267 WREG32(RADEON_CP_CSQ_MODE, 0);
1268 WREG32(RADEON_CP_CSQ_CNTL, 0);
1269 WREG32(R_000770_SCRATCH_UMSK, 0);
1270 if (r100_gui_wait_for_idle(rdev)) {
1271 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
1272 }
1273 }
1274
1275 /*
1276 * CS functions
1277 */
r100_reloc_pitch_offset(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt,unsigned idx,unsigned reg)1278 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1279 struct radeon_cs_packet *pkt,
1280 unsigned idx,
1281 unsigned reg)
1282 {
1283 int r;
1284 u32 tile_flags = 0;
1285 u32 tmp;
1286 struct radeon_bo_list *reloc;
1287 u32 value;
1288
1289 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1290 if (r) {
1291 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1292 idx, reg);
1293 radeon_cs_dump_packet(p, pkt);
1294 return r;
1295 }
1296
1297 value = radeon_get_ib_value(p, idx);
1298 tmp = value & 0x003fffff;
1299 tmp += (((u32)reloc->gpu_offset) >> 10);
1300
1301 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1302 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1303 tile_flags |= RADEON_DST_TILE_MACRO;
1304 if (reloc->tiling_flags & RADEON_TILING_MICRO) {
1305 if (reg == RADEON_SRC_PITCH_OFFSET) {
1306 DRM_ERROR("Cannot src blit from microtiled surface\n");
1307 radeon_cs_dump_packet(p, pkt);
1308 return -EINVAL;
1309 }
1310 tile_flags |= RADEON_DST_TILE_MICRO;
1311 }
1312
1313 tmp |= tile_flags;
1314 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1315 } else
1316 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1317 return 0;
1318 }
1319
r100_packet3_load_vbpntr(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt,int idx)1320 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1321 struct radeon_cs_packet *pkt,
1322 int idx)
1323 {
1324 unsigned c, i;
1325 struct radeon_bo_list *reloc;
1326 struct r100_cs_track *track;
1327 int r = 0;
1328 volatile uint32_t *ib;
1329 u32 idx_value;
1330
1331 ib = p->ib.ptr;
1332 track = (struct r100_cs_track *)p->track;
1333 c = radeon_get_ib_value(p, idx++) & 0x1F;
1334 if (c > 16) {
1335 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1336 pkt->opcode);
1337 radeon_cs_dump_packet(p, pkt);
1338 return -EINVAL;
1339 }
1340 track->num_arrays = c;
1341 for (i = 0; i < (c - 1); i+=2, idx+=3) {
1342 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1343 if (r) {
1344 DRM_ERROR("No reloc for packet3 %d\n",
1345 pkt->opcode);
1346 radeon_cs_dump_packet(p, pkt);
1347 return r;
1348 }
1349 idx_value = radeon_get_ib_value(p, idx);
1350 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1351
1352 track->arrays[i + 0].esize = idx_value >> 8;
1353 track->arrays[i + 0].robj = reloc->robj;
1354 track->arrays[i + 0].esize &= 0x7F;
1355 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1356 if (r) {
1357 DRM_ERROR("No reloc for packet3 %d\n",
1358 pkt->opcode);
1359 radeon_cs_dump_packet(p, pkt);
1360 return r;
1361 }
1362 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);
1363 track->arrays[i + 1].robj = reloc->robj;
1364 track->arrays[i + 1].esize = idx_value >> 24;
1365 track->arrays[i + 1].esize &= 0x7F;
1366 }
1367 if (c & 1) {
1368 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1369 if (r) {
1370 DRM_ERROR("No reloc for packet3 %d\n",
1371 pkt->opcode);
1372 radeon_cs_dump_packet(p, pkt);
1373 return r;
1374 }
1375 idx_value = radeon_get_ib_value(p, idx);
1376 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1377 track->arrays[i + 0].robj = reloc->robj;
1378 track->arrays[i + 0].esize = idx_value >> 8;
1379 track->arrays[i + 0].esize &= 0x7F;
1380 }
1381 return r;
1382 }
1383
r100_cs_parse_packet0(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt,const unsigned * auth,unsigned n,radeon_packet0_check_t check)1384 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1385 struct radeon_cs_packet *pkt,
1386 const unsigned *auth, unsigned n,
1387 radeon_packet0_check_t check)
1388 {
1389 unsigned reg;
1390 unsigned i, j, m;
1391 unsigned idx;
1392 int r;
1393
1394 idx = pkt->idx + 1;
1395 reg = pkt->reg;
1396 /* Check that register fall into register range
1397 * determined by the number of entry (n) in the
1398 * safe register bitmap.
1399 */
1400 if (pkt->one_reg_wr) {
1401 if ((reg >> 7) > n) {
1402 return -EINVAL;
1403 }
1404 } else {
1405 if (((reg + (pkt->count << 2)) >> 7) > n) {
1406 return -EINVAL;
1407 }
1408 }
1409 for (i = 0; i <= pkt->count; i++, idx++) {
1410 j = (reg >> 7);
1411 m = 1 << ((reg >> 2) & 31);
1412 if (auth[j] & m) {
1413 r = check(p, pkt, idx, reg);
1414 if (r) {
1415 return r;
1416 }
1417 }
1418 if (pkt->one_reg_wr) {
1419 if (!(auth[j] & m)) {
1420 break;
1421 }
1422 } else {
1423 reg += 4;
1424 }
1425 }
1426 return 0;
1427 }
1428
1429 /**
1430 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1431 * @parser: parser structure holding parsing context.
1432 *
1433 * Userspace sends a special sequence for VLINE waits.
1434 * PACKET0 - VLINE_START_END + value
1435 * PACKET0 - WAIT_UNTIL +_value
1436 * RELOC (P3) - crtc_id in reloc.
1437 *
1438 * This function parses this and relocates the VLINE START END
1439 * and WAIT UNTIL packets to the correct crtc.
1440 * It also detects a switched off crtc and nulls out the
1441 * wait in that case.
1442 */
r100_cs_packet_parse_vline(struct radeon_cs_parser * p)1443 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1444 {
1445 struct drm_crtc *crtc;
1446 struct radeon_crtc *radeon_crtc;
1447 struct radeon_cs_packet p3reloc, waitreloc;
1448 int crtc_id;
1449 int r;
1450 uint32_t header, h_idx, reg;
1451 volatile uint32_t *ib;
1452
1453 ib = p->ib.ptr;
1454
1455 /* parse the wait until */
1456 r = radeon_cs_packet_parse(p, &waitreloc, p->idx);
1457 if (r)
1458 return r;
1459
1460 /* check its a wait until and only 1 count */
1461 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1462 waitreloc.count != 0) {
1463 DRM_ERROR("vline wait had illegal wait until segment\n");
1464 return -EINVAL;
1465 }
1466
1467 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1468 DRM_ERROR("vline wait had illegal wait until\n");
1469 return -EINVAL;
1470 }
1471
1472 /* jump over the NOP */
1473 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1474 if (r)
1475 return r;
1476
1477 h_idx = p->idx - 2;
1478 p->idx += waitreloc.count + 2;
1479 p->idx += p3reloc.count + 2;
1480
1481 header = radeon_get_ib_value(p, h_idx);
1482 crtc_id = radeon_get_ib_value(p, h_idx + 5);
1483 reg = R100_CP_PACKET0_GET_REG(header);
1484 crtc = drm_crtc_find(p->rdev->ddev, p->filp, crtc_id);
1485 if (!crtc) {
1486 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1487 return -ENOENT;
1488 }
1489 radeon_crtc = to_radeon_crtc(crtc);
1490 crtc_id = radeon_crtc->crtc_id;
1491
1492 if (!crtc->enabled) {
1493 /* if the CRTC isn't enabled - we need to nop out the wait until */
1494 ib[h_idx + 2] = PACKET2(0);
1495 ib[h_idx + 3] = PACKET2(0);
1496 } else if (crtc_id == 1) {
1497 switch (reg) {
1498 case AVIVO_D1MODE_VLINE_START_END:
1499 header &= ~R300_CP_PACKET0_REG_MASK;
1500 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1501 break;
1502 case RADEON_CRTC_GUI_TRIG_VLINE:
1503 header &= ~R300_CP_PACKET0_REG_MASK;
1504 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1505 break;
1506 default:
1507 DRM_ERROR("unknown crtc reloc\n");
1508 return -EINVAL;
1509 }
1510 ib[h_idx] = header;
1511 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1512 }
1513
1514 return 0;
1515 }
1516
r100_get_vtx_size(uint32_t vtx_fmt)1517 static int r100_get_vtx_size(uint32_t vtx_fmt)
1518 {
1519 int vtx_size;
1520 vtx_size = 2;
1521 /* ordered according to bits in spec */
1522 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1523 vtx_size++;
1524 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1525 vtx_size += 3;
1526 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1527 vtx_size++;
1528 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1529 vtx_size++;
1530 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1531 vtx_size += 3;
1532 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1533 vtx_size++;
1534 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1535 vtx_size++;
1536 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1537 vtx_size += 2;
1538 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1539 vtx_size += 2;
1540 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1541 vtx_size++;
1542 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1543 vtx_size += 2;
1544 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1545 vtx_size++;
1546 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1547 vtx_size += 2;
1548 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1549 vtx_size++;
1550 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1551 vtx_size++;
1552 /* blend weight */
1553 if (vtx_fmt & (0x7 << 15))
1554 vtx_size += (vtx_fmt >> 15) & 0x7;
1555 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1556 vtx_size += 3;
1557 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1558 vtx_size += 2;
1559 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1560 vtx_size++;
1561 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1562 vtx_size++;
1563 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1564 vtx_size++;
1565 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1566 vtx_size++;
1567 return vtx_size;
1568 }
1569
r100_packet0_check(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt,unsigned idx,unsigned reg)1570 static int r100_packet0_check(struct radeon_cs_parser *p,
1571 struct radeon_cs_packet *pkt,
1572 unsigned idx, unsigned reg)
1573 {
1574 struct radeon_bo_list *reloc;
1575 struct r100_cs_track *track;
1576 volatile uint32_t *ib;
1577 uint32_t tmp;
1578 int r;
1579 int i, face;
1580 u32 tile_flags = 0;
1581 u32 idx_value;
1582
1583 ib = p->ib.ptr;
1584 track = (struct r100_cs_track *)p->track;
1585
1586 idx_value = radeon_get_ib_value(p, idx);
1587
1588 switch (reg) {
1589 case RADEON_CRTC_GUI_TRIG_VLINE:
1590 r = r100_cs_packet_parse_vline(p);
1591 if (r) {
1592 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1593 idx, reg);
1594 radeon_cs_dump_packet(p, pkt);
1595 return r;
1596 }
1597 break;
1598 /* FIXME: only allow PACKET3 blit? easier to check for out of
1599 * range access */
1600 case RADEON_DST_PITCH_OFFSET:
1601 case RADEON_SRC_PITCH_OFFSET:
1602 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1603 if (r)
1604 return r;
1605 break;
1606 case RADEON_RB3D_DEPTHOFFSET:
1607 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1608 if (r) {
1609 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1610 idx, reg);
1611 radeon_cs_dump_packet(p, pkt);
1612 return r;
1613 }
1614 track->zb.robj = reloc->robj;
1615 track->zb.offset = idx_value;
1616 track->zb_dirty = true;
1617 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1618 break;
1619 case RADEON_RB3D_COLOROFFSET:
1620 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1621 if (r) {
1622 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1623 idx, reg);
1624 radeon_cs_dump_packet(p, pkt);
1625 return r;
1626 }
1627 track->cb[0].robj = reloc->robj;
1628 track->cb[0].offset = idx_value;
1629 track->cb_dirty = true;
1630 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1631 break;
1632 case RADEON_PP_TXOFFSET_0:
1633 case RADEON_PP_TXOFFSET_1:
1634 case RADEON_PP_TXOFFSET_2:
1635 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1636 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1637 if (r) {
1638 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1639 idx, reg);
1640 radeon_cs_dump_packet(p, pkt);
1641 return r;
1642 }
1643 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1644 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1645 tile_flags |= RADEON_TXO_MACRO_TILE;
1646 if (reloc->tiling_flags & RADEON_TILING_MICRO)
1647 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1648
1649 tmp = idx_value & ~(0x7 << 2);
1650 tmp |= tile_flags;
1651 ib[idx] = tmp + ((u32)reloc->gpu_offset);
1652 } else
1653 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1654 track->textures[i].robj = reloc->robj;
1655 track->tex_dirty = true;
1656 break;
1657 case RADEON_PP_CUBIC_OFFSET_T0_0:
1658 case RADEON_PP_CUBIC_OFFSET_T0_1:
1659 case RADEON_PP_CUBIC_OFFSET_T0_2:
1660 case RADEON_PP_CUBIC_OFFSET_T0_3:
1661 case RADEON_PP_CUBIC_OFFSET_T0_4:
1662 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1663 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1664 if (r) {
1665 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1666 idx, reg);
1667 radeon_cs_dump_packet(p, pkt);
1668 return r;
1669 }
1670 track->textures[0].cube_info[i].offset = idx_value;
1671 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1672 track->textures[0].cube_info[i].robj = reloc->robj;
1673 track->tex_dirty = true;
1674 break;
1675 case RADEON_PP_CUBIC_OFFSET_T1_0:
1676 case RADEON_PP_CUBIC_OFFSET_T1_1:
1677 case RADEON_PP_CUBIC_OFFSET_T1_2:
1678 case RADEON_PP_CUBIC_OFFSET_T1_3:
1679 case RADEON_PP_CUBIC_OFFSET_T1_4:
1680 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1681 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1682 if (r) {
1683 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1684 idx, reg);
1685 radeon_cs_dump_packet(p, pkt);
1686 return r;
1687 }
1688 track->textures[1].cube_info[i].offset = idx_value;
1689 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1690 track->textures[1].cube_info[i].robj = reloc->robj;
1691 track->tex_dirty = true;
1692 break;
1693 case RADEON_PP_CUBIC_OFFSET_T2_0:
1694 case RADEON_PP_CUBIC_OFFSET_T2_1:
1695 case RADEON_PP_CUBIC_OFFSET_T2_2:
1696 case RADEON_PP_CUBIC_OFFSET_T2_3:
1697 case RADEON_PP_CUBIC_OFFSET_T2_4:
1698 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1699 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1700 if (r) {
1701 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1702 idx, reg);
1703 radeon_cs_dump_packet(p, pkt);
1704 return r;
1705 }
1706 track->textures[2].cube_info[i].offset = idx_value;
1707 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1708 track->textures[2].cube_info[i].robj = reloc->robj;
1709 track->tex_dirty = true;
1710 break;
1711 case RADEON_RE_WIDTH_HEIGHT:
1712 track->maxy = ((idx_value >> 16) & 0x7FF);
1713 track->cb_dirty = true;
1714 track->zb_dirty = true;
1715 break;
1716 case RADEON_RB3D_COLORPITCH:
1717 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1718 if (r) {
1719 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1720 idx, reg);
1721 radeon_cs_dump_packet(p, pkt);
1722 return r;
1723 }
1724 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1725 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1726 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1727 if (reloc->tiling_flags & RADEON_TILING_MICRO)
1728 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1729
1730 tmp = idx_value & ~(0x7 << 16);
1731 tmp |= tile_flags;
1732 ib[idx] = tmp;
1733 } else
1734 ib[idx] = idx_value;
1735
1736 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1737 track->cb_dirty = true;
1738 break;
1739 case RADEON_RB3D_DEPTHPITCH:
1740 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1741 track->zb_dirty = true;
1742 break;
1743 case RADEON_RB3D_CNTL:
1744 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1745 case 7:
1746 case 8:
1747 case 9:
1748 case 11:
1749 case 12:
1750 track->cb[0].cpp = 1;
1751 break;
1752 case 3:
1753 case 4:
1754 case 15:
1755 track->cb[0].cpp = 2;
1756 break;
1757 case 6:
1758 track->cb[0].cpp = 4;
1759 break;
1760 default:
1761 DRM_ERROR("Invalid color buffer format (%d) !\n",
1762 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1763 return -EINVAL;
1764 }
1765 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1766 track->cb_dirty = true;
1767 track->zb_dirty = true;
1768 break;
1769 case RADEON_RB3D_ZSTENCILCNTL:
1770 switch (idx_value & 0xf) {
1771 case 0:
1772 track->zb.cpp = 2;
1773 break;
1774 case 2:
1775 case 3:
1776 case 4:
1777 case 5:
1778 case 9:
1779 case 11:
1780 track->zb.cpp = 4;
1781 break;
1782 default:
1783 break;
1784 }
1785 track->zb_dirty = true;
1786 break;
1787 case RADEON_RB3D_ZPASS_ADDR:
1788 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1789 if (r) {
1790 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1791 idx, reg);
1792 radeon_cs_dump_packet(p, pkt);
1793 return r;
1794 }
1795 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1796 break;
1797 case RADEON_PP_CNTL:
1798 {
1799 uint32_t temp = idx_value >> 4;
1800 for (i = 0; i < track->num_texture; i++)
1801 track->textures[i].enabled = !!(temp & (1 << i));
1802 track->tex_dirty = true;
1803 }
1804 break;
1805 case RADEON_SE_VF_CNTL:
1806 track->vap_vf_cntl = idx_value;
1807 break;
1808 case RADEON_SE_VTX_FMT:
1809 track->vtx_size = r100_get_vtx_size(idx_value);
1810 break;
1811 case RADEON_PP_TEX_SIZE_0:
1812 case RADEON_PP_TEX_SIZE_1:
1813 case RADEON_PP_TEX_SIZE_2:
1814 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1815 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1816 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1817 track->tex_dirty = true;
1818 break;
1819 case RADEON_PP_TEX_PITCH_0:
1820 case RADEON_PP_TEX_PITCH_1:
1821 case RADEON_PP_TEX_PITCH_2:
1822 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1823 track->textures[i].pitch = idx_value + 32;
1824 track->tex_dirty = true;
1825 break;
1826 case RADEON_PP_TXFILTER_0:
1827 case RADEON_PP_TXFILTER_1:
1828 case RADEON_PP_TXFILTER_2:
1829 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1830 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1831 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1832 tmp = (idx_value >> 23) & 0x7;
1833 if (tmp == 2 || tmp == 6)
1834 track->textures[i].roundup_w = false;
1835 tmp = (idx_value >> 27) & 0x7;
1836 if (tmp == 2 || tmp == 6)
1837 track->textures[i].roundup_h = false;
1838 track->tex_dirty = true;
1839 break;
1840 case RADEON_PP_TXFORMAT_0:
1841 case RADEON_PP_TXFORMAT_1:
1842 case RADEON_PP_TXFORMAT_2:
1843 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1844 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1845 track->textures[i].use_pitch = true;
1846 } else {
1847 track->textures[i].use_pitch = false;
1848 track->textures[i].width = 1 << ((idx_value & RADEON_TXFORMAT_WIDTH_MASK) >> RADEON_TXFORMAT_WIDTH_SHIFT);
1849 track->textures[i].height = 1 << ((idx_value & RADEON_TXFORMAT_HEIGHT_MASK) >> RADEON_TXFORMAT_HEIGHT_SHIFT);
1850 }
1851 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1852 track->textures[i].tex_coord_type = 2;
1853 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1854 case RADEON_TXFORMAT_I8:
1855 case RADEON_TXFORMAT_RGB332:
1856 case RADEON_TXFORMAT_Y8:
1857 track->textures[i].cpp = 1;
1858 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1859 break;
1860 case RADEON_TXFORMAT_AI88:
1861 case RADEON_TXFORMAT_ARGB1555:
1862 case RADEON_TXFORMAT_RGB565:
1863 case RADEON_TXFORMAT_ARGB4444:
1864 case RADEON_TXFORMAT_VYUY422:
1865 case RADEON_TXFORMAT_YVYU422:
1866 case RADEON_TXFORMAT_SHADOW16:
1867 case RADEON_TXFORMAT_LDUDV655:
1868 case RADEON_TXFORMAT_DUDV88:
1869 track->textures[i].cpp = 2;
1870 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1871 break;
1872 case RADEON_TXFORMAT_ARGB8888:
1873 case RADEON_TXFORMAT_RGBA8888:
1874 case RADEON_TXFORMAT_SHADOW32:
1875 case RADEON_TXFORMAT_LDUDUV8888:
1876 track->textures[i].cpp = 4;
1877 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1878 break;
1879 case RADEON_TXFORMAT_DXT1:
1880 track->textures[i].cpp = 1;
1881 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1882 break;
1883 case RADEON_TXFORMAT_DXT23:
1884 case RADEON_TXFORMAT_DXT45:
1885 track->textures[i].cpp = 1;
1886 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1887 break;
1888 }
1889 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1890 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1891 track->tex_dirty = true;
1892 break;
1893 case RADEON_PP_CUBIC_FACES_0:
1894 case RADEON_PP_CUBIC_FACES_1:
1895 case RADEON_PP_CUBIC_FACES_2:
1896 tmp = idx_value;
1897 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1898 for (face = 0; face < 4; face++) {
1899 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1900 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1901 }
1902 track->tex_dirty = true;
1903 break;
1904 default:
1905 pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx);
1906 return -EINVAL;
1907 }
1908 return 0;
1909 }
1910
r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt,struct radeon_bo * robj)1911 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1912 struct radeon_cs_packet *pkt,
1913 struct radeon_bo *robj)
1914 {
1915 unsigned idx;
1916 u32 value;
1917 idx = pkt->idx + 1;
1918 value = radeon_get_ib_value(p, idx + 2);
1919 if ((value + 1) > radeon_bo_size(robj)) {
1920 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1921 "(need %u have %lu) !\n",
1922 value + 1,
1923 radeon_bo_size(robj));
1924 return -EINVAL;
1925 }
1926 return 0;
1927 }
1928
r100_packet3_check(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt)1929 static int r100_packet3_check(struct radeon_cs_parser *p,
1930 struct radeon_cs_packet *pkt)
1931 {
1932 struct radeon_bo_list *reloc;
1933 struct r100_cs_track *track;
1934 unsigned idx;
1935 volatile uint32_t *ib;
1936 int r;
1937
1938 ib = p->ib.ptr;
1939 idx = pkt->idx + 1;
1940 track = (struct r100_cs_track *)p->track;
1941 switch (pkt->opcode) {
1942 case PACKET3_3D_LOAD_VBPNTR:
1943 r = r100_packet3_load_vbpntr(p, pkt, idx);
1944 if (r)
1945 return r;
1946 break;
1947 case PACKET3_INDX_BUFFER:
1948 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1949 if (r) {
1950 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1951 radeon_cs_dump_packet(p, pkt);
1952 return r;
1953 }
1954 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);
1955 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1956 if (r) {
1957 return r;
1958 }
1959 break;
1960 case 0x23:
1961 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1962 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1963 if (r) {
1964 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1965 radeon_cs_dump_packet(p, pkt);
1966 return r;
1967 }
1968 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);
1969 track->num_arrays = 1;
1970 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1971
1972 track->arrays[0].robj = reloc->robj;
1973 track->arrays[0].esize = track->vtx_size;
1974
1975 track->max_indx = radeon_get_ib_value(p, idx+1);
1976
1977 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1978 track->immd_dwords = pkt->count - 1;
1979 r = r100_cs_track_check(p->rdev, track);
1980 if (r)
1981 return r;
1982 break;
1983 case PACKET3_3D_DRAW_IMMD:
1984 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1985 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1986 return -EINVAL;
1987 }
1988 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1989 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1990 track->immd_dwords = pkt->count - 1;
1991 r = r100_cs_track_check(p->rdev, track);
1992 if (r)
1993 return r;
1994 break;
1995 /* triggers drawing using in-packet vertex data */
1996 case PACKET3_3D_DRAW_IMMD_2:
1997 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1998 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1999 return -EINVAL;
2000 }
2001 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
2002 track->immd_dwords = pkt->count;
2003 r = r100_cs_track_check(p->rdev, track);
2004 if (r)
2005 return r;
2006 break;
2007 /* triggers drawing using in-packet vertex data */
2008 case PACKET3_3D_DRAW_VBUF_2:
2009 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
2010 r = r100_cs_track_check(p->rdev, track);
2011 if (r)
2012 return r;
2013 break;
2014 /* triggers drawing of vertex buffers setup elsewhere */
2015 case PACKET3_3D_DRAW_INDX_2:
2016 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
2017 r = r100_cs_track_check(p->rdev, track);
2018 if (r)
2019 return r;
2020 break;
2021 /* triggers drawing using indices to vertex buffer */
2022 case PACKET3_3D_DRAW_VBUF:
2023 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2024 r = r100_cs_track_check(p->rdev, track);
2025 if (r)
2026 return r;
2027 break;
2028 /* triggers drawing of vertex buffers setup elsewhere */
2029 case PACKET3_3D_DRAW_INDX:
2030 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2031 r = r100_cs_track_check(p->rdev, track);
2032 if (r)
2033 return r;
2034 break;
2035 /* triggers drawing using indices to vertex buffer */
2036 case PACKET3_3D_CLEAR_HIZ:
2037 case PACKET3_3D_CLEAR_ZMASK:
2038 if (p->rdev->hyperz_filp != p->filp)
2039 return -EINVAL;
2040 break;
2041 case PACKET3_NOP:
2042 break;
2043 default:
2044 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2045 return -EINVAL;
2046 }
2047 return 0;
2048 }
2049
r100_cs_parse(struct radeon_cs_parser * p)2050 int r100_cs_parse(struct radeon_cs_parser *p)
2051 {
2052 struct radeon_cs_packet pkt;
2053 struct r100_cs_track *track;
2054 int r;
2055
2056 track = kzalloc(sizeof(*track), GFP_KERNEL);
2057 if (!track)
2058 return -ENOMEM;
2059 r100_cs_track_clear(p->rdev, track);
2060 p->track = track;
2061 do {
2062 r = radeon_cs_packet_parse(p, &pkt, p->idx);
2063 if (r) {
2064 return r;
2065 }
2066 p->idx += pkt.count + 2;
2067 switch (pkt.type) {
2068 case RADEON_PACKET_TYPE0:
2069 if (p->rdev->family >= CHIP_R200)
2070 r = r100_cs_parse_packet0(p, &pkt,
2071 p->rdev->config.r100.reg_safe_bm,
2072 p->rdev->config.r100.reg_safe_bm_size,
2073 &r200_packet0_check);
2074 else
2075 r = r100_cs_parse_packet0(p, &pkt,
2076 p->rdev->config.r100.reg_safe_bm,
2077 p->rdev->config.r100.reg_safe_bm_size,
2078 &r100_packet0_check);
2079 break;
2080 case RADEON_PACKET_TYPE2:
2081 break;
2082 case RADEON_PACKET_TYPE3:
2083 r = r100_packet3_check(p, &pkt);
2084 break;
2085 default:
2086 DRM_ERROR("Unknown packet type %d !\n",
2087 pkt.type);
2088 return -EINVAL;
2089 }
2090 if (r)
2091 return r;
2092 } while (p->idx < p->chunk_ib->length_dw);
2093 return 0;
2094 }
2095
r100_cs_track_texture_print(struct r100_cs_track_texture * t)2096 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2097 {
2098 DRM_ERROR("pitch %d\n", t->pitch);
2099 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2100 DRM_ERROR("width %d\n", t->width);
2101 DRM_ERROR("width_11 %d\n", t->width_11);
2102 DRM_ERROR("height %d\n", t->height);
2103 DRM_ERROR("height_11 %d\n", t->height_11);
2104 DRM_ERROR("num levels %d\n", t->num_levels);
2105 DRM_ERROR("depth %d\n", t->txdepth);
2106 DRM_ERROR("bpp %d\n", t->cpp);
2107 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2108 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2109 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2110 DRM_ERROR("compress format %d\n", t->compress_format);
2111 }
2112
r100_track_compress_size(int compress_format,int w,int h)2113 static int r100_track_compress_size(int compress_format, int w, int h)
2114 {
2115 int block_width, block_height, block_bytes;
2116 int wblocks, hblocks;
2117 int min_wblocks;
2118 int sz;
2119
2120 block_width = 4;
2121 block_height = 4;
2122
2123 switch (compress_format) {
2124 case R100_TRACK_COMP_DXT1:
2125 block_bytes = 8;
2126 min_wblocks = 4;
2127 break;
2128 default:
2129 case R100_TRACK_COMP_DXT35:
2130 block_bytes = 16;
2131 min_wblocks = 2;
2132 break;
2133 }
2134
2135 hblocks = (h + block_height - 1) / block_height;
2136 wblocks = (w + block_width - 1) / block_width;
2137 if (wblocks < min_wblocks)
2138 wblocks = min_wblocks;
2139 sz = wblocks * hblocks * block_bytes;
2140 return sz;
2141 }
2142
r100_cs_track_cube(struct radeon_device * rdev,struct r100_cs_track * track,unsigned idx)2143 static int r100_cs_track_cube(struct radeon_device *rdev,
2144 struct r100_cs_track *track, unsigned idx)
2145 {
2146 unsigned face, w, h;
2147 struct radeon_bo *cube_robj;
2148 unsigned long size;
2149 unsigned compress_format = track->textures[idx].compress_format;
2150
2151 for (face = 0; face < 5; face++) {
2152 cube_robj = track->textures[idx].cube_info[face].robj;
2153 w = track->textures[idx].cube_info[face].width;
2154 h = track->textures[idx].cube_info[face].height;
2155
2156 if (compress_format) {
2157 size = r100_track_compress_size(compress_format, w, h);
2158 } else
2159 size = w * h;
2160 size *= track->textures[idx].cpp;
2161
2162 size += track->textures[idx].cube_info[face].offset;
2163
2164 if (size > radeon_bo_size(cube_robj)) {
2165 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2166 size, radeon_bo_size(cube_robj));
2167 r100_cs_track_texture_print(&track->textures[idx]);
2168 return -1;
2169 }
2170 }
2171 return 0;
2172 }
2173
r100_cs_track_texture_check(struct radeon_device * rdev,struct r100_cs_track * track)2174 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2175 struct r100_cs_track *track)
2176 {
2177 struct radeon_bo *robj;
2178 unsigned long size;
2179 unsigned u, i, w, h, d;
2180 int ret;
2181
2182 for (u = 0; u < track->num_texture; u++) {
2183 if (!track->textures[u].enabled)
2184 continue;
2185 if (track->textures[u].lookup_disable)
2186 continue;
2187 robj = track->textures[u].robj;
2188 if (robj == NULL) {
2189 DRM_ERROR("No texture bound to unit %u\n", u);
2190 return -EINVAL;
2191 }
2192 size = 0;
2193 for (i = 0; i <= track->textures[u].num_levels; i++) {
2194 if (track->textures[u].use_pitch) {
2195 if (rdev->family < CHIP_R300)
2196 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2197 else
2198 w = track->textures[u].pitch / (1 << i);
2199 } else {
2200 w = track->textures[u].width;
2201 if (rdev->family >= CHIP_RV515)
2202 w |= track->textures[u].width_11;
2203 w = w / (1 << i);
2204 if (track->textures[u].roundup_w)
2205 w = roundup_pow_of_two(w);
2206 }
2207 h = track->textures[u].height;
2208 if (rdev->family >= CHIP_RV515)
2209 h |= track->textures[u].height_11;
2210 h = h / (1 << i);
2211 if (track->textures[u].roundup_h)
2212 h = roundup_pow_of_two(h);
2213 if (track->textures[u].tex_coord_type == 1) {
2214 d = (1 << track->textures[u].txdepth) / (1 << i);
2215 if (!d)
2216 d = 1;
2217 } else {
2218 d = 1;
2219 }
2220 if (track->textures[u].compress_format) {
2221
2222 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2223 /* compressed textures are block based */
2224 } else
2225 size += w * h * d;
2226 }
2227 size *= track->textures[u].cpp;
2228
2229 switch (track->textures[u].tex_coord_type) {
2230 case 0:
2231 case 1:
2232 break;
2233 case 2:
2234 if (track->separate_cube) {
2235 ret = r100_cs_track_cube(rdev, track, u);
2236 if (ret)
2237 return ret;
2238 } else
2239 size *= 6;
2240 break;
2241 default:
2242 DRM_ERROR("Invalid texture coordinate type %u for unit "
2243 "%u\n", track->textures[u].tex_coord_type, u);
2244 return -EINVAL;
2245 }
2246 if (size > radeon_bo_size(robj)) {
2247 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2248 "%lu\n", u, size, radeon_bo_size(robj));
2249 r100_cs_track_texture_print(&track->textures[u]);
2250 return -EINVAL;
2251 }
2252 }
2253 return 0;
2254 }
2255
r100_cs_track_check(struct radeon_device * rdev,struct r100_cs_track * track)2256 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2257 {
2258 unsigned i;
2259 unsigned long size;
2260 unsigned prim_walk;
2261 unsigned nverts;
2262 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
2263
2264 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
2265 !track->blend_read_enable)
2266 num_cb = 0;
2267
2268 for (i = 0; i < num_cb; i++) {
2269 if (track->cb[i].robj == NULL) {
2270 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2271 return -EINVAL;
2272 }
2273 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2274 size += track->cb[i].offset;
2275 if (size > radeon_bo_size(track->cb[i].robj)) {
2276 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2277 "(need %lu have %lu) !\n", i, size,
2278 radeon_bo_size(track->cb[i].robj));
2279 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2280 i, track->cb[i].pitch, track->cb[i].cpp,
2281 track->cb[i].offset, track->maxy);
2282 return -EINVAL;
2283 }
2284 }
2285 track->cb_dirty = false;
2286
2287 if (track->zb_dirty && track->z_enabled) {
2288 if (track->zb.robj == NULL) {
2289 DRM_ERROR("[drm] No buffer for z buffer !\n");
2290 return -EINVAL;
2291 }
2292 size = track->zb.pitch * track->zb.cpp * track->maxy;
2293 size += track->zb.offset;
2294 if (size > radeon_bo_size(track->zb.robj)) {
2295 DRM_ERROR("[drm] Buffer too small for z buffer "
2296 "(need %lu have %lu) !\n", size,
2297 radeon_bo_size(track->zb.robj));
2298 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2299 track->zb.pitch, track->zb.cpp,
2300 track->zb.offset, track->maxy);
2301 return -EINVAL;
2302 }
2303 }
2304 track->zb_dirty = false;
2305
2306 if (track->aa_dirty && track->aaresolve) {
2307 if (track->aa.robj == NULL) {
2308 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
2309 return -EINVAL;
2310 }
2311 /* I believe the format comes from colorbuffer0. */
2312 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
2313 size += track->aa.offset;
2314 if (size > radeon_bo_size(track->aa.robj)) {
2315 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
2316 "(need %lu have %lu) !\n", i, size,
2317 radeon_bo_size(track->aa.robj));
2318 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
2319 i, track->aa.pitch, track->cb[0].cpp,
2320 track->aa.offset, track->maxy);
2321 return -EINVAL;
2322 }
2323 }
2324 track->aa_dirty = false;
2325
2326 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2327 if (track->vap_vf_cntl & (1 << 14)) {
2328 nverts = track->vap_alt_nverts;
2329 } else {
2330 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2331 }
2332 switch (prim_walk) {
2333 case 1:
2334 for (i = 0; i < track->num_arrays; i++) {
2335 size = track->arrays[i].esize * track->max_indx * 4;
2336 if (track->arrays[i].robj == NULL) {
2337 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2338 "bound\n", prim_walk, i);
2339 return -EINVAL;
2340 }
2341 if (size > radeon_bo_size(track->arrays[i].robj)) {
2342 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2343 "need %lu dwords have %lu dwords\n",
2344 prim_walk, i, size >> 2,
2345 radeon_bo_size(track->arrays[i].robj)
2346 >> 2);
2347 DRM_ERROR("Max indices %u\n", track->max_indx);
2348 return -EINVAL;
2349 }
2350 }
2351 break;
2352 case 2:
2353 for (i = 0; i < track->num_arrays; i++) {
2354 size = track->arrays[i].esize * (nverts - 1) * 4;
2355 if (track->arrays[i].robj == NULL) {
2356 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2357 "bound\n", prim_walk, i);
2358 return -EINVAL;
2359 }
2360 if (size > radeon_bo_size(track->arrays[i].robj)) {
2361 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2362 "need %lu dwords have %lu dwords\n",
2363 prim_walk, i, size >> 2,
2364 radeon_bo_size(track->arrays[i].robj)
2365 >> 2);
2366 return -EINVAL;
2367 }
2368 }
2369 break;
2370 case 3:
2371 size = track->vtx_size * nverts;
2372 if (size != track->immd_dwords) {
2373 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2374 track->immd_dwords, size);
2375 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2376 nverts, track->vtx_size);
2377 return -EINVAL;
2378 }
2379 break;
2380 default:
2381 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2382 prim_walk);
2383 return -EINVAL;
2384 }
2385
2386 if (track->tex_dirty) {
2387 track->tex_dirty = false;
2388 return r100_cs_track_texture_check(rdev, track);
2389 }
2390 return 0;
2391 }
2392
r100_cs_track_clear(struct radeon_device * rdev,struct r100_cs_track * track)2393 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2394 {
2395 unsigned i, face;
2396
2397 track->cb_dirty = true;
2398 track->zb_dirty = true;
2399 track->tex_dirty = true;
2400 track->aa_dirty = true;
2401
2402 if (rdev->family < CHIP_R300) {
2403 track->num_cb = 1;
2404 if (rdev->family <= CHIP_RS200)
2405 track->num_texture = 3;
2406 else
2407 track->num_texture = 6;
2408 track->maxy = 2048;
2409 track->separate_cube = true;
2410 } else {
2411 track->num_cb = 4;
2412 track->num_texture = 16;
2413 track->maxy = 4096;
2414 track->separate_cube = false;
2415 track->aaresolve = false;
2416 track->aa.robj = NULL;
2417 }
2418
2419 for (i = 0; i < track->num_cb; i++) {
2420 track->cb[i].robj = NULL;
2421 track->cb[i].pitch = 8192;
2422 track->cb[i].cpp = 16;
2423 track->cb[i].offset = 0;
2424 }
2425 track->z_enabled = true;
2426 track->zb.robj = NULL;
2427 track->zb.pitch = 8192;
2428 track->zb.cpp = 4;
2429 track->zb.offset = 0;
2430 track->vtx_size = 0x7F;
2431 track->immd_dwords = 0xFFFFFFFFUL;
2432 track->num_arrays = 11;
2433 track->max_indx = 0x00FFFFFFUL;
2434 for (i = 0; i < track->num_arrays; i++) {
2435 track->arrays[i].robj = NULL;
2436 track->arrays[i].esize = 0x7F;
2437 }
2438 for (i = 0; i < track->num_texture; i++) {
2439 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2440 track->textures[i].pitch = 16536;
2441 track->textures[i].width = 16536;
2442 track->textures[i].height = 16536;
2443 track->textures[i].width_11 = 1 << 11;
2444 track->textures[i].height_11 = 1 << 11;
2445 track->textures[i].num_levels = 12;
2446 if (rdev->family <= CHIP_RS200) {
2447 track->textures[i].tex_coord_type = 0;
2448 track->textures[i].txdepth = 0;
2449 } else {
2450 track->textures[i].txdepth = 16;
2451 track->textures[i].tex_coord_type = 1;
2452 }
2453 track->textures[i].cpp = 64;
2454 track->textures[i].robj = NULL;
2455 /* CS IB emission code makes sure texture unit are disabled */
2456 track->textures[i].enabled = false;
2457 track->textures[i].lookup_disable = false;
2458 track->textures[i].roundup_w = true;
2459 track->textures[i].roundup_h = true;
2460 if (track->separate_cube)
2461 for (face = 0; face < 5; face++) {
2462 track->textures[i].cube_info[face].robj = NULL;
2463 track->textures[i].cube_info[face].width = 16536;
2464 track->textures[i].cube_info[face].height = 16536;
2465 track->textures[i].cube_info[face].offset = 0;
2466 }
2467 }
2468 }
2469
2470 /*
2471 * Global GPU functions
2472 */
r100_errata(struct radeon_device * rdev)2473 static void r100_errata(struct radeon_device *rdev)
2474 {
2475 rdev->pll_errata = 0;
2476
2477 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2478 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2479 }
2480
2481 if (rdev->family == CHIP_RV100 ||
2482 rdev->family == CHIP_RS100 ||
2483 rdev->family == CHIP_RS200) {
2484 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2485 }
2486 }
2487
r100_rbbm_fifo_wait_for_entry(struct radeon_device * rdev,unsigned n)2488 static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2489 {
2490 unsigned i;
2491 uint32_t tmp;
2492
2493 for (i = 0; i < rdev->usec_timeout; i++) {
2494 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2495 if (tmp >= n) {
2496 return 0;
2497 }
2498 udelay(1);
2499 }
2500 return -1;
2501 }
2502
r100_gui_wait_for_idle(struct radeon_device * rdev)2503 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2504 {
2505 unsigned i;
2506 uint32_t tmp;
2507
2508 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2509 pr_warn("radeon: wait for empty RBBM fifo failed! Bad things might happen.\n");
2510 }
2511 for (i = 0; i < rdev->usec_timeout; i++) {
2512 tmp = RREG32(RADEON_RBBM_STATUS);
2513 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2514 return 0;
2515 }
2516 udelay(1);
2517 }
2518 return -1;
2519 }
2520
r100_mc_wait_for_idle(struct radeon_device * rdev)2521 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2522 {
2523 unsigned i;
2524 uint32_t tmp;
2525
2526 for (i = 0; i < rdev->usec_timeout; i++) {
2527 /* read MC_STATUS */
2528 tmp = RREG32(RADEON_MC_STATUS);
2529 if (tmp & RADEON_MC_IDLE) {
2530 return 0;
2531 }
2532 udelay(1);
2533 }
2534 return -1;
2535 }
2536
r100_gpu_is_lockup(struct radeon_device * rdev,struct radeon_ring * ring)2537 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2538 {
2539 u32 rbbm_status;
2540
2541 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2542 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2543 radeon_ring_lockup_update(rdev, ring);
2544 return false;
2545 }
2546 return radeon_ring_test_lockup(rdev, ring);
2547 }
2548
2549 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
r100_enable_bm(struct radeon_device * rdev)2550 void r100_enable_bm(struct radeon_device *rdev)
2551 {
2552 uint32_t tmp;
2553 /* Enable bus mastering */
2554 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2555 WREG32(RADEON_BUS_CNTL, tmp);
2556 }
2557
r100_bm_disable(struct radeon_device * rdev)2558 void r100_bm_disable(struct radeon_device *rdev)
2559 {
2560 u32 tmp;
2561
2562 /* disable bus mastering */
2563 tmp = RREG32(R_000030_BUS_CNTL);
2564 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2565 mdelay(1);
2566 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2567 mdelay(1);
2568 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2569 tmp = RREG32(RADEON_BUS_CNTL);
2570 mdelay(1);
2571 pci_clear_master(rdev->pdev);
2572 mdelay(1);
2573 }
2574
r100_asic_reset(struct radeon_device * rdev,bool hard)2575 int r100_asic_reset(struct radeon_device *rdev, bool hard)
2576 {
2577 struct r100_mc_save save;
2578 u32 status, tmp;
2579 int ret = 0;
2580
2581 status = RREG32(R_000E40_RBBM_STATUS);
2582 if (!G_000E40_GUI_ACTIVE(status)) {
2583 return 0;
2584 }
2585 r100_mc_stop(rdev, &save);
2586 status = RREG32(R_000E40_RBBM_STATUS);
2587 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2588 /* stop CP */
2589 WREG32(RADEON_CP_CSQ_CNTL, 0);
2590 tmp = RREG32(RADEON_CP_RB_CNTL);
2591 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2592 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2593 WREG32(RADEON_CP_RB_WPTR, 0);
2594 WREG32(RADEON_CP_RB_CNTL, tmp);
2595 /* save PCI state */
2596 pci_save_state(rdev->pdev);
2597 /* disable bus mastering */
2598 r100_bm_disable(rdev);
2599 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2600 S_0000F0_SOFT_RESET_RE(1) |
2601 S_0000F0_SOFT_RESET_PP(1) |
2602 S_0000F0_SOFT_RESET_RB(1));
2603 RREG32(R_0000F0_RBBM_SOFT_RESET);
2604 mdelay(500);
2605 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2606 mdelay(1);
2607 status = RREG32(R_000E40_RBBM_STATUS);
2608 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2609 /* reset CP */
2610 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2611 RREG32(R_0000F0_RBBM_SOFT_RESET);
2612 mdelay(500);
2613 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2614 mdelay(1);
2615 status = RREG32(R_000E40_RBBM_STATUS);
2616 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2617 /* restore PCI & busmastering */
2618 pci_restore_state(rdev->pdev);
2619 r100_enable_bm(rdev);
2620 /* Check if GPU is idle */
2621 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2622 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2623 dev_err(rdev->dev, "failed to reset GPU\n");
2624 ret = -1;
2625 } else
2626 dev_info(rdev->dev, "GPU reset succeed\n");
2627 r100_mc_resume(rdev, &save);
2628 return ret;
2629 }
2630
r100_set_common_regs(struct radeon_device * rdev)2631 void r100_set_common_regs(struct radeon_device *rdev)
2632 {
2633 struct drm_device *dev = rdev->ddev;
2634 bool force_dac2 = false;
2635 u32 tmp;
2636
2637 /* set these so they don't interfere with anything */
2638 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2639 WREG32(RADEON_SUBPIC_CNTL, 0);
2640 WREG32(RADEON_VIPH_CONTROL, 0);
2641 WREG32(RADEON_I2C_CNTL_1, 0);
2642 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2643 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2644 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2645
2646 /* always set up dac2 on rn50 and some rv100 as lots
2647 * of servers seem to wire it up to a VGA port but
2648 * don't report it in the bios connector
2649 * table.
2650 */
2651 switch (dev->pdev->device) {
2652 /* RN50 */
2653 case 0x515e:
2654 case 0x5969:
2655 force_dac2 = true;
2656 break;
2657 /* RV100*/
2658 case 0x5159:
2659 case 0x515a:
2660 /* DELL triple head servers */
2661 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2662 ((dev->pdev->subsystem_device == 0x016c) ||
2663 (dev->pdev->subsystem_device == 0x016d) ||
2664 (dev->pdev->subsystem_device == 0x016e) ||
2665 (dev->pdev->subsystem_device == 0x016f) ||
2666 (dev->pdev->subsystem_device == 0x0170) ||
2667 (dev->pdev->subsystem_device == 0x017d) ||
2668 (dev->pdev->subsystem_device == 0x017e) ||
2669 (dev->pdev->subsystem_device == 0x0183) ||
2670 (dev->pdev->subsystem_device == 0x018a) ||
2671 (dev->pdev->subsystem_device == 0x019a)))
2672 force_dac2 = true;
2673 break;
2674 }
2675
2676 if (force_dac2) {
2677 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2678 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2679 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2680
2681 /* For CRT on DAC2, don't turn it on if BIOS didn't
2682 enable it, even it's detected.
2683 */
2684
2685 /* force it to crtc0 */
2686 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2687 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2688 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2689
2690 /* set up the TV DAC */
2691 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2692 RADEON_TV_DAC_STD_MASK |
2693 RADEON_TV_DAC_RDACPD |
2694 RADEON_TV_DAC_GDACPD |
2695 RADEON_TV_DAC_BDACPD |
2696 RADEON_TV_DAC_BGADJ_MASK |
2697 RADEON_TV_DAC_DACADJ_MASK);
2698 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2699 RADEON_TV_DAC_NHOLD |
2700 RADEON_TV_DAC_STD_PS2 |
2701 (0x58 << 16));
2702
2703 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2704 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2705 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2706 }
2707
2708 /* switch PM block to ACPI mode */
2709 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2710 tmp &= ~RADEON_PM_MODE_SEL;
2711 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2712
2713 }
2714
2715 /*
2716 * VRAM info
2717 */
r100_vram_get_type(struct radeon_device * rdev)2718 static void r100_vram_get_type(struct radeon_device *rdev)
2719 {
2720 uint32_t tmp;
2721
2722 rdev->mc.vram_is_ddr = false;
2723 if (rdev->flags & RADEON_IS_IGP)
2724 rdev->mc.vram_is_ddr = true;
2725 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2726 rdev->mc.vram_is_ddr = true;
2727 if ((rdev->family == CHIP_RV100) ||
2728 (rdev->family == CHIP_RS100) ||
2729 (rdev->family == CHIP_RS200)) {
2730 tmp = RREG32(RADEON_MEM_CNTL);
2731 if (tmp & RV100_HALF_MODE) {
2732 rdev->mc.vram_width = 32;
2733 } else {
2734 rdev->mc.vram_width = 64;
2735 }
2736 if (rdev->flags & RADEON_SINGLE_CRTC) {
2737 rdev->mc.vram_width /= 4;
2738 rdev->mc.vram_is_ddr = true;
2739 }
2740 } else if (rdev->family <= CHIP_RV280) {
2741 tmp = RREG32(RADEON_MEM_CNTL);
2742 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2743 rdev->mc.vram_width = 128;
2744 } else {
2745 rdev->mc.vram_width = 64;
2746 }
2747 } else {
2748 /* newer IGPs */
2749 rdev->mc.vram_width = 128;
2750 }
2751 }
2752
r100_get_accessible_vram(struct radeon_device * rdev)2753 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2754 {
2755 u32 aper_size;
2756 u8 byte;
2757
2758 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2759
2760 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2761 * that is has the 2nd generation multifunction PCI interface
2762 */
2763 if (rdev->family == CHIP_RV280 ||
2764 rdev->family >= CHIP_RV350) {
2765 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2766 ~RADEON_HDP_APER_CNTL);
2767 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2768 return aper_size * 2;
2769 }
2770
2771 /* Older cards have all sorts of funny issues to deal with. First
2772 * check if it's a multifunction card by reading the PCI config
2773 * header type... Limit those to one aperture size
2774 */
2775 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2776 if (byte & 0x80) {
2777 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2778 DRM_INFO("Limiting VRAM to one aperture\n");
2779 return aper_size;
2780 }
2781
2782 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2783 * have set it up. We don't write this as it's broken on some ASICs but
2784 * we expect the BIOS to have done the right thing (might be too optimistic...)
2785 */
2786 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2787 return aper_size * 2;
2788 return aper_size;
2789 }
2790
r100_vram_init_sizes(struct radeon_device * rdev)2791 void r100_vram_init_sizes(struct radeon_device *rdev)
2792 {
2793 u64 config_aper_size;
2794
2795 /* work out accessible VRAM */
2796 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2797 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2798 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2799 /* FIXME we don't use the second aperture yet when we could use it */
2800 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2801 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2802 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2803 if (rdev->flags & RADEON_IS_IGP) {
2804 uint32_t tom;
2805 /* read NB_TOM to get the amount of ram stolen for the GPU */
2806 tom = RREG32(RADEON_NB_TOM);
2807 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2808 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2809 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2810 } else {
2811 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2812 /* Some production boards of m6 will report 0
2813 * if it's 8 MB
2814 */
2815 if (rdev->mc.real_vram_size == 0) {
2816 rdev->mc.real_vram_size = 8192 * 1024;
2817 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2818 }
2819 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2820 * Novell bug 204882 + along with lots of ubuntu ones
2821 */
2822 if (rdev->mc.aper_size > config_aper_size)
2823 config_aper_size = rdev->mc.aper_size;
2824
2825 if (config_aper_size > rdev->mc.real_vram_size)
2826 rdev->mc.mc_vram_size = config_aper_size;
2827 else
2828 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2829 }
2830 }
2831
r100_vga_set_state(struct radeon_device * rdev,bool state)2832 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2833 {
2834 uint32_t temp;
2835
2836 temp = RREG32(RADEON_CONFIG_CNTL);
2837 if (!state) {
2838 temp &= ~RADEON_CFG_VGA_RAM_EN;
2839 temp |= RADEON_CFG_VGA_IO_DIS;
2840 } else {
2841 temp &= ~RADEON_CFG_VGA_IO_DIS;
2842 }
2843 WREG32(RADEON_CONFIG_CNTL, temp);
2844 }
2845
r100_mc_init(struct radeon_device * rdev)2846 static void r100_mc_init(struct radeon_device *rdev)
2847 {
2848 u64 base;
2849
2850 r100_vram_get_type(rdev);
2851 r100_vram_init_sizes(rdev);
2852 base = rdev->mc.aper_base;
2853 if (rdev->flags & RADEON_IS_IGP)
2854 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2855 radeon_vram_location(rdev, &rdev->mc, base);
2856 rdev->mc.gtt_base_align = 0;
2857 if (!(rdev->flags & RADEON_IS_AGP))
2858 radeon_gtt_location(rdev, &rdev->mc);
2859 radeon_update_bandwidth_info(rdev);
2860 }
2861
2862
2863 /*
2864 * Indirect registers accessor
2865 */
r100_pll_errata_after_index(struct radeon_device * rdev)2866 void r100_pll_errata_after_index(struct radeon_device *rdev)
2867 {
2868 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2869 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2870 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2871 }
2872 }
2873
r100_pll_errata_after_data(struct radeon_device * rdev)2874 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2875 {
2876 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2877 * or the chip could hang on a subsequent access
2878 */
2879 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2880 mdelay(5);
2881 }
2882
2883 /* This function is required to workaround a hardware bug in some (all?)
2884 * revisions of the R300. This workaround should be called after every
2885 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2886 * may not be correct.
2887 */
2888 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2889 uint32_t save, tmp;
2890
2891 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2892 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2893 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2894 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2895 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2896 }
2897 }
2898
r100_pll_rreg(struct radeon_device * rdev,uint32_t reg)2899 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2900 {
2901 unsigned long flags;
2902 uint32_t data;
2903
2904 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2905 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2906 r100_pll_errata_after_index(rdev);
2907 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2908 r100_pll_errata_after_data(rdev);
2909 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2910 return data;
2911 }
2912
r100_pll_wreg(struct radeon_device * rdev,uint32_t reg,uint32_t v)2913 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2914 {
2915 unsigned long flags;
2916
2917 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2918 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2919 r100_pll_errata_after_index(rdev);
2920 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2921 r100_pll_errata_after_data(rdev);
2922 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2923 }
2924
r100_set_safe_registers(struct radeon_device * rdev)2925 static void r100_set_safe_registers(struct radeon_device *rdev)
2926 {
2927 if (ASIC_IS_RN50(rdev)) {
2928 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2929 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2930 } else if (rdev->family < CHIP_R200) {
2931 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2932 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2933 } else {
2934 r200_set_safe_registers(rdev);
2935 }
2936 }
2937
2938 /*
2939 * Debugfs info
2940 */
2941 #if defined(CONFIG_DEBUG_FS)
r100_debugfs_rbbm_info(struct seq_file * m,void * data)2942 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2943 {
2944 struct drm_info_node *node = (struct drm_info_node *) m->private;
2945 struct drm_device *dev = node->minor->dev;
2946 struct radeon_device *rdev = dev->dev_private;
2947 uint32_t reg, value;
2948 unsigned i;
2949
2950 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2951 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2952 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2953 for (i = 0; i < 64; i++) {
2954 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2955 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2956 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2957 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2958 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2959 }
2960 return 0;
2961 }
2962
r100_debugfs_cp_ring_info(struct seq_file * m,void * data)2963 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2964 {
2965 struct drm_info_node *node = (struct drm_info_node *) m->private;
2966 struct drm_device *dev = node->minor->dev;
2967 struct radeon_device *rdev = dev->dev_private;
2968 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2969 uint32_t rdp, wdp;
2970 unsigned count, i, j;
2971
2972 radeon_ring_free_size(rdev, ring);
2973 rdp = RREG32(RADEON_CP_RB_RPTR);
2974 wdp = RREG32(RADEON_CP_RB_WPTR);
2975 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2976 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2977 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2978 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2979 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2980 seq_printf(m, "%u dwords in ring\n", count);
2981 if (ring->ready) {
2982 for (j = 0; j <= count; j++) {
2983 i = (rdp + j) & ring->ptr_mask;
2984 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2985 }
2986 }
2987 return 0;
2988 }
2989
2990
r100_debugfs_cp_csq_fifo(struct seq_file * m,void * data)2991 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2992 {
2993 struct drm_info_node *node = (struct drm_info_node *) m->private;
2994 struct drm_device *dev = node->minor->dev;
2995 struct radeon_device *rdev = dev->dev_private;
2996 uint32_t csq_stat, csq2_stat, tmp;
2997 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2998 unsigned i;
2999
3000 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
3001 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
3002 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
3003 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
3004 r_rptr = (csq_stat >> 0) & 0x3ff;
3005 r_wptr = (csq_stat >> 10) & 0x3ff;
3006 ib1_rptr = (csq_stat >> 20) & 0x3ff;
3007 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
3008 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
3009 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
3010 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
3011 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
3012 seq_printf(m, "Ring rptr %u\n", r_rptr);
3013 seq_printf(m, "Ring wptr %u\n", r_wptr);
3014 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
3015 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
3016 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
3017 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
3018 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
3019 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
3020 seq_printf(m, "Ring fifo:\n");
3021 for (i = 0; i < 256; i++) {
3022 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3023 tmp = RREG32(RADEON_CP_CSQ_DATA);
3024 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
3025 }
3026 seq_printf(m, "Indirect1 fifo:\n");
3027 for (i = 256; i <= 512; i++) {
3028 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3029 tmp = RREG32(RADEON_CP_CSQ_DATA);
3030 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
3031 }
3032 seq_printf(m, "Indirect2 fifo:\n");
3033 for (i = 640; i < ib1_wptr; i++) {
3034 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3035 tmp = RREG32(RADEON_CP_CSQ_DATA);
3036 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
3037 }
3038 return 0;
3039 }
3040
r100_debugfs_mc_info(struct seq_file * m,void * data)3041 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
3042 {
3043 struct drm_info_node *node = (struct drm_info_node *) m->private;
3044 struct drm_device *dev = node->minor->dev;
3045 struct radeon_device *rdev = dev->dev_private;
3046 uint32_t tmp;
3047
3048 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3049 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3050 tmp = RREG32(RADEON_MC_FB_LOCATION);
3051 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3052 tmp = RREG32(RADEON_BUS_CNTL);
3053 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3054 tmp = RREG32(RADEON_MC_AGP_LOCATION);
3055 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3056 tmp = RREG32(RADEON_AGP_BASE);
3057 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3058 tmp = RREG32(RADEON_HOST_PATH_CNTL);
3059 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3060 tmp = RREG32(0x01D0);
3061 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3062 tmp = RREG32(RADEON_AIC_LO_ADDR);
3063 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3064 tmp = RREG32(RADEON_AIC_HI_ADDR);
3065 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3066 tmp = RREG32(0x01E4);
3067 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3068 return 0;
3069 }
3070
3071 static struct drm_info_list r100_debugfs_rbbm_list[] = {
3072 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
3073 };
3074
3075 static struct drm_info_list r100_debugfs_cp_list[] = {
3076 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
3077 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
3078 };
3079
3080 static struct drm_info_list r100_debugfs_mc_info_list[] = {
3081 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
3082 };
3083 #endif
3084
r100_debugfs_rbbm_init(struct radeon_device * rdev)3085 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
3086 {
3087 #if defined(CONFIG_DEBUG_FS)
3088 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
3089 #else
3090 return 0;
3091 #endif
3092 }
3093
r100_debugfs_cp_init(struct radeon_device * rdev)3094 int r100_debugfs_cp_init(struct radeon_device *rdev)
3095 {
3096 #if defined(CONFIG_DEBUG_FS)
3097 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
3098 #else
3099 return 0;
3100 #endif
3101 }
3102
r100_debugfs_mc_info_init(struct radeon_device * rdev)3103 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
3104 {
3105 #if defined(CONFIG_DEBUG_FS)
3106 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
3107 #else
3108 return 0;
3109 #endif
3110 }
3111
r100_set_surface_reg(struct radeon_device * rdev,int reg,uint32_t tiling_flags,uint32_t pitch,uint32_t offset,uint32_t obj_size)3112 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3113 uint32_t tiling_flags, uint32_t pitch,
3114 uint32_t offset, uint32_t obj_size)
3115 {
3116 int surf_index = reg * 16;
3117 int flags = 0;
3118
3119 if (rdev->family <= CHIP_RS200) {
3120 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3121 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3122 flags |= RADEON_SURF_TILE_COLOR_BOTH;
3123 if (tiling_flags & RADEON_TILING_MACRO)
3124 flags |= RADEON_SURF_TILE_COLOR_MACRO;
3125 /* setting pitch to 0 disables tiling */
3126 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3127 == 0)
3128 pitch = 0;
3129 } else if (rdev->family <= CHIP_RV280) {
3130 if (tiling_flags & (RADEON_TILING_MACRO))
3131 flags |= R200_SURF_TILE_COLOR_MACRO;
3132 if (tiling_flags & RADEON_TILING_MICRO)
3133 flags |= R200_SURF_TILE_COLOR_MICRO;
3134 } else {
3135 if (tiling_flags & RADEON_TILING_MACRO)
3136 flags |= R300_SURF_TILE_MACRO;
3137 if (tiling_flags & RADEON_TILING_MICRO)
3138 flags |= R300_SURF_TILE_MICRO;
3139 }
3140
3141 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3142 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3143 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3144 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3145
3146 /* r100/r200 divide by 16 */
3147 if (rdev->family < CHIP_R300)
3148 flags |= pitch / 16;
3149 else
3150 flags |= pitch / 8;
3151
3152
3153 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3154 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3155 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3156 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3157 return 0;
3158 }
3159
r100_clear_surface_reg(struct radeon_device * rdev,int reg)3160 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3161 {
3162 int surf_index = reg * 16;
3163 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3164 }
3165
r100_bandwidth_update(struct radeon_device * rdev)3166 void r100_bandwidth_update(struct radeon_device *rdev)
3167 {
3168 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3169 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
3170 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff;
3171 fixed20_12 crit_point_ff = {0};
3172 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3173 fixed20_12 memtcas_ff[8] = {
3174 dfixed_init(1),
3175 dfixed_init(2),
3176 dfixed_init(3),
3177 dfixed_init(0),
3178 dfixed_init_half(1),
3179 dfixed_init_half(2),
3180 dfixed_init(0),
3181 };
3182 fixed20_12 memtcas_rs480_ff[8] = {
3183 dfixed_init(0),
3184 dfixed_init(1),
3185 dfixed_init(2),
3186 dfixed_init(3),
3187 dfixed_init(0),
3188 dfixed_init_half(1),
3189 dfixed_init_half(2),
3190 dfixed_init_half(3),
3191 };
3192 fixed20_12 memtcas2_ff[8] = {
3193 dfixed_init(0),
3194 dfixed_init(1),
3195 dfixed_init(2),
3196 dfixed_init(3),
3197 dfixed_init(4),
3198 dfixed_init(5),
3199 dfixed_init(6),
3200 dfixed_init(7),
3201 };
3202 fixed20_12 memtrbs[8] = {
3203 dfixed_init(1),
3204 dfixed_init_half(1),
3205 dfixed_init(2),
3206 dfixed_init_half(2),
3207 dfixed_init(3),
3208 dfixed_init_half(3),
3209 dfixed_init(4),
3210 dfixed_init_half(4)
3211 };
3212 fixed20_12 memtrbs_r4xx[8] = {
3213 dfixed_init(4),
3214 dfixed_init(5),
3215 dfixed_init(6),
3216 dfixed_init(7),
3217 dfixed_init(8),
3218 dfixed_init(9),
3219 dfixed_init(10),
3220 dfixed_init(11)
3221 };
3222 fixed20_12 min_mem_eff;
3223 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3224 fixed20_12 cur_latency_mclk, cur_latency_sclk;
3225 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate = {0},
3226 disp_drain_rate2, read_return_rate;
3227 fixed20_12 time_disp1_drop_priority;
3228 int c;
3229 int cur_size = 16; /* in octawords */
3230 int critical_point = 0, critical_point2;
3231 /* uint32_t read_return_rate, time_disp1_drop_priority; */
3232 int stop_req, max_stop_req;
3233 struct drm_display_mode *mode1 = NULL;
3234 struct drm_display_mode *mode2 = NULL;
3235 uint32_t pixel_bytes1 = 0;
3236 uint32_t pixel_bytes2 = 0;
3237
3238 /* Guess line buffer size to be 8192 pixels */
3239 u32 lb_size = 8192;
3240
3241 if (!rdev->mode_info.mode_config_initialized)
3242 return;
3243
3244 crit_point_ff.full = 0;
3245 disp_drain_rate.full = 0;
3246
3247 radeon_update_display_priority(rdev);
3248
3249 if (rdev->mode_info.crtcs[0]->base.enabled) {
3250 const struct drm_framebuffer *fb =
3251 rdev->mode_info.crtcs[0]->base.primary->fb;
3252
3253 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3254 pixel_bytes1 = fb->format->cpp[0];
3255 }
3256 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3257 if (rdev->mode_info.crtcs[1]->base.enabled) {
3258 const struct drm_framebuffer *fb =
3259 rdev->mode_info.crtcs[1]->base.primary->fb;
3260
3261 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3262 pixel_bytes2 = fb->format->cpp[0];
3263 }
3264 }
3265
3266 min_mem_eff.full = dfixed_const_8(0);
3267 /* get modes */
3268 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3269 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3270 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3271 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3272 /* check crtc enables */
3273 if (mode2)
3274 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3275 if (mode1)
3276 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3277 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3278 }
3279
3280 /*
3281 * determine is there is enough bw for current mode
3282 */
3283 sclk_ff = rdev->pm.sclk;
3284 mclk_ff = rdev->pm.mclk;
3285
3286 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3287 temp_ff.full = dfixed_const(temp);
3288 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
3289
3290 pix_clk.full = 0;
3291 pix_clk2.full = 0;
3292 peak_disp_bw.full = 0;
3293 if (mode1) {
3294 temp_ff.full = dfixed_const(1000);
3295 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3296 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3297 temp_ff.full = dfixed_const(pixel_bytes1);
3298 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3299 }
3300 if (mode2) {
3301 temp_ff.full = dfixed_const(1000);
3302 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3303 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
3304 temp_ff.full = dfixed_const(pixel_bytes2);
3305 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3306 }
3307
3308 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3309 if (peak_disp_bw.full >= mem_bw.full) {
3310 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3311 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3312 }
3313
3314 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
3315 temp = RREG32(RADEON_MEM_TIMING_CNTL);
3316 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3317 mem_trcd = ((temp >> 2) & 0x3) + 1;
3318 mem_trp = ((temp & 0x3)) + 1;
3319 mem_tras = ((temp & 0x70) >> 4) + 1;
3320 } else if (rdev->family == CHIP_R300 ||
3321 rdev->family == CHIP_R350) { /* r300, r350 */
3322 mem_trcd = (temp & 0x7) + 1;
3323 mem_trp = ((temp >> 8) & 0x7) + 1;
3324 mem_tras = ((temp >> 11) & 0xf) + 4;
3325 } else if (rdev->family == CHIP_RV350 ||
3326 rdev->family == CHIP_RV380) {
3327 /* rv3x0 */
3328 mem_trcd = (temp & 0x7) + 3;
3329 mem_trp = ((temp >> 8) & 0x7) + 3;
3330 mem_tras = ((temp >> 11) & 0xf) + 6;
3331 } else if (rdev->family == CHIP_R420 ||
3332 rdev->family == CHIP_R423 ||
3333 rdev->family == CHIP_RV410) {
3334 /* r4xx */
3335 mem_trcd = (temp & 0xf) + 3;
3336 if (mem_trcd > 15)
3337 mem_trcd = 15;
3338 mem_trp = ((temp >> 8) & 0xf) + 3;
3339 if (mem_trp > 15)
3340 mem_trp = 15;
3341 mem_tras = ((temp >> 12) & 0x1f) + 6;
3342 if (mem_tras > 31)
3343 mem_tras = 31;
3344 } else { /* RV200, R200 */
3345 mem_trcd = (temp & 0x7) + 1;
3346 mem_trp = ((temp >> 8) & 0x7) + 1;
3347 mem_tras = ((temp >> 12) & 0xf) + 4;
3348 }
3349 /* convert to FF */
3350 trcd_ff.full = dfixed_const(mem_trcd);
3351 trp_ff.full = dfixed_const(mem_trp);
3352 tras_ff.full = dfixed_const(mem_tras);
3353
3354 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3355 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3356 data = (temp & (7 << 20)) >> 20;
3357 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3358 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3359 tcas_ff = memtcas_rs480_ff[data];
3360 else
3361 tcas_ff = memtcas_ff[data];
3362 } else
3363 tcas_ff = memtcas2_ff[data];
3364
3365 if (rdev->family == CHIP_RS400 ||
3366 rdev->family == CHIP_RS480) {
3367 /* extra cas latency stored in bits 23-25 0-4 clocks */
3368 data = (temp >> 23) & 0x7;
3369 if (data < 5)
3370 tcas_ff.full += dfixed_const(data);
3371 }
3372
3373 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3374 /* on the R300, Tcas is included in Trbs.
3375 */
3376 temp = RREG32(RADEON_MEM_CNTL);
3377 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3378 if (data == 1) {
3379 if (R300_MEM_USE_CD_CH_ONLY & temp) {
3380 temp = RREG32(R300_MC_IND_INDEX);
3381 temp &= ~R300_MC_IND_ADDR_MASK;
3382 temp |= R300_MC_READ_CNTL_CD_mcind;
3383 WREG32(R300_MC_IND_INDEX, temp);
3384 temp = RREG32(R300_MC_IND_DATA);
3385 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3386 } else {
3387 temp = RREG32(R300_MC_READ_CNTL_AB);
3388 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3389 }
3390 } else {
3391 temp = RREG32(R300_MC_READ_CNTL_AB);
3392 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3393 }
3394 if (rdev->family == CHIP_RV410 ||
3395 rdev->family == CHIP_R420 ||
3396 rdev->family == CHIP_R423)
3397 trbs_ff = memtrbs_r4xx[data];
3398 else
3399 trbs_ff = memtrbs[data];
3400 tcas_ff.full += trbs_ff.full;
3401 }
3402
3403 sclk_eff_ff.full = sclk_ff.full;
3404
3405 if (rdev->flags & RADEON_IS_AGP) {
3406 fixed20_12 agpmode_ff;
3407 agpmode_ff.full = dfixed_const(radeon_agpmode);
3408 temp_ff.full = dfixed_const_666(16);
3409 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3410 }
3411 /* TODO PCIE lanes may affect this - agpmode == 16?? */
3412
3413 if (ASIC_IS_R300(rdev)) {
3414 sclk_delay_ff.full = dfixed_const(250);
3415 } else {
3416 if ((rdev->family == CHIP_RV100) ||
3417 rdev->flags & RADEON_IS_IGP) {
3418 if (rdev->mc.vram_is_ddr)
3419 sclk_delay_ff.full = dfixed_const(41);
3420 else
3421 sclk_delay_ff.full = dfixed_const(33);
3422 } else {
3423 if (rdev->mc.vram_width == 128)
3424 sclk_delay_ff.full = dfixed_const(57);
3425 else
3426 sclk_delay_ff.full = dfixed_const(41);
3427 }
3428 }
3429
3430 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3431
3432 if (rdev->mc.vram_is_ddr) {
3433 if (rdev->mc.vram_width == 32) {
3434 k1.full = dfixed_const(40);
3435 c = 3;
3436 } else {
3437 k1.full = dfixed_const(20);
3438 c = 1;
3439 }
3440 } else {
3441 k1.full = dfixed_const(40);
3442 c = 3;
3443 }
3444
3445 temp_ff.full = dfixed_const(2);
3446 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3447 temp_ff.full = dfixed_const(c);
3448 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3449 temp_ff.full = dfixed_const(4);
3450 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3451 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3452 mc_latency_mclk.full += k1.full;
3453
3454 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3455 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3456
3457 /*
3458 HW cursor time assuming worst case of full size colour cursor.
3459 */
3460 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3461 temp_ff.full += trcd_ff.full;
3462 if (temp_ff.full < tras_ff.full)
3463 temp_ff.full = tras_ff.full;
3464 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3465
3466 temp_ff.full = dfixed_const(cur_size);
3467 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3468 /*
3469 Find the total latency for the display data.
3470 */
3471 disp_latency_overhead.full = dfixed_const(8);
3472 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3473 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3474 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3475
3476 if (mc_latency_mclk.full > mc_latency_sclk.full)
3477 disp_latency.full = mc_latency_mclk.full;
3478 else
3479 disp_latency.full = mc_latency_sclk.full;
3480
3481 /* setup Max GRPH_STOP_REQ default value */
3482 if (ASIC_IS_RV100(rdev))
3483 max_stop_req = 0x5c;
3484 else
3485 max_stop_req = 0x7c;
3486
3487 if (mode1) {
3488 /* CRTC1
3489 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3490 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3491 */
3492 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3493
3494 if (stop_req > max_stop_req)
3495 stop_req = max_stop_req;
3496
3497 /*
3498 Find the drain rate of the display buffer.
3499 */
3500 temp_ff.full = dfixed_const((16/pixel_bytes1));
3501 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3502
3503 /*
3504 Find the critical point of the display buffer.
3505 */
3506 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3507 crit_point_ff.full += dfixed_const_half(0);
3508
3509 critical_point = dfixed_trunc(crit_point_ff);
3510
3511 if (rdev->disp_priority == 2) {
3512 critical_point = 0;
3513 }
3514
3515 /*
3516 The critical point should never be above max_stop_req-4. Setting
3517 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3518 */
3519 if (max_stop_req - critical_point < 4)
3520 critical_point = 0;
3521
3522 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3523 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3524 critical_point = 0x10;
3525 }
3526
3527 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3528 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3529 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3530 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3531 if ((rdev->family == CHIP_R350) &&
3532 (stop_req > 0x15)) {
3533 stop_req -= 0x10;
3534 }
3535 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3536 temp |= RADEON_GRPH_BUFFER_SIZE;
3537 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3538 RADEON_GRPH_CRITICAL_AT_SOF |
3539 RADEON_GRPH_STOP_CNTL);
3540 /*
3541 Write the result into the register.
3542 */
3543 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3544 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3545
3546 #if 0
3547 if ((rdev->family == CHIP_RS400) ||
3548 (rdev->family == CHIP_RS480)) {
3549 /* attempt to program RS400 disp regs correctly ??? */
3550 temp = RREG32(RS400_DISP1_REG_CNTL);
3551 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3552 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3553 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3554 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3555 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3556 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3557 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3558 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3559 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3560 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3561 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3562 }
3563 #endif
3564
3565 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3566 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3567 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3568 }
3569
3570 if (mode2) {
3571 u32 grph2_cntl;
3572 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3573
3574 if (stop_req > max_stop_req)
3575 stop_req = max_stop_req;
3576
3577 /*
3578 Find the drain rate of the display buffer.
3579 */
3580 temp_ff.full = dfixed_const((16/pixel_bytes2));
3581 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3582
3583 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3584 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3585 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3586 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3587 if ((rdev->family == CHIP_R350) &&
3588 (stop_req > 0x15)) {
3589 stop_req -= 0x10;
3590 }
3591 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3592 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3593 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3594 RADEON_GRPH_CRITICAL_AT_SOF |
3595 RADEON_GRPH_STOP_CNTL);
3596
3597 if ((rdev->family == CHIP_RS100) ||
3598 (rdev->family == CHIP_RS200))
3599 critical_point2 = 0;
3600 else {
3601 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3602 temp_ff.full = dfixed_const(temp);
3603 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3604 if (sclk_ff.full < temp_ff.full)
3605 temp_ff.full = sclk_ff.full;
3606
3607 read_return_rate.full = temp_ff.full;
3608
3609 if (mode1) {
3610 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3611 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3612 } else {
3613 time_disp1_drop_priority.full = 0;
3614 }
3615 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3616 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3617 crit_point_ff.full += dfixed_const_half(0);
3618
3619 critical_point2 = dfixed_trunc(crit_point_ff);
3620
3621 if (rdev->disp_priority == 2) {
3622 critical_point2 = 0;
3623 }
3624
3625 if (max_stop_req - critical_point2 < 4)
3626 critical_point2 = 0;
3627
3628 }
3629
3630 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3631 /* some R300 cards have problem with this set to 0 */
3632 critical_point2 = 0x10;
3633 }
3634
3635 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3636 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3637
3638 if ((rdev->family == CHIP_RS400) ||
3639 (rdev->family == CHIP_RS480)) {
3640 #if 0
3641 /* attempt to program RS400 disp2 regs correctly ??? */
3642 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3643 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3644 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3645 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3646 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3647 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3648 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3649 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3650 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3651 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3652 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3653 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3654 #endif
3655 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3656 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3657 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3658 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3659 }
3660
3661 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3662 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3663 }
3664
3665 /* Save number of lines the linebuffer leads before the scanout */
3666 if (mode1)
3667 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);
3668
3669 if (mode2)
3670 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);
3671 }
3672
r100_ring_test(struct radeon_device * rdev,struct radeon_ring * ring)3673 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3674 {
3675 uint32_t scratch;
3676 uint32_t tmp = 0;
3677 unsigned i;
3678 int r;
3679
3680 r = radeon_scratch_get(rdev, &scratch);
3681 if (r) {
3682 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3683 return r;
3684 }
3685 WREG32(scratch, 0xCAFEDEAD);
3686 r = radeon_ring_lock(rdev, ring, 2);
3687 if (r) {
3688 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3689 radeon_scratch_free(rdev, scratch);
3690 return r;
3691 }
3692 radeon_ring_write(ring, PACKET0(scratch, 0));
3693 radeon_ring_write(ring, 0xDEADBEEF);
3694 radeon_ring_unlock_commit(rdev, ring, false);
3695 for (i = 0; i < rdev->usec_timeout; i++) {
3696 tmp = RREG32(scratch);
3697 if (tmp == 0xDEADBEEF) {
3698 break;
3699 }
3700 udelay(1);
3701 }
3702 if (i < rdev->usec_timeout) {
3703 DRM_INFO("ring test succeeded in %d usecs\n", i);
3704 } else {
3705 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3706 scratch, tmp);
3707 r = -EINVAL;
3708 }
3709 radeon_scratch_free(rdev, scratch);
3710 return r;
3711 }
3712
r100_ring_ib_execute(struct radeon_device * rdev,struct radeon_ib * ib)3713 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3714 {
3715 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3716
3717 if (ring->rptr_save_reg) {
3718 u32 next_rptr = ring->wptr + 2 + 3;
3719 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3720 radeon_ring_write(ring, next_rptr);
3721 }
3722
3723 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3724 radeon_ring_write(ring, ib->gpu_addr);
3725 radeon_ring_write(ring, ib->length_dw);
3726 }
3727
r100_ib_test(struct radeon_device * rdev,struct radeon_ring * ring)3728 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3729 {
3730 struct radeon_ib ib;
3731 uint32_t scratch;
3732 uint32_t tmp = 0;
3733 unsigned i;
3734 int r;
3735
3736 r = radeon_scratch_get(rdev, &scratch);
3737 if (r) {
3738 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3739 return r;
3740 }
3741 WREG32(scratch, 0xCAFEDEAD);
3742 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
3743 if (r) {
3744 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3745 goto free_scratch;
3746 }
3747 ib.ptr[0] = PACKET0(scratch, 0);
3748 ib.ptr[1] = 0xDEADBEEF;
3749 ib.ptr[2] = PACKET2(0);
3750 ib.ptr[3] = PACKET2(0);
3751 ib.ptr[4] = PACKET2(0);
3752 ib.ptr[5] = PACKET2(0);
3753 ib.ptr[6] = PACKET2(0);
3754 ib.ptr[7] = PACKET2(0);
3755 ib.length_dw = 8;
3756 r = radeon_ib_schedule(rdev, &ib, NULL, false);
3757 if (r) {
3758 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3759 goto free_ib;
3760 }
3761 r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
3762 RADEON_USEC_IB_TEST_TIMEOUT));
3763 if (r < 0) {
3764 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3765 goto free_ib;
3766 } else if (r == 0) {
3767 DRM_ERROR("radeon: fence wait timed out.\n");
3768 r = -ETIMEDOUT;
3769 goto free_ib;
3770 }
3771 r = 0;
3772 for (i = 0; i < rdev->usec_timeout; i++) {
3773 tmp = RREG32(scratch);
3774 if (tmp == 0xDEADBEEF) {
3775 break;
3776 }
3777 udelay(1);
3778 }
3779 if (i < rdev->usec_timeout) {
3780 DRM_INFO("ib test succeeded in %u usecs\n", i);
3781 } else {
3782 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3783 scratch, tmp);
3784 r = -EINVAL;
3785 }
3786 free_ib:
3787 radeon_ib_free(rdev, &ib);
3788 free_scratch:
3789 radeon_scratch_free(rdev, scratch);
3790 return r;
3791 }
3792
r100_mc_stop(struct radeon_device * rdev,struct r100_mc_save * save)3793 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3794 {
3795 /* Shutdown CP we shouldn't need to do that but better be safe than
3796 * sorry
3797 */
3798 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3799 WREG32(R_000740_CP_CSQ_CNTL, 0);
3800
3801 /* Save few CRTC registers */
3802 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3803 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3804 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3805 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3806 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3807 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3808 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3809 }
3810
3811 /* Disable VGA aperture access */
3812 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3813 /* Disable cursor, overlay, crtc */
3814 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3815 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3816 S_000054_CRTC_DISPLAY_DIS(1));
3817 WREG32(R_000050_CRTC_GEN_CNTL,
3818 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3819 S_000050_CRTC_DISP_REQ_EN_B(1));
3820 WREG32(R_000420_OV0_SCALE_CNTL,
3821 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3822 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3823 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3824 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3825 S_000360_CUR2_LOCK(1));
3826 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3827 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3828 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3829 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3830 WREG32(R_000360_CUR2_OFFSET,
3831 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3832 }
3833 }
3834
r100_mc_resume(struct radeon_device * rdev,struct r100_mc_save * save)3835 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3836 {
3837 /* Update base address for crtc */
3838 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3839 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3840 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3841 }
3842 /* Restore CRTC registers */
3843 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3844 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3845 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3846 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3847 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3848 }
3849 }
3850
r100_vga_render_disable(struct radeon_device * rdev)3851 void r100_vga_render_disable(struct radeon_device *rdev)
3852 {
3853 u32 tmp;
3854
3855 tmp = RREG8(R_0003C2_GENMO_WT);
3856 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3857 }
3858
r100_debugfs(struct radeon_device * rdev)3859 static void r100_debugfs(struct radeon_device *rdev)
3860 {
3861 int r;
3862
3863 r = r100_debugfs_mc_info_init(rdev);
3864 if (r)
3865 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3866 }
3867
r100_mc_program(struct radeon_device * rdev)3868 static void r100_mc_program(struct radeon_device *rdev)
3869 {
3870 struct r100_mc_save save;
3871
3872 /* Stops all mc clients */
3873 r100_mc_stop(rdev, &save);
3874 if (rdev->flags & RADEON_IS_AGP) {
3875 WREG32(R_00014C_MC_AGP_LOCATION,
3876 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3877 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3878 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3879 if (rdev->family > CHIP_RV200)
3880 WREG32(R_00015C_AGP_BASE_2,
3881 upper_32_bits(rdev->mc.agp_base) & 0xff);
3882 } else {
3883 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3884 WREG32(R_000170_AGP_BASE, 0);
3885 if (rdev->family > CHIP_RV200)
3886 WREG32(R_00015C_AGP_BASE_2, 0);
3887 }
3888 /* Wait for mc idle */
3889 if (r100_mc_wait_for_idle(rdev))
3890 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3891 /* Program MC, should be a 32bits limited address space */
3892 WREG32(R_000148_MC_FB_LOCATION,
3893 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3894 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3895 r100_mc_resume(rdev, &save);
3896 }
3897
r100_clock_startup(struct radeon_device * rdev)3898 static void r100_clock_startup(struct radeon_device *rdev)
3899 {
3900 u32 tmp;
3901
3902 if (radeon_dynclks != -1 && radeon_dynclks)
3903 radeon_legacy_set_clock_gating(rdev, 1);
3904 /* We need to force on some of the block */
3905 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3906 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3907 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3908 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3909 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3910 }
3911
r100_startup(struct radeon_device * rdev)3912 static int r100_startup(struct radeon_device *rdev)
3913 {
3914 int r;
3915
3916 /* set common regs */
3917 r100_set_common_regs(rdev);
3918 /* program mc */
3919 r100_mc_program(rdev);
3920 /* Resume clock */
3921 r100_clock_startup(rdev);
3922 /* Initialize GART (initialize after TTM so we can allocate
3923 * memory through TTM but finalize after TTM) */
3924 r100_enable_bm(rdev);
3925 if (rdev->flags & RADEON_IS_PCI) {
3926 r = r100_pci_gart_enable(rdev);
3927 if (r)
3928 return r;
3929 }
3930
3931 /* allocate wb buffer */
3932 r = radeon_wb_init(rdev);
3933 if (r)
3934 return r;
3935
3936 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3937 if (r) {
3938 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3939 return r;
3940 }
3941
3942 /* Enable IRQ */
3943 if (!rdev->irq.installed) {
3944 r = radeon_irq_kms_init(rdev);
3945 if (r)
3946 return r;
3947 }
3948
3949 r100_irq_set(rdev);
3950 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3951 /* 1M ring buffer */
3952 r = r100_cp_init(rdev, 1024 * 1024);
3953 if (r) {
3954 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3955 return r;
3956 }
3957
3958 r = radeon_ib_pool_init(rdev);
3959 if (r) {
3960 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3961 return r;
3962 }
3963
3964 return 0;
3965 }
3966
r100_resume(struct radeon_device * rdev)3967 int r100_resume(struct radeon_device *rdev)
3968 {
3969 int r;
3970
3971 /* Make sur GART are not working */
3972 if (rdev->flags & RADEON_IS_PCI)
3973 r100_pci_gart_disable(rdev);
3974 /* Resume clock before doing reset */
3975 r100_clock_startup(rdev);
3976 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3977 if (radeon_asic_reset(rdev)) {
3978 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3979 RREG32(R_000E40_RBBM_STATUS),
3980 RREG32(R_0007C0_CP_STAT));
3981 }
3982 /* post */
3983 radeon_combios_asic_init(rdev->ddev);
3984 /* Resume clock after posting */
3985 r100_clock_startup(rdev);
3986 /* Initialize surface registers */
3987 radeon_surface_init(rdev);
3988
3989 rdev->accel_working = true;
3990 r = r100_startup(rdev);
3991 if (r) {
3992 rdev->accel_working = false;
3993 }
3994 return r;
3995 }
3996
r100_suspend(struct radeon_device * rdev)3997 int r100_suspend(struct radeon_device *rdev)
3998 {
3999 radeon_pm_suspend(rdev);
4000 r100_cp_disable(rdev);
4001 radeon_wb_disable(rdev);
4002 r100_irq_disable(rdev);
4003 if (rdev->flags & RADEON_IS_PCI)
4004 r100_pci_gart_disable(rdev);
4005 return 0;
4006 }
4007
r100_fini(struct radeon_device * rdev)4008 void r100_fini(struct radeon_device *rdev)
4009 {
4010 radeon_pm_fini(rdev);
4011 r100_cp_fini(rdev);
4012 radeon_wb_fini(rdev);
4013 radeon_ib_pool_fini(rdev);
4014 radeon_gem_fini(rdev);
4015 if (rdev->flags & RADEON_IS_PCI)
4016 r100_pci_gart_fini(rdev);
4017 radeon_agp_fini(rdev);
4018 radeon_irq_kms_fini(rdev);
4019 radeon_fence_driver_fini(rdev);
4020 radeon_bo_fini(rdev);
4021 radeon_atombios_fini(rdev);
4022 kfree(rdev->bios);
4023 rdev->bios = NULL;
4024 }
4025
4026 /*
4027 * Due to how kexec works, it can leave the hw fully initialised when it
4028 * boots the new kernel. However doing our init sequence with the CP and
4029 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
4030 * do some quick sanity checks and restore sane values to avoid this
4031 * problem.
4032 */
r100_restore_sanity(struct radeon_device * rdev)4033 void r100_restore_sanity(struct radeon_device *rdev)
4034 {
4035 u32 tmp;
4036
4037 tmp = RREG32(RADEON_CP_CSQ_CNTL);
4038 if (tmp) {
4039 WREG32(RADEON_CP_CSQ_CNTL, 0);
4040 }
4041 tmp = RREG32(RADEON_CP_RB_CNTL);
4042 if (tmp) {
4043 WREG32(RADEON_CP_RB_CNTL, 0);
4044 }
4045 tmp = RREG32(RADEON_SCRATCH_UMSK);
4046 if (tmp) {
4047 WREG32(RADEON_SCRATCH_UMSK, 0);
4048 }
4049 }
4050
r100_init(struct radeon_device * rdev)4051 int r100_init(struct radeon_device *rdev)
4052 {
4053 int r;
4054
4055 /* Register debugfs file specific to this group of asics */
4056 r100_debugfs(rdev);
4057 /* Disable VGA */
4058 r100_vga_render_disable(rdev);
4059 /* Initialize scratch registers */
4060 radeon_scratch_init(rdev);
4061 /* Initialize surface registers */
4062 radeon_surface_init(rdev);
4063 /* sanity check some register to avoid hangs like after kexec */
4064 r100_restore_sanity(rdev);
4065 /* TODO: disable VGA need to use VGA request */
4066 /* BIOS*/
4067 if (!radeon_get_bios(rdev)) {
4068 if (ASIC_IS_AVIVO(rdev))
4069 return -EINVAL;
4070 }
4071 if (rdev->is_atom_bios) {
4072 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4073 return -EINVAL;
4074 } else {
4075 r = radeon_combios_init(rdev);
4076 if (r)
4077 return r;
4078 }
4079 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4080 if (radeon_asic_reset(rdev)) {
4081 dev_warn(rdev->dev,
4082 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4083 RREG32(R_000E40_RBBM_STATUS),
4084 RREG32(R_0007C0_CP_STAT));
4085 }
4086 /* check if cards are posted or not */
4087 if (radeon_boot_test_post_card(rdev) == false)
4088 return -EINVAL;
4089 /* Set asic errata */
4090 r100_errata(rdev);
4091 /* Initialize clocks */
4092 radeon_get_clock_info(rdev->ddev);
4093 /* initialize AGP */
4094 if (rdev->flags & RADEON_IS_AGP) {
4095 r = radeon_agp_init(rdev);
4096 if (r) {
4097 radeon_agp_disable(rdev);
4098 }
4099 }
4100 /* initialize VRAM */
4101 r100_mc_init(rdev);
4102 /* Fence driver */
4103 r = radeon_fence_driver_init(rdev);
4104 if (r)
4105 return r;
4106 /* Memory manager */
4107 r = radeon_bo_init(rdev);
4108 if (r)
4109 return r;
4110 if (rdev->flags & RADEON_IS_PCI) {
4111 r = r100_pci_gart_init(rdev);
4112 if (r)
4113 return r;
4114 }
4115 r100_set_safe_registers(rdev);
4116
4117 /* Initialize power management */
4118 radeon_pm_init(rdev);
4119
4120 rdev->accel_working = true;
4121 r = r100_startup(rdev);
4122 if (r) {
4123 /* Somethings want wront with the accel init stop accel */
4124 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4125 r100_cp_fini(rdev);
4126 radeon_wb_fini(rdev);
4127 radeon_ib_pool_fini(rdev);
4128 radeon_irq_kms_fini(rdev);
4129 if (rdev->flags & RADEON_IS_PCI)
4130 r100_pci_gart_fini(rdev);
4131 rdev->accel_working = false;
4132 }
4133 return 0;
4134 }
4135
r100_mm_rreg_slow(struct radeon_device * rdev,uint32_t reg)4136 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg)
4137 {
4138 unsigned long flags;
4139 uint32_t ret;
4140
4141 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4142 #ifdef __NetBSD__
4143 bus_space_write_4(rdev->rmmio_bst, rdev->rmmio_bsh,
4144 RADEON_MM_INDEX, reg);
4145 ret = bus_space_read_4(rdev->rmmio_bst, rdev->rmmio_bsh,
4146 RADEON_MM_DATA);
4147 #else
4148 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4149 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4150 #endif
4151 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4152 return ret;
4153 }
4154
r100_mm_wreg_slow(struct radeon_device * rdev,uint32_t reg,uint32_t v)4155 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4156 {
4157 unsigned long flags;
4158
4159 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4160 #ifdef __NetBSD__
4161 bus_space_write_4(rdev->rmmio_bst, rdev->rmmio_bsh,
4162 RADEON_MM_INDEX, reg);
4163 bus_space_write_4(rdev->rmmio_bst, rdev->rmmio_bsh,
4164 RADEON_MM_DATA, v);
4165 #else
4166 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4167 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4168 #endif
4169 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4170 }
4171
r100_io_rreg(struct radeon_device * rdev,u32 reg)4172 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4173 {
4174 #ifdef __NetBSD__
4175 if (reg < rdev->rio_mem_size) {
4176 return bus_space_read_4(rdev->rio_mem_bst, rdev->rio_mem_bsh,
4177 reg);
4178 } else {
4179 bus_space_write_4(rdev->rio_mem_bst, rdev->rio_mem_bsh,
4180 RADEON_MM_INDEX, reg);
4181 return bus_space_read_4(rdev->rio_mem_bst, rdev->rio_mem_bsh,
4182 RADEON_MM_DATA);
4183 }
4184 #else
4185 if (reg < rdev->rio_mem_size)
4186 return ioread32(rdev->rio_mem + reg);
4187 else {
4188 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4189 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4190 }
4191 #endif
4192 }
4193
r100_io_wreg(struct radeon_device * rdev,u32 reg,u32 v)4194 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4195 {
4196 #ifdef __NetBSD__
4197 if (reg < rdev->rio_mem_size) {
4198 bus_space_write_4(rdev->rio_mem_bst, rdev->rio_mem_bsh, reg,
4199 v);
4200 } else {
4201 bus_space_write_4(rdev->rio_mem_bst, rdev->rio_mem_bsh,
4202 RADEON_MM_INDEX, reg);
4203 bus_space_write_4(rdev->rio_mem_bst, rdev->rio_mem_bsh,
4204 RADEON_MM_DATA, v);
4205 }
4206 #else
4207 if (reg < rdev->rio_mem_size)
4208 iowrite32(v, rdev->rio_mem + reg);
4209 else {
4210 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4211 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4212 }
4213 #endif
4214 }
4215