1 /* $NetBSD: radeon_r600_cs.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $ */
2
3 /*
4 * Copyright 2008 Advanced Micro Devices, Inc.
5 * Copyright 2008 Red Hat Inc.
6 * Copyright 2009 Jerome Glisse.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
24 * OTHER DEALINGS IN THE SOFTWARE.
25 *
26 * Authors: Dave Airlie
27 * Alex Deucher
28 * Jerome Glisse
29 */
30 #include <sys/cdefs.h>
31 __KERNEL_RCSID(0, "$NetBSD: radeon_r600_cs.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $");
32
33 #include <linux/kernel.h>
34
35 #include "radeon.h"
36 #include "radeon_asic.h"
37 #include "r600d.h"
38 #include "r600_reg_safe.h"
39
40 static int r600_nomm;
41 extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
42
43
44 struct r600_cs_track {
45 /* configuration we miror so that we use same code btw kms/ums */
46 u32 group_size;
47 u32 nbanks;
48 u32 npipes;
49 /* value we track */
50 u32 sq_config;
51 u32 log_nsamples;
52 u32 nsamples;
53 u32 cb_color_base_last[8];
54 struct radeon_bo *cb_color_bo[8];
55 u64 cb_color_bo_mc[8];
56 u64 cb_color_bo_offset[8];
57 struct radeon_bo *cb_color_frag_bo[8];
58 u64 cb_color_frag_offset[8];
59 struct radeon_bo *cb_color_tile_bo[8];
60 u64 cb_color_tile_offset[8];
61 u32 cb_color_mask[8];
62 u32 cb_color_info[8];
63 u32 cb_color_view[8];
64 u32 cb_color_size_idx[8]; /* unused */
65 u32 cb_target_mask;
66 u32 cb_shader_mask; /* unused */
67 bool is_resolve;
68 u32 cb_color_size[8];
69 u32 vgt_strmout_en;
70 u32 vgt_strmout_buffer_en;
71 struct radeon_bo *vgt_strmout_bo[4];
72 u64 vgt_strmout_bo_mc[4]; /* unused */
73 u32 vgt_strmout_bo_offset[4];
74 u32 vgt_strmout_size[4];
75 u32 db_depth_control;
76 u32 db_depth_info;
77 u32 db_depth_size_idx;
78 u32 db_depth_view;
79 u32 db_depth_size;
80 u32 db_offset;
81 struct radeon_bo *db_bo;
82 u64 db_bo_mc;
83 bool sx_misc_kill_all_prims;
84 bool cb_dirty;
85 bool db_dirty;
86 bool streamout_dirty;
87 struct radeon_bo *htile_bo;
88 u64 htile_offset;
89 u32 htile_surface;
90 };
91
92 #define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 }
93 #define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc, CHIP_R600 }
94 #define FMT_24_BIT(fmt) [fmt] = { 1, 1, 4, 0, CHIP_R600 }
95 #define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc, CHIP_R600 }
96 #define FMT_48_BIT(fmt) [fmt] = { 1, 1, 8, 0, CHIP_R600 }
97 #define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc, CHIP_R600 }
98 #define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0, CHIP_R600 }
99 #define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 }
100
101 struct gpu_formats {
102 unsigned blockwidth;
103 unsigned blockheight;
104 unsigned blocksize;
105 unsigned valid_color;
106 enum radeon_family min_family;
107 };
108
109 static const struct gpu_formats color_formats_table[] = {
110 /* 8 bit */
111 FMT_8_BIT(V_038004_COLOR_8, 1),
112 FMT_8_BIT(V_038004_COLOR_4_4, 1),
113 FMT_8_BIT(V_038004_COLOR_3_3_2, 1),
114 FMT_8_BIT(V_038004_FMT_1, 0),
115
116 /* 16-bit */
117 FMT_16_BIT(V_038004_COLOR_16, 1),
118 FMT_16_BIT(V_038004_COLOR_16_FLOAT, 1),
119 FMT_16_BIT(V_038004_COLOR_8_8, 1),
120 FMT_16_BIT(V_038004_COLOR_5_6_5, 1),
121 FMT_16_BIT(V_038004_COLOR_6_5_5, 1),
122 FMT_16_BIT(V_038004_COLOR_1_5_5_5, 1),
123 FMT_16_BIT(V_038004_COLOR_4_4_4_4, 1),
124 FMT_16_BIT(V_038004_COLOR_5_5_5_1, 1),
125
126 /* 24-bit */
127 FMT_24_BIT(V_038004_FMT_8_8_8),
128
129 /* 32-bit */
130 FMT_32_BIT(V_038004_COLOR_32, 1),
131 FMT_32_BIT(V_038004_COLOR_32_FLOAT, 1),
132 FMT_32_BIT(V_038004_COLOR_16_16, 1),
133 FMT_32_BIT(V_038004_COLOR_16_16_FLOAT, 1),
134 FMT_32_BIT(V_038004_COLOR_8_24, 1),
135 FMT_32_BIT(V_038004_COLOR_8_24_FLOAT, 1),
136 FMT_32_BIT(V_038004_COLOR_24_8, 1),
137 FMT_32_BIT(V_038004_COLOR_24_8_FLOAT, 1),
138 FMT_32_BIT(V_038004_COLOR_10_11_11, 1),
139 FMT_32_BIT(V_038004_COLOR_10_11_11_FLOAT, 1),
140 FMT_32_BIT(V_038004_COLOR_11_11_10, 1),
141 FMT_32_BIT(V_038004_COLOR_11_11_10_FLOAT, 1),
142 FMT_32_BIT(V_038004_COLOR_2_10_10_10, 1),
143 FMT_32_BIT(V_038004_COLOR_8_8_8_8, 1),
144 FMT_32_BIT(V_038004_COLOR_10_10_10_2, 1),
145 FMT_32_BIT(V_038004_FMT_5_9_9_9_SHAREDEXP, 0),
146 FMT_32_BIT(V_038004_FMT_32_AS_8, 0),
147 FMT_32_BIT(V_038004_FMT_32_AS_8_8, 0),
148
149 /* 48-bit */
150 FMT_48_BIT(V_038004_FMT_16_16_16),
151 FMT_48_BIT(V_038004_FMT_16_16_16_FLOAT),
152
153 /* 64-bit */
154 FMT_64_BIT(V_038004_COLOR_X24_8_32_FLOAT, 1),
155 FMT_64_BIT(V_038004_COLOR_32_32, 1),
156 FMT_64_BIT(V_038004_COLOR_32_32_FLOAT, 1),
157 FMT_64_BIT(V_038004_COLOR_16_16_16_16, 1),
158 FMT_64_BIT(V_038004_COLOR_16_16_16_16_FLOAT, 1),
159
160 FMT_96_BIT(V_038004_FMT_32_32_32),
161 FMT_96_BIT(V_038004_FMT_32_32_32_FLOAT),
162
163 /* 128-bit */
164 FMT_128_BIT(V_038004_COLOR_32_32_32_32, 1),
165 FMT_128_BIT(V_038004_COLOR_32_32_32_32_FLOAT, 1),
166
167 [V_038004_FMT_GB_GR] = { 2, 1, 4, 0 },
168 [V_038004_FMT_BG_RG] = { 2, 1, 4, 0 },
169
170 /* block compressed formats */
171 [V_038004_FMT_BC1] = { 4, 4, 8, 0 },
172 [V_038004_FMT_BC2] = { 4, 4, 16, 0 },
173 [V_038004_FMT_BC3] = { 4, 4, 16, 0 },
174 [V_038004_FMT_BC4] = { 4, 4, 8, 0 },
175 [V_038004_FMT_BC5] = { 4, 4, 16, 0},
176 [V_038004_FMT_BC6] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
177 [V_038004_FMT_BC7] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
178
179 /* The other Evergreen formats */
180 [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR},
181 };
182
r600_fmt_is_valid_color(u32 format)183 bool r600_fmt_is_valid_color(u32 format)
184 {
185 if (format >= ARRAY_SIZE(color_formats_table))
186 return false;
187
188 if (color_formats_table[format].valid_color)
189 return true;
190
191 return false;
192 }
193
r600_fmt_is_valid_texture(u32 format,enum radeon_family family)194 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family)
195 {
196 if (format >= ARRAY_SIZE(color_formats_table))
197 return false;
198
199 if (family < color_formats_table[format].min_family)
200 return false;
201
202 if (color_formats_table[format].blockwidth > 0)
203 return true;
204
205 return false;
206 }
207
r600_fmt_get_blocksize(u32 format)208 int r600_fmt_get_blocksize(u32 format)
209 {
210 if (format >= ARRAY_SIZE(color_formats_table))
211 return 0;
212
213 return color_formats_table[format].blocksize;
214 }
215
r600_fmt_get_nblocksx(u32 format,u32 w)216 int r600_fmt_get_nblocksx(u32 format, u32 w)
217 {
218 unsigned bw;
219
220 if (format >= ARRAY_SIZE(color_formats_table))
221 return 0;
222
223 bw = color_formats_table[format].blockwidth;
224 if (bw == 0)
225 return 0;
226
227 return (w + bw - 1) / bw;
228 }
229
r600_fmt_get_nblocksy(u32 format,u32 h)230 int r600_fmt_get_nblocksy(u32 format, u32 h)
231 {
232 unsigned bh;
233
234 if (format >= ARRAY_SIZE(color_formats_table))
235 return 0;
236
237 bh = color_formats_table[format].blockheight;
238 if (bh == 0)
239 return 0;
240
241 return (h + bh - 1) / bh;
242 }
243
244 struct array_mode_checker {
245 int array_mode;
246 u32 group_size;
247 u32 nbanks;
248 u32 npipes;
249 u32 nsamples;
250 u32 blocksize;
251 };
252
253 /* returns alignment in pixels for pitch/height/depth and bytes for base */
r600_get_array_mode_alignment(struct array_mode_checker * values,u32 * pitch_align,u32 * height_align,u32 * depth_align,u64 * base_align)254 static int r600_get_array_mode_alignment(struct array_mode_checker *values,
255 u32 *pitch_align,
256 u32 *height_align,
257 u32 *depth_align,
258 u64 *base_align)
259 {
260 u32 tile_width = 8;
261 u32 tile_height = 8;
262 u32 macro_tile_width = values->nbanks;
263 u32 macro_tile_height = values->npipes;
264 u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples;
265 u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes;
266
267 switch (values->array_mode) {
268 case ARRAY_LINEAR_GENERAL:
269 /* technically tile_width/_height for pitch/height */
270 *pitch_align = 1; /* tile_width */
271 *height_align = 1; /* tile_height */
272 *depth_align = 1;
273 *base_align = 1;
274 break;
275 case ARRAY_LINEAR_ALIGNED:
276 *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize));
277 *height_align = 1;
278 *depth_align = 1;
279 *base_align = values->group_size;
280 break;
281 case ARRAY_1D_TILED_THIN1:
282 *pitch_align = max((u32)tile_width,
283 (u32)(values->group_size /
284 (tile_height * values->blocksize * values->nsamples)));
285 *height_align = tile_height;
286 *depth_align = 1;
287 *base_align = values->group_size;
288 break;
289 case ARRAY_2D_TILED_THIN1:
290 *pitch_align = max((u32)macro_tile_width * tile_width,
291 (u32)((values->group_size * values->nbanks) /
292 (values->blocksize * values->nsamples * tile_width)));
293 *height_align = macro_tile_height * tile_height;
294 *depth_align = 1;
295 *base_align = max(macro_tile_bytes,
296 (*pitch_align) * values->blocksize * (*height_align) * values->nsamples);
297 break;
298 default:
299 return -EINVAL;
300 }
301
302 return 0;
303 }
304
r600_cs_track_init(struct r600_cs_track * track)305 static void r600_cs_track_init(struct r600_cs_track *track)
306 {
307 int i;
308
309 /* assume DX9 mode */
310 track->sq_config = DX9_CONSTS;
311 for (i = 0; i < 8; i++) {
312 track->cb_color_base_last[i] = 0;
313 track->cb_color_size[i] = 0;
314 track->cb_color_size_idx[i] = 0;
315 track->cb_color_info[i] = 0;
316 track->cb_color_view[i] = 0xFFFFFFFF;
317 track->cb_color_bo[i] = NULL;
318 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
319 track->cb_color_bo_mc[i] = 0xFFFFFFFF;
320 track->cb_color_frag_bo[i] = NULL;
321 track->cb_color_frag_offset[i] = 0xFFFFFFFF;
322 track->cb_color_tile_bo[i] = NULL;
323 track->cb_color_tile_offset[i] = 0xFFFFFFFF;
324 track->cb_color_mask[i] = 0xFFFFFFFF;
325 }
326 track->is_resolve = false;
327 track->nsamples = 16;
328 track->log_nsamples = 4;
329 track->cb_target_mask = 0xFFFFFFFF;
330 track->cb_shader_mask = 0xFFFFFFFF;
331 track->cb_dirty = true;
332 track->db_bo = NULL;
333 track->db_bo_mc = 0xFFFFFFFF;
334 /* assume the biggest format and that htile is enabled */
335 track->db_depth_info = 7 | (1 << 25);
336 track->db_depth_view = 0xFFFFC000;
337 track->db_depth_size = 0xFFFFFFFF;
338 track->db_depth_size_idx = 0;
339 track->db_depth_control = 0xFFFFFFFF;
340 track->db_dirty = true;
341 track->htile_bo = NULL;
342 track->htile_offset = 0xFFFFFFFF;
343 track->htile_surface = 0;
344
345 for (i = 0; i < 4; i++) {
346 track->vgt_strmout_size[i] = 0;
347 track->vgt_strmout_bo[i] = NULL;
348 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
349 track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF;
350 }
351 track->streamout_dirty = true;
352 track->sx_misc_kill_all_prims = false;
353 }
354
r600_cs_track_validate_cb(struct radeon_cs_parser * p,int i)355 static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
356 {
357 struct r600_cs_track *track = p->track;
358 u32 slice_tile_max, tmp;
359 u32 height, height_align, pitch, pitch_align, depth_align;
360 u64 base_offset, base_align;
361 struct array_mode_checker array_check;
362 volatile u32 *ib = p->ib.ptr;
363 unsigned array_mode;
364 u32 format;
365 /* When resolve is used, the second colorbuffer has always 1 sample. */
366 unsigned nsamples = track->is_resolve && i == 1 ? 1 : track->nsamples;
367
368 format = G_0280A0_FORMAT(track->cb_color_info[i]);
369 if (!r600_fmt_is_valid_color(format)) {
370 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
371 __func__, __LINE__, format,
372 i, track->cb_color_info[i]);
373 return -EINVAL;
374 }
375 /* pitch in pixels */
376 pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8;
377 slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
378 slice_tile_max *= 64;
379 height = slice_tile_max / pitch;
380 if (height > 8192)
381 height = 8192;
382 array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
383
384 base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i];
385 array_check.array_mode = array_mode;
386 array_check.group_size = track->group_size;
387 array_check.nbanks = track->nbanks;
388 array_check.npipes = track->npipes;
389 array_check.nsamples = nsamples;
390 array_check.blocksize = r600_fmt_get_blocksize(format);
391 if (r600_get_array_mode_alignment(&array_check,
392 &pitch_align, &height_align, &depth_align, &base_align)) {
393 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
394 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
395 track->cb_color_info[i]);
396 return -EINVAL;
397 }
398 switch (array_mode) {
399 case V_0280A0_ARRAY_LINEAR_GENERAL:
400 break;
401 case V_0280A0_ARRAY_LINEAR_ALIGNED:
402 break;
403 case V_0280A0_ARRAY_1D_TILED_THIN1:
404 /* avoid breaking userspace */
405 if (height > 7)
406 height &= ~0x7;
407 break;
408 case V_0280A0_ARRAY_2D_TILED_THIN1:
409 break;
410 default:
411 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
412 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
413 track->cb_color_info[i]);
414 return -EINVAL;
415 }
416
417 if (!IS_ALIGNED(pitch, pitch_align)) {
418 dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n",
419 __func__, __LINE__, pitch, pitch_align, array_mode);
420 return -EINVAL;
421 }
422 if (!IS_ALIGNED(height, height_align)) {
423 dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n",
424 __func__, __LINE__, height, height_align, array_mode);
425 return -EINVAL;
426 }
427 if (!IS_ALIGNED(base_offset, base_align)) {
428 dev_warn(p->dev, "%s offset[%d] 0x%"PRIx64" 0x%"PRIx64", %d not aligned\n", __func__, i,
429 base_offset, base_align, array_mode);
430 return -EINVAL;
431 }
432
433 /* check offset */
434 tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) *
435 r600_fmt_get_blocksize(format) * nsamples;
436 switch (array_mode) {
437 default:
438 case V_0280A0_ARRAY_LINEAR_GENERAL:
439 case V_0280A0_ARRAY_LINEAR_ALIGNED:
440 tmp += track->cb_color_view[i] & 0xFF;
441 break;
442 case V_0280A0_ARRAY_1D_TILED_THIN1:
443 case V_0280A0_ARRAY_2D_TILED_THIN1:
444 tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp;
445 break;
446 }
447 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
448 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
449 /* the initial DDX does bad things with the CB size occasionally */
450 /* it rounds up height too far for slice tile max but the BO is smaller */
451 /* r600c,g also seem to flush at bad times in some apps resulting in
452 * bogus values here. So for linear just allow anything to avoid breaking
453 * broken userspace.
454 */
455 } else {
456 dev_warn(p->dev, "%s offset[%d] %d %"PRIu64" %d %lu too big (%d %d) (%d %d %d)\n",
457 __func__, i, array_mode,
458 track->cb_color_bo_offset[i], tmp,
459 radeon_bo_size(track->cb_color_bo[i]),
460 pitch, height, r600_fmt_get_nblocksx(format, pitch),
461 r600_fmt_get_nblocksy(format, height),
462 r600_fmt_get_blocksize(format));
463 return -EINVAL;
464 }
465 }
466 /* limit max tile */
467 tmp = (height * pitch) >> 6;
468 if (tmp < slice_tile_max)
469 slice_tile_max = tmp;
470 tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
471 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
472 ib[track->cb_color_size_idx[i]] = tmp;
473
474 /* FMASK/CMASK */
475 switch (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
476 case V_0280A0_TILE_DISABLE:
477 break;
478 case V_0280A0_FRAG_ENABLE:
479 if (track->nsamples > 1) {
480 uint32_t tile_max = G_028100_FMASK_TILE_MAX(track->cb_color_mask[i]);
481 /* the tile size is 8x8, but the size is in units of bits.
482 * for bytes, do just * 8. */
483 uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1);
484
485 if (bytes + track->cb_color_frag_offset[i] >
486 radeon_bo_size(track->cb_color_frag_bo[i])) {
487 dev_warn(p->dev, "%s FMASK_TILE_MAX too large "
488 "(tile_max=%u, bytes=%u, offset=%"PRIu64", bo_size=%lu)\n",
489 __func__, tile_max, bytes,
490 track->cb_color_frag_offset[i],
491 radeon_bo_size(track->cb_color_frag_bo[i]));
492 return -EINVAL;
493 }
494 }
495 /* fall through */
496 case V_0280A0_CLEAR_ENABLE:
497 {
498 uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]);
499 /* One block = 128x128 pixels, one 8x8 tile has 4 bits..
500 * (128*128) / (8*8) / 2 = 128 bytes per block. */
501 uint32_t bytes = (block_max + 1) * 128;
502
503 if (bytes + track->cb_color_tile_offset[i] >
504 radeon_bo_size(track->cb_color_tile_bo[i])) {
505 dev_warn(p->dev, "%s CMASK_BLOCK_MAX too large "
506 "(block_max=%u, bytes=%u, offset=%"PRIu64", bo_size=%lu)\n",
507 __func__, block_max, bytes,
508 track->cb_color_tile_offset[i],
509 radeon_bo_size(track->cb_color_tile_bo[i]));
510 return -EINVAL;
511 }
512 break;
513 }
514 default:
515 dev_warn(p->dev, "%s invalid tile mode\n", __func__);
516 return -EINVAL;
517 }
518 return 0;
519 }
520
r600_cs_track_validate_db(struct radeon_cs_parser * p)521 static int r600_cs_track_validate_db(struct radeon_cs_parser *p)
522 {
523 struct r600_cs_track *track = p->track;
524 u32 nviews, bpe, ntiles, slice_tile_max, tmp;
525 u32 height_align, pitch_align, depth_align;
526 u32 pitch = 8192;
527 u32 height = 8192;
528 u64 base_offset, base_align;
529 struct array_mode_checker array_check;
530 int array_mode;
531 volatile u32 *ib = p->ib.ptr;
532
533
534 if (track->db_bo == NULL) {
535 dev_warn(p->dev, "z/stencil with no depth buffer\n");
536 return -EINVAL;
537 }
538 switch (G_028010_FORMAT(track->db_depth_info)) {
539 case V_028010_DEPTH_16:
540 bpe = 2;
541 break;
542 case V_028010_DEPTH_X8_24:
543 case V_028010_DEPTH_8_24:
544 case V_028010_DEPTH_X8_24_FLOAT:
545 case V_028010_DEPTH_8_24_FLOAT:
546 case V_028010_DEPTH_32_FLOAT:
547 bpe = 4;
548 break;
549 case V_028010_DEPTH_X24_8_32_FLOAT:
550 bpe = 8;
551 break;
552 default:
553 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
554 return -EINVAL;
555 }
556 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
557 if (!track->db_depth_size_idx) {
558 dev_warn(p->dev, "z/stencil buffer size not set\n");
559 return -EINVAL;
560 }
561 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
562 tmp = (tmp / bpe) >> 6;
563 if (!tmp) {
564 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
565 track->db_depth_size, bpe, track->db_offset,
566 radeon_bo_size(track->db_bo));
567 return -EINVAL;
568 }
569 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
570 } else {
571 /* pitch in pixels */
572 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
573 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
574 slice_tile_max *= 64;
575 height = slice_tile_max / pitch;
576 if (height > 8192)
577 height = 8192;
578 base_offset = track->db_bo_mc + track->db_offset;
579 array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
580 array_check.array_mode = array_mode;
581 array_check.group_size = track->group_size;
582 array_check.nbanks = track->nbanks;
583 array_check.npipes = track->npipes;
584 array_check.nsamples = track->nsamples;
585 array_check.blocksize = bpe;
586 if (r600_get_array_mode_alignment(&array_check,
587 &pitch_align, &height_align, &depth_align, &base_align)) {
588 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
589 G_028010_ARRAY_MODE(track->db_depth_info),
590 track->db_depth_info);
591 return -EINVAL;
592 }
593 switch (array_mode) {
594 case V_028010_ARRAY_1D_TILED_THIN1:
595 /* don't break userspace */
596 height &= ~0x7;
597 break;
598 case V_028010_ARRAY_2D_TILED_THIN1:
599 break;
600 default:
601 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
602 G_028010_ARRAY_MODE(track->db_depth_info),
603 track->db_depth_info);
604 return -EINVAL;
605 }
606
607 if (!IS_ALIGNED(pitch, pitch_align)) {
608 dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n",
609 __func__, __LINE__, pitch, pitch_align, array_mode);
610 return -EINVAL;
611 }
612 if (!IS_ALIGNED(height, height_align)) {
613 dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n",
614 __func__, __LINE__, height, height_align, array_mode);
615 return -EINVAL;
616 }
617 if (!IS_ALIGNED(base_offset, base_align)) {
618 dev_warn(p->dev, "%s offset 0x%"PRIx64", 0x%"PRIx64", %d not aligned\n", __func__,
619 base_offset, base_align, array_mode);
620 return -EINVAL;
621 }
622
623 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
624 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
625 tmp = ntiles * bpe * 64 * nviews * track->nsamples;
626 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
627 dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",
628 array_mode,
629 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
630 radeon_bo_size(track->db_bo));
631 return -EINVAL;
632 }
633 }
634
635 /* hyperz */
636 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
637 unsigned long size;
638 unsigned nbx, nby;
639
640 if (track->htile_bo == NULL) {
641 dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n",
642 __func__, __LINE__, track->db_depth_info);
643 return -EINVAL;
644 }
645 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
646 dev_warn(p->dev, "%s:%d htile can't be enabled with bogus db_depth_size 0x%08x\n",
647 __func__, __LINE__, track->db_depth_size);
648 return -EINVAL;
649 }
650
651 nbx = pitch;
652 nby = height;
653 if (G_028D24_LINEAR(track->htile_surface)) {
654 /* nbx must be 16 htiles aligned == 16 * 8 pixel aligned */
655 nbx = round_up(nbx, 16 * 8);
656 /* nby is npipes htiles aligned == npipes * 8 pixel aligned */
657 nby = round_up(nby, track->npipes * 8);
658 } else {
659 /* always assume 8x8 htile */
660 /* align is htile align * 8, htile align vary according to
661 * number of pipe and tile width and nby
662 */
663 switch (track->npipes) {
664 case 8:
665 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
666 nbx = round_up(nbx, 64 * 8);
667 nby = round_up(nby, 64 * 8);
668 break;
669 case 4:
670 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
671 nbx = round_up(nbx, 64 * 8);
672 nby = round_up(nby, 32 * 8);
673 break;
674 case 2:
675 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
676 nbx = round_up(nbx, 32 * 8);
677 nby = round_up(nby, 32 * 8);
678 break;
679 case 1:
680 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
681 nbx = round_up(nbx, 32 * 8);
682 nby = round_up(nby, 16 * 8);
683 break;
684 default:
685 dev_warn(p->dev, "%s:%d invalid num pipes %d\n",
686 __func__, __LINE__, track->npipes);
687 return -EINVAL;
688 }
689 }
690 /* compute number of htile */
691 nbx = nbx >> 3;
692 nby = nby >> 3;
693 /* size must be aligned on npipes * 2K boundary */
694 size = roundup(nbx * nby * 4, track->npipes * (2 << 10));
695 size += track->htile_offset;
696
697 if (size > radeon_bo_size(track->htile_bo)) {
698 dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n",
699 __func__, __LINE__, radeon_bo_size(track->htile_bo),
700 size, nbx, nby);
701 return -EINVAL;
702 }
703 }
704
705 track->db_dirty = false;
706 return 0;
707 }
708
r600_cs_track_check(struct radeon_cs_parser * p)709 static int r600_cs_track_check(struct radeon_cs_parser *p)
710 {
711 struct r600_cs_track *track = p->track;
712 u32 tmp;
713 int r, i;
714
715 /* on legacy kernel we don't perform advanced check */
716 if (p->rdev == NULL)
717 return 0;
718
719 /* check streamout */
720 if (track->streamout_dirty && track->vgt_strmout_en) {
721 for (i = 0; i < 4; i++) {
722 if (track->vgt_strmout_buffer_en & (1 << i)) {
723 if (track->vgt_strmout_bo[i]) {
724 u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
725 (u64)track->vgt_strmout_size[i];
726 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
727 DRM_ERROR("streamout %d bo too small: 0x%"PRIx64", 0x%lx\n",
728 i, offset,
729 radeon_bo_size(track->vgt_strmout_bo[i]));
730 return -EINVAL;
731 }
732 } else {
733 dev_warn(p->dev, "No buffer for streamout %d\n", i);
734 return -EINVAL;
735 }
736 }
737 }
738 track->streamout_dirty = false;
739 }
740
741 if (track->sx_misc_kill_all_prims)
742 return 0;
743
744 /* check that we have a cb for each enabled target, we don't check
745 * shader_mask because it seems mesa isn't always setting it :(
746 */
747 if (track->cb_dirty) {
748 tmp = track->cb_target_mask;
749
750 /* We must check both colorbuffers for RESOLVE. */
751 if (track->is_resolve) {
752 tmp |= 0xff;
753 }
754
755 for (i = 0; i < 8; i++) {
756 u32 format = G_0280A0_FORMAT(track->cb_color_info[i]);
757
758 if (format != V_0280A0_COLOR_INVALID &&
759 (tmp >> (i * 4)) & 0xF) {
760 /* at least one component is enabled */
761 if (track->cb_color_bo[i] == NULL) {
762 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
763 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
764 return -EINVAL;
765 }
766 /* perform rewrite of CB_COLOR[0-7]_SIZE */
767 r = r600_cs_track_validate_cb(p, i);
768 if (r)
769 return r;
770 }
771 }
772 track->cb_dirty = false;
773 }
774
775 /* Check depth buffer */
776 if (track->db_dirty &&
777 G_028010_FORMAT(track->db_depth_info) != V_028010_DEPTH_INVALID &&
778 (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
779 G_028800_Z_ENABLE(track->db_depth_control))) {
780 r = r600_cs_track_validate_db(p);
781 if (r)
782 return r;
783 }
784
785 return 0;
786 }
787
788 /**
789 * r600_cs_packet_parse_vline() - parse userspace VLINE packet
790 * @parser: parser structure holding parsing context.
791 *
792 * This is an R600-specific function for parsing VLINE packets.
793 * Real work is done by r600_cs_common_vline_parse function.
794 * Here we just set up ASIC-specific register table and call
795 * the common implementation function.
796 */
r600_cs_packet_parse_vline(struct radeon_cs_parser * p)797 static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
798 {
799 static uint32_t vline_start_end[2] = {AVIVO_D1MODE_VLINE_START_END,
800 AVIVO_D2MODE_VLINE_START_END};
801 static uint32_t vline_status[2] = {AVIVO_D1MODE_VLINE_STATUS,
802 AVIVO_D2MODE_VLINE_STATUS};
803
804 return r600_cs_common_vline_parse(p, vline_start_end, vline_status);
805 }
806
807 /**
808 * r600_cs_common_vline_parse() - common vline parser
809 * @parser: parser structure holding parsing context.
810 * @vline_start_end: table of vline_start_end registers
811 * @vline_status: table of vline_status registers
812 *
813 * Userspace sends a special sequence for VLINE waits.
814 * PACKET0 - VLINE_START_END + value
815 * PACKET3 - WAIT_REG_MEM poll vline status reg
816 * RELOC (P3) - crtc_id in reloc.
817 *
818 * This function parses this and relocates the VLINE START END
819 * and WAIT_REG_MEM packets to the correct crtc.
820 * It also detects a switched off crtc and nulls out the
821 * wait in that case. This function is common for all ASICs that
822 * are R600 and newer. The parsing algorithm is the same, and only
823 * differs in which registers are used.
824 *
825 * Caller is the ASIC-specific function which passes the parser
826 * context and ASIC-specific register table
827 */
r600_cs_common_vline_parse(struct radeon_cs_parser * p,uint32_t * vline_start_end,uint32_t * vline_status)828 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
829 uint32_t *vline_start_end,
830 uint32_t *vline_status)
831 {
832 struct drm_crtc *crtc;
833 struct radeon_crtc *radeon_crtc;
834 struct radeon_cs_packet p3reloc, wait_reg_mem;
835 int crtc_id;
836 int r;
837 uint32_t header, h_idx, reg, wait_reg_mem_info;
838 volatile uint32_t *ib;
839
840 ib = p->ib.ptr;
841
842 /* parse the WAIT_REG_MEM */
843 r = radeon_cs_packet_parse(p, &wait_reg_mem, p->idx);
844 if (r)
845 return r;
846
847 /* check its a WAIT_REG_MEM */
848 if (wait_reg_mem.type != RADEON_PACKET_TYPE3 ||
849 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
850 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
851 return -EINVAL;
852 }
853
854 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
855 /* bit 4 is reg (0) or mem (1) */
856 if (wait_reg_mem_info & 0x10) {
857 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM instead of REG\n");
858 return -EINVAL;
859 }
860 /* bit 8 is me (0) or pfp (1) */
861 if (wait_reg_mem_info & 0x100) {
862 DRM_ERROR("vline WAIT_REG_MEM waiting on PFP instead of ME\n");
863 return -EINVAL;
864 }
865 /* waiting for value to be equal */
866 if ((wait_reg_mem_info & 0x7) != 0x3) {
867 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
868 return -EINVAL;
869 }
870 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != vline_status[0]) {
871 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
872 return -EINVAL;
873 }
874
875 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != RADEON_VLINE_STAT) {
876 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
877 return -EINVAL;
878 }
879
880 /* jump over the NOP */
881 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
882 if (r)
883 return r;
884
885 h_idx = p->idx - 2;
886 p->idx += wait_reg_mem.count + 2;
887 p->idx += p3reloc.count + 2;
888
889 header = radeon_get_ib_value(p, h_idx);
890 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
891 reg = R600_CP_PACKET0_GET_REG(header);
892
893 crtc = drm_crtc_find(p->rdev->ddev, p->filp, crtc_id);
894 if (!crtc) {
895 DRM_ERROR("cannot find crtc %d\n", crtc_id);
896 return -ENOENT;
897 }
898 radeon_crtc = to_radeon_crtc(crtc);
899 crtc_id = radeon_crtc->crtc_id;
900
901 if (!crtc->enabled) {
902 /* CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
903 ib[h_idx + 2] = PACKET2(0);
904 ib[h_idx + 3] = PACKET2(0);
905 ib[h_idx + 4] = PACKET2(0);
906 ib[h_idx + 5] = PACKET2(0);
907 ib[h_idx + 6] = PACKET2(0);
908 ib[h_idx + 7] = PACKET2(0);
909 ib[h_idx + 8] = PACKET2(0);
910 } else if (reg == vline_start_end[0]) {
911 header &= ~R600_CP_PACKET0_REG_MASK;
912 header |= vline_start_end[crtc_id] >> 2;
913 ib[h_idx] = header;
914 ib[h_idx + 4] = vline_status[crtc_id] >> 2;
915 } else {
916 DRM_ERROR("unknown crtc reloc\n");
917 return -EINVAL;
918 }
919 return 0;
920 }
921
r600_packet0_check(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt,unsigned idx,unsigned reg)922 static int r600_packet0_check(struct radeon_cs_parser *p,
923 struct radeon_cs_packet *pkt,
924 unsigned idx, unsigned reg)
925 {
926 int r;
927
928 switch (reg) {
929 case AVIVO_D1MODE_VLINE_START_END:
930 r = r600_cs_packet_parse_vline(p);
931 if (r) {
932 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
933 idx, reg);
934 return r;
935 }
936 break;
937 default:
938 pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx);
939 return -EINVAL;
940 }
941 return 0;
942 }
943
r600_cs_parse_packet0(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt)944 static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
945 struct radeon_cs_packet *pkt)
946 {
947 unsigned reg, i;
948 unsigned idx;
949 int r;
950
951 idx = pkt->idx + 1;
952 reg = pkt->reg;
953 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
954 r = r600_packet0_check(p, pkt, idx, reg);
955 if (r) {
956 return r;
957 }
958 }
959 return 0;
960 }
961
962 /**
963 * r600_cs_check_reg() - check if register is authorized or not
964 * @parser: parser structure holding parsing context
965 * @reg: register we are testing
966 * @idx: index into the cs buffer
967 *
968 * This function will test against r600_reg_safe_bm and return 0
969 * if register is safe. If register is not flag as safe this function
970 * will test it against a list of register needind special handling.
971 */
r600_cs_check_reg(struct radeon_cs_parser * p,u32 reg,u32 idx)972 static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
973 {
974 struct r600_cs_track *track = (struct r600_cs_track *)p->track;
975 struct radeon_bo_list *reloc;
976 u32 m, i, tmp, *ib;
977 int r;
978
979 i = (reg >> 7);
980 if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
981 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
982 return -EINVAL;
983 }
984 m = 1 << ((reg >> 2) & 31);
985 if (!(r600_reg_safe_bm[i] & m))
986 return 0;
987 ib = p->ib.ptr;
988 switch (reg) {
989 /* force following reg to 0 in an attempt to disable out buffer
990 * which will need us to better understand how it works to perform
991 * security check on it (Jerome)
992 */
993 case R_0288A8_SQ_ESGS_RING_ITEMSIZE:
994 case R_008C44_SQ_ESGS_RING_SIZE:
995 case R_0288B0_SQ_ESTMP_RING_ITEMSIZE:
996 case R_008C54_SQ_ESTMP_RING_SIZE:
997 case R_0288C0_SQ_FBUF_RING_ITEMSIZE:
998 case R_008C74_SQ_FBUF_RING_SIZE:
999 case R_0288B4_SQ_GSTMP_RING_ITEMSIZE:
1000 case R_008C5C_SQ_GSTMP_RING_SIZE:
1001 case R_0288AC_SQ_GSVS_RING_ITEMSIZE:
1002 case R_008C4C_SQ_GSVS_RING_SIZE:
1003 case R_0288BC_SQ_PSTMP_RING_ITEMSIZE:
1004 case R_008C6C_SQ_PSTMP_RING_SIZE:
1005 case R_0288C4_SQ_REDUC_RING_ITEMSIZE:
1006 case R_008C7C_SQ_REDUC_RING_SIZE:
1007 case R_0288B8_SQ_VSTMP_RING_ITEMSIZE:
1008 case R_008C64_SQ_VSTMP_RING_SIZE:
1009 case R_0288C8_SQ_GS_VERT_ITEMSIZE:
1010 /* get value to populate the IB don't remove */
1011 /*tmp =radeon_get_ib_value(p, idx);
1012 ib[idx] = 0;*/
1013 break;
1014 case SQ_ESGS_RING_BASE:
1015 case SQ_GSVS_RING_BASE:
1016 case SQ_ESTMP_RING_BASE:
1017 case SQ_GSTMP_RING_BASE:
1018 case SQ_PSTMP_RING_BASE:
1019 case SQ_VSTMP_RING_BASE:
1020 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1021 if (r) {
1022 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1023 "0x%04X\n", reg);
1024 return -EINVAL;
1025 }
1026 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1027 break;
1028 case SQ_CONFIG:
1029 track->sq_config = radeon_get_ib_value(p, idx);
1030 break;
1031 case R_028800_DB_DEPTH_CONTROL:
1032 track->db_depth_control = radeon_get_ib_value(p, idx);
1033 track->db_dirty = true;
1034 break;
1035 case R_028010_DB_DEPTH_INFO:
1036 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
1037 radeon_cs_packet_next_is_pkt3_nop(p)) {
1038 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1039 if (r) {
1040 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1041 "0x%04X\n", reg);
1042 return -EINVAL;
1043 }
1044 track->db_depth_info = radeon_get_ib_value(p, idx);
1045 ib[idx] &= C_028010_ARRAY_MODE;
1046 track->db_depth_info &= C_028010_ARRAY_MODE;
1047 if (reloc->tiling_flags & RADEON_TILING_MACRO) {
1048 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
1049 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
1050 } else {
1051 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1052 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1053 }
1054 } else {
1055 track->db_depth_info = radeon_get_ib_value(p, idx);
1056 }
1057 track->db_dirty = true;
1058 break;
1059 case R_028004_DB_DEPTH_VIEW:
1060 track->db_depth_view = radeon_get_ib_value(p, idx);
1061 track->db_dirty = true;
1062 break;
1063 case R_028000_DB_DEPTH_SIZE:
1064 track->db_depth_size = radeon_get_ib_value(p, idx);
1065 track->db_depth_size_idx = idx;
1066 track->db_dirty = true;
1067 break;
1068 case R_028AB0_VGT_STRMOUT_EN:
1069 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
1070 track->streamout_dirty = true;
1071 break;
1072 case R_028B20_VGT_STRMOUT_BUFFER_EN:
1073 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
1074 track->streamout_dirty = true;
1075 break;
1076 case VGT_STRMOUT_BUFFER_BASE_0:
1077 case VGT_STRMOUT_BUFFER_BASE_1:
1078 case VGT_STRMOUT_BUFFER_BASE_2:
1079 case VGT_STRMOUT_BUFFER_BASE_3:
1080 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1081 if (r) {
1082 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1083 "0x%04X\n", reg);
1084 return -EINVAL;
1085 }
1086 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
1087 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1088 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1089 track->vgt_strmout_bo[tmp] = reloc->robj;
1090 track->vgt_strmout_bo_mc[tmp] = reloc->gpu_offset;
1091 track->streamout_dirty = true;
1092 break;
1093 case VGT_STRMOUT_BUFFER_SIZE_0:
1094 case VGT_STRMOUT_BUFFER_SIZE_1:
1095 case VGT_STRMOUT_BUFFER_SIZE_2:
1096 case VGT_STRMOUT_BUFFER_SIZE_3:
1097 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
1098 /* size in register is DWs, convert to bytes */
1099 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
1100 track->streamout_dirty = true;
1101 break;
1102 case CP_COHER_BASE:
1103 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1104 if (r) {
1105 dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
1106 "0x%04X\n", reg);
1107 return -EINVAL;
1108 }
1109 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1110 break;
1111 case R_028238_CB_TARGET_MASK:
1112 track->cb_target_mask = radeon_get_ib_value(p, idx);
1113 track->cb_dirty = true;
1114 break;
1115 case R_02823C_CB_SHADER_MASK:
1116 track->cb_shader_mask = radeon_get_ib_value(p, idx);
1117 break;
1118 case R_028C04_PA_SC_AA_CONFIG:
1119 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
1120 track->log_nsamples = tmp;
1121 track->nsamples = 1 << tmp;
1122 track->cb_dirty = true;
1123 break;
1124 case R_028808_CB_COLOR_CONTROL:
1125 tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx));
1126 track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX;
1127 track->cb_dirty = true;
1128 break;
1129 case R_0280A0_CB_COLOR0_INFO:
1130 case R_0280A4_CB_COLOR1_INFO:
1131 case R_0280A8_CB_COLOR2_INFO:
1132 case R_0280AC_CB_COLOR3_INFO:
1133 case R_0280B0_CB_COLOR4_INFO:
1134 case R_0280B4_CB_COLOR5_INFO:
1135 case R_0280B8_CB_COLOR6_INFO:
1136 case R_0280BC_CB_COLOR7_INFO:
1137 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
1138 radeon_cs_packet_next_is_pkt3_nop(p)) {
1139 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1140 if (r) {
1141 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1142 return -EINVAL;
1143 }
1144 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1145 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1146 if (reloc->tiling_flags & RADEON_TILING_MACRO) {
1147 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1148 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1149 } else if (reloc->tiling_flags & RADEON_TILING_MICRO) {
1150 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1151 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1152 }
1153 } else {
1154 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1155 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1156 }
1157 track->cb_dirty = true;
1158 break;
1159 case R_028080_CB_COLOR0_VIEW:
1160 case R_028084_CB_COLOR1_VIEW:
1161 case R_028088_CB_COLOR2_VIEW:
1162 case R_02808C_CB_COLOR3_VIEW:
1163 case R_028090_CB_COLOR4_VIEW:
1164 case R_028094_CB_COLOR5_VIEW:
1165 case R_028098_CB_COLOR6_VIEW:
1166 case R_02809C_CB_COLOR7_VIEW:
1167 tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4;
1168 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1169 track->cb_dirty = true;
1170 break;
1171 case R_028060_CB_COLOR0_SIZE:
1172 case R_028064_CB_COLOR1_SIZE:
1173 case R_028068_CB_COLOR2_SIZE:
1174 case R_02806C_CB_COLOR3_SIZE:
1175 case R_028070_CB_COLOR4_SIZE:
1176 case R_028074_CB_COLOR5_SIZE:
1177 case R_028078_CB_COLOR6_SIZE:
1178 case R_02807C_CB_COLOR7_SIZE:
1179 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
1180 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
1181 track->cb_color_size_idx[tmp] = idx;
1182 track->cb_dirty = true;
1183 break;
1184 /* This register were added late, there is userspace
1185 * which does provide relocation for those but set
1186 * 0 offset. In order to avoid breaking old userspace
1187 * we detect this and set address to point to last
1188 * CB_COLOR0_BASE, note that if userspace doesn't set
1189 * CB_COLOR0_BASE before this register we will report
1190 * error. Old userspace always set CB_COLOR0_BASE
1191 * before any of this.
1192 */
1193 case R_0280E0_CB_COLOR0_FRAG:
1194 case R_0280E4_CB_COLOR1_FRAG:
1195 case R_0280E8_CB_COLOR2_FRAG:
1196 case R_0280EC_CB_COLOR3_FRAG:
1197 case R_0280F0_CB_COLOR4_FRAG:
1198 case R_0280F4_CB_COLOR5_FRAG:
1199 case R_0280F8_CB_COLOR6_FRAG:
1200 case R_0280FC_CB_COLOR7_FRAG:
1201 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
1202 if (!radeon_cs_packet_next_is_pkt3_nop(p)) {
1203 if (!track->cb_color_base_last[tmp]) {
1204 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1205 return -EINVAL;
1206 }
1207 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
1208 track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp];
1209 ib[idx] = track->cb_color_base_last[tmp];
1210 } else {
1211 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1212 if (r) {
1213 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1214 return -EINVAL;
1215 }
1216 track->cb_color_frag_bo[tmp] = reloc->robj;
1217 track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8;
1218 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1219 }
1220 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1221 track->cb_dirty = true;
1222 }
1223 break;
1224 case R_0280C0_CB_COLOR0_TILE:
1225 case R_0280C4_CB_COLOR1_TILE:
1226 case R_0280C8_CB_COLOR2_TILE:
1227 case R_0280CC_CB_COLOR3_TILE:
1228 case R_0280D0_CB_COLOR4_TILE:
1229 case R_0280D4_CB_COLOR5_TILE:
1230 case R_0280D8_CB_COLOR6_TILE:
1231 case R_0280DC_CB_COLOR7_TILE:
1232 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
1233 if (!radeon_cs_packet_next_is_pkt3_nop(p)) {
1234 if (!track->cb_color_base_last[tmp]) {
1235 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1236 return -EINVAL;
1237 }
1238 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
1239 track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp];
1240 ib[idx] = track->cb_color_base_last[tmp];
1241 } else {
1242 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1243 if (r) {
1244 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1245 return -EINVAL;
1246 }
1247 track->cb_color_tile_bo[tmp] = reloc->robj;
1248 track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8;
1249 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1250 }
1251 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1252 track->cb_dirty = true;
1253 }
1254 break;
1255 case R_028100_CB_COLOR0_MASK:
1256 case R_028104_CB_COLOR1_MASK:
1257 case R_028108_CB_COLOR2_MASK:
1258 case R_02810C_CB_COLOR3_MASK:
1259 case R_028110_CB_COLOR4_MASK:
1260 case R_028114_CB_COLOR5_MASK:
1261 case R_028118_CB_COLOR6_MASK:
1262 case R_02811C_CB_COLOR7_MASK:
1263 tmp = (reg - R_028100_CB_COLOR0_MASK) / 4;
1264 track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx);
1265 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1266 track->cb_dirty = true;
1267 }
1268 break;
1269 case CB_COLOR0_BASE:
1270 case CB_COLOR1_BASE:
1271 case CB_COLOR2_BASE:
1272 case CB_COLOR3_BASE:
1273 case CB_COLOR4_BASE:
1274 case CB_COLOR5_BASE:
1275 case CB_COLOR6_BASE:
1276 case CB_COLOR7_BASE:
1277 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1278 if (r) {
1279 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1280 "0x%04X\n", reg);
1281 return -EINVAL;
1282 }
1283 tmp = (reg - CB_COLOR0_BASE) / 4;
1284 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1285 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1286 track->cb_color_base_last[tmp] = ib[idx];
1287 track->cb_color_bo[tmp] = reloc->robj;
1288 track->cb_color_bo_mc[tmp] = reloc->gpu_offset;
1289 track->cb_dirty = true;
1290 break;
1291 case DB_DEPTH_BASE:
1292 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1293 if (r) {
1294 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1295 "0x%04X\n", reg);
1296 return -EINVAL;
1297 }
1298 track->db_offset = radeon_get_ib_value(p, idx) << 8;
1299 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1300 track->db_bo = reloc->robj;
1301 track->db_bo_mc = reloc->gpu_offset;
1302 track->db_dirty = true;
1303 break;
1304 case DB_HTILE_DATA_BASE:
1305 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1306 if (r) {
1307 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1308 "0x%04X\n", reg);
1309 return -EINVAL;
1310 }
1311 track->htile_offset = radeon_get_ib_value(p, idx) << 8;
1312 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1313 track->htile_bo = reloc->robj;
1314 track->db_dirty = true;
1315 break;
1316 case DB_HTILE_SURFACE:
1317 track->htile_surface = radeon_get_ib_value(p, idx);
1318 /* force 8x8 htile width and height */
1319 ib[idx] |= 3;
1320 track->db_dirty = true;
1321 break;
1322 case SQ_PGM_START_FS:
1323 case SQ_PGM_START_ES:
1324 case SQ_PGM_START_VS:
1325 case SQ_PGM_START_GS:
1326 case SQ_PGM_START_PS:
1327 case SQ_ALU_CONST_CACHE_GS_0:
1328 case SQ_ALU_CONST_CACHE_GS_1:
1329 case SQ_ALU_CONST_CACHE_GS_2:
1330 case SQ_ALU_CONST_CACHE_GS_3:
1331 case SQ_ALU_CONST_CACHE_GS_4:
1332 case SQ_ALU_CONST_CACHE_GS_5:
1333 case SQ_ALU_CONST_CACHE_GS_6:
1334 case SQ_ALU_CONST_CACHE_GS_7:
1335 case SQ_ALU_CONST_CACHE_GS_8:
1336 case SQ_ALU_CONST_CACHE_GS_9:
1337 case SQ_ALU_CONST_CACHE_GS_10:
1338 case SQ_ALU_CONST_CACHE_GS_11:
1339 case SQ_ALU_CONST_CACHE_GS_12:
1340 case SQ_ALU_CONST_CACHE_GS_13:
1341 case SQ_ALU_CONST_CACHE_GS_14:
1342 case SQ_ALU_CONST_CACHE_GS_15:
1343 case SQ_ALU_CONST_CACHE_PS_0:
1344 case SQ_ALU_CONST_CACHE_PS_1:
1345 case SQ_ALU_CONST_CACHE_PS_2:
1346 case SQ_ALU_CONST_CACHE_PS_3:
1347 case SQ_ALU_CONST_CACHE_PS_4:
1348 case SQ_ALU_CONST_CACHE_PS_5:
1349 case SQ_ALU_CONST_CACHE_PS_6:
1350 case SQ_ALU_CONST_CACHE_PS_7:
1351 case SQ_ALU_CONST_CACHE_PS_8:
1352 case SQ_ALU_CONST_CACHE_PS_9:
1353 case SQ_ALU_CONST_CACHE_PS_10:
1354 case SQ_ALU_CONST_CACHE_PS_11:
1355 case SQ_ALU_CONST_CACHE_PS_12:
1356 case SQ_ALU_CONST_CACHE_PS_13:
1357 case SQ_ALU_CONST_CACHE_PS_14:
1358 case SQ_ALU_CONST_CACHE_PS_15:
1359 case SQ_ALU_CONST_CACHE_VS_0:
1360 case SQ_ALU_CONST_CACHE_VS_1:
1361 case SQ_ALU_CONST_CACHE_VS_2:
1362 case SQ_ALU_CONST_CACHE_VS_3:
1363 case SQ_ALU_CONST_CACHE_VS_4:
1364 case SQ_ALU_CONST_CACHE_VS_5:
1365 case SQ_ALU_CONST_CACHE_VS_6:
1366 case SQ_ALU_CONST_CACHE_VS_7:
1367 case SQ_ALU_CONST_CACHE_VS_8:
1368 case SQ_ALU_CONST_CACHE_VS_9:
1369 case SQ_ALU_CONST_CACHE_VS_10:
1370 case SQ_ALU_CONST_CACHE_VS_11:
1371 case SQ_ALU_CONST_CACHE_VS_12:
1372 case SQ_ALU_CONST_CACHE_VS_13:
1373 case SQ_ALU_CONST_CACHE_VS_14:
1374 case SQ_ALU_CONST_CACHE_VS_15:
1375 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1376 if (r) {
1377 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1378 "0x%04X\n", reg);
1379 return -EINVAL;
1380 }
1381 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1382 break;
1383 case SX_MEMORY_EXPORT_BASE:
1384 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1385 if (r) {
1386 dev_warn(p->dev, "bad SET_CONFIG_REG "
1387 "0x%04X\n", reg);
1388 return -EINVAL;
1389 }
1390 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1391 break;
1392 case SX_MISC:
1393 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
1394 break;
1395 default:
1396 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1397 return -EINVAL;
1398 }
1399 return 0;
1400 }
1401
r600_mip_minify(unsigned size,unsigned level)1402 unsigned r600_mip_minify(unsigned size, unsigned level)
1403 {
1404 unsigned val;
1405
1406 val = max(1U, size >> level);
1407 if (level > 0)
1408 val = roundup_pow_of_two(val);
1409 return val;
1410 }
1411
r600_texture_size(unsigned nfaces,unsigned blevel,unsigned llevel,unsigned w0,unsigned h0,unsigned d0,unsigned nsamples,unsigned format,unsigned block_align,unsigned height_align,unsigned base_align,unsigned * l0_size,unsigned * mipmap_size)1412 static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
1413 unsigned w0, unsigned h0, unsigned d0, unsigned nsamples, unsigned format,
1414 unsigned block_align, unsigned height_align, unsigned base_align,
1415 unsigned *l0_size, unsigned *mipmap_size)
1416 {
1417 unsigned offset, i, level;
1418 unsigned width, height, depth, size;
1419 unsigned blocksize;
1420 unsigned nbx, nby;
1421 unsigned nlevels = llevel - blevel + 1;
1422
1423 *l0_size = -1;
1424 blocksize = r600_fmt_get_blocksize(format);
1425
1426 w0 = r600_mip_minify(w0, 0);
1427 h0 = r600_mip_minify(h0, 0);
1428 d0 = r600_mip_minify(d0, 0);
1429 for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
1430 width = r600_mip_minify(w0, i);
1431 nbx = r600_fmt_get_nblocksx(format, width);
1432
1433 nbx = round_up(nbx, block_align);
1434
1435 height = r600_mip_minify(h0, i);
1436 nby = r600_fmt_get_nblocksy(format, height);
1437 nby = round_up(nby, height_align);
1438
1439 depth = r600_mip_minify(d0, i);
1440
1441 size = nbx * nby * blocksize * nsamples;
1442 if (nfaces)
1443 size *= nfaces;
1444 else
1445 size *= depth;
1446
1447 if (i == 0)
1448 *l0_size = size;
1449
1450 if (i == 0 || i == 1)
1451 offset = round_up(offset, base_align);
1452
1453 offset += size;
1454 }
1455 *mipmap_size = offset;
1456 if (llevel == 0)
1457 *mipmap_size = *l0_size;
1458 if (!blevel)
1459 *mipmap_size -= *l0_size;
1460 }
1461
1462 /**
1463 * r600_check_texture_resource() - check if register is authorized or not
1464 * @p: parser structure holding parsing context
1465 * @idx: index into the cs buffer
1466 * @texture: texture's bo structure
1467 * @mipmap: mipmap's bo structure
1468 *
1469 * This function will check that the resource has valid field and that
1470 * the texture and mipmap bo object are big enough to cover this resource.
1471 */
r600_check_texture_resource(struct radeon_cs_parser * p,u32 idx,struct radeon_bo * texture,struct radeon_bo * mipmap,u64 base_offset,u64 mip_offset,u32 tiling_flags)1472 static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
1473 struct radeon_bo *texture,
1474 struct radeon_bo *mipmap,
1475 u64 base_offset,
1476 u64 mip_offset,
1477 u32 tiling_flags)
1478 {
1479 struct r600_cs_track *track = p->track;
1480 u32 dim, nfaces, llevel, blevel, w0, h0, d0;
1481 u32 word0, word1, l0_size, mipmap_size, word2, word3, word4, word5;
1482 u32 height_align, pitch, pitch_align, depth_align;
1483 u32 barray, larray;
1484 u64 base_align;
1485 struct array_mode_checker array_check;
1486 u32 format;
1487 bool is_array;
1488
1489 /* on legacy kernel we don't perform advanced check */
1490 if (p->rdev == NULL)
1491 return 0;
1492
1493 /* convert to bytes */
1494 base_offset <<= 8;
1495 mip_offset <<= 8;
1496
1497 word0 = radeon_get_ib_value(p, idx + 0);
1498 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1499 if (tiling_flags & RADEON_TILING_MACRO)
1500 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1501 else if (tiling_flags & RADEON_TILING_MICRO)
1502 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1503 }
1504 word1 = radeon_get_ib_value(p, idx + 1);
1505 word2 = radeon_get_ib_value(p, idx + 2) << 8;
1506 word3 = radeon_get_ib_value(p, idx + 3) << 8;
1507 word4 = radeon_get_ib_value(p, idx + 4);
1508 word5 = radeon_get_ib_value(p, idx + 5);
1509 dim = G_038000_DIM(word0);
1510 w0 = G_038000_TEX_WIDTH(word0) + 1;
1511 pitch = (G_038000_PITCH(word0) + 1) * 8;
1512 h0 = G_038004_TEX_HEIGHT(word1) + 1;
1513 d0 = G_038004_TEX_DEPTH(word1);
1514 format = G_038004_DATA_FORMAT(word1);
1515 blevel = G_038010_BASE_LEVEL(word4);
1516 llevel = G_038014_LAST_LEVEL(word5);
1517 /* pitch in texels */
1518 array_check.array_mode = G_038000_TILE_MODE(word0);
1519 array_check.group_size = track->group_size;
1520 array_check.nbanks = track->nbanks;
1521 array_check.npipes = track->npipes;
1522 array_check.nsamples = 1;
1523 array_check.blocksize = r600_fmt_get_blocksize(format);
1524 nfaces = 1;
1525 is_array = false;
1526 switch (dim) {
1527 case V_038000_SQ_TEX_DIM_1D:
1528 case V_038000_SQ_TEX_DIM_2D:
1529 case V_038000_SQ_TEX_DIM_3D:
1530 break;
1531 case V_038000_SQ_TEX_DIM_CUBEMAP:
1532 if (p->family >= CHIP_RV770)
1533 nfaces = 8;
1534 else
1535 nfaces = 6;
1536 break;
1537 case V_038000_SQ_TEX_DIM_1D_ARRAY:
1538 case V_038000_SQ_TEX_DIM_2D_ARRAY:
1539 is_array = true;
1540 break;
1541 case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
1542 is_array = true;
1543 /* fall through */
1544 case V_038000_SQ_TEX_DIM_2D_MSAA:
1545 array_check.nsamples = 1 << llevel;
1546 llevel = 0;
1547 break;
1548 default:
1549 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
1550 return -EINVAL;
1551 }
1552 if (!r600_fmt_is_valid_texture(format, p->family)) {
1553 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
1554 __func__, __LINE__, format);
1555 return -EINVAL;
1556 }
1557
1558 if (r600_get_array_mode_alignment(&array_check,
1559 &pitch_align, &height_align, &depth_align, &base_align)) {
1560 dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n",
1561 __func__, __LINE__, G_038000_TILE_MODE(word0));
1562 return -EINVAL;
1563 }
1564
1565 /* XXX check height as well... */
1566
1567 if (!IS_ALIGNED(pitch, pitch_align)) {
1568 dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n",
1569 __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0));
1570 return -EINVAL;
1571 }
1572 if (!IS_ALIGNED(base_offset, base_align)) {
1573 dev_warn(p->dev, "%s:%d tex base offset (0x%"PRIx64", 0x%"PRIx64", %d) invalid\n",
1574 __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0));
1575 return -EINVAL;
1576 }
1577 if (!IS_ALIGNED(mip_offset, base_align)) {
1578 dev_warn(p->dev, "%s:%d tex mip offset (0x%"PRIx64", 0x%"PRIx64", %d) invalid\n",
1579 __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0));
1580 return -EINVAL;
1581 }
1582
1583 if (blevel > llevel) {
1584 dev_warn(p->dev, "texture blevel %d > llevel %d\n",
1585 blevel, llevel);
1586 }
1587 if (is_array) {
1588 barray = G_038014_BASE_ARRAY(word5);
1589 larray = G_038014_LAST_ARRAY(word5);
1590
1591 nfaces = larray - barray + 1;
1592 }
1593 r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, array_check.nsamples, format,
1594 pitch_align, height_align, base_align,
1595 &l0_size, &mipmap_size);
1596 /* using get ib will give us the offset into the texture bo */
1597 if ((l0_size + word2) > radeon_bo_size(texture)) {
1598 dev_warn(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n",
1599 w0, h0, pitch_align, height_align,
1600 array_check.array_mode, format, word2,
1601 l0_size, radeon_bo_size(texture));
1602 dev_warn(p->dev, "alignments %d %d %d %"PRIu64"\n", pitch, pitch_align, height_align, base_align);
1603 return -EINVAL;
1604 }
1605 /* using get ib will give us the offset into the mipmap bo */
1606 if ((mipmap_size + word3) > radeon_bo_size(mipmap)) {
1607 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
1608 w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/
1609 }
1610 return 0;
1611 }
1612
r600_is_safe_reg(struct radeon_cs_parser * p,u32 reg,u32 idx)1613 static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1614 {
1615 u32 m, i;
1616
1617 i = (reg >> 7);
1618 if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
1619 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1620 return false;
1621 }
1622 m = 1 << ((reg >> 2) & 31);
1623 if (!(r600_reg_safe_bm[i] & m))
1624 return true;
1625 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1626 return false;
1627 }
1628
r600_packet3_check(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt)1629 static int r600_packet3_check(struct radeon_cs_parser *p,
1630 struct radeon_cs_packet *pkt)
1631 {
1632 struct radeon_bo_list *reloc;
1633 struct r600_cs_track *track;
1634 volatile u32 *ib;
1635 unsigned idx;
1636 unsigned i;
1637 unsigned start_reg, end_reg, reg;
1638 int r;
1639 u32 idx_value;
1640
1641 track = (struct r600_cs_track *)p->track;
1642 ib = p->ib.ptr;
1643 idx = pkt->idx + 1;
1644 idx_value = radeon_get_ib_value(p, idx);
1645
1646 switch (pkt->opcode) {
1647 case PACKET3_SET_PREDICATION:
1648 {
1649 int pred_op;
1650 int tmp;
1651 uint64_t offset;
1652
1653 if (pkt->count != 1) {
1654 DRM_ERROR("bad SET PREDICATION\n");
1655 return -EINVAL;
1656 }
1657
1658 tmp = radeon_get_ib_value(p, idx + 1);
1659 pred_op = (tmp >> 16) & 0x7;
1660
1661 /* for the clear predicate operation */
1662 if (pred_op == 0)
1663 return 0;
1664
1665 if (pred_op > 2) {
1666 DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
1667 return -EINVAL;
1668 }
1669
1670 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1671 if (r) {
1672 DRM_ERROR("bad SET PREDICATION\n");
1673 return -EINVAL;
1674 }
1675
1676 offset = reloc->gpu_offset +
1677 (idx_value & 0xfffffff0) +
1678 ((u64)(tmp & 0xff) << 32);
1679
1680 ib[idx + 0] = offset;
1681 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1682 }
1683 break;
1684
1685 case PACKET3_START_3D_CMDBUF:
1686 if (p->family >= CHIP_RV770 || pkt->count) {
1687 DRM_ERROR("bad START_3D\n");
1688 return -EINVAL;
1689 }
1690 break;
1691 case PACKET3_CONTEXT_CONTROL:
1692 if (pkt->count != 1) {
1693 DRM_ERROR("bad CONTEXT_CONTROL\n");
1694 return -EINVAL;
1695 }
1696 break;
1697 case PACKET3_INDEX_TYPE:
1698 case PACKET3_NUM_INSTANCES:
1699 if (pkt->count) {
1700 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
1701 return -EINVAL;
1702 }
1703 break;
1704 case PACKET3_DRAW_INDEX:
1705 {
1706 uint64_t offset;
1707 if (pkt->count != 3) {
1708 DRM_ERROR("bad DRAW_INDEX\n");
1709 return -EINVAL;
1710 }
1711 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1712 if (r) {
1713 DRM_ERROR("bad DRAW_INDEX\n");
1714 return -EINVAL;
1715 }
1716
1717 offset = reloc->gpu_offset +
1718 idx_value +
1719 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1720
1721 ib[idx+0] = offset;
1722 ib[idx+1] = upper_32_bits(offset) & 0xff;
1723
1724 r = r600_cs_track_check(p);
1725 if (r) {
1726 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1727 return r;
1728 }
1729 break;
1730 }
1731 case PACKET3_DRAW_INDEX_AUTO:
1732 if (pkt->count != 1) {
1733 DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1734 return -EINVAL;
1735 }
1736 r = r600_cs_track_check(p);
1737 if (r) {
1738 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1739 return r;
1740 }
1741 break;
1742 case PACKET3_DRAW_INDEX_IMMD_BE:
1743 case PACKET3_DRAW_INDEX_IMMD:
1744 if (pkt->count < 2) {
1745 DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1746 return -EINVAL;
1747 }
1748 r = r600_cs_track_check(p);
1749 if (r) {
1750 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1751 return r;
1752 }
1753 break;
1754 case PACKET3_WAIT_REG_MEM:
1755 if (pkt->count != 5) {
1756 DRM_ERROR("bad WAIT_REG_MEM\n");
1757 return -EINVAL;
1758 }
1759 /* bit 4 is reg (0) or mem (1) */
1760 if (idx_value & 0x10) {
1761 uint64_t offset;
1762
1763 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1764 if (r) {
1765 DRM_ERROR("bad WAIT_REG_MEM\n");
1766 return -EINVAL;
1767 }
1768
1769 offset = reloc->gpu_offset +
1770 (radeon_get_ib_value(p, idx+1) & 0xfffffff0) +
1771 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1772
1773 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0);
1774 ib[idx+2] = upper_32_bits(offset) & 0xff;
1775 } else if (idx_value & 0x100) {
1776 DRM_ERROR("cannot use PFP on REG wait\n");
1777 return -EINVAL;
1778 }
1779 break;
1780 case PACKET3_CP_DMA:
1781 {
1782 u32 command, size;
1783 u64 offset, tmp;
1784 if (pkt->count != 4) {
1785 DRM_ERROR("bad CP DMA\n");
1786 return -EINVAL;
1787 }
1788 command = radeon_get_ib_value(p, idx+4);
1789 size = command & 0x1fffff;
1790 if (command & PACKET3_CP_DMA_CMD_SAS) {
1791 /* src address space is register */
1792 DRM_ERROR("CP DMA SAS not supported\n");
1793 return -EINVAL;
1794 } else {
1795 if (command & PACKET3_CP_DMA_CMD_SAIC) {
1796 DRM_ERROR("CP DMA SAIC only supported for registers\n");
1797 return -EINVAL;
1798 }
1799 /* src address space is memory */
1800 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1801 if (r) {
1802 DRM_ERROR("bad CP DMA SRC\n");
1803 return -EINVAL;
1804 }
1805
1806 tmp = radeon_get_ib_value(p, idx) +
1807 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1808
1809 offset = reloc->gpu_offset + tmp;
1810
1811 if ((tmp + size) > radeon_bo_size(reloc->robj)) {
1812 dev_warn(p->dev, "CP DMA src buffer too small (%"PRIu64" %lu)\n",
1813 tmp + size, radeon_bo_size(reloc->robj));
1814 return -EINVAL;
1815 }
1816
1817 ib[idx] = offset;
1818 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1819 }
1820 if (command & PACKET3_CP_DMA_CMD_DAS) {
1821 /* dst address space is register */
1822 DRM_ERROR("CP DMA DAS not supported\n");
1823 return -EINVAL;
1824 } else {
1825 /* dst address space is memory */
1826 if (command & PACKET3_CP_DMA_CMD_DAIC) {
1827 DRM_ERROR("CP DMA DAIC only supported for registers\n");
1828 return -EINVAL;
1829 }
1830 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1831 if (r) {
1832 DRM_ERROR("bad CP DMA DST\n");
1833 return -EINVAL;
1834 }
1835
1836 tmp = radeon_get_ib_value(p, idx+2) +
1837 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32);
1838
1839 offset = reloc->gpu_offset + tmp;
1840
1841 if ((tmp + size) > radeon_bo_size(reloc->robj)) {
1842 dev_warn(p->dev, "CP DMA dst buffer too small (%"PRIu64" %lu)\n",
1843 tmp + size, radeon_bo_size(reloc->robj));
1844 return -EINVAL;
1845 }
1846
1847 ib[idx+2] = offset;
1848 ib[idx+3] = upper_32_bits(offset) & 0xff;
1849 }
1850 break;
1851 }
1852 case PACKET3_SURFACE_SYNC:
1853 if (pkt->count != 3) {
1854 DRM_ERROR("bad SURFACE_SYNC\n");
1855 return -EINVAL;
1856 }
1857 /* 0xffffffff/0x0 is flush all cache flag */
1858 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1859 radeon_get_ib_value(p, idx + 2) != 0) {
1860 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1861 if (r) {
1862 DRM_ERROR("bad SURFACE_SYNC\n");
1863 return -EINVAL;
1864 }
1865 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1866 }
1867 break;
1868 case PACKET3_EVENT_WRITE:
1869 if (pkt->count != 2 && pkt->count != 0) {
1870 DRM_ERROR("bad EVENT_WRITE\n");
1871 return -EINVAL;
1872 }
1873 if (pkt->count) {
1874 uint64_t offset;
1875
1876 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1877 if (r) {
1878 DRM_ERROR("bad EVENT_WRITE\n");
1879 return -EINVAL;
1880 }
1881 offset = reloc->gpu_offset +
1882 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +
1883 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1884
1885 ib[idx+1] = offset & 0xfffffff8;
1886 ib[idx+2] = upper_32_bits(offset) & 0xff;
1887 }
1888 break;
1889 case PACKET3_EVENT_WRITE_EOP:
1890 {
1891 uint64_t offset;
1892
1893 if (pkt->count != 4) {
1894 DRM_ERROR("bad EVENT_WRITE_EOP\n");
1895 return -EINVAL;
1896 }
1897 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1898 if (r) {
1899 DRM_ERROR("bad EVENT_WRITE\n");
1900 return -EINVAL;
1901 }
1902
1903 offset = reloc->gpu_offset +
1904 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
1905 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1906
1907 ib[idx+1] = offset & 0xfffffffc;
1908 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1909 break;
1910 }
1911 case PACKET3_SET_CONFIG_REG:
1912 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
1913 end_reg = 4 * pkt->count + start_reg - 4;
1914 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
1915 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
1916 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
1917 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
1918 return -EINVAL;
1919 }
1920 for (i = 0; i < pkt->count; i++) {
1921 reg = start_reg + (4 * i);
1922 r = r600_cs_check_reg(p, reg, idx+1+i);
1923 if (r)
1924 return r;
1925 }
1926 break;
1927 case PACKET3_SET_CONTEXT_REG:
1928 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
1929 end_reg = 4 * pkt->count + start_reg - 4;
1930 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
1931 (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
1932 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
1933 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
1934 return -EINVAL;
1935 }
1936 for (i = 0; i < pkt->count; i++) {
1937 reg = start_reg + (4 * i);
1938 r = r600_cs_check_reg(p, reg, idx+1+i);
1939 if (r)
1940 return r;
1941 }
1942 break;
1943 case PACKET3_SET_RESOURCE:
1944 if (pkt->count % 7) {
1945 DRM_ERROR("bad SET_RESOURCE\n");
1946 return -EINVAL;
1947 }
1948 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
1949 end_reg = 4 * pkt->count + start_reg - 4;
1950 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
1951 (start_reg >= PACKET3_SET_RESOURCE_END) ||
1952 (end_reg >= PACKET3_SET_RESOURCE_END)) {
1953 DRM_ERROR("bad SET_RESOURCE\n");
1954 return -EINVAL;
1955 }
1956 for (i = 0; i < (pkt->count / 7); i++) {
1957 struct radeon_bo *texture, *mipmap;
1958 u32 size, offset, base_offset, mip_offset;
1959
1960 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
1961 case SQ_TEX_VTX_VALID_TEXTURE:
1962 /* tex base */
1963 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1964 if (r) {
1965 DRM_ERROR("bad SET_RESOURCE\n");
1966 return -EINVAL;
1967 }
1968 base_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1969 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1970 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1971 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1972 else if (reloc->tiling_flags & RADEON_TILING_MICRO)
1973 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1974 }
1975 texture = reloc->robj;
1976 /* tex mip base */
1977 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1978 if (r) {
1979 DRM_ERROR("bad SET_RESOURCE\n");
1980 return -EINVAL;
1981 }
1982 mip_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
1983 mipmap = reloc->robj;
1984 r = r600_check_texture_resource(p, idx+(i*7)+1,
1985 texture, mipmap,
1986 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2),
1987 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3),
1988 reloc->tiling_flags);
1989 if (r)
1990 return r;
1991 ib[idx+1+(i*7)+2] += base_offset;
1992 ib[idx+1+(i*7)+3] += mip_offset;
1993 break;
1994 case SQ_TEX_VTX_VALID_BUFFER:
1995 {
1996 uint64_t offset64;
1997 /* vtx base */
1998 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1999 if (r) {
2000 DRM_ERROR("bad SET_RESOURCE\n");
2001 return -EINVAL;
2002 }
2003 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
2004 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;
2005 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
2006 /* force size to size of the buffer */
2007 dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n",
2008 size + offset, radeon_bo_size(reloc->robj));
2009 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset;
2010 }
2011
2012 offset64 = reloc->gpu_offset + offset;
2013 ib[idx+1+(i*8)+0] = offset64;
2014 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) |
2015 (upper_32_bits(offset64) & 0xff);
2016 break;
2017 }
2018 case SQ_TEX_VTX_INVALID_TEXTURE:
2019 case SQ_TEX_VTX_INVALID_BUFFER:
2020 default:
2021 DRM_ERROR("bad SET_RESOURCE\n");
2022 return -EINVAL;
2023 }
2024 }
2025 break;
2026 case PACKET3_SET_ALU_CONST:
2027 if (track->sq_config & DX9_CONSTS) {
2028 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
2029 end_reg = 4 * pkt->count + start_reg - 4;
2030 if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
2031 (start_reg >= PACKET3_SET_ALU_CONST_END) ||
2032 (end_reg >= PACKET3_SET_ALU_CONST_END)) {
2033 DRM_ERROR("bad SET_ALU_CONST\n");
2034 return -EINVAL;
2035 }
2036 }
2037 break;
2038 case PACKET3_SET_BOOL_CONST:
2039 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
2040 end_reg = 4 * pkt->count + start_reg - 4;
2041 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
2042 (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
2043 (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
2044 DRM_ERROR("bad SET_BOOL_CONST\n");
2045 return -EINVAL;
2046 }
2047 break;
2048 case PACKET3_SET_LOOP_CONST:
2049 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
2050 end_reg = 4 * pkt->count + start_reg - 4;
2051 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
2052 (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
2053 (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
2054 DRM_ERROR("bad SET_LOOP_CONST\n");
2055 return -EINVAL;
2056 }
2057 break;
2058 case PACKET3_SET_CTL_CONST:
2059 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
2060 end_reg = 4 * pkt->count + start_reg - 4;
2061 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
2062 (start_reg >= PACKET3_SET_CTL_CONST_END) ||
2063 (end_reg >= PACKET3_SET_CTL_CONST_END)) {
2064 DRM_ERROR("bad SET_CTL_CONST\n");
2065 return -EINVAL;
2066 }
2067 break;
2068 case PACKET3_SET_SAMPLER:
2069 if (pkt->count % 3) {
2070 DRM_ERROR("bad SET_SAMPLER\n");
2071 return -EINVAL;
2072 }
2073 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
2074 end_reg = 4 * pkt->count + start_reg - 4;
2075 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
2076 (start_reg >= PACKET3_SET_SAMPLER_END) ||
2077 (end_reg >= PACKET3_SET_SAMPLER_END)) {
2078 DRM_ERROR("bad SET_SAMPLER\n");
2079 return -EINVAL;
2080 }
2081 break;
2082 case PACKET3_STRMOUT_BASE_UPDATE:
2083 /* RS780 and RS880 also need this */
2084 if (p->family < CHIP_RS780) {
2085 DRM_ERROR("STRMOUT_BASE_UPDATE only supported on 7xx\n");
2086 return -EINVAL;
2087 }
2088 if (pkt->count != 1) {
2089 DRM_ERROR("bad STRMOUT_BASE_UPDATE packet count\n");
2090 return -EINVAL;
2091 }
2092 if (idx_value > 3) {
2093 DRM_ERROR("bad STRMOUT_BASE_UPDATE index\n");
2094 return -EINVAL;
2095 }
2096 {
2097 u64 offset;
2098
2099 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
2100 if (r) {
2101 DRM_ERROR("bad STRMOUT_BASE_UPDATE reloc\n");
2102 return -EINVAL;
2103 }
2104
2105 if (reloc->robj != track->vgt_strmout_bo[idx_value]) {
2106 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo does not match\n");
2107 return -EINVAL;
2108 }
2109
2110 offset = radeon_get_ib_value(p, idx+1) << 8;
2111 if (offset != track->vgt_strmout_bo_offset[idx_value]) {
2112 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo offset does not match: 0x%"PRIx64", 0x%x\n",
2113 offset, track->vgt_strmout_bo_offset[idx_value]);
2114 return -EINVAL;
2115 }
2116
2117 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2118 DRM_ERROR("bad STRMOUT_BASE_UPDATE bo too small: 0x%"PRIx64", 0x%lx\n",
2119 offset + 4, radeon_bo_size(reloc->robj));
2120 return -EINVAL;
2121 }
2122 ib[idx+1] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
2123 }
2124 break;
2125 case PACKET3_SURFACE_BASE_UPDATE:
2126 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
2127 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
2128 return -EINVAL;
2129 }
2130 if (pkt->count) {
2131 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
2132 return -EINVAL;
2133 }
2134 break;
2135 case PACKET3_STRMOUT_BUFFER_UPDATE:
2136 if (pkt->count != 4) {
2137 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n");
2138 return -EINVAL;
2139 }
2140 /* Updating memory at DST_ADDRESS. */
2141 if (idx_value & 0x1) {
2142 u64 offset;
2143 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
2144 if (r) {
2145 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
2146 return -EINVAL;
2147 }
2148 offset = radeon_get_ib_value(p, idx+1);
2149 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2150 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2151 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%"PRIx64", 0x%lx\n",
2152 offset + 4, radeon_bo_size(reloc->robj));
2153 return -EINVAL;
2154 }
2155 offset += reloc->gpu_offset;
2156 ib[idx+1] = offset;
2157 ib[idx+2] = upper_32_bits(offset) & 0xff;
2158 }
2159 /* Reading data from SRC_ADDRESS. */
2160 if (((idx_value >> 1) & 0x3) == 2) {
2161 u64 offset;
2162 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
2163 if (r) {
2164 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
2165 return -EINVAL;
2166 }
2167 offset = radeon_get_ib_value(p, idx+3);
2168 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2169 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2170 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%"PRIx64", 0x%lx\n",
2171 offset + 4, radeon_bo_size(reloc->robj));
2172 return -EINVAL;
2173 }
2174 offset += reloc->gpu_offset;
2175 ib[idx+3] = offset;
2176 ib[idx+4] = upper_32_bits(offset) & 0xff;
2177 }
2178 break;
2179 case PACKET3_MEM_WRITE:
2180 {
2181 u64 offset;
2182
2183 if (pkt->count != 3) {
2184 DRM_ERROR("bad MEM_WRITE (invalid count)\n");
2185 return -EINVAL;
2186 }
2187 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
2188 if (r) {
2189 DRM_ERROR("bad MEM_WRITE (missing reloc)\n");
2190 return -EINVAL;
2191 }
2192 offset = radeon_get_ib_value(p, idx+0);
2193 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL;
2194 if (offset & 0x7) {
2195 DRM_ERROR("bad MEM_WRITE (address not qwords aligned)\n");
2196 return -EINVAL;
2197 }
2198 if ((offset + 8) > radeon_bo_size(reloc->robj)) {
2199 DRM_ERROR("bad MEM_WRITE bo too small: 0x%"PRIx64", 0x%lx\n",
2200 offset + 8, radeon_bo_size(reloc->robj));
2201 return -EINVAL;
2202 }
2203 offset += reloc->gpu_offset;
2204 ib[idx+0] = offset;
2205 ib[idx+1] = upper_32_bits(offset) & 0xff;
2206 break;
2207 }
2208 case PACKET3_COPY_DW:
2209 if (pkt->count != 4) {
2210 DRM_ERROR("bad COPY_DW (invalid count)\n");
2211 return -EINVAL;
2212 }
2213 if (idx_value & 0x1) {
2214 u64 offset;
2215 /* SRC is memory. */
2216 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
2217 if (r) {
2218 DRM_ERROR("bad COPY_DW (missing src reloc)\n");
2219 return -EINVAL;
2220 }
2221 offset = radeon_get_ib_value(p, idx+1);
2222 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2223 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2224 DRM_ERROR("bad COPY_DW src bo too small: 0x%"PRIx64", 0x%lx\n",
2225 offset + 4, radeon_bo_size(reloc->robj));
2226 return -EINVAL;
2227 }
2228 offset += reloc->gpu_offset;
2229 ib[idx+1] = offset;
2230 ib[idx+2] = upper_32_bits(offset) & 0xff;
2231 } else {
2232 /* SRC is a reg. */
2233 reg = radeon_get_ib_value(p, idx+1) << 2;
2234 if (!r600_is_safe_reg(p, reg, idx+1))
2235 return -EINVAL;
2236 }
2237 if (idx_value & 0x2) {
2238 u64 offset;
2239 /* DST is memory. */
2240 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
2241 if (r) {
2242 DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
2243 return -EINVAL;
2244 }
2245 offset = radeon_get_ib_value(p, idx+3);
2246 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2247 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2248 DRM_ERROR("bad COPY_DW dst bo too small: 0x%"PRIx64", 0x%lx\n",
2249 offset + 4, radeon_bo_size(reloc->robj));
2250 return -EINVAL;
2251 }
2252 offset += reloc->gpu_offset;
2253 ib[idx+3] = offset;
2254 ib[idx+4] = upper_32_bits(offset) & 0xff;
2255 } else {
2256 /* DST is a reg. */
2257 reg = radeon_get_ib_value(p, idx+3) << 2;
2258 if (!r600_is_safe_reg(p, reg, idx+3))
2259 return -EINVAL;
2260 }
2261 break;
2262 case PACKET3_NOP:
2263 break;
2264 default:
2265 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2266 return -EINVAL;
2267 }
2268 return 0;
2269 }
2270
r600_cs_parse(struct radeon_cs_parser * p)2271 int r600_cs_parse(struct radeon_cs_parser *p)
2272 {
2273 struct radeon_cs_packet pkt;
2274 struct r600_cs_track *track;
2275 int r;
2276
2277 if (p->track == NULL) {
2278 /* initialize tracker, we are in kms */
2279 track = kzalloc(sizeof(*track), GFP_KERNEL);
2280 if (track == NULL)
2281 return -ENOMEM;
2282 r600_cs_track_init(track);
2283 if (p->rdev->family < CHIP_RV770) {
2284 track->npipes = p->rdev->config.r600.tiling_npipes;
2285 track->nbanks = p->rdev->config.r600.tiling_nbanks;
2286 track->group_size = p->rdev->config.r600.tiling_group_size;
2287 } else if (p->rdev->family <= CHIP_RV740) {
2288 track->npipes = p->rdev->config.rv770.tiling_npipes;
2289 track->nbanks = p->rdev->config.rv770.tiling_nbanks;
2290 track->group_size = p->rdev->config.rv770.tiling_group_size;
2291 }
2292 p->track = track;
2293 }
2294 do {
2295 r = radeon_cs_packet_parse(p, &pkt, p->idx);
2296 if (r) {
2297 kfree(p->track);
2298 p->track = NULL;
2299 return r;
2300 }
2301 p->idx += pkt.count + 2;
2302 switch (pkt.type) {
2303 case RADEON_PACKET_TYPE0:
2304 r = r600_cs_parse_packet0(p, &pkt);
2305 break;
2306 case RADEON_PACKET_TYPE2:
2307 break;
2308 case RADEON_PACKET_TYPE3:
2309 r = r600_packet3_check(p, &pkt);
2310 break;
2311 default:
2312 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
2313 kfree(p->track);
2314 p->track = NULL;
2315 return -EINVAL;
2316 }
2317 if (r) {
2318 kfree(p->track);
2319 p->track = NULL;
2320 return r;
2321 }
2322 } while (p->idx < p->chunk_ib->length_dw);
2323 #if 0
2324 for (r = 0; r < p->ib.length_dw; r++) {
2325 pr_info("%05d 0x%08X\n", r, p->ib.ptr[r]);
2326 mdelay(1);
2327 }
2328 #endif
2329 kfree(p->track);
2330 p->track = NULL;
2331 return 0;
2332 }
2333
2334 /*
2335 * DMA
2336 */
2337 /**
2338 * r600_dma_cs_next_reloc() - parse next reloc
2339 * @p: parser structure holding parsing context.
2340 * @cs_reloc: reloc informations
2341 *
2342 * Return the next reloc, do bo validation and compute
2343 * GPU offset using the provided start.
2344 **/
r600_dma_cs_next_reloc(struct radeon_cs_parser * p,struct radeon_bo_list ** cs_reloc)2345 int r600_dma_cs_next_reloc(struct radeon_cs_parser *p,
2346 struct radeon_bo_list **cs_reloc)
2347 {
2348 unsigned idx;
2349
2350 *cs_reloc = NULL;
2351 if (p->chunk_relocs == NULL) {
2352 DRM_ERROR("No relocation chunk !\n");
2353 return -EINVAL;
2354 }
2355 idx = p->dma_reloc_idx;
2356 if (idx >= p->nrelocs) {
2357 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
2358 idx, p->nrelocs);
2359 return -EINVAL;
2360 }
2361 *cs_reloc = &p->relocs[idx];
2362 p->dma_reloc_idx++;
2363 return 0;
2364 }
2365
2366 #define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28)
2367 #define GET_DMA_COUNT(h) ((h) & 0x0000ffff)
2368 #define GET_DMA_T(h) (((h) & 0x00800000) >> 23)
2369
2370 /**
2371 * r600_dma_cs_parse() - parse the DMA IB
2372 * @p: parser structure holding parsing context.
2373 *
2374 * Parses the DMA IB from the CS ioctl and updates
2375 * the GPU addresses based on the reloc information and
2376 * checks for errors. (R6xx-R7xx)
2377 * Returns 0 for success and an error on failure.
2378 **/
r600_dma_cs_parse(struct radeon_cs_parser * p)2379 int r600_dma_cs_parse(struct radeon_cs_parser *p)
2380 {
2381 struct radeon_cs_chunk *ib_chunk = p->chunk_ib;
2382 struct radeon_bo_list *src_reloc, *dst_reloc;
2383 u32 header, cmd, count, tiled;
2384 volatile u32 *ib = p->ib.ptr;
2385 u32 idx, idx_value;
2386 u64 src_offset, dst_offset;
2387 int r;
2388
2389 do {
2390 if (p->idx >= ib_chunk->length_dw) {
2391 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
2392 p->idx, ib_chunk->length_dw);
2393 return -EINVAL;
2394 }
2395 idx = p->idx;
2396 header = radeon_get_ib_value(p, idx);
2397 cmd = GET_DMA_CMD(header);
2398 count = GET_DMA_COUNT(header);
2399 tiled = GET_DMA_T(header);
2400
2401 switch (cmd) {
2402 case DMA_PACKET_WRITE:
2403 r = r600_dma_cs_next_reloc(p, &dst_reloc);
2404 if (r) {
2405 DRM_ERROR("bad DMA_PACKET_WRITE\n");
2406 return -EINVAL;
2407 }
2408 if (tiled) {
2409 dst_offset = radeon_get_ib_value(p, idx+1);
2410 dst_offset <<= 8;
2411
2412 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
2413 p->idx += count + 5;
2414 } else {
2415 dst_offset = radeon_get_ib_value(p, idx+1);
2416 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2417
2418 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
2419 ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
2420 p->idx += count + 3;
2421 }
2422 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2423 dev_warn(p->dev, "DMA write buffer too small (%"PRIu64" %lu)\n",
2424 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2425 return -EINVAL;
2426 }
2427 break;
2428 case DMA_PACKET_COPY:
2429 r = r600_dma_cs_next_reloc(p, &src_reloc);
2430 if (r) {
2431 DRM_ERROR("bad DMA_PACKET_COPY\n");
2432 return -EINVAL;
2433 }
2434 r = r600_dma_cs_next_reloc(p, &dst_reloc);
2435 if (r) {
2436 DRM_ERROR("bad DMA_PACKET_COPY\n");
2437 return -EINVAL;
2438 }
2439 if (tiled) {
2440 idx_value = radeon_get_ib_value(p, idx + 2);
2441 /* detile bit */
2442 if (idx_value & (1 << 31)) {
2443 /* tiled src, linear dst */
2444 src_offset = radeon_get_ib_value(p, idx+1);
2445 src_offset <<= 8;
2446 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);
2447
2448 dst_offset = radeon_get_ib_value(p, idx+5);
2449 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;
2450 ib[idx+5] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
2451 ib[idx+6] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
2452 } else {
2453 /* linear src, tiled dst */
2454 src_offset = radeon_get_ib_value(p, idx+5);
2455 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;
2456 ib[idx+5] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
2457 ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
2458
2459 dst_offset = radeon_get_ib_value(p, idx+1);
2460 dst_offset <<= 8;
2461 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);
2462 }
2463 p->idx += 7;
2464 } else {
2465 if (p->family >= CHIP_RV770) {
2466 src_offset = radeon_get_ib_value(p, idx+2);
2467 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2468 dst_offset = radeon_get_ib_value(p, idx+1);
2469 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
2470
2471 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
2472 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
2473 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;
2474 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
2475 p->idx += 5;
2476 } else {
2477 src_offset = radeon_get_ib_value(p, idx+2);
2478 src_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
2479 dst_offset = radeon_get_ib_value(p, idx+1);
2480 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16;
2481
2482 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
2483 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
2484 ib[idx+3] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
2485 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) & 0xff) << 16;
2486 p->idx += 4;
2487 }
2488 }
2489 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
2490 dev_warn(p->dev, "DMA copy src buffer too small (%"PRIu64" %lu)\n",
2491 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
2492 return -EINVAL;
2493 }
2494 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2495 dev_warn(p->dev, "DMA write dst buffer too small (%"PRIu64" %lu)\n",
2496 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2497 return -EINVAL;
2498 }
2499 break;
2500 case DMA_PACKET_CONSTANT_FILL:
2501 if (p->family < CHIP_RV770) {
2502 DRM_ERROR("Constant Fill is 7xx only !\n");
2503 return -EINVAL;
2504 }
2505 r = r600_dma_cs_next_reloc(p, &dst_reloc);
2506 if (r) {
2507 DRM_ERROR("bad DMA_PACKET_WRITE\n");
2508 return -EINVAL;
2509 }
2510 dst_offset = radeon_get_ib_value(p, idx+1);
2511 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;
2512 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2513 dev_warn(p->dev, "DMA constant fill buffer too small (%"PRIu64" %lu)\n",
2514 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2515 return -EINVAL;
2516 }
2517 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);
2518 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000;
2519 p->idx += 4;
2520 break;
2521 case DMA_PACKET_NOP:
2522 p->idx += 1;
2523 break;
2524 default:
2525 DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx);
2526 return -EINVAL;
2527 }
2528 } while (p->idx < p->chunk_ib->length_dw);
2529 #if 0
2530 for (r = 0; r < p->ib->length_dw; r++) {
2531 pr_info("%05d 0x%08X\n", r, p->ib.ptr[r]);
2532 mdelay(1);
2533 }
2534 #endif
2535 return 0;
2536 }
2537