1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 /***************************************************************************** 8 * 9 * Module: __INC_HAL8192CPHYREG_H 10 * 11 * 12 * Note: 1. Define PMAC/BB register map 13 * 2. Define RF register map 14 * 3. PMAC/BB register bit mask. 15 * 4. RF reg bit mask. 16 * 5. Other BB/RF relative definition. 17 * 18 * 19 * Export: Constants, macro, functions(API), global variables(None). 20 * 21 * Abbrev: 22 * 23 * History: 24 * Data Who Remark 25 * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. 26 * 2. Reorganize code architecture. 27 *09/25/2008 MH 1. Add RL6052 register definition 28 * 29 *****************************************************************************/ 30 #ifndef __INC_HAL8192CPHYREG_H 31 #define __INC_HAL8192CPHYREG_H 32 33 34 /*--------------------------Define Parameters-------------------------------*/ 35 36 /* */ 37 /* 8192S Register offset definition */ 38 /* */ 39 40 /* */ 41 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */ 42 /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */ 43 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */ 44 /* 3. RF register 0x00-2E */ 45 /* 4. Bit Mask for BB/RF register */ 46 /* 5. Other definition for BB/RF R/W */ 47 /* */ 48 49 /* */ 50 /* 3. Page8(0x800) */ 51 /* */ 52 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting?? */ 53 54 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ 55 #define rFPGA0_XA_HSSIParameter2 0x824 56 #define rFPGA0_XB_HSSIParameter1 0x828 57 #define rFPGA0_XB_HSSIParameter2 0x82c 58 #define rTxAGC_B_Rate18_06 0x830 59 #define rTxAGC_B_Rate54_24 0x834 60 #define rTxAGC_B_CCK1_55_Mcs32 0x838 61 #define rTxAGC_B_Mcs03_Mcs00 0x83c 62 63 #define rTxAGC_B_Mcs07_Mcs04 0x848 64 65 #define rFPGA0_XA_LSSIParameter 0x840 66 #define rFPGA0_XB_LSSIParameter 0x844 67 68 #define rFPGA0_XCD_SwitchControl 0x85c 69 70 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ 71 #define rFPGA0_XB_RFInterfaceOE 0x864 72 73 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c 74 75 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ 76 #define rFPGA0_XCD_RFInterfaceSW 0x874 77 78 #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Transceiver LSSI Readback */ 79 #define rFPGA0_XB_LSSIReadBack 0x8a4 80 81 #define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */ 82 #define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */ 83 84 /* */ 85 /* 4. Page9(0x900) */ 86 /* */ 87 #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC RF BW Setting?? */ 88 89 #define rS0S1_PathSwitch 0x948 90 91 /* */ 92 /* 5. PageA(0xA00) */ 93 /* */ 94 /* Set Control channel to upper or lower. These settings are required only for 40MHz */ 95 #define rCCK0_System 0xa00 96 97 #define rCCK0_AFESetting 0xa04 /* Disable init gain now Select RX path by RSSI */ 98 99 /* */ 100 /* PageB(0xB00) */ 101 /* */ 102 #define rConfig_AntA 0xb68 103 #define rConfig_AntB 0xb6c 104 105 /* */ 106 /* 6. PageC(0xC00) */ 107 /* */ 108 #define rOFDM0_TRxPathEnable 0xc04 109 #define rOFDM0_TRMuxPar 0xc08 110 111 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imbalance matrix */ 112 #define rOFDM0_XBRxIQImbalance 0xc1c 113 114 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 115 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 116 117 #define rOFDM0_AGCRSSITable 0xc78 118 119 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ 120 #define rOFDM0_XBTxIQImbalance 0xc88 121 #define rOFDM0_XCTxAFE 0xc94 122 #define rOFDM0_XDTxAFE 0xc9c 123 124 #define rOFDM0_RxIQExtAnta 0xca0 125 #define rOFDM0_TxPseudoNoiseWgt 0xce4 126 127 /* */ 128 /* 7. PageD(0xD00) */ 129 /* */ 130 #define rOFDM1_LSTF 0xd00 131 132 /* */ 133 /* 8. PageE(0xE00) */ 134 /* */ 135 #define rTxAGC_A_Rate18_06 0xe00 136 #define rTxAGC_A_Rate54_24 0xe04 137 #define rTxAGC_A_CCK1_Mcs32 0xe08 138 #define rTxAGC_A_Mcs03_Mcs00 0xe10 139 #define rTxAGC_A_Mcs07_Mcs04 0xe14 140 141 #define rFPGA0_IQK 0xe28 142 #define rTx_IQK_Tone_A 0xe30 143 #define rRx_IQK_Tone_A 0xe34 144 #define rTx_IQK_PI_A 0xe38 145 #define rRx_IQK_PI_A 0xe3c 146 147 #define rTx_IQK 0xe40 148 #define rRx_IQK 0xe44 149 #define rIQK_AGC_Pts 0xe48 150 #define rIQK_AGC_Rsp 0xe4c 151 #define rTx_IQK_Tone_B 0xe50 152 #define rRx_IQK_Tone_B 0xe54 153 #define rTx_IQK_PI_B 0xe58 154 #define rRx_IQK_PI_B 0xe5c 155 156 #define rBlue_Tooth 0xe6c 157 #define rRx_Wait_CCA 0xe70 158 #define rTx_CCK_RFON 0xe74 159 #define rTx_CCK_BBON 0xe78 160 #define rTx_OFDM_RFON 0xe7c 161 #define rTx_OFDM_BBON 0xe80 162 #define rTx_To_Rx 0xe84 163 #define rTx_To_Tx 0xe88 164 #define rRx_CCK 0xe8c 165 166 #define rTx_Power_Before_IQK_A 0xe94 167 #define rTx_Power_After_IQK_A 0xe9c 168 169 #define rRx_Power_Before_IQK_A_2 0xea4 170 #define rRx_Power_After_IQK_A_2 0xeac 171 172 #define rRx_OFDM 0xed0 173 #define rRx_Wait_RIFS 0xed4 174 #define rRx_TO_Rx 0xed8 175 #define rStandby 0xedc 176 #define rSleep 0xee0 177 #define rPMPD_ANAEN 0xeec 178 179 /* */ 180 /* RL6052 Register definition */ 181 /* */ 182 #define RF_AC 0x00 /* */ 183 184 #define RF_TXM_IDAC 0x08 /* */ 185 186 #define RF_CHNLBW 0x18 /* RF channel and BW switch */ 187 188 #define RF_RCK_OS 0x30 /* RF TX PA control */ 189 190 #define RF_TXPA_G1 0x31 /* RF TX PA control */ 191 #define RF_TXPA_G2 0x32 /* RF TX PA control */ 192 193 #define RF_WE_LUT 0xEF 194 195 /* 2. Page8(0x800) */ 196 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ 197 198 #define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ 199 #define b3WireAddressLength 0x400 200 201 #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ 202 203 #define bLSSIReadAddress 0x7f800000 /* T65 RF */ 204 205 #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ 206 207 #define bLSSIReadBackData 0xfffff /* T65 RF */ 208 209 /* 4. PageA(0xA00) */ 210 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ 211 212 /* */ 213 /* Other Definition */ 214 /* */ 215 216 /* for PutRegsetting & GetRegSetting BitMask */ 217 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ 218 #define bMaskByte1 0xff00 219 #define bMaskByte2 0xff0000 220 #define bMaskByte3 0xff000000 221 #define bMaskHWord 0xffff0000 222 #define bMaskLWord 0x0000ffff 223 #define bMaskDWord 0xffffffff 224 #define bMaskH3Bytes 0xffffff00 225 #define bMask12Bits 0xfff 226 #define bMaskH4Bits 0xf0000000 227 228 #define bEnable 0x1 /* Useless */ 229 230 #define rDPDT_control 0x92c 231 232 #endif /* __INC_HAL8192SPHYREG_H */ 233