1 /* $NetBSD: radeon_atombios.c,v 1.4 2021/12/18 23:45:43 riastradh Exp $ */
2
3 /*
4 * Copyright 2007-8 Advanced Micro Devices, Inc.
5 * Copyright 2008 Red Hat Inc.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
23 * OTHER DEALINGS IN THE SOFTWARE.
24 *
25 * Authors: Dave Airlie
26 * Alex Deucher
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: radeon_atombios.c,v 1.4 2021/12/18 23:45:43 riastradh Exp $");
31
32 #include <linux/pci.h>
33
34 #include <drm/drm_device.h>
35 #include <drm/radeon_drm.h>
36
37 #include "radeon.h"
38
39 #include "atom.h"
40 #include "atom-bits.h"
41 #include "radeon_asic.h"
42
43 extern void
44 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
45 uint32_t supported_device, u16 caps);
46
47 /* from radeon_legacy_encoder.c */
48 extern void
49 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
50 uint32_t supported_device);
51
52 union atom_supported_devices {
53 struct _ATOM_SUPPORTED_DEVICES_INFO info;
54 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
55 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
56 };
57
radeon_lookup_i2c_gpio_quirks(struct radeon_device * rdev,ATOM_GPIO_I2C_ASSIGMENT * gpio,u8 index)58 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
59 ATOM_GPIO_I2C_ASSIGMENT *gpio,
60 u8 index)
61 {
62 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
63 if ((rdev->family == CHIP_R420) ||
64 (rdev->family == CHIP_R423) ||
65 (rdev->family == CHIP_RV410)) {
66 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
67 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
68 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
69 gpio->ucClkMaskShift = 0x19;
70 gpio->ucDataMaskShift = 0x18;
71 }
72 }
73
74 /* some evergreen boards have bad data for this entry */
75 if (ASIC_IS_DCE4(rdev)) {
76 if ((index == 7) &&
77 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
78 (gpio->sucI2cId.ucAccess == 0)) {
79 gpio->sucI2cId.ucAccess = 0x97;
80 gpio->ucDataMaskShift = 8;
81 gpio->ucDataEnShift = 8;
82 gpio->ucDataY_Shift = 8;
83 gpio->ucDataA_Shift = 8;
84 }
85 }
86
87 /* some DCE3 boards have bad data for this entry */
88 if (ASIC_IS_DCE3(rdev)) {
89 if ((index == 4) &&
90 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
91 (gpio->sucI2cId.ucAccess == 0x94))
92 gpio->sucI2cId.ucAccess = 0x14;
93 }
94 }
95
radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT * gpio)96 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
97 {
98 struct radeon_i2c_bus_rec i2c;
99
100 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
101
102 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
103 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
104 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
105 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
106 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
107 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
108 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
109 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
110 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
111 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
112 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
113 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
114 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
115 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
116 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
117 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
118
119 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
120 i2c.hw_capable = true;
121 else
122 i2c.hw_capable = false;
123
124 if (gpio->sucI2cId.ucAccess == 0xa0)
125 i2c.mm_i2c = true;
126 else
127 i2c.mm_i2c = false;
128
129 i2c.i2c_id = gpio->sucI2cId.ucAccess;
130
131 if (i2c.mask_clk_reg)
132 i2c.valid = true;
133 else
134 i2c.valid = false;
135
136 return i2c;
137 }
138
radeon_lookup_i2c_gpio(struct radeon_device * rdev,uint8_t id)139 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
140 uint8_t id)
141 {
142 struct atom_context *ctx = rdev->mode_info.atom_context;
143 ATOM_GPIO_I2C_ASSIGMENT *gpio;
144 struct radeon_i2c_bus_rec i2c;
145 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
146 struct _ATOM_GPIO_I2C_INFO *i2c_info;
147 uint16_t data_offset, size;
148 int i, num_indices;
149
150 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
151 i2c.valid = false;
152
153 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
154 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
155
156 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
157 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
158
159 gpio = &i2c_info->asGPIO_Info[0];
160 for (i = 0; i < num_indices; i++) {
161
162 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
163
164 if (gpio->sucI2cId.ucAccess == id) {
165 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
166 break;
167 }
168 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
169 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
170 }
171 }
172
173 return i2c;
174 }
175
radeon_atombios_i2c_init(struct radeon_device * rdev)176 void radeon_atombios_i2c_init(struct radeon_device *rdev)
177 {
178 struct atom_context *ctx = rdev->mode_info.atom_context;
179 ATOM_GPIO_I2C_ASSIGMENT *gpio;
180 struct radeon_i2c_bus_rec i2c;
181 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
182 struct _ATOM_GPIO_I2C_INFO *i2c_info;
183 uint16_t data_offset, size;
184 int i, num_indices;
185 char stmp[32];
186
187 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
188 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
189
190 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
191 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
192
193 gpio = &i2c_info->asGPIO_Info[0];
194 for (i = 0; i < num_indices; i++) {
195 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
196
197 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
198
199 if (i2c.valid) {
200 snprintf(stmp, sizeof stmp, "0x%x", i2c.i2c_id);
201 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
202 }
203 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
204 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
205 }
206 }
207 }
208
radeon_atombios_lookup_gpio(struct radeon_device * rdev,u8 id)209 struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
210 u8 id)
211 {
212 struct atom_context *ctx = rdev->mode_info.atom_context;
213 struct radeon_gpio_rec gpio;
214 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
215 struct _ATOM_GPIO_PIN_LUT *gpio_info;
216 ATOM_GPIO_PIN_ASSIGNMENT *pin;
217 u16 data_offset, size;
218 int i, num_indices;
219
220 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
221 gpio.valid = false;
222
223 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
224 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
225
226 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
227 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
228
229 pin = gpio_info->asGPIO_Pin;
230 for (i = 0; i < num_indices; i++) {
231 if (id == pin->ucGPIO_ID) {
232 gpio.id = pin->ucGPIO_ID;
233 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
234 gpio.shift = pin->ucGpioPinBitShift;
235 gpio.mask = (1 << pin->ucGpioPinBitShift);
236 gpio.valid = true;
237 break;
238 }
239 pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
240 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
241 }
242 }
243
244 return gpio;
245 }
246
radeon_atom_get_hpd_info_from_gpio(struct radeon_device * rdev,struct radeon_gpio_rec * gpio)247 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
248 struct radeon_gpio_rec *gpio)
249 {
250 struct radeon_hpd hpd;
251 u32 reg;
252
253 memset(&hpd, 0, sizeof(struct radeon_hpd));
254
255 if (ASIC_IS_DCE6(rdev))
256 reg = SI_DC_GPIO_HPD_A;
257 else if (ASIC_IS_DCE4(rdev))
258 reg = EVERGREEN_DC_GPIO_HPD_A;
259 else
260 reg = AVIVO_DC_GPIO_HPD_A;
261
262 hpd.gpio = *gpio;
263 if (gpio->reg == reg) {
264 switch(gpio->mask) {
265 case (1 << 0):
266 hpd.hpd = RADEON_HPD_1;
267 break;
268 case (1 << 8):
269 hpd.hpd = RADEON_HPD_2;
270 break;
271 case (1 << 16):
272 hpd.hpd = RADEON_HPD_3;
273 break;
274 case (1 << 24):
275 hpd.hpd = RADEON_HPD_4;
276 break;
277 case (1 << 26):
278 hpd.hpd = RADEON_HPD_5;
279 break;
280 case (1 << 28):
281 hpd.hpd = RADEON_HPD_6;
282 break;
283 default:
284 hpd.hpd = RADEON_HPD_NONE;
285 break;
286 }
287 } else
288 hpd.hpd = RADEON_HPD_NONE;
289 return hpd;
290 }
291
radeon_atom_apply_quirks(struct drm_device * dev,uint32_t supported_device,int * connector_type,struct radeon_i2c_bus_rec * i2c_bus,uint16_t * line_mux,struct radeon_hpd * hpd)292 static bool radeon_atom_apply_quirks(struct drm_device *dev,
293 uint32_t supported_device,
294 int *connector_type,
295 struct radeon_i2c_bus_rec *i2c_bus,
296 uint16_t *line_mux,
297 struct radeon_hpd *hpd)
298 {
299
300 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
301 if ((dev->pdev->device == 0x791e) &&
302 (dev->pdev->subsystem_vendor == 0x1043) &&
303 (dev->pdev->subsystem_device == 0x826d)) {
304 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
305 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
306 *connector_type = DRM_MODE_CONNECTOR_DVID;
307 }
308
309 /* Asrock RS600 board lists the DVI port as HDMI */
310 if ((dev->pdev->device == 0x7941) &&
311 (dev->pdev->subsystem_vendor == 0x1849) &&
312 (dev->pdev->subsystem_device == 0x7941)) {
313 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
314 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
315 *connector_type = DRM_MODE_CONNECTOR_DVID;
316 }
317
318 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
319 if ((dev->pdev->device == 0x796e) &&
320 (dev->pdev->subsystem_vendor == 0x1462) &&
321 (dev->pdev->subsystem_device == 0x7302)) {
322 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
323 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
324 return false;
325 }
326
327 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
328 if ((dev->pdev->device == 0x7941) &&
329 (dev->pdev->subsystem_vendor == 0x147b) &&
330 (dev->pdev->subsystem_device == 0x2412)) {
331 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
332 return false;
333 }
334
335 /* Falcon NW laptop lists vga ddc line for LVDS */
336 if ((dev->pdev->device == 0x5653) &&
337 (dev->pdev->subsystem_vendor == 0x1462) &&
338 (dev->pdev->subsystem_device == 0x0291)) {
339 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
340 i2c_bus->valid = false;
341 *line_mux = 53;
342 }
343 }
344
345 /* HIS X1300 is DVI+VGA, not DVI+DVI */
346 if ((dev->pdev->device == 0x7146) &&
347 (dev->pdev->subsystem_vendor == 0x17af) &&
348 (dev->pdev->subsystem_device == 0x2058)) {
349 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
350 return false;
351 }
352
353 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
354 if ((dev->pdev->device == 0x7142) &&
355 (dev->pdev->subsystem_vendor == 0x1458) &&
356 (dev->pdev->subsystem_device == 0x2134)) {
357 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
358 return false;
359 }
360
361
362 /* Funky macbooks */
363 if ((dev->pdev->device == 0x71C5) &&
364 (dev->pdev->subsystem_vendor == 0x106b) &&
365 (dev->pdev->subsystem_device == 0x0080)) {
366 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
367 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
368 return false;
369 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
370 *line_mux = 0x90;
371 }
372
373 /* mac rv630, rv730, others */
374 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
375 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
376 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
377 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
378 }
379
380 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
381 if ((dev->pdev->device == 0x9598) &&
382 (dev->pdev->subsystem_vendor == 0x1043) &&
383 (dev->pdev->subsystem_device == 0x01da)) {
384 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
385 *connector_type = DRM_MODE_CONNECTOR_DVII;
386 }
387 }
388
389 /* ASUS HD 3600 board lists the DVI port as HDMI */
390 if ((dev->pdev->device == 0x9598) &&
391 (dev->pdev->subsystem_vendor == 0x1043) &&
392 (dev->pdev->subsystem_device == 0x01e4)) {
393 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
394 *connector_type = DRM_MODE_CONNECTOR_DVII;
395 }
396 }
397
398 /* ASUS HD 3450 board lists the DVI port as HDMI */
399 if ((dev->pdev->device == 0x95C5) &&
400 (dev->pdev->subsystem_vendor == 0x1043) &&
401 (dev->pdev->subsystem_device == 0x01e2)) {
402 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
403 *connector_type = DRM_MODE_CONNECTOR_DVII;
404 }
405 }
406
407 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
408 * HDMI + VGA reporting as HDMI
409 */
410 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
411 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
412 *connector_type = DRM_MODE_CONNECTOR_VGA;
413 *line_mux = 0;
414 }
415 }
416
417 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
418 * on the laptop and a DVI port on the docking station and
419 * both share the same encoder, hpd pin, and ddc line.
420 * So while the bios table is technically correct,
421 * we drop the DVI port here since xrandr has no concept of
422 * encoders and will try and drive both connectors
423 * with different crtcs which isn't possible on the hardware
424 * side and leaves no crtcs for LVDS or VGA.
425 */
426 if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
427 (dev->pdev->subsystem_vendor == 0x1025) &&
428 (dev->pdev->subsystem_device == 0x013c)) {
429 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
430 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
431 /* actually it's a DVI-D port not DVI-I */
432 *connector_type = DRM_MODE_CONNECTOR_DVID;
433 return false;
434 }
435 }
436
437 /* XFX Pine Group device rv730 reports no VGA DDC lines
438 * even though they are wired up to record 0x93
439 */
440 if ((dev->pdev->device == 0x9498) &&
441 (dev->pdev->subsystem_vendor == 0x1682) &&
442 (dev->pdev->subsystem_device == 0x2452) &&
443 (i2c_bus->valid == false) &&
444 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
445 struct radeon_device *rdev = dev->dev_private;
446 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
447 }
448
449 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
450 if (((dev->pdev->device == 0x9802) ||
451 (dev->pdev->device == 0x9805) ||
452 (dev->pdev->device == 0x9806)) &&
453 (dev->pdev->subsystem_vendor == 0x1734) &&
454 (dev->pdev->subsystem_device == 0x11bd)) {
455 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
456 *connector_type = DRM_MODE_CONNECTOR_DVII;
457 *line_mux = 0x3103;
458 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
459 *connector_type = DRM_MODE_CONNECTOR_DVII;
460 }
461 }
462
463 return true;
464 }
465
466 static const int supported_devices_connector_convert[] = {
467 DRM_MODE_CONNECTOR_Unknown,
468 DRM_MODE_CONNECTOR_VGA,
469 DRM_MODE_CONNECTOR_DVII,
470 DRM_MODE_CONNECTOR_DVID,
471 DRM_MODE_CONNECTOR_DVIA,
472 DRM_MODE_CONNECTOR_SVIDEO,
473 DRM_MODE_CONNECTOR_Composite,
474 DRM_MODE_CONNECTOR_LVDS,
475 DRM_MODE_CONNECTOR_Unknown,
476 DRM_MODE_CONNECTOR_Unknown,
477 DRM_MODE_CONNECTOR_HDMIA,
478 DRM_MODE_CONNECTOR_HDMIB,
479 DRM_MODE_CONNECTOR_Unknown,
480 DRM_MODE_CONNECTOR_Unknown,
481 DRM_MODE_CONNECTOR_9PinDIN,
482 DRM_MODE_CONNECTOR_DisplayPort
483 };
484
485 static const uint16_t supported_devices_connector_object_id_convert[] = {
486 CONNECTOR_OBJECT_ID_NONE,
487 CONNECTOR_OBJECT_ID_VGA,
488 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
489 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
490 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
491 CONNECTOR_OBJECT_ID_COMPOSITE,
492 CONNECTOR_OBJECT_ID_SVIDEO,
493 CONNECTOR_OBJECT_ID_LVDS,
494 CONNECTOR_OBJECT_ID_9PIN_DIN,
495 CONNECTOR_OBJECT_ID_9PIN_DIN,
496 CONNECTOR_OBJECT_ID_DISPLAYPORT,
497 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
498 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
499 CONNECTOR_OBJECT_ID_SVIDEO
500 };
501
502 static const int object_connector_convert[] = {
503 DRM_MODE_CONNECTOR_Unknown,
504 DRM_MODE_CONNECTOR_DVII,
505 DRM_MODE_CONNECTOR_DVII,
506 DRM_MODE_CONNECTOR_DVID,
507 DRM_MODE_CONNECTOR_DVID,
508 DRM_MODE_CONNECTOR_VGA,
509 DRM_MODE_CONNECTOR_Composite,
510 DRM_MODE_CONNECTOR_SVIDEO,
511 DRM_MODE_CONNECTOR_Unknown,
512 DRM_MODE_CONNECTOR_Unknown,
513 DRM_MODE_CONNECTOR_9PinDIN,
514 DRM_MODE_CONNECTOR_Unknown,
515 DRM_MODE_CONNECTOR_HDMIA,
516 DRM_MODE_CONNECTOR_HDMIB,
517 DRM_MODE_CONNECTOR_LVDS,
518 DRM_MODE_CONNECTOR_9PinDIN,
519 DRM_MODE_CONNECTOR_Unknown,
520 DRM_MODE_CONNECTOR_Unknown,
521 DRM_MODE_CONNECTOR_Unknown,
522 DRM_MODE_CONNECTOR_DisplayPort,
523 DRM_MODE_CONNECTOR_eDP,
524 DRM_MODE_CONNECTOR_Unknown
525 };
526
radeon_get_atom_connector_info_from_object_table(struct drm_device * dev)527 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
528 {
529 struct radeon_device *rdev = dev->dev_private;
530 struct radeon_mode_info *mode_info = &rdev->mode_info;
531 struct atom_context *ctx = mode_info->atom_context;
532 int index = GetIndexIntoMasterTable(DATA, Object_Header);
533 u16 size, data_offset;
534 u8 frev, crev;
535 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
536 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
537 ATOM_OBJECT_TABLE *router_obj;
538 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
539 ATOM_OBJECT_HEADER *obj_header;
540 int i, j, k, path_size, device_support;
541 int connector_type;
542 u16 igp_lane_info, conn_id, connector_object_id;
543 struct radeon_i2c_bus_rec ddc_bus;
544 struct radeon_router router;
545 struct radeon_gpio_rec gpio;
546 struct radeon_hpd hpd;
547
548 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
549 return false;
550
551 if (crev < 2)
552 return false;
553
554 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
555 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
556 (ctx->bios + data_offset +
557 le16_to_cpu(obj_header->usDisplayPathTableOffset));
558 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
559 (ctx->bios + data_offset +
560 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
561 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
562 (ctx->bios + data_offset +
563 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
564 router_obj = (ATOM_OBJECT_TABLE *)
565 (ctx->bios + data_offset +
566 le16_to_cpu(obj_header->usRouterObjectTableOffset));
567 device_support = le16_to_cpu(obj_header->usDeviceSupport);
568
569 path_size = 0;
570 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
571 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
572 ATOM_DISPLAY_OBJECT_PATH *path;
573 addr += path_size;
574 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
575 path_size += le16_to_cpu(path->usSize);
576
577 if (device_support & le16_to_cpu(path->usDeviceTag)) {
578 uint8_t con_obj_id, con_obj_num;
579
580 con_obj_id =
581 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
582 >> OBJECT_ID_SHIFT;
583 con_obj_num =
584 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
585 >> ENUM_ID_SHIFT;
586
587 /* TODO CV support */
588 if (le16_to_cpu(path->usDeviceTag) ==
589 ATOM_DEVICE_CV_SUPPORT)
590 continue;
591
592 /* IGP chips */
593 if ((rdev->flags & RADEON_IS_IGP) &&
594 (con_obj_id ==
595 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
596 uint16_t igp_offset = 0;
597 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
598
599 index =
600 GetIndexIntoMasterTable(DATA,
601 IntegratedSystemInfo);
602
603 if (atom_parse_data_header(ctx, index, &size, &frev,
604 &crev, &igp_offset)) {
605
606 if (crev >= 2) {
607 igp_obj =
608 (ATOM_INTEGRATED_SYSTEM_INFO_V2
609 *) (ctx->bios + igp_offset);
610
611 if (igp_obj) {
612 uint32_t slot_config, ct;
613
614 if (con_obj_num == 1)
615 slot_config =
616 igp_obj->
617 ulDDISlot1Config;
618 else
619 slot_config =
620 igp_obj->
621 ulDDISlot2Config;
622
623 ct = (slot_config >> 16) & 0xff;
624 connector_type =
625 object_connector_convert
626 [ct];
627 connector_object_id = ct;
628 igp_lane_info =
629 slot_config & 0xffff;
630 } else
631 continue;
632 } else
633 continue;
634 } else {
635 igp_lane_info = 0;
636 connector_type =
637 object_connector_convert[con_obj_id];
638 connector_object_id = con_obj_id;
639 }
640 } else {
641 igp_lane_info = 0;
642 connector_type =
643 object_connector_convert[con_obj_id];
644 connector_object_id = con_obj_id;
645 }
646
647 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
648 continue;
649
650 router.ddc_valid = false;
651 router.cd_valid = false;
652 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
653 uint8_t grph_obj_type =
654 (le16_to_cpu(path->usGraphicObjIds[j]) &
655 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
656
657 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
658 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
659 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
660 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
661 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
662 (ctx->bios + data_offset +
663 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
664 ATOM_ENCODER_CAP_RECORD *cap_record;
665 u16 caps = 0;
666
667 while (record->ucRecordSize > 0 &&
668 record->ucRecordType > 0 &&
669 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
670 switch (record->ucRecordType) {
671 case ATOM_ENCODER_CAP_RECORD_TYPE:
672 cap_record =(ATOM_ENCODER_CAP_RECORD *)
673 record;
674 caps = le16_to_cpu(cap_record->usEncoderCap);
675 break;
676 }
677 record = (ATOM_COMMON_RECORD_HEADER *)
678 ((char *)record + record->ucRecordSize);
679 }
680 radeon_add_atom_encoder(dev,
681 encoder_obj,
682 le16_to_cpu
683 (path->
684 usDeviceTag),
685 caps);
686 }
687 }
688 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
689 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
690 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
691 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
692 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
693 (ctx->bios + data_offset +
694 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
695 ATOM_I2C_RECORD *i2c_record;
696 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
697 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
698 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
699 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
700 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
701 (ctx->bios + data_offset +
702 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
703 u8 *num_dst_objs = (u8 *)
704 ((u8 *)router_src_dst_table + 1 +
705 (router_src_dst_table->ucNumberOfSrc * 2));
706 u16 *dst_objs = (u16 *)(num_dst_objs + 1);
707 int enum_id;
708
709 router.router_id = router_obj_id;
710 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
711 if (le16_to_cpu(path->usConnObjectId) ==
712 le16_to_cpu(dst_objs[enum_id]))
713 break;
714 }
715
716 while (record->ucRecordSize > 0 &&
717 record->ucRecordType > 0 &&
718 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
719 switch (record->ucRecordType) {
720 case ATOM_I2C_RECORD_TYPE:
721 i2c_record =
722 (ATOM_I2C_RECORD *)
723 record;
724 i2c_config =
725 (ATOM_I2C_ID_CONFIG_ACCESS *)
726 &i2c_record->sucI2cId;
727 router.i2c_info =
728 radeon_lookup_i2c_gpio(rdev,
729 i2c_config->
730 ucAccess);
731 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
732 break;
733 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
734 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
735 record;
736 router.ddc_valid = true;
737 router.ddc_mux_type = ddc_path->ucMuxType;
738 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
739 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
740 break;
741 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
742 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
743 record;
744 router.cd_valid = true;
745 router.cd_mux_type = cd_path->ucMuxType;
746 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
747 router.cd_mux_state = cd_path->ucMuxState[enum_id];
748 break;
749 }
750 record = (ATOM_COMMON_RECORD_HEADER *)
751 ((char *)record + record->ucRecordSize);
752 }
753 }
754 }
755 }
756 }
757
758 /* look up gpio for ddc, hpd */
759 ddc_bus.valid = false;
760 hpd.hpd = RADEON_HPD_NONE;
761 if ((le16_to_cpu(path->usDeviceTag) &
762 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
763 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
764 if (le16_to_cpu(path->usConnObjectId) ==
765 le16_to_cpu(con_obj->asObjects[j].
766 usObjectID)) {
767 ATOM_COMMON_RECORD_HEADER
768 *record =
769 (ATOM_COMMON_RECORD_HEADER
770 *)
771 (ctx->bios + data_offset +
772 le16_to_cpu(con_obj->
773 asObjects[j].
774 usRecordOffset));
775 ATOM_I2C_RECORD *i2c_record;
776 ATOM_HPD_INT_RECORD *hpd_record;
777 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
778
779 while (record->ucRecordSize > 0 &&
780 record->ucRecordType > 0 &&
781 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
782 switch (record->ucRecordType) {
783 case ATOM_I2C_RECORD_TYPE:
784 i2c_record =
785 (ATOM_I2C_RECORD *)
786 record;
787 i2c_config =
788 (ATOM_I2C_ID_CONFIG_ACCESS *)
789 &i2c_record->sucI2cId;
790 ddc_bus = radeon_lookup_i2c_gpio(rdev,
791 i2c_config->
792 ucAccess);
793 break;
794 case ATOM_HPD_INT_RECORD_TYPE:
795 hpd_record =
796 (ATOM_HPD_INT_RECORD *)
797 record;
798 gpio = radeon_atombios_lookup_gpio(rdev,
799 hpd_record->ucHPDIntGPIOID);
800 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
801 hpd.plugged_state = hpd_record->ucPlugged_PinState;
802 break;
803 }
804 record =
805 (ATOM_COMMON_RECORD_HEADER
806 *) ((char *)record
807 +
808 record->
809 ucRecordSize);
810 }
811 break;
812 }
813 }
814 }
815
816 /* needed for aux chan transactions */
817 ddc_bus.hpd = hpd.hpd;
818
819 conn_id = le16_to_cpu(path->usConnObjectId);
820
821 if (!radeon_atom_apply_quirks
822 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
823 &ddc_bus, &conn_id, &hpd))
824 continue;
825
826 radeon_add_atom_connector(dev,
827 conn_id,
828 le16_to_cpu(path->
829 usDeviceTag),
830 connector_type, &ddc_bus,
831 igp_lane_info,
832 connector_object_id,
833 &hpd,
834 &router);
835
836 }
837 }
838
839 radeon_link_encoder_connector(dev);
840
841 radeon_setup_mst_connector(dev);
842 return true;
843 }
844
atombios_get_connector_object_id(struct drm_device * dev,int connector_type,uint16_t devices)845 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
846 int connector_type,
847 uint16_t devices)
848 {
849 struct radeon_device *rdev = dev->dev_private;
850
851 if (rdev->flags & RADEON_IS_IGP) {
852 return supported_devices_connector_object_id_convert
853 [connector_type];
854 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
855 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
856 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
857 struct radeon_mode_info *mode_info = &rdev->mode_info;
858 struct atom_context *ctx = mode_info->atom_context;
859 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
860 uint16_t size, data_offset;
861 uint8_t frev, crev;
862 ATOM_XTMDS_INFO *xtmds;
863
864 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
865 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
866
867 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
868 if (connector_type == DRM_MODE_CONNECTOR_DVII)
869 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
870 else
871 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
872 } else {
873 if (connector_type == DRM_MODE_CONNECTOR_DVII)
874 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
875 else
876 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
877 }
878 } else
879 return supported_devices_connector_object_id_convert
880 [connector_type];
881 } else {
882 return supported_devices_connector_object_id_convert
883 [connector_type];
884 }
885 }
886
887 struct bios_connector {
888 bool valid;
889 uint16_t line_mux;
890 uint16_t devices;
891 int connector_type;
892 struct radeon_i2c_bus_rec ddc_bus;
893 struct radeon_hpd hpd;
894 };
895
radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device * dev)896 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
897 drm_device
898 *dev)
899 {
900 struct radeon_device *rdev = dev->dev_private;
901 struct radeon_mode_info *mode_info = &rdev->mode_info;
902 struct atom_context *ctx = mode_info->atom_context;
903 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
904 uint16_t size, data_offset;
905 uint8_t frev, crev;
906 uint16_t device_support;
907 uint8_t dac;
908 union atom_supported_devices *supported_devices;
909 int i, j, max_device;
910 struct bios_connector *bios_connectors;
911 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
912 struct radeon_router router;
913
914 router.ddc_valid = false;
915 router.cd_valid = false;
916
917 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
918 if (!bios_connectors)
919 return false;
920
921 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
922 &data_offset)) {
923 kfree(bios_connectors);
924 return false;
925 }
926
927 supported_devices =
928 (union atom_supported_devices *)(ctx->bios + data_offset);
929
930 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
931
932 if (frev > 1)
933 max_device = ATOM_MAX_SUPPORTED_DEVICE;
934 else
935 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
936
937 for (i = 0; i < max_device; i++) {
938 ATOM_CONNECTOR_INFO_I2C ci =
939 supported_devices->info.asConnInfo[i];
940
941 bios_connectors[i].valid = false;
942
943 if (!(device_support & (1 << i))) {
944 continue;
945 }
946
947 if (i == ATOM_DEVICE_CV_INDEX) {
948 DRM_DEBUG_KMS("Skipping Component Video\n");
949 continue;
950 }
951
952 bios_connectors[i].connector_type =
953 supported_devices_connector_convert[ci.sucConnectorInfo.
954 sbfAccess.
955 bfConnectorType];
956
957 if (bios_connectors[i].connector_type ==
958 DRM_MODE_CONNECTOR_Unknown)
959 continue;
960
961 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
962
963 bios_connectors[i].line_mux =
964 ci.sucI2cId.ucAccess;
965
966 /* give tv unique connector ids */
967 if (i == ATOM_DEVICE_TV1_INDEX) {
968 bios_connectors[i].ddc_bus.valid = false;
969 bios_connectors[i].line_mux = 50;
970 } else if (i == ATOM_DEVICE_TV2_INDEX) {
971 bios_connectors[i].ddc_bus.valid = false;
972 bios_connectors[i].line_mux = 51;
973 } else if (i == ATOM_DEVICE_CV_INDEX) {
974 bios_connectors[i].ddc_bus.valid = false;
975 bios_connectors[i].line_mux = 52;
976 } else
977 bios_connectors[i].ddc_bus =
978 radeon_lookup_i2c_gpio(rdev,
979 bios_connectors[i].line_mux);
980
981 if ((crev > 1) && (frev > 1)) {
982 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
983 switch (isb) {
984 case 0x4:
985 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
986 break;
987 case 0xa:
988 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
989 break;
990 default:
991 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
992 break;
993 }
994 } else {
995 if (i == ATOM_DEVICE_DFP1_INDEX)
996 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
997 else if (i == ATOM_DEVICE_DFP2_INDEX)
998 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
999 else
1000 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1001 }
1002
1003 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1004 * shared with a DVI port, we'll pick up the DVI connector when we
1005 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1006 */
1007 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1008 bios_connectors[i].connector_type =
1009 DRM_MODE_CONNECTOR_VGA;
1010
1011 if (!radeon_atom_apply_quirks
1012 (dev, (1 << i), &bios_connectors[i].connector_type,
1013 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1014 &bios_connectors[i].hpd))
1015 continue;
1016
1017 bios_connectors[i].valid = true;
1018 bios_connectors[i].devices = (1 << i);
1019
1020 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1021 radeon_add_atom_encoder(dev,
1022 radeon_get_encoder_enum(dev,
1023 (1 << i),
1024 dac),
1025 (1 << i),
1026 0);
1027 else
1028 radeon_add_legacy_encoder(dev,
1029 radeon_get_encoder_enum(dev,
1030 (1 << i),
1031 dac),
1032 (1 << i));
1033 }
1034
1035 /* combine shared connectors */
1036 for (i = 0; i < max_device; i++) {
1037 if (bios_connectors[i].valid) {
1038 for (j = 0; j < max_device; j++) {
1039 if (bios_connectors[j].valid && (i != j)) {
1040 if (bios_connectors[i].line_mux ==
1041 bios_connectors[j].line_mux) {
1042 /* make sure not to combine LVDS */
1043 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1044 bios_connectors[i].line_mux = 53;
1045 bios_connectors[i].ddc_bus.valid = false;
1046 continue;
1047 }
1048 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1049 bios_connectors[j].line_mux = 53;
1050 bios_connectors[j].ddc_bus.valid = false;
1051 continue;
1052 }
1053 /* combine analog and digital for DVI-I */
1054 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1055 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1056 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1057 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1058 bios_connectors[i].devices |=
1059 bios_connectors[j].devices;
1060 bios_connectors[i].connector_type =
1061 DRM_MODE_CONNECTOR_DVII;
1062 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1063 bios_connectors[i].hpd =
1064 bios_connectors[j].hpd;
1065 bios_connectors[j].valid = false;
1066 }
1067 }
1068 }
1069 }
1070 }
1071 }
1072
1073 /* add the connectors */
1074 for (i = 0; i < max_device; i++) {
1075 if (bios_connectors[i].valid) {
1076 uint16_t connector_object_id =
1077 atombios_get_connector_object_id(dev,
1078 bios_connectors[i].connector_type,
1079 bios_connectors[i].devices);
1080 radeon_add_atom_connector(dev,
1081 bios_connectors[i].line_mux,
1082 bios_connectors[i].devices,
1083 bios_connectors[i].
1084 connector_type,
1085 &bios_connectors[i].ddc_bus,
1086 0,
1087 connector_object_id,
1088 &bios_connectors[i].hpd,
1089 &router);
1090 }
1091 }
1092
1093 radeon_link_encoder_connector(dev);
1094
1095 kfree(bios_connectors);
1096 return true;
1097 }
1098
1099 union firmware_info {
1100 ATOM_FIRMWARE_INFO info;
1101 ATOM_FIRMWARE_INFO_V1_2 info_12;
1102 ATOM_FIRMWARE_INFO_V1_3 info_13;
1103 ATOM_FIRMWARE_INFO_V1_4 info_14;
1104 ATOM_FIRMWARE_INFO_V2_1 info_21;
1105 ATOM_FIRMWARE_INFO_V2_2 info_22;
1106 };
1107
1108 union igp_info {
1109 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1110 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1111 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1112 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1113 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
1114 };
1115
radeon_atombios_get_dentist_vco_freq(struct radeon_device * rdev)1116 static void radeon_atombios_get_dentist_vco_freq(struct radeon_device *rdev)
1117 {
1118 struct radeon_mode_info *mode_info = &rdev->mode_info;
1119 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1120 union igp_info *igp_info;
1121 u8 frev, crev;
1122 u16 data_offset;
1123
1124 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1125 &frev, &crev, &data_offset)) {
1126 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1127 data_offset);
1128 rdev->clock.vco_freq =
1129 le32_to_cpu(igp_info->info_6.ulDentistVCOFreq);
1130 }
1131 }
1132
radeon_atom_get_clock_info(struct drm_device * dev)1133 bool radeon_atom_get_clock_info(struct drm_device *dev)
1134 {
1135 struct radeon_device *rdev = dev->dev_private;
1136 struct radeon_mode_info *mode_info = &rdev->mode_info;
1137 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1138 union firmware_info *firmware_info;
1139 uint8_t frev, crev;
1140 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1141 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1142 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1143 struct radeon_pll *spll = &rdev->clock.spll;
1144 struct radeon_pll *mpll = &rdev->clock.mpll;
1145 uint16_t data_offset;
1146
1147 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1148 &frev, &crev, &data_offset)) {
1149 firmware_info =
1150 (union firmware_info *)(mode_info->atom_context->bios +
1151 data_offset);
1152 /* pixel clocks */
1153 p1pll->reference_freq =
1154 le16_to_cpu(firmware_info->info.usReferenceClock);
1155 p1pll->reference_div = 0;
1156
1157 if ((frev < 2) && (crev < 2))
1158 p1pll->pll_out_min =
1159 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1160 else
1161 p1pll->pll_out_min =
1162 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1163 p1pll->pll_out_max =
1164 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1165
1166 if (((frev < 2) && (crev >= 4)) || (frev >= 2)) {
1167 p1pll->lcd_pll_out_min =
1168 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1169 if (p1pll->lcd_pll_out_min == 0)
1170 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1171 p1pll->lcd_pll_out_max =
1172 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1173 if (p1pll->lcd_pll_out_max == 0)
1174 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1175 } else {
1176 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1177 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1178 }
1179
1180 if (p1pll->pll_out_min == 0) {
1181 if (ASIC_IS_AVIVO(rdev))
1182 p1pll->pll_out_min = 64800;
1183 else
1184 p1pll->pll_out_min = 20000;
1185 }
1186
1187 p1pll->pll_in_min =
1188 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1189 p1pll->pll_in_max =
1190 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1191
1192 *p2pll = *p1pll;
1193
1194 /* system clock */
1195 if (ASIC_IS_DCE4(rdev))
1196 spll->reference_freq =
1197 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1198 else
1199 spll->reference_freq =
1200 le16_to_cpu(firmware_info->info.usReferenceClock);
1201 spll->reference_div = 0;
1202
1203 spll->pll_out_min =
1204 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1205 spll->pll_out_max =
1206 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1207
1208 /* ??? */
1209 if (spll->pll_out_min == 0) {
1210 if (ASIC_IS_AVIVO(rdev))
1211 spll->pll_out_min = 64800;
1212 else
1213 spll->pll_out_min = 20000;
1214 }
1215
1216 spll->pll_in_min =
1217 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1218 spll->pll_in_max =
1219 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1220
1221 /* memory clock */
1222 if (ASIC_IS_DCE4(rdev))
1223 mpll->reference_freq =
1224 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1225 else
1226 mpll->reference_freq =
1227 le16_to_cpu(firmware_info->info.usReferenceClock);
1228 mpll->reference_div = 0;
1229
1230 mpll->pll_out_min =
1231 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1232 mpll->pll_out_max =
1233 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1234
1235 /* ??? */
1236 if (mpll->pll_out_min == 0) {
1237 if (ASIC_IS_AVIVO(rdev))
1238 mpll->pll_out_min = 64800;
1239 else
1240 mpll->pll_out_min = 20000;
1241 }
1242
1243 mpll->pll_in_min =
1244 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1245 mpll->pll_in_max =
1246 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1247
1248 rdev->clock.default_sclk =
1249 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1250 rdev->clock.default_mclk =
1251 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1252
1253 if (ASIC_IS_DCE4(rdev)) {
1254 rdev->clock.default_dispclk =
1255 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1256 if (rdev->clock.default_dispclk == 0) {
1257 if (ASIC_IS_DCE6(rdev))
1258 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1259 else if (ASIC_IS_DCE5(rdev))
1260 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1261 else
1262 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1263 }
1264 /* set a reasonable default for DP */
1265 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
1266 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
1267 rdev->clock.default_dispclk / 100);
1268 rdev->clock.default_dispclk = 60000;
1269 }
1270 rdev->clock.dp_extclk =
1271 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1272 rdev->clock.current_dispclk = rdev->clock.default_dispclk;
1273 }
1274 *dcpll = *p1pll;
1275
1276 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1277 if (rdev->clock.max_pixel_clock == 0)
1278 rdev->clock.max_pixel_clock = 40000;
1279
1280 /* not technically a clock, but... */
1281 rdev->mode_info.firmware_flags =
1282 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1283
1284 if (ASIC_IS_DCE8(rdev))
1285 rdev->clock.vco_freq =
1286 le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq);
1287 else if (ASIC_IS_DCE5(rdev))
1288 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1289 else if (ASIC_IS_DCE41(rdev))
1290 radeon_atombios_get_dentist_vco_freq(rdev);
1291 else
1292 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1293
1294 if (rdev->clock.vco_freq == 0)
1295 rdev->clock.vco_freq = 360000; /* 3.6 GHz */
1296
1297 return true;
1298 }
1299
1300 return false;
1301 }
1302
radeon_atombios_sideport_present(struct radeon_device * rdev)1303 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1304 {
1305 struct radeon_mode_info *mode_info = &rdev->mode_info;
1306 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1307 union igp_info *igp_info;
1308 u8 frev, crev;
1309 u16 data_offset;
1310
1311 /* sideport is AMD only */
1312 if (rdev->family == CHIP_RS600)
1313 return false;
1314
1315 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1316 &frev, &crev, &data_offset)) {
1317 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1318 data_offset);
1319 switch (crev) {
1320 case 1:
1321 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1322 return true;
1323 break;
1324 case 2:
1325 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1326 return true;
1327 break;
1328 default:
1329 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1330 break;
1331 }
1332 }
1333 return false;
1334 }
1335
radeon_atombios_get_tmds_info(struct radeon_encoder * encoder,struct radeon_encoder_int_tmds * tmds)1336 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1337 struct radeon_encoder_int_tmds *tmds)
1338 {
1339 struct drm_device *dev = encoder->base.dev;
1340 struct radeon_device *rdev = dev->dev_private;
1341 struct radeon_mode_info *mode_info = &rdev->mode_info;
1342 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1343 uint16_t data_offset;
1344 struct _ATOM_TMDS_INFO *tmds_info;
1345 uint8_t frev, crev;
1346 uint16_t maxfreq;
1347 int i;
1348
1349 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1350 &frev, &crev, &data_offset)) {
1351 tmds_info =
1352 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1353 data_offset);
1354
1355 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1356 for (i = 0; i < 4; i++) {
1357 tmds->tmds_pll[i].freq =
1358 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1359 tmds->tmds_pll[i].value =
1360 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1361 tmds->tmds_pll[i].value |=
1362 (tmds_info->asMiscInfo[i].
1363 ucPLL_VCO_Gain & 0x3f) << 6;
1364 tmds->tmds_pll[i].value |=
1365 (tmds_info->asMiscInfo[i].
1366 ucPLL_DutyCycle & 0xf) << 12;
1367 tmds->tmds_pll[i].value |=
1368 (tmds_info->asMiscInfo[i].
1369 ucPLL_VoltageSwing & 0xf) << 16;
1370
1371 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1372 tmds->tmds_pll[i].freq,
1373 tmds->tmds_pll[i].value);
1374
1375 if (maxfreq == tmds->tmds_pll[i].freq) {
1376 tmds->tmds_pll[i].freq = 0xffffffff;
1377 break;
1378 }
1379 }
1380 return true;
1381 }
1382 return false;
1383 }
1384
radeon_atombios_get_ppll_ss_info(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id)1385 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1386 struct radeon_atom_ss *ss,
1387 int id)
1388 {
1389 struct radeon_mode_info *mode_info = &rdev->mode_info;
1390 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1391 uint16_t data_offset, size;
1392 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1393 struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign;
1394 uint8_t frev, crev;
1395 int i, num_indices;
1396
1397 memset(ss, 0, sizeof(struct radeon_atom_ss));
1398 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1399 &frev, &crev, &data_offset)) {
1400 ss_info =
1401 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1402
1403 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1404 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1405 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1406 ((u8 *)&ss_info->asSS_Info[0]);
1407 for (i = 0; i < num_indices; i++) {
1408 if (ss_assign->ucSS_Id == id) {
1409 ss->percentage =
1410 le16_to_cpu(ss_assign->usSpreadSpectrumPercentage);
1411 ss->type = ss_assign->ucSpreadSpectrumType;
1412 ss->step = ss_assign->ucSS_Step;
1413 ss->delay = ss_assign->ucSS_Delay;
1414 ss->range = ss_assign->ucSS_Range;
1415 ss->refdiv = ss_assign->ucRecommendedRef_Div;
1416 return true;
1417 }
1418 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1419 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT));
1420 }
1421 }
1422 return false;
1423 }
1424
radeon_atombios_get_igp_ss_overrides(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id)1425 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1426 struct radeon_atom_ss *ss,
1427 int id)
1428 {
1429 struct radeon_mode_info *mode_info = &rdev->mode_info;
1430 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1431 u16 data_offset, size;
1432 union igp_info *igp_info;
1433 u8 frev, crev;
1434 u16 percentage = 0, rate = 0;
1435
1436 /* get any igp specific overrides */
1437 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1438 &frev, &crev, &data_offset)) {
1439 igp_info = (union igp_info *)
1440 (mode_info->atom_context->bios + data_offset);
1441 switch (crev) {
1442 case 6:
1443 switch (id) {
1444 case ASIC_INTERNAL_SS_ON_TMDS:
1445 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1446 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1447 break;
1448 case ASIC_INTERNAL_SS_ON_HDMI:
1449 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1450 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1451 break;
1452 case ASIC_INTERNAL_SS_ON_LVDS:
1453 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1454 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1455 break;
1456 }
1457 break;
1458 case 7:
1459 switch (id) {
1460 case ASIC_INTERNAL_SS_ON_TMDS:
1461 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1462 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1463 break;
1464 case ASIC_INTERNAL_SS_ON_HDMI:
1465 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1466 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1467 break;
1468 case ASIC_INTERNAL_SS_ON_LVDS:
1469 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1470 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1471 break;
1472 }
1473 break;
1474 case 8:
1475 switch (id) {
1476 case ASIC_INTERNAL_SS_ON_TMDS:
1477 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
1478 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
1479 break;
1480 case ASIC_INTERNAL_SS_ON_HDMI:
1481 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
1482 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
1483 break;
1484 case ASIC_INTERNAL_SS_ON_LVDS:
1485 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
1486 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
1487 break;
1488 }
1489 break;
1490 default:
1491 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1492 break;
1493 }
1494 if (percentage)
1495 ss->percentage = percentage;
1496 if (rate)
1497 ss->rate = rate;
1498 }
1499 }
1500
1501 union asic_ss_info {
1502 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1503 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1504 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1505 };
1506
1507 union asic_ss_assignment {
1508 struct _ATOM_ASIC_SS_ASSIGNMENT v1;
1509 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
1510 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
1511 };
1512
radeon_atombios_get_asic_ss_info(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id,u32 clock)1513 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1514 struct radeon_atom_ss *ss,
1515 int id, u32 clock)
1516 {
1517 struct radeon_mode_info *mode_info = &rdev->mode_info;
1518 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1519 uint16_t data_offset, size;
1520 union asic_ss_info *ss_info;
1521 union asic_ss_assignment *ss_assign;
1522 uint8_t frev, crev;
1523 int i, num_indices;
1524
1525 if (id == ASIC_INTERNAL_MEMORY_SS) {
1526 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
1527 return false;
1528 }
1529 if (id == ASIC_INTERNAL_ENGINE_SS) {
1530 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
1531 return false;
1532 }
1533
1534 memset(ss, 0, sizeof(struct radeon_atom_ss));
1535 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1536 &frev, &crev, &data_offset)) {
1537
1538 ss_info =
1539 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1540
1541 switch (frev) {
1542 case 1:
1543 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1544 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1545
1546 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
1547 for (i = 0; i < num_indices; i++) {
1548 if ((ss_assign->v1.ucClockIndication == id) &&
1549 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
1550 ss->percentage =
1551 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
1552 ss->type = ss_assign->v1.ucSpreadSpectrumMode;
1553 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
1554 ss->percentage_divider = 100;
1555 return true;
1556 }
1557 ss_assign = (union asic_ss_assignment *)
1558 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
1559 }
1560 break;
1561 case 2:
1562 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1563 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1564 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
1565 for (i = 0; i < num_indices; i++) {
1566 if ((ss_assign->v2.ucClockIndication == id) &&
1567 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
1568 ss->percentage =
1569 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
1570 ss->type = ss_assign->v2.ucSpreadSpectrumMode;
1571 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
1572 ss->percentage_divider = 100;
1573 if ((crev == 2) &&
1574 ((id == ASIC_INTERNAL_ENGINE_SS) ||
1575 (id == ASIC_INTERNAL_MEMORY_SS)))
1576 ss->rate /= 100;
1577 return true;
1578 }
1579 ss_assign = (union asic_ss_assignment *)
1580 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
1581 }
1582 break;
1583 case 3:
1584 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1585 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1586 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
1587 for (i = 0; i < num_indices; i++) {
1588 if ((ss_assign->v3.ucClockIndication == id) &&
1589 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
1590 ss->percentage =
1591 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
1592 ss->type = ss_assign->v3.ucSpreadSpectrumMode;
1593 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
1594 if (ss_assign->v3.ucSpreadSpectrumMode &
1595 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
1596 ss->percentage_divider = 1000;
1597 else
1598 ss->percentage_divider = 100;
1599 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
1600 (id == ASIC_INTERNAL_MEMORY_SS))
1601 ss->rate /= 100;
1602 if (rdev->flags & RADEON_IS_IGP)
1603 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1604 return true;
1605 }
1606 ss_assign = (union asic_ss_assignment *)
1607 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
1608 }
1609 break;
1610 default:
1611 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1612 break;
1613 }
1614
1615 }
1616 return false;
1617 }
1618
1619 union lvds_info {
1620 struct _ATOM_LVDS_INFO info;
1621 struct _ATOM_LVDS_INFO_V12 info_12;
1622 };
1623
radeon_atombios_get_lvds_info(struct radeon_encoder * encoder)1624 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1625 radeon_encoder
1626 *encoder)
1627 {
1628 struct drm_device *dev = encoder->base.dev;
1629 struct radeon_device *rdev = dev->dev_private;
1630 struct radeon_mode_info *mode_info = &rdev->mode_info;
1631 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1632 uint16_t data_offset, misc;
1633 union lvds_info *lvds_info;
1634 uint8_t frev, crev;
1635 struct radeon_encoder_atom_dig *lvds = NULL;
1636 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1637
1638 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1639 &frev, &crev, &data_offset)) {
1640 lvds_info =
1641 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1642 lvds =
1643 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1644
1645 if (!lvds)
1646 return NULL;
1647
1648 lvds->native_mode.clock =
1649 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1650 lvds->native_mode.hdisplay =
1651 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1652 lvds->native_mode.vdisplay =
1653 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1654 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1655 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1656 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1657 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1658 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1659 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1660 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1661 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1662 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1663 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1664 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1665 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1666 lvds->panel_pwr_delay =
1667 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1668 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1669
1670 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1671 if (misc & ATOM_VSYNC_POLARITY)
1672 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1673 if (misc & ATOM_HSYNC_POLARITY)
1674 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1675 if (misc & ATOM_COMPOSITESYNC)
1676 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1677 if (misc & ATOM_INTERLACE)
1678 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1679 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1680 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1681
1682 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1683 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1684
1685 /* set crtc values */
1686 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1687
1688 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1689
1690 encoder->native_mode = lvds->native_mode;
1691
1692 if (encoder_enum == 2)
1693 lvds->linkb = true;
1694 else
1695 lvds->linkb = false;
1696
1697 /* parse the lcd record table */
1698 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1699 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1700 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1701 bool bad_record = false;
1702 u8 *record;
1703
1704 if ((frev == 1) && (crev < 2))
1705 /* absolute */
1706 record = (u8 *)(mode_info->atom_context->bios +
1707 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1708 else
1709 /* relative */
1710 record = (u8 *)(mode_info->atom_context->bios +
1711 data_offset +
1712 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1713 while (*record != ATOM_RECORD_END_TYPE) {
1714 switch (*record) {
1715 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1716 record += sizeof(ATOM_PATCH_RECORD_MODE);
1717 break;
1718 case LCD_RTS_RECORD_TYPE:
1719 record += sizeof(ATOM_LCD_RTS_RECORD);
1720 break;
1721 case LCD_CAP_RECORD_TYPE:
1722 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1723 break;
1724 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1725 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1726 if (fake_edid_record->ucFakeEDIDLength) {
1727 struct edid *edid;
1728 int edid_size =
1729 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1730 edid = kmalloc(edid_size, GFP_KERNEL);
1731 if (edid) {
1732 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1733 fake_edid_record->ucFakeEDIDLength);
1734
1735 if (drm_edid_is_valid(edid)) {
1736 rdev->mode_info.bios_hardcoded_edid = edid;
1737 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1738 } else
1739 kfree(edid);
1740 }
1741 }
1742 record += fake_edid_record->ucFakeEDIDLength ?
1743 fake_edid_record->ucFakeEDIDLength + 2 :
1744 sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1745 break;
1746 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1747 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1748 lvds->native_mode.width_mm = panel_res_record->usHSize;
1749 lvds->native_mode.height_mm = panel_res_record->usVSize;
1750 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1751 break;
1752 default:
1753 DRM_ERROR("Bad LCD record %d\n", *record);
1754 bad_record = true;
1755 break;
1756 }
1757 if (bad_record)
1758 break;
1759 }
1760 }
1761 }
1762 return lvds;
1763 }
1764
1765 struct radeon_encoder_primary_dac *
radeon_atombios_get_primary_dac_info(struct radeon_encoder * encoder)1766 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1767 {
1768 struct drm_device *dev = encoder->base.dev;
1769 struct radeon_device *rdev = dev->dev_private;
1770 struct radeon_mode_info *mode_info = &rdev->mode_info;
1771 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1772 uint16_t data_offset;
1773 struct _COMPASSIONATE_DATA *dac_info;
1774 uint8_t frev, crev;
1775 uint8_t bg, dac;
1776 struct radeon_encoder_primary_dac *p_dac = NULL;
1777
1778 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1779 &frev, &crev, &data_offset)) {
1780 dac_info = (struct _COMPASSIONATE_DATA *)
1781 (mode_info->atom_context->bios + data_offset);
1782
1783 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1784
1785 if (!p_dac)
1786 return NULL;
1787
1788 bg = dac_info->ucDAC1_BG_Adjustment;
1789 dac = dac_info->ucDAC1_DAC_Adjustment;
1790 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1791
1792 }
1793 return p_dac;
1794 }
1795
radeon_atom_get_tv_timings(struct radeon_device * rdev,int index,struct drm_display_mode * mode)1796 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1797 struct drm_display_mode *mode)
1798 {
1799 struct radeon_mode_info *mode_info = &rdev->mode_info;
1800 ATOM_ANALOG_TV_INFO *tv_info;
1801 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1802 ATOM_DTD_FORMAT *dtd_timings;
1803 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1804 u8 frev, crev;
1805 u16 data_offset, misc;
1806
1807 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1808 &frev, &crev, &data_offset))
1809 return false;
1810
1811 switch (crev) {
1812 case 1:
1813 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1814 if (index >= MAX_SUPPORTED_TV_TIMING)
1815 return false;
1816
1817 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1818 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1819 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1820 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1821 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1822
1823 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1824 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1825 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1826 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1827 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1828
1829 mode->flags = 0;
1830 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1831 if (misc & ATOM_VSYNC_POLARITY)
1832 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1833 if (misc & ATOM_HSYNC_POLARITY)
1834 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1835 if (misc & ATOM_COMPOSITESYNC)
1836 mode->flags |= DRM_MODE_FLAG_CSYNC;
1837 if (misc & ATOM_INTERLACE)
1838 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1839 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1840 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1841
1842 mode->crtc_clock = mode->clock =
1843 le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1844
1845 if (index == 1) {
1846 /* PAL timings appear to have wrong values for totals */
1847 mode->crtc_htotal -= 1;
1848 mode->crtc_vtotal -= 1;
1849 }
1850 break;
1851 case 2:
1852 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1853 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1854 return false;
1855
1856 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1857 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1858 le16_to_cpu(dtd_timings->usHBlanking_Time);
1859 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1860 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1861 le16_to_cpu(dtd_timings->usHSyncOffset);
1862 mode->crtc_hsync_end = mode->crtc_hsync_start +
1863 le16_to_cpu(dtd_timings->usHSyncWidth);
1864
1865 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1866 le16_to_cpu(dtd_timings->usVBlanking_Time);
1867 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1868 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1869 le16_to_cpu(dtd_timings->usVSyncOffset);
1870 mode->crtc_vsync_end = mode->crtc_vsync_start +
1871 le16_to_cpu(dtd_timings->usVSyncWidth);
1872
1873 mode->flags = 0;
1874 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1875 if (misc & ATOM_VSYNC_POLARITY)
1876 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1877 if (misc & ATOM_HSYNC_POLARITY)
1878 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1879 if (misc & ATOM_COMPOSITESYNC)
1880 mode->flags |= DRM_MODE_FLAG_CSYNC;
1881 if (misc & ATOM_INTERLACE)
1882 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1883 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1884 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1885
1886 mode->crtc_clock = mode->clock =
1887 le16_to_cpu(dtd_timings->usPixClk) * 10;
1888 break;
1889 }
1890 return true;
1891 }
1892
1893 enum radeon_tv_std
radeon_atombios_get_tv_info(struct radeon_device * rdev)1894 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1895 {
1896 struct radeon_mode_info *mode_info = &rdev->mode_info;
1897 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1898 uint16_t data_offset;
1899 uint8_t frev, crev;
1900 struct _ATOM_ANALOG_TV_INFO *tv_info;
1901 enum radeon_tv_std tv_std = TV_STD_NTSC;
1902
1903 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1904 &frev, &crev, &data_offset)) {
1905
1906 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1907 (mode_info->atom_context->bios + data_offset);
1908
1909 switch (tv_info->ucTV_BootUpDefaultStandard) {
1910 case ATOM_TV_NTSC:
1911 tv_std = TV_STD_NTSC;
1912 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1913 break;
1914 case ATOM_TV_NTSCJ:
1915 tv_std = TV_STD_NTSC_J;
1916 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1917 break;
1918 case ATOM_TV_PAL:
1919 tv_std = TV_STD_PAL;
1920 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1921 break;
1922 case ATOM_TV_PALM:
1923 tv_std = TV_STD_PAL_M;
1924 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1925 break;
1926 case ATOM_TV_PALN:
1927 tv_std = TV_STD_PAL_N;
1928 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1929 break;
1930 case ATOM_TV_PALCN:
1931 tv_std = TV_STD_PAL_CN;
1932 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1933 break;
1934 case ATOM_TV_PAL60:
1935 tv_std = TV_STD_PAL_60;
1936 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1937 break;
1938 case ATOM_TV_SECAM:
1939 tv_std = TV_STD_SECAM;
1940 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1941 break;
1942 default:
1943 tv_std = TV_STD_NTSC;
1944 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1945 break;
1946 }
1947 }
1948 return tv_std;
1949 }
1950
1951 struct radeon_encoder_tv_dac *
radeon_atombios_get_tv_dac_info(struct radeon_encoder * encoder)1952 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1953 {
1954 struct drm_device *dev = encoder->base.dev;
1955 struct radeon_device *rdev = dev->dev_private;
1956 struct radeon_mode_info *mode_info = &rdev->mode_info;
1957 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1958 uint16_t data_offset;
1959 struct _COMPASSIONATE_DATA *dac_info;
1960 uint8_t frev, crev;
1961 uint8_t bg, dac;
1962 struct radeon_encoder_tv_dac *tv_dac = NULL;
1963
1964 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1965 &frev, &crev, &data_offset)) {
1966
1967 dac_info = (struct _COMPASSIONATE_DATA *)
1968 (mode_info->atom_context->bios + data_offset);
1969
1970 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1971
1972 if (!tv_dac)
1973 return NULL;
1974
1975 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1976 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1977 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1978
1979 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1980 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1981 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1982
1983 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1984 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1985 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1986
1987 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1988 }
1989 return tv_dac;
1990 }
1991
1992 static const char *thermal_controller_names[] = {
1993 "NONE",
1994 "lm63",
1995 "adm1032",
1996 "adm1030",
1997 "max6649",
1998 "lm63", /* lm64 */
1999 "f75375",
2000 "asc7xxx",
2001 };
2002
2003 static const char *pp_lib_thermal_controller_names[] = {
2004 "NONE",
2005 "lm63",
2006 "adm1032",
2007 "adm1030",
2008 "max6649",
2009 "lm63", /* lm64 */
2010 "f75375",
2011 "RV6xx",
2012 "RV770",
2013 "adt7473",
2014 "NONE",
2015 "External GPIO",
2016 "Evergreen",
2017 "emc2103",
2018 "Sumo",
2019 "Northern Islands",
2020 "Southern Islands",
2021 "lm96163",
2022 "Sea Islands",
2023 };
2024
2025 union power_info {
2026 struct _ATOM_POWERPLAY_INFO info;
2027 struct _ATOM_POWERPLAY_INFO_V2 info_2;
2028 struct _ATOM_POWERPLAY_INFO_V3 info_3;
2029 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2030 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2031 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2032 };
2033
2034 union pplib_clock_info {
2035 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2036 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2037 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2038 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2039 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
2040 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
2041 };
2042
2043 union pplib_power_state {
2044 struct _ATOM_PPLIB_STATE v1;
2045 struct _ATOM_PPLIB_STATE_V2 v2;
2046 };
2047
radeon_atombios_parse_misc_flags_1_3(struct radeon_device * rdev,int state_index,u32 misc,u32 misc2)2048 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
2049 int state_index,
2050 u32 misc, u32 misc2)
2051 {
2052 rdev->pm.power_state[state_index].misc = misc;
2053 rdev->pm.power_state[state_index].misc2 = misc2;
2054 /* order matters! */
2055 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
2056 rdev->pm.power_state[state_index].type =
2057 POWER_STATE_TYPE_POWERSAVE;
2058 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
2059 rdev->pm.power_state[state_index].type =
2060 POWER_STATE_TYPE_BATTERY;
2061 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
2062 rdev->pm.power_state[state_index].type =
2063 POWER_STATE_TYPE_BATTERY;
2064 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
2065 rdev->pm.power_state[state_index].type =
2066 POWER_STATE_TYPE_BALANCED;
2067 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
2068 rdev->pm.power_state[state_index].type =
2069 POWER_STATE_TYPE_PERFORMANCE;
2070 rdev->pm.power_state[state_index].flags &=
2071 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2072 }
2073 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
2074 rdev->pm.power_state[state_index].type =
2075 POWER_STATE_TYPE_BALANCED;
2076 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
2077 rdev->pm.power_state[state_index].type =
2078 POWER_STATE_TYPE_DEFAULT;
2079 rdev->pm.default_power_state_index = state_index;
2080 rdev->pm.power_state[state_index].default_clock_mode =
2081 &rdev->pm.power_state[state_index].clock_info[0];
2082 } else if (state_index == 0) {
2083 rdev->pm.power_state[state_index].clock_info[0].flags |=
2084 RADEON_PM_MODE_NO_DISPLAY;
2085 }
2086 }
2087
radeon_atombios_parse_power_table_1_3(struct radeon_device * rdev)2088 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2089 {
2090 struct radeon_mode_info *mode_info = &rdev->mode_info;
2091 u32 misc, misc2 = 0;
2092 int num_modes = 0, i;
2093 int state_index = 0;
2094 struct radeon_i2c_bus_rec i2c_bus;
2095 union power_info *power_info;
2096 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2097 u16 data_offset;
2098 u8 frev, crev;
2099
2100 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2101 &frev, &crev, &data_offset))
2102 return state_index;
2103 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2104
2105 /* add the i2c bus for thermal/fan chip */
2106 if ((power_info->info.ucOverdriveThermalController > 0) &&
2107 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
2108 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2109 thermal_controller_names[power_info->info.ucOverdriveThermalController],
2110 power_info->info.ucOverdriveControllerAddress >> 1);
2111 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2112 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2113 if (rdev->pm.i2c_bus) {
2114 struct i2c_board_info info = { };
2115 const char *name = thermal_controller_names[power_info->info.
2116 ucOverdriveThermalController];
2117 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2118 strlcpy(info.type, name, sizeof(info.type));
2119 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2120 }
2121 }
2122 num_modes = power_info->info.ucNumOfPowerModeEntries;
2123 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2124 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2125 if (num_modes == 0)
2126 return state_index;
2127 rdev->pm.power_state = kcalloc(num_modes,
2128 sizeof(struct radeon_power_state),
2129 GFP_KERNEL);
2130 if (!rdev->pm.power_state)
2131 return state_index;
2132 /* last mode is usually default, array is low to high */
2133 for (i = 0; i < num_modes; i++) {
2134 rdev->pm.power_state[state_index].clock_info =
2135 kcalloc(1, sizeof(struct radeon_pm_clock_info),
2136 GFP_KERNEL);
2137 if (!rdev->pm.power_state[state_index].clock_info)
2138 return state_index;
2139 rdev->pm.power_state[state_index].num_clock_modes = 1;
2140 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2141 switch (frev) {
2142 case 1:
2143 rdev->pm.power_state[state_index].clock_info[0].mclk =
2144 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2145 rdev->pm.power_state[state_index].clock_info[0].sclk =
2146 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2147 /* skip invalid modes */
2148 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2149 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2150 continue;
2151 rdev->pm.power_state[state_index].pcie_lanes =
2152 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2153 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2154 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2155 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2156 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2157 VOLTAGE_GPIO;
2158 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2159 radeon_atombios_lookup_gpio(rdev,
2160 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2161 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2162 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2163 true;
2164 else
2165 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2166 false;
2167 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2168 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2169 VOLTAGE_VDDC;
2170 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2171 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2172 }
2173 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2174 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2175 state_index++;
2176 break;
2177 case 2:
2178 rdev->pm.power_state[state_index].clock_info[0].mclk =
2179 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2180 rdev->pm.power_state[state_index].clock_info[0].sclk =
2181 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2182 /* skip invalid modes */
2183 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2184 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2185 continue;
2186 rdev->pm.power_state[state_index].pcie_lanes =
2187 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2188 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2189 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2190 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2191 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2192 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2193 VOLTAGE_GPIO;
2194 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2195 radeon_atombios_lookup_gpio(rdev,
2196 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2197 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2198 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2199 true;
2200 else
2201 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2202 false;
2203 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2204 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2205 VOLTAGE_VDDC;
2206 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2207 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2208 }
2209 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2210 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2211 state_index++;
2212 break;
2213 case 3:
2214 rdev->pm.power_state[state_index].clock_info[0].mclk =
2215 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2216 rdev->pm.power_state[state_index].clock_info[0].sclk =
2217 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2218 /* skip invalid modes */
2219 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2220 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2221 continue;
2222 rdev->pm.power_state[state_index].pcie_lanes =
2223 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2224 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2225 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2226 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2227 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2228 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2229 VOLTAGE_GPIO;
2230 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2231 radeon_atombios_lookup_gpio(rdev,
2232 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2233 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2234 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2235 true;
2236 else
2237 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2238 false;
2239 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2240 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2241 VOLTAGE_VDDC;
2242 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2243 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2244 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2245 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2246 true;
2247 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2248 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2249 }
2250 }
2251 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2252 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2253 state_index++;
2254 break;
2255 }
2256 }
2257 /* last mode is usually default */
2258 if (rdev->pm.default_power_state_index == -1) {
2259 rdev->pm.power_state[state_index - 1].type =
2260 POWER_STATE_TYPE_DEFAULT;
2261 rdev->pm.default_power_state_index = state_index - 1;
2262 rdev->pm.power_state[state_index - 1].default_clock_mode =
2263 &rdev->pm.power_state[state_index - 1].clock_info[0];
2264 rdev->pm.power_state[state_index].flags &=
2265 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2266 rdev->pm.power_state[state_index].misc = 0;
2267 rdev->pm.power_state[state_index].misc2 = 0;
2268 }
2269 return state_index;
2270 }
2271
radeon_atombios_add_pplib_thermal_controller(struct radeon_device * rdev,ATOM_PPLIB_THERMALCONTROLLER * controller)2272 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2273 ATOM_PPLIB_THERMALCONTROLLER *controller)
2274 {
2275 struct radeon_i2c_bus_rec i2c_bus;
2276
2277 /* add the i2c bus for thermal/fan chip */
2278 if (controller->ucType > 0) {
2279 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN)
2280 rdev->pm.no_fan = true;
2281 rdev->pm.fan_pulses_per_revolution =
2282 controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
2283 if (rdev->pm.fan_pulses_per_revolution) {
2284 rdev->pm.fan_min_rpm = controller->ucFanMinRPM;
2285 rdev->pm.fan_max_rpm = controller->ucFanMaxRPM;
2286 }
2287 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2288 DRM_INFO("Internal thermal controller %s fan control\n",
2289 (controller->ucFanParameters &
2290 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2291 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2292 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2293 DRM_INFO("Internal thermal controller %s fan control\n",
2294 (controller->ucFanParameters &
2295 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2296 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2297 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2298 DRM_INFO("Internal thermal controller %s fan control\n",
2299 (controller->ucFanParameters &
2300 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2301 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2302 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2303 DRM_INFO("Internal thermal controller %s fan control\n",
2304 (controller->ucFanParameters &
2305 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2306 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2307 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2308 DRM_INFO("Internal thermal controller %s fan control\n",
2309 (controller->ucFanParameters &
2310 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2311 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2312 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2313 DRM_INFO("Internal thermal controller %s fan control\n",
2314 (controller->ucFanParameters &
2315 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2316 rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2317 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
2318 DRM_INFO("Internal thermal controller %s fan control\n",
2319 (controller->ucFanParameters &
2320 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2321 rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
2322 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) {
2323 DRM_INFO("Internal thermal controller %s fan control\n",
2324 (controller->ucFanParameters &
2325 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2326 rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
2327 } else if (controller->ucType ==
2328 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) {
2329 DRM_INFO("External GPIO thermal controller %s fan control\n",
2330 (controller->ucFanParameters &
2331 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2332 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
2333 } else if (controller->ucType ==
2334 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) {
2335 DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
2336 (controller->ucFanParameters &
2337 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2338 rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
2339 } else if (controller->ucType ==
2340 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
2341 DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
2342 (controller->ucFanParameters &
2343 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2344 rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
2345 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2346 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2347 pp_lib_thermal_controller_names[controller->ucType],
2348 controller->ucI2cAddress >> 1,
2349 (controller->ucFanParameters &
2350 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2351 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
2352 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2353 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2354 if (rdev->pm.i2c_bus) {
2355 struct i2c_board_info info = { };
2356 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2357 info.addr = controller->ucI2cAddress >> 1;
2358 strlcpy(info.type, name, sizeof(info.type));
2359 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2360 }
2361 } else {
2362 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2363 controller->ucType,
2364 controller->ucI2cAddress >> 1,
2365 (controller->ucFanParameters &
2366 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2367 }
2368 }
2369 }
2370
radeon_atombios_get_default_voltages(struct radeon_device * rdev,u16 * vddc,u16 * vddci,u16 * mvdd)2371 void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2372 u16 *vddc, u16 *vddci, u16 *mvdd)
2373 {
2374 struct radeon_mode_info *mode_info = &rdev->mode_info;
2375 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2376 u8 frev, crev;
2377 u16 data_offset;
2378 union firmware_info *firmware_info;
2379
2380 *vddc = 0;
2381 *vddci = 0;
2382 *mvdd = 0;
2383
2384 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2385 &frev, &crev, &data_offset)) {
2386 firmware_info =
2387 (union firmware_info *)(mode_info->atom_context->bios +
2388 data_offset);
2389 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2390 if ((frev == 2) && (crev >= 2)) {
2391 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2392 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
2393 }
2394 }
2395 }
2396
radeon_atombios_parse_pplib_non_clock_info(struct radeon_device * rdev,int state_index,int mode_index,struct _ATOM_PPLIB_NONCLOCK_INFO * non_clock_info)2397 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2398 int state_index, int mode_index,
2399 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2400 {
2401 int j;
2402 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2403 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2404 u16 vddc, vddci, mvdd;
2405
2406 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
2407
2408 rdev->pm.power_state[state_index].misc = misc;
2409 rdev->pm.power_state[state_index].misc2 = misc2;
2410 rdev->pm.power_state[state_index].pcie_lanes =
2411 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2412 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2413 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2414 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2415 rdev->pm.power_state[state_index].type =
2416 POWER_STATE_TYPE_BATTERY;
2417 break;
2418 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2419 rdev->pm.power_state[state_index].type =
2420 POWER_STATE_TYPE_BALANCED;
2421 break;
2422 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2423 rdev->pm.power_state[state_index].type =
2424 POWER_STATE_TYPE_PERFORMANCE;
2425 break;
2426 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2427 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2428 rdev->pm.power_state[state_index].type =
2429 POWER_STATE_TYPE_PERFORMANCE;
2430 break;
2431 }
2432 rdev->pm.power_state[state_index].flags = 0;
2433 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2434 rdev->pm.power_state[state_index].flags |=
2435 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2436 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2437 rdev->pm.power_state[state_index].type =
2438 POWER_STATE_TYPE_DEFAULT;
2439 rdev->pm.default_power_state_index = state_index;
2440 rdev->pm.power_state[state_index].default_clock_mode =
2441 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2442 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2443 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2444 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2445 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2446 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2447 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2448 } else {
2449 u16 max_vddci = 0;
2450
2451 if (ASIC_IS_DCE4(rdev))
2452 radeon_atom_get_max_voltage(rdev,
2453 SET_VOLTAGE_TYPE_ASIC_VDDCI,
2454 &max_vddci);
2455 /* patch the table values with the default sclk/mclk from firmware info */
2456 for (j = 0; j < mode_index; j++) {
2457 rdev->pm.power_state[state_index].clock_info[j].mclk =
2458 rdev->clock.default_mclk;
2459 rdev->pm.power_state[state_index].clock_info[j].sclk =
2460 rdev->clock.default_sclk;
2461 if (vddc)
2462 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2463 vddc;
2464 if (max_vddci)
2465 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2466 max_vddci;
2467 }
2468 }
2469 }
2470 }
2471
radeon_atombios_parse_pplib_clock_info(struct radeon_device * rdev,int state_index,int mode_index,union pplib_clock_info * clock_info)2472 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2473 int state_index, int mode_index,
2474 union pplib_clock_info *clock_info)
2475 {
2476 u32 sclk, mclk;
2477 u16 vddc;
2478
2479 if (rdev->flags & RADEON_IS_IGP) {
2480 if (rdev->family >= CHIP_PALM) {
2481 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2482 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2483 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2484 } else {
2485 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2486 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2487 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2488 }
2489 } else if (rdev->family >= CHIP_BONAIRE) {
2490 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
2491 sclk |= clock_info->ci.ucEngineClockHigh << 16;
2492 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
2493 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
2494 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2495 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2496 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2497 VOLTAGE_NONE;
2498 } else if (rdev->family >= CHIP_TAHITI) {
2499 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2500 sclk |= clock_info->si.ucEngineClockHigh << 16;
2501 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2502 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2503 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2504 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2505 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2506 VOLTAGE_SW;
2507 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2508 le16_to_cpu(clock_info->si.usVDDC);
2509 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2510 le16_to_cpu(clock_info->si.usVDDCI);
2511 } else if (rdev->family >= CHIP_CEDAR) {
2512 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2513 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2514 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2515 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2516 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2517 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2518 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2519 VOLTAGE_SW;
2520 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2521 le16_to_cpu(clock_info->evergreen.usVDDC);
2522 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2523 le16_to_cpu(clock_info->evergreen.usVDDCI);
2524 } else {
2525 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2526 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2527 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2528 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2529 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2530 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2531 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2532 VOLTAGE_SW;
2533 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2534 le16_to_cpu(clock_info->r600.usVDDC);
2535 }
2536
2537 /* patch up vddc if necessary */
2538 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2539 case ATOM_VIRTUAL_VOLTAGE_ID0:
2540 case ATOM_VIRTUAL_VOLTAGE_ID1:
2541 case ATOM_VIRTUAL_VOLTAGE_ID2:
2542 case ATOM_VIRTUAL_VOLTAGE_ID3:
2543 case ATOM_VIRTUAL_VOLTAGE_ID4:
2544 case ATOM_VIRTUAL_VOLTAGE_ID5:
2545 case ATOM_VIRTUAL_VOLTAGE_ID6:
2546 case ATOM_VIRTUAL_VOLTAGE_ID7:
2547 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2548 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2549 &vddc) == 0)
2550 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2551 break;
2552 default:
2553 break;
2554 }
2555
2556 if (rdev->flags & RADEON_IS_IGP) {
2557 /* skip invalid modes */
2558 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2559 return false;
2560 } else {
2561 /* skip invalid modes */
2562 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2563 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2564 return false;
2565 }
2566 return true;
2567 }
2568
radeon_atombios_parse_power_table_4_5(struct radeon_device * rdev)2569 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2570 {
2571 struct radeon_mode_info *mode_info = &rdev->mode_info;
2572 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2573 union pplib_power_state *power_state;
2574 int i, j;
2575 int state_index = 0, mode_index = 0;
2576 union pplib_clock_info *clock_info;
2577 bool valid;
2578 union power_info *power_info;
2579 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2580 u16 data_offset;
2581 u8 frev, crev;
2582
2583 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2584 &frev, &crev, &data_offset))
2585 return state_index;
2586 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2587
2588 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2589 if (power_info->pplib.ucNumStates == 0)
2590 return state_index;
2591 rdev->pm.power_state = kcalloc(power_info->pplib.ucNumStates,
2592 sizeof(struct radeon_power_state),
2593 GFP_KERNEL);
2594 if (!rdev->pm.power_state)
2595 return state_index;
2596 /* first mode is usually default, followed by low to high */
2597 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2598 mode_index = 0;
2599 power_state = (union pplib_power_state *)
2600 (mode_info->atom_context->bios + data_offset +
2601 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2602 i * power_info->pplib.ucStateEntrySize);
2603 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2604 (mode_info->atom_context->bios + data_offset +
2605 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2606 (power_state->v1.ucNonClockStateIndex *
2607 power_info->pplib.ucNonClockSize));
2608 rdev->pm.power_state[i].clock_info =
2609 kcalloc((power_info->pplib.ucStateEntrySize - 1) ?
2610 (power_info->pplib.ucStateEntrySize - 1) : 1,
2611 sizeof(struct radeon_pm_clock_info),
2612 GFP_KERNEL);
2613 if (!rdev->pm.power_state[i].clock_info)
2614 return state_index;
2615 if (power_info->pplib.ucStateEntrySize - 1) {
2616 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2617 clock_info = (union pplib_clock_info *)
2618 (mode_info->atom_context->bios + data_offset +
2619 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2620 (power_state->v1.ucClockStateIndices[j] *
2621 power_info->pplib.ucClockInfoSize));
2622 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2623 state_index, mode_index,
2624 clock_info);
2625 if (valid)
2626 mode_index++;
2627 }
2628 } else {
2629 rdev->pm.power_state[state_index].clock_info[0].mclk =
2630 rdev->clock.default_mclk;
2631 rdev->pm.power_state[state_index].clock_info[0].sclk =
2632 rdev->clock.default_sclk;
2633 mode_index++;
2634 }
2635 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2636 if (mode_index) {
2637 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2638 non_clock_info);
2639 state_index++;
2640 }
2641 }
2642 /* if multiple clock modes, mark the lowest as no display */
2643 for (i = 0; i < state_index; i++) {
2644 if (rdev->pm.power_state[i].num_clock_modes > 1)
2645 rdev->pm.power_state[i].clock_info[0].flags |=
2646 RADEON_PM_MODE_NO_DISPLAY;
2647 }
2648 /* first mode is usually default */
2649 if (rdev->pm.default_power_state_index == -1) {
2650 rdev->pm.power_state[0].type =
2651 POWER_STATE_TYPE_DEFAULT;
2652 rdev->pm.default_power_state_index = 0;
2653 rdev->pm.power_state[0].default_clock_mode =
2654 &rdev->pm.power_state[0].clock_info[0];
2655 }
2656 return state_index;
2657 }
2658
radeon_atombios_parse_power_table_6(struct radeon_device * rdev)2659 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2660 {
2661 struct radeon_mode_info *mode_info = &rdev->mode_info;
2662 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2663 union pplib_power_state *power_state;
2664 int i, j, non_clock_array_index, clock_array_index;
2665 int state_index = 0, mode_index = 0;
2666 union pplib_clock_info *clock_info;
2667 struct _StateArray *state_array;
2668 struct _ClockInfoArray *clock_info_array;
2669 struct _NonClockInfoArray *non_clock_info_array;
2670 bool valid;
2671 union power_info *power_info;
2672 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2673 u16 data_offset;
2674 u8 frev, crev;
2675 u8 *power_state_offset;
2676
2677 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2678 &frev, &crev, &data_offset))
2679 return state_index;
2680 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2681
2682 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2683 state_array = (struct _StateArray *)
2684 (mode_info->atom_context->bios + data_offset +
2685 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2686 clock_info_array = (struct _ClockInfoArray *)
2687 (mode_info->atom_context->bios + data_offset +
2688 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2689 non_clock_info_array = (struct _NonClockInfoArray *)
2690 (mode_info->atom_context->bios + data_offset +
2691 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2692 if (state_array->ucNumEntries == 0)
2693 return state_index;
2694 rdev->pm.power_state = kcalloc(state_array->ucNumEntries,
2695 sizeof(struct radeon_power_state),
2696 GFP_KERNEL);
2697 if (!rdev->pm.power_state)
2698 return state_index;
2699 power_state_offset = (u8 *)state_array->states;
2700 for (i = 0; i < state_array->ucNumEntries; i++) {
2701 mode_index = 0;
2702 power_state = (union pplib_power_state *)power_state_offset;
2703 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2704 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2705 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2706 rdev->pm.power_state[i].clock_info =
2707 kcalloc(power_state->v2.ucNumDPMLevels ?
2708 power_state->v2.ucNumDPMLevels : 1,
2709 sizeof(struct radeon_pm_clock_info),
2710 GFP_KERNEL);
2711 if (!rdev->pm.power_state[i].clock_info)
2712 return state_index;
2713 if (power_state->v2.ucNumDPMLevels) {
2714 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2715 clock_array_index = power_state->v2.clockInfoIndex[j];
2716 clock_info = (union pplib_clock_info *)
2717 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2718 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2719 state_index, mode_index,
2720 clock_info);
2721 if (valid)
2722 mode_index++;
2723 }
2724 } else {
2725 rdev->pm.power_state[state_index].clock_info[0].mclk =
2726 rdev->clock.default_mclk;
2727 rdev->pm.power_state[state_index].clock_info[0].sclk =
2728 rdev->clock.default_sclk;
2729 mode_index++;
2730 }
2731 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2732 if (mode_index) {
2733 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2734 non_clock_info);
2735 state_index++;
2736 }
2737 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2738 }
2739 /* if multiple clock modes, mark the lowest as no display */
2740 for (i = 0; i < state_index; i++) {
2741 if (rdev->pm.power_state[i].num_clock_modes > 1)
2742 rdev->pm.power_state[i].clock_info[0].flags |=
2743 RADEON_PM_MODE_NO_DISPLAY;
2744 }
2745 /* first mode is usually default */
2746 if (rdev->pm.default_power_state_index == -1) {
2747 rdev->pm.power_state[0].type =
2748 POWER_STATE_TYPE_DEFAULT;
2749 rdev->pm.default_power_state_index = 0;
2750 rdev->pm.power_state[0].default_clock_mode =
2751 &rdev->pm.power_state[0].clock_info[0];
2752 }
2753 return state_index;
2754 }
2755
radeon_atombios_get_power_modes(struct radeon_device * rdev)2756 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2757 {
2758 struct radeon_mode_info *mode_info = &rdev->mode_info;
2759 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2760 u16 data_offset;
2761 u8 frev, crev;
2762 int state_index = 0;
2763
2764 rdev->pm.default_power_state_index = -1;
2765
2766 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2767 &frev, &crev, &data_offset)) {
2768 switch (frev) {
2769 case 1:
2770 case 2:
2771 case 3:
2772 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2773 break;
2774 case 4:
2775 case 5:
2776 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2777 break;
2778 case 6:
2779 state_index = radeon_atombios_parse_power_table_6(rdev);
2780 break;
2781 default:
2782 break;
2783 }
2784 }
2785
2786 if (state_index == 0) {
2787 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2788 if (rdev->pm.power_state) {
2789 rdev->pm.power_state[0].clock_info =
2790 kcalloc(1,
2791 sizeof(struct radeon_pm_clock_info),
2792 GFP_KERNEL);
2793 if (rdev->pm.power_state[0].clock_info) {
2794 /* add the default mode */
2795 rdev->pm.power_state[state_index].type =
2796 POWER_STATE_TYPE_DEFAULT;
2797 rdev->pm.power_state[state_index].num_clock_modes = 1;
2798 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2799 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2800 rdev->pm.power_state[state_index].default_clock_mode =
2801 &rdev->pm.power_state[state_index].clock_info[0];
2802 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2803 rdev->pm.power_state[state_index].pcie_lanes = 16;
2804 rdev->pm.default_power_state_index = state_index;
2805 rdev->pm.power_state[state_index].flags = 0;
2806 state_index++;
2807 }
2808 }
2809 }
2810
2811 rdev->pm.num_power_states = state_index;
2812
2813 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2814 rdev->pm.current_clock_mode_index = 0;
2815 if (rdev->pm.default_power_state_index >= 0)
2816 rdev->pm.current_vddc =
2817 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2818 else
2819 rdev->pm.current_vddc = 0;
2820 }
2821
2822 union get_clock_dividers {
2823 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2824 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2825 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2826 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2827 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
2828 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
2829 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
2830 };
2831
radeon_atom_get_clock_dividers(struct radeon_device * rdev,u8 clock_type,u32 clock,bool strobe_mode,struct atom_clock_dividers * dividers)2832 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2833 u8 clock_type,
2834 u32 clock,
2835 bool strobe_mode,
2836 struct atom_clock_dividers *dividers)
2837 {
2838 union get_clock_dividers args;
2839 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2840 u8 frev, crev;
2841
2842 memset(&args, 0, sizeof(args));
2843 memset(dividers, 0, sizeof(struct atom_clock_dividers));
2844
2845 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2846 return -EINVAL;
2847
2848 switch (crev) {
2849 case 1:
2850 /* r4xx, r5xx */
2851 args.v1.ucAction = clock_type;
2852 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */
2853
2854 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2855
2856 dividers->post_div = args.v1.ucPostDiv;
2857 dividers->fb_div = args.v1.ucFbDiv;
2858 dividers->enable_post_div = true;
2859 break;
2860 case 2:
2861 case 3:
2862 case 5:
2863 /* r6xx, r7xx, evergreen, ni, si */
2864 if (rdev->family <= CHIP_RV770) {
2865 args.v2.ucAction = clock_type;
2866 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */
2867
2868 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2869
2870 dividers->post_div = args.v2.ucPostDiv;
2871 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2872 dividers->ref_div = args.v2.ucAction;
2873 if (rdev->family == CHIP_RV770) {
2874 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2875 true : false;
2876 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2877 } else
2878 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2879 } else {
2880 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2881 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2882
2883 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2884
2885 dividers->post_div = args.v3.ucPostDiv;
2886 dividers->enable_post_div = (args.v3.ucCntlFlag &
2887 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2888 dividers->enable_dithen = (args.v3.ucCntlFlag &
2889 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2890 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2891 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2892 dividers->ref_div = args.v3.ucRefDiv;
2893 dividers->vco_mode = (args.v3.ucCntlFlag &
2894 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2895 } else {
2896 /* for SI we use ComputeMemoryClockParam for memory plls */
2897 if (rdev->family >= CHIP_TAHITI)
2898 return -EINVAL;
2899 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2900 if (strobe_mode)
2901 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2902
2903 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2904
2905 dividers->post_div = args.v5.ucPostDiv;
2906 dividers->enable_post_div = (args.v5.ucCntlFlag &
2907 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2908 dividers->enable_dithen = (args.v5.ucCntlFlag &
2909 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2910 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2911 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2912 dividers->ref_div = args.v5.ucRefDiv;
2913 dividers->vco_mode = (args.v5.ucCntlFlag &
2914 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2915 }
2916 }
2917 break;
2918 case 4:
2919 /* fusion */
2920 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
2921
2922 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2923
2924 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
2925 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2926 break;
2927 case 6:
2928 /* CI */
2929 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
2930 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
2931 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
2932
2933 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2934
2935 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
2936 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
2937 dividers->ref_div = args.v6_out.ucPllRefDiv;
2938 dividers->post_div = args.v6_out.ucPllPostDiv;
2939 dividers->flags = args.v6_out.ucPllCntlFlag;
2940 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
2941 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
2942 break;
2943 default:
2944 return -EINVAL;
2945 }
2946 return 0;
2947 }
2948
radeon_atom_get_memory_pll_dividers(struct radeon_device * rdev,u32 clock,bool strobe_mode,struct atom_mpll_param * mpll_param)2949 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
2950 u32 clock,
2951 bool strobe_mode,
2952 struct atom_mpll_param *mpll_param)
2953 {
2954 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
2955 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
2956 u8 frev, crev;
2957
2958 memset(&args, 0, sizeof(args));
2959 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
2960
2961 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2962 return -EINVAL;
2963
2964 switch (frev) {
2965 case 2:
2966 switch (crev) {
2967 case 1:
2968 /* SI */
2969 args.ulClock = cpu_to_le32(clock); /* 10 khz */
2970 args.ucInputFlag = 0;
2971 if (strobe_mode)
2972 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
2973
2974 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2975
2976 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
2977 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
2978 mpll_param->post_div = args.ucPostDiv;
2979 mpll_param->dll_speed = args.ucDllSpeed;
2980 mpll_param->bwcntl = args.ucBWCntl;
2981 mpll_param->vco_mode =
2982 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
2983 mpll_param->yclk_sel =
2984 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
2985 mpll_param->qdr =
2986 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
2987 mpll_param->half_rate =
2988 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
2989 break;
2990 default:
2991 return -EINVAL;
2992 }
2993 break;
2994 default:
2995 return -EINVAL;
2996 }
2997 return 0;
2998 }
2999
radeon_atom_set_clock_gating(struct radeon_device * rdev,int enable)3000 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
3001 {
3002 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
3003 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
3004
3005 args.ucEnable = enable;
3006
3007 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3008 }
3009
radeon_atom_get_engine_clock(struct radeon_device * rdev)3010 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
3011 {
3012 GET_ENGINE_CLOCK_PS_ALLOCATION args;
3013 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
3014
3015 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3016 return le32_to_cpu(args.ulReturnEngineClock);
3017 }
3018
radeon_atom_get_memory_clock(struct radeon_device * rdev)3019 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
3020 {
3021 GET_MEMORY_CLOCK_PS_ALLOCATION args;
3022 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
3023
3024 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3025 return le32_to_cpu(args.ulReturnMemoryClock);
3026 }
3027
radeon_atom_set_engine_clock(struct radeon_device * rdev,uint32_t eng_clock)3028 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
3029 uint32_t eng_clock)
3030 {
3031 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3032 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
3033
3034 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
3035
3036 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3037 }
3038
radeon_atom_set_memory_clock(struct radeon_device * rdev,uint32_t mem_clock)3039 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
3040 uint32_t mem_clock)
3041 {
3042 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3043 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
3044
3045 if (rdev->flags & RADEON_IS_IGP)
3046 return;
3047
3048 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
3049
3050 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3051 }
3052
radeon_atom_set_engine_dram_timings(struct radeon_device * rdev,u32 eng_clock,u32 mem_clock)3053 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
3054 u32 eng_clock, u32 mem_clock)
3055 {
3056 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3057 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3058 u32 tmp;
3059
3060 memset(&args, 0, sizeof(args));
3061
3062 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
3063 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
3064
3065 args.ulTargetEngineClock = cpu_to_le32(tmp);
3066 if (mem_clock)
3067 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
3068
3069 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3070 }
3071
radeon_atom_update_memory_dll(struct radeon_device * rdev,u32 mem_clock)3072 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
3073 u32 mem_clock)
3074 {
3075 u32 args;
3076 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3077
3078 args = cpu_to_le32(mem_clock); /* 10 khz */
3079
3080 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3081 }
3082
radeon_atom_set_ac_timing(struct radeon_device * rdev,u32 mem_clock)3083 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
3084 u32 mem_clock)
3085 {
3086 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3087 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3088 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);
3089
3090 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */
3091
3092 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3093 }
3094
3095 union set_voltage {
3096 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
3097 struct _SET_VOLTAGE_PARAMETERS v1;
3098 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
3099 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
3100 };
3101
radeon_atom_set_voltage(struct radeon_device * rdev,u16 voltage_level,u8 voltage_type)3102 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
3103 {
3104 union set_voltage args;
3105 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3106 u8 frev, crev, volt_index = voltage_level;
3107
3108 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3109 return;
3110
3111 /* 0xff01 is a flag rather then an actual voltage */
3112 if (voltage_level == 0xff01)
3113 return;
3114
3115 switch (crev) {
3116 case 1:
3117 args.v1.ucVoltageType = voltage_type;
3118 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
3119 args.v1.ucVoltageIndex = volt_index;
3120 break;
3121 case 2:
3122 args.v2.ucVoltageType = voltage_type;
3123 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
3124 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3125 break;
3126 case 3:
3127 args.v3.ucVoltageType = voltage_type;
3128 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
3129 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
3130 break;
3131 default:
3132 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3133 return;
3134 }
3135
3136 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3137 }
3138
radeon_atom_get_max_vddc(struct radeon_device * rdev,u8 voltage_type,u16 voltage_id,u16 * voltage)3139 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
3140 u16 voltage_id, u16 *voltage)
3141 {
3142 union set_voltage args;
3143 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3144 u8 frev, crev;
3145
3146 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3147 return -EINVAL;
3148
3149 switch (crev) {
3150 case 1:
3151 return -EINVAL;
3152 case 2:
3153 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
3154 args.v2.ucVoltageMode = 0;
3155 args.v2.usVoltageLevel = 0;
3156
3157 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3158
3159 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
3160 break;
3161 case 3:
3162 args.v3.ucVoltageType = voltage_type;
3163 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
3164 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
3165
3166 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3167
3168 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
3169 break;
3170 default:
3171 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3172 return -EINVAL;
3173 }
3174
3175 return 0;
3176 }
3177
radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device * rdev,u16 * voltage,u16 leakage_idx)3178 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
3179 u16 *voltage,
3180 u16 leakage_idx)
3181 {
3182 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
3183 }
3184
radeon_atom_get_leakage_id_from_vbios(struct radeon_device * rdev,u16 * leakage_id)3185 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
3186 u16 *leakage_id)
3187 {
3188 union set_voltage args;
3189 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3190 u8 frev, crev;
3191
3192 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3193 return -EINVAL;
3194
3195 switch (crev) {
3196 case 3:
3197 case 4:
3198 args.v3.ucVoltageType = 0;
3199 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
3200 args.v3.usVoltageLevel = 0;
3201
3202 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3203
3204 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
3205 break;
3206 default:
3207 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3208 return -EINVAL;
3209 }
3210
3211 return 0;
3212 }
3213
radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device * rdev,u16 * vddc,u16 * vddci,u16 virtual_voltage_id,u16 vbios_voltage_id)3214 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
3215 u16 *vddc, u16 *vddci,
3216 u16 virtual_voltage_id,
3217 u16 vbios_voltage_id)
3218 {
3219 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
3220 u8 frev, crev;
3221 u16 data_offset, size;
3222 int i, j;
3223 ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
3224 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
3225
3226 *vddc = 0;
3227 *vddci = 0;
3228
3229 if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3230 &frev, &crev, &data_offset))
3231 return -EINVAL;
3232
3233 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
3234 (rdev->mode_info.atom_context->bios + data_offset);
3235
3236 switch (frev) {
3237 case 1:
3238 return -EINVAL;
3239 case 2:
3240 switch (crev) {
3241 case 1:
3242 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
3243 return -EINVAL;
3244 leakage_bin = (u16 *)
3245 (rdev->mode_info.atom_context->bios + data_offset +
3246 le16_to_cpu(profile->usLeakageBinArrayOffset));
3247 vddc_id_buf = (u16 *)
3248 (rdev->mode_info.atom_context->bios + data_offset +
3249 le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
3250 vddc_buf = (u16 *)
3251 (rdev->mode_info.atom_context->bios + data_offset +
3252 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
3253 vddci_id_buf = (u16 *)
3254 (rdev->mode_info.atom_context->bios + data_offset +
3255 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
3256 vddci_buf = (u16 *)
3257 (rdev->mode_info.atom_context->bios + data_offset +
3258 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
3259
3260 if (profile->ucElbVDDC_Num > 0) {
3261 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
3262 if (vddc_id_buf[i] == virtual_voltage_id) {
3263 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3264 if (vbios_voltage_id <= leakage_bin[j]) {
3265 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
3266 break;
3267 }
3268 }
3269 break;
3270 }
3271 }
3272 }
3273 if (profile->ucElbVDDCI_Num > 0) {
3274 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
3275 if (vddci_id_buf[i] == virtual_voltage_id) {
3276 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3277 if (vbios_voltage_id <= leakage_bin[j]) {
3278 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
3279 break;
3280 }
3281 }
3282 break;
3283 }
3284 }
3285 }
3286 break;
3287 default:
3288 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3289 return -EINVAL;
3290 }
3291 break;
3292 default:
3293 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3294 return -EINVAL;
3295 }
3296
3297 return 0;
3298 }
3299
3300 union get_voltage_info {
3301 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
3302 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
3303 };
3304
radeon_atom_get_voltage_evv(struct radeon_device * rdev,u16 virtual_voltage_id,u16 * voltage)3305 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
3306 u16 virtual_voltage_id,
3307 u16 *voltage)
3308 {
3309 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
3310 u32 entry_id;
3311 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
3312 union get_voltage_info args;
3313
3314 for (entry_id = 0; entry_id < count; entry_id++) {
3315 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
3316 virtual_voltage_id)
3317 break;
3318 }
3319
3320 if (entry_id >= count)
3321 return -EINVAL;
3322
3323 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
3324 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
3325 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
3326 args.in.ulSCLKFreq =
3327 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
3328
3329 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3330
3331 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
3332
3333 return 0;
3334 }
3335
radeon_atom_get_voltage_gpio_settings(struct radeon_device * rdev,u16 voltage_level,u8 voltage_type,u32 * gpio_value,u32 * gpio_mask)3336 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
3337 u16 voltage_level, u8 voltage_type,
3338 u32 *gpio_value, u32 *gpio_mask)
3339 {
3340 union set_voltage args;
3341 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3342 u8 frev, crev;
3343
3344 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3345 return -EINVAL;
3346
3347 switch (crev) {
3348 case 1:
3349 return -EINVAL;
3350 case 2:
3351 args.v2.ucVoltageType = voltage_type;
3352 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK;
3353 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3354
3355 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3356
3357 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2);
3358
3359 args.v2.ucVoltageType = voltage_type;
3360 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL;
3361 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3362
3363 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3364
3365 *gpio_value = le32_to_cpu(*(u32 *)&args.v2);
3366 break;
3367 default:
3368 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3369 return -EINVAL;
3370 }
3371
3372 return 0;
3373 }
3374
3375 union voltage_object_info {
3376 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
3377 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
3378 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
3379 };
3380
3381 union voltage_object {
3382 struct _ATOM_VOLTAGE_OBJECT v1;
3383 struct _ATOM_VOLTAGE_OBJECT_V2 v2;
3384 union _ATOM_VOLTAGE_OBJECT_V3 v3;
3385 };
3386
atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO * v1,u8 voltage_type)3387 static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1,
3388 u8 voltage_type)
3389 {
3390 u32 size = le16_to_cpu(v1->sHeader.usStructureSize);
3391 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]);
3392 u8 *start = (u8 *)v1;
3393
3394 while (offset < size) {
3395 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset);
3396 if (vo->ucVoltageType == voltage_type)
3397 return vo;
3398 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) +
3399 vo->asFormula.ucNumOfVoltageEntries;
3400 }
3401 return NULL;
3402 }
3403
atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 * v2,u8 voltage_type)3404 static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2,
3405 u8 voltage_type)
3406 {
3407 u32 size = le16_to_cpu(v2->sHeader.usStructureSize);
3408 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]);
3409 u8 *start = (u8*)v2;
3410
3411 while (offset < size) {
3412 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset);
3413 if (vo->ucVoltageType == voltage_type)
3414 return vo;
3415 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) +
3416 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY));
3417 }
3418 return NULL;
3419 }
3420
atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 * v3,u8 voltage_type,u8 voltage_mode)3421 static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
3422 u8 voltage_type, u8 voltage_mode)
3423 {
3424 u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
3425 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
3426 u8 *start = (u8*)v3;
3427
3428 while (offset < size) {
3429 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
3430 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
3431 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
3432 return vo;
3433 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
3434 }
3435 return NULL;
3436 }
3437
3438 bool
radeon_atom_is_voltage_gpio(struct radeon_device * rdev,u8 voltage_type,u8 voltage_mode)3439 radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
3440 u8 voltage_type, u8 voltage_mode)
3441 {
3442 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3443 u8 frev, crev;
3444 u16 data_offset, size;
3445 union voltage_object_info *voltage_info;
3446 union voltage_object *voltage_object = NULL;
3447
3448 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3449 &frev, &crev, &data_offset)) {
3450 voltage_info = (union voltage_object_info *)
3451 (rdev->mode_info.atom_context->bios + data_offset);
3452
3453 switch (frev) {
3454 case 1:
3455 case 2:
3456 switch (crev) {
3457 case 1:
3458 voltage_object = (union voltage_object *)
3459 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3460 if (voltage_object &&
3461 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3462 return true;
3463 break;
3464 case 2:
3465 voltage_object = (union voltage_object *)
3466 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3467 if (voltage_object &&
3468 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3469 return true;
3470 break;
3471 default:
3472 DRM_ERROR("unknown voltage object table\n");
3473 return false;
3474 }
3475 break;
3476 case 3:
3477 switch (crev) {
3478 case 1:
3479 if (atom_lookup_voltage_object_v3(&voltage_info->v3,
3480 voltage_type, voltage_mode))
3481 return true;
3482 break;
3483 default:
3484 DRM_ERROR("unknown voltage object table\n");
3485 return false;
3486 }
3487 break;
3488 default:
3489 DRM_ERROR("unknown voltage object table\n");
3490 return false;
3491 }
3492
3493 }
3494 return false;
3495 }
3496
radeon_atom_get_svi2_info(struct radeon_device * rdev,u8 voltage_type,u8 * svd_gpio_id,u8 * svc_gpio_id)3497 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
3498 u8 voltage_type,
3499 u8 *svd_gpio_id, u8 *svc_gpio_id)
3500 {
3501 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3502 u8 frev, crev;
3503 u16 data_offset, size;
3504 union voltage_object_info *voltage_info;
3505 union voltage_object *voltage_object = NULL;
3506
3507 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3508 &frev, &crev, &data_offset)) {
3509 voltage_info = (union voltage_object_info *)
3510 (rdev->mode_info.atom_context->bios + data_offset);
3511
3512 switch (frev) {
3513 case 3:
3514 switch (crev) {
3515 case 1:
3516 voltage_object = (union voltage_object *)
3517 atom_lookup_voltage_object_v3(&voltage_info->v3,
3518 voltage_type,
3519 VOLTAGE_OBJ_SVID2);
3520 if (voltage_object) {
3521 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
3522 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
3523 } else {
3524 return -EINVAL;
3525 }
3526 break;
3527 default:
3528 DRM_ERROR("unknown voltage object table\n");
3529 return -EINVAL;
3530 }
3531 break;
3532 default:
3533 DRM_ERROR("unknown voltage object table\n");
3534 return -EINVAL;
3535 }
3536
3537 }
3538 return 0;
3539 }
3540
radeon_atom_get_max_voltage(struct radeon_device * rdev,u8 voltage_type,u16 * max_voltage)3541 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
3542 u8 voltage_type, u16 *max_voltage)
3543 {
3544 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3545 u8 frev, crev;
3546 u16 data_offset, size;
3547 union voltage_object_info *voltage_info;
3548 union voltage_object *voltage_object = NULL;
3549
3550 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3551 &frev, &crev, &data_offset)) {
3552 voltage_info = (union voltage_object_info *)
3553 (rdev->mode_info.atom_context->bios + data_offset);
3554
3555 switch (crev) {
3556 case 1:
3557 voltage_object = (union voltage_object *)
3558 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3559 if (voltage_object) {
3560 ATOM_VOLTAGE_FORMULA *formula =
3561 &voltage_object->v1.asFormula;
3562 if (formula->ucFlag & 1)
3563 *max_voltage =
3564 le16_to_cpu(formula->usVoltageBaseLevel) +
3565 formula->ucNumOfVoltageEntries / 2 *
3566 le16_to_cpu(formula->usVoltageStep);
3567 else
3568 *max_voltage =
3569 le16_to_cpu(formula->usVoltageBaseLevel) +
3570 (formula->ucNumOfVoltageEntries - 1) *
3571 le16_to_cpu(formula->usVoltageStep);
3572 return 0;
3573 }
3574 break;
3575 case 2:
3576 voltage_object = (union voltage_object *)
3577 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3578 if (voltage_object) {
3579 ATOM_VOLTAGE_FORMULA_V2 *formula =
3580 &voltage_object->v2.asFormula;
3581 if (formula->ucNumOfVoltageEntries) {
3582 VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *)
3583 ((u8 *)&formula->asVIDAdjustEntries[0] +
3584 (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1)));
3585 *max_voltage =
3586 le16_to_cpu(lut->usVoltageValue);
3587 return 0;
3588 }
3589 }
3590 break;
3591 default:
3592 DRM_ERROR("unknown voltage object table\n");
3593 return -EINVAL;
3594 }
3595
3596 }
3597 return -EINVAL;
3598 }
3599
radeon_atom_get_min_voltage(struct radeon_device * rdev,u8 voltage_type,u16 * min_voltage)3600 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
3601 u8 voltage_type, u16 *min_voltage)
3602 {
3603 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3604 u8 frev, crev;
3605 u16 data_offset, size;
3606 union voltage_object_info *voltage_info;
3607 union voltage_object *voltage_object = NULL;
3608
3609 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3610 &frev, &crev, &data_offset)) {
3611 voltage_info = (union voltage_object_info *)
3612 (rdev->mode_info.atom_context->bios + data_offset);
3613
3614 switch (crev) {
3615 case 1:
3616 voltage_object = (union voltage_object *)
3617 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3618 if (voltage_object) {
3619 ATOM_VOLTAGE_FORMULA *formula =
3620 &voltage_object->v1.asFormula;
3621 *min_voltage =
3622 le16_to_cpu(formula->usVoltageBaseLevel);
3623 return 0;
3624 }
3625 break;
3626 case 2:
3627 voltage_object = (union voltage_object *)
3628 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3629 if (voltage_object) {
3630 ATOM_VOLTAGE_FORMULA_V2 *formula =
3631 &voltage_object->v2.asFormula;
3632 if (formula->ucNumOfVoltageEntries) {
3633 *min_voltage =
3634 le16_to_cpu(formula->asVIDAdjustEntries[
3635 0
3636 ].usVoltageValue);
3637 return 0;
3638 }
3639 }
3640 break;
3641 default:
3642 DRM_ERROR("unknown voltage object table\n");
3643 return -EINVAL;
3644 }
3645
3646 }
3647 return -EINVAL;
3648 }
3649
radeon_atom_get_voltage_step(struct radeon_device * rdev,u8 voltage_type,u16 * voltage_step)3650 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
3651 u8 voltage_type, u16 *voltage_step)
3652 {
3653 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3654 u8 frev, crev;
3655 u16 data_offset, size;
3656 union voltage_object_info *voltage_info;
3657 union voltage_object *voltage_object = NULL;
3658
3659 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3660 &frev, &crev, &data_offset)) {
3661 voltage_info = (union voltage_object_info *)
3662 (rdev->mode_info.atom_context->bios + data_offset);
3663
3664 switch (crev) {
3665 case 1:
3666 voltage_object = (union voltage_object *)
3667 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3668 if (voltage_object) {
3669 ATOM_VOLTAGE_FORMULA *formula =
3670 &voltage_object->v1.asFormula;
3671 if (formula->ucFlag & 1)
3672 *voltage_step =
3673 (le16_to_cpu(formula->usVoltageStep) + 1) / 2;
3674 else
3675 *voltage_step =
3676 le16_to_cpu(formula->usVoltageStep);
3677 return 0;
3678 }
3679 break;
3680 case 2:
3681 return -EINVAL;
3682 default:
3683 DRM_ERROR("unknown voltage object table\n");
3684 return -EINVAL;
3685 }
3686
3687 }
3688 return -EINVAL;
3689 }
3690
radeon_atom_round_to_true_voltage(struct radeon_device * rdev,u8 voltage_type,u16 nominal_voltage,u16 * true_voltage)3691 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
3692 u8 voltage_type,
3693 u16 nominal_voltage,
3694 u16 *true_voltage)
3695 {
3696 u16 min_voltage, max_voltage, voltage_step;
3697
3698 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
3699 return -EINVAL;
3700 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
3701 return -EINVAL;
3702 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
3703 return -EINVAL;
3704
3705 if (nominal_voltage <= min_voltage)
3706 *true_voltage = min_voltage;
3707 else if (nominal_voltage >= max_voltage)
3708 *true_voltage = max_voltage;
3709 else
3710 *true_voltage = min_voltage +
3711 ((nominal_voltage - min_voltage) / voltage_step) *
3712 voltage_step;
3713
3714 return 0;
3715 }
3716
radeon_atom_get_voltage_table(struct radeon_device * rdev,u8 voltage_type,u8 voltage_mode,struct atom_voltage_table * voltage_table)3717 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
3718 u8 voltage_type, u8 voltage_mode,
3719 struct atom_voltage_table *voltage_table)
3720 {
3721 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3722 u8 frev, crev;
3723 u16 data_offset, size;
3724 int i, ret;
3725 union voltage_object_info *voltage_info;
3726 union voltage_object *voltage_object = NULL;
3727
3728 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3729 &frev, &crev, &data_offset)) {
3730 voltage_info = (union voltage_object_info *)
3731 (rdev->mode_info.atom_context->bios + data_offset);
3732
3733 switch (frev) {
3734 case 1:
3735 case 2:
3736 switch (crev) {
3737 case 1:
3738 DRM_ERROR("old table version %d, %d\n", frev, crev);
3739 return -EINVAL;
3740 case 2:
3741 voltage_object = (union voltage_object *)
3742 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3743 if (voltage_object) {
3744 ATOM_VOLTAGE_FORMULA_V2 *formula =
3745 &voltage_object->v2.asFormula;
3746 VOLTAGE_LUT_ENTRY *lut;
3747 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES)
3748 return -EINVAL;
3749 lut = &formula->asVIDAdjustEntries[0];
3750 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) {
3751 voltage_table->entries[i].value =
3752 le16_to_cpu(lut->usVoltageValue);
3753 ret = radeon_atom_get_voltage_gpio_settings(rdev,
3754 voltage_table->entries[i].value,
3755 voltage_type,
3756 &voltage_table->entries[i].smio_low,
3757 &voltage_table->mask_low);
3758 if (ret)
3759 return ret;
3760 lut = (VOLTAGE_LUT_ENTRY *)
3761 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY));
3762 }
3763 voltage_table->count = formula->ucNumOfVoltageEntries;
3764 return 0;
3765 }
3766 break;
3767 default:
3768 DRM_ERROR("unknown voltage object table\n");
3769 return -EINVAL;
3770 }
3771 break;
3772 case 3:
3773 switch (crev) {
3774 case 1:
3775 voltage_object = (union voltage_object *)
3776 atom_lookup_voltage_object_v3(&voltage_info->v3,
3777 voltage_type, voltage_mode);
3778 if (voltage_object) {
3779 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
3780 &voltage_object->v3.asGpioVoltageObj;
3781 VOLTAGE_LUT_ENTRY_V2 *lut;
3782 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
3783 return -EINVAL;
3784 lut = &gpio->asVolGpioLut[0];
3785 for (i = 0; i < gpio->ucGpioEntryNum; i++) {
3786 voltage_table->entries[i].value =
3787 le16_to_cpu(lut->usVoltageValue);
3788 voltage_table->entries[i].smio_low =
3789 le32_to_cpu(lut->ulVoltageId);
3790 lut = (VOLTAGE_LUT_ENTRY_V2 *)
3791 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
3792 }
3793 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
3794 voltage_table->count = gpio->ucGpioEntryNum;
3795 voltage_table->phase_delay = gpio->ucPhaseDelay;
3796 return 0;
3797 }
3798 break;
3799 default:
3800 DRM_ERROR("unknown voltage object table\n");
3801 return -EINVAL;
3802 }
3803 break;
3804 default:
3805 DRM_ERROR("unknown voltage object table\n");
3806 return -EINVAL;
3807 }
3808 }
3809 return -EINVAL;
3810 }
3811
3812 union vram_info {
3813 struct _ATOM_VRAM_INFO_V3 v1_3;
3814 struct _ATOM_VRAM_INFO_V4 v1_4;
3815 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
3816 };
3817
radeon_atom_get_memory_info(struct radeon_device * rdev,u8 module_index,struct atom_memory_info * mem_info)3818 int radeon_atom_get_memory_info(struct radeon_device *rdev,
3819 u8 module_index, struct atom_memory_info *mem_info)
3820 {
3821 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3822 u8 frev, crev, i;
3823 u16 data_offset, size;
3824 union vram_info *vram_info;
3825
3826 memset(mem_info, 0, sizeof(struct atom_memory_info));
3827
3828 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3829 &frev, &crev, &data_offset)) {
3830 vram_info = (union vram_info *)
3831 (rdev->mode_info.atom_context->bios + data_offset);
3832 switch (frev) {
3833 case 1:
3834 switch (crev) {
3835 case 3:
3836 /* r6xx */
3837 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) {
3838 ATOM_VRAM_MODULE_V3 *vram_module =
3839 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo;
3840
3841 for (i = 0; i < module_index; i++) {
3842 if (le16_to_cpu(vram_module->usSize) == 0)
3843 return -EINVAL;
3844 vram_module = (ATOM_VRAM_MODULE_V3 *)
3845 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize));
3846 }
3847 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf;
3848 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0;
3849 } else
3850 return -EINVAL;
3851 break;
3852 case 4:
3853 /* r7xx, evergreen */
3854 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3855 ATOM_VRAM_MODULE_V4 *vram_module =
3856 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3857
3858 for (i = 0; i < module_index; i++) {
3859 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3860 return -EINVAL;
3861 vram_module = (ATOM_VRAM_MODULE_V4 *)
3862 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3863 }
3864 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3865 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3866 } else
3867 return -EINVAL;
3868 break;
3869 default:
3870 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3871 return -EINVAL;
3872 }
3873 break;
3874 case 2:
3875 switch (crev) {
3876 case 1:
3877 /* ni */
3878 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3879 ATOM_VRAM_MODULE_V7 *vram_module =
3880 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo;
3881
3882 for (i = 0; i < module_index; i++) {
3883 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3884 return -EINVAL;
3885 vram_module = (ATOM_VRAM_MODULE_V7 *)
3886 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3887 }
3888 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3889 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3890 } else
3891 return -EINVAL;
3892 break;
3893 default:
3894 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3895 return -EINVAL;
3896 }
3897 break;
3898 default:
3899 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3900 return -EINVAL;
3901 }
3902 return 0;
3903 }
3904 return -EINVAL;
3905 }
3906
radeon_atom_get_mclk_range_table(struct radeon_device * rdev,bool gddr5,u8 module_index,struct atom_memory_clock_range_table * mclk_range_table)3907 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3908 bool gddr5, u8 module_index,
3909 struct atom_memory_clock_range_table *mclk_range_table)
3910 {
3911 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3912 u8 frev, crev, i;
3913 u16 data_offset, size;
3914 union vram_info *vram_info;
3915 u32 mem_timing_size = gddr5 ?
3916 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT);
3917
3918 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table));
3919
3920 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3921 &frev, &crev, &data_offset)) {
3922 vram_info = (union vram_info *)
3923 (rdev->mode_info.atom_context->bios + data_offset);
3924 switch (frev) {
3925 case 1:
3926 switch (crev) {
3927 case 3:
3928 DRM_ERROR("old table version %d, %d\n", frev, crev);
3929 return -EINVAL;
3930 case 4:
3931 /* r7xx, evergreen */
3932 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3933 ATOM_VRAM_MODULE_V4 *vram_module =
3934 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3935 ATOM_MEMORY_TIMING_FORMAT *format;
3936
3937 for (i = 0; i < module_index; i++) {
3938 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3939 return -EINVAL;
3940 vram_module = (ATOM_VRAM_MODULE_V4 *)
3941 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3942 }
3943 mclk_range_table->num_entries = (u8)
3944 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) /
3945 mem_timing_size);
3946 format = &vram_module->asMemTiming[0];
3947 for (i = 0; i < mclk_range_table->num_entries; i++) {
3948 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange);
3949 format = (ATOM_MEMORY_TIMING_FORMAT *)
3950 ((u8 *)format + mem_timing_size);
3951 }
3952 } else
3953 return -EINVAL;
3954 break;
3955 default:
3956 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3957 return -EINVAL;
3958 }
3959 break;
3960 case 2:
3961 DRM_ERROR("new table version %d, %d\n", frev, crev);
3962 return -EINVAL;
3963 default:
3964 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3965 return -EINVAL;
3966 }
3967 return 0;
3968 }
3969 return -EINVAL;
3970 }
3971
3972 #define MEM_ID_MASK 0xff000000
3973 #define MEM_ID_SHIFT 24
3974 #define CLOCK_RANGE_MASK 0x00ffffff
3975 #define CLOCK_RANGE_SHIFT 0
3976 #define LOW_NIBBLE_MASK 0xf
3977 #define DATA_EQU_PREV 0
3978 #define DATA_FROM_TABLE 4
3979
radeon_atom_init_mc_reg_table(struct radeon_device * rdev,u8 module_index,struct atom_mc_reg_table * reg_table)3980 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3981 u8 module_index,
3982 struct atom_mc_reg_table *reg_table)
3983 {
3984 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3985 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
3986 u32 i = 0, j;
3987 u16 data_offset, size;
3988 union vram_info *vram_info;
3989
3990 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
3991
3992 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3993 &frev, &crev, &data_offset)) {
3994 vram_info = (union vram_info *)
3995 (rdev->mode_info.atom_context->bios + data_offset);
3996 switch (frev) {
3997 case 1:
3998 DRM_ERROR("old table version %d, %d\n", frev, crev);
3999 return -EINVAL;
4000 case 2:
4001 switch (crev) {
4002 case 1:
4003 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
4004 ATOM_INIT_REG_BLOCK *reg_block =
4005 (ATOM_INIT_REG_BLOCK *)
4006 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
4007 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
4008 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4009 ((u8 *)reg_block + (2 * sizeof(u16)) +
4010 le16_to_cpu(reg_block->usRegIndexTblSize));
4011 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0];
4012 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
4013 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
4014 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
4015 return -EINVAL;
4016 while (i < num_entries) {
4017 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
4018 break;
4019 reg_table->mc_reg_address[i].s1 =
4020 (u16)(le16_to_cpu(format->usRegIndex));
4021 reg_table->mc_reg_address[i].pre_reg_data =
4022 (u8)(format->ucPreRegDataLength);
4023 i++;
4024 format = (ATOM_INIT_REG_INDEX_FORMAT *)
4025 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
4026 }
4027 reg_table->last = i;
4028 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
4029 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
4030 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
4031 >> MEM_ID_SHIFT);
4032 if (module_index == t_mem_id) {
4033 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
4034 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
4035 >> CLOCK_RANGE_SHIFT);
4036 for (i = 0, j = 1; i < reg_table->last; i++) {
4037 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
4038 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4039 (u32)le32_to_cpu(*((u32 *)reg_data + j));
4040 j++;
4041 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
4042 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4043 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
4044 }
4045 }
4046 num_ranges++;
4047 }
4048 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4049 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
4050 }
4051 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
4052 return -EINVAL;
4053 reg_table->num_entries = num_ranges;
4054 } else
4055 return -EINVAL;
4056 break;
4057 default:
4058 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4059 return -EINVAL;
4060 }
4061 break;
4062 default:
4063 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4064 return -EINVAL;
4065 }
4066 return 0;
4067 }
4068 return -EINVAL;
4069 }
4070
radeon_atom_initialize_bios_scratch_regs(struct drm_device * dev)4071 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
4072 {
4073 struct radeon_device *rdev = dev->dev_private;
4074 uint32_t bios_2_scratch, bios_6_scratch;
4075
4076 if (rdev->family >= CHIP_R600) {
4077 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4078 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4079 } else {
4080 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4081 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4082 }
4083
4084 /* let the bios control the backlight */
4085 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
4086
4087 /* tell the bios not to handle mode switching */
4088 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
4089
4090 /* clear the vbios dpms state */
4091 if (ASIC_IS_DCE4(rdev))
4092 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
4093
4094 if (rdev->family >= CHIP_R600) {
4095 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4096 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4097 } else {
4098 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4099 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4100 }
4101
4102 }
4103
radeon_save_bios_scratch_regs(struct radeon_device * rdev)4104 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
4105 {
4106 uint32_t scratch_reg;
4107 int i;
4108
4109 if (rdev->family >= CHIP_R600)
4110 scratch_reg = R600_BIOS_0_SCRATCH;
4111 else
4112 scratch_reg = RADEON_BIOS_0_SCRATCH;
4113
4114 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4115 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
4116 }
4117
radeon_restore_bios_scratch_regs(struct radeon_device * rdev)4118 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
4119 {
4120 uint32_t scratch_reg;
4121 int i;
4122
4123 if (rdev->family >= CHIP_R600)
4124 scratch_reg = R600_BIOS_0_SCRATCH;
4125 else
4126 scratch_reg = RADEON_BIOS_0_SCRATCH;
4127
4128 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4129 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
4130 }
4131
radeon_atom_output_lock(struct drm_encoder * encoder,bool lock)4132 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
4133 {
4134 struct drm_device *dev = encoder->dev;
4135 struct radeon_device *rdev = dev->dev_private;
4136 uint32_t bios_6_scratch;
4137
4138 if (rdev->family >= CHIP_R600)
4139 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4140 else
4141 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4142
4143 if (lock) {
4144 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
4145 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
4146 } else {
4147 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
4148 bios_6_scratch |= ATOM_S6_ACC_MODE;
4149 }
4150
4151 if (rdev->family >= CHIP_R600)
4152 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4153 else
4154 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4155 }
4156
4157 /* at some point we may want to break this out into individual functions */
4158 void
radeon_atombios_connected_scratch_regs(struct drm_connector * connector,struct drm_encoder * encoder,bool connected)4159 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
4160 struct drm_encoder *encoder,
4161 bool connected)
4162 {
4163 struct drm_device *dev = connector->dev;
4164 struct radeon_device *rdev = dev->dev_private;
4165 struct radeon_connector *radeon_connector =
4166 to_radeon_connector(connector);
4167 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4168 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
4169
4170 if (rdev->family >= CHIP_R600) {
4171 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
4172 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4173 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4174 } else {
4175 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
4176 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4177 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4178 }
4179
4180 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
4181 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
4182 if (connected) {
4183 DRM_DEBUG_KMS("TV1 connected\n");
4184 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
4185 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
4186 } else {
4187 DRM_DEBUG_KMS("TV1 disconnected\n");
4188 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
4189 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
4190 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
4191 }
4192 }
4193 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
4194 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
4195 if (connected) {
4196 DRM_DEBUG_KMS("CV connected\n");
4197 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
4198 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
4199 } else {
4200 DRM_DEBUG_KMS("CV disconnected\n");
4201 bios_0_scratch &= ~ATOM_S0_CV_MASK;
4202 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
4203 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
4204 }
4205 }
4206 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
4207 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
4208 if (connected) {
4209 DRM_DEBUG_KMS("LCD1 connected\n");
4210 bios_0_scratch |= ATOM_S0_LCD1;
4211 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
4212 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
4213 } else {
4214 DRM_DEBUG_KMS("LCD1 disconnected\n");
4215 bios_0_scratch &= ~ATOM_S0_LCD1;
4216 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
4217 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
4218 }
4219 }
4220 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
4221 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
4222 if (connected) {
4223 DRM_DEBUG_KMS("CRT1 connected\n");
4224 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
4225 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
4226 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
4227 } else {
4228 DRM_DEBUG_KMS("CRT1 disconnected\n");
4229 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
4230 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
4231 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
4232 }
4233 }
4234 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
4235 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
4236 if (connected) {
4237 DRM_DEBUG_KMS("CRT2 connected\n");
4238 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
4239 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
4240 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
4241 } else {
4242 DRM_DEBUG_KMS("CRT2 disconnected\n");
4243 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
4244 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
4245 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
4246 }
4247 }
4248 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
4249 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
4250 if (connected) {
4251 DRM_DEBUG_KMS("DFP1 connected\n");
4252 bios_0_scratch |= ATOM_S0_DFP1;
4253 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
4254 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
4255 } else {
4256 DRM_DEBUG_KMS("DFP1 disconnected\n");
4257 bios_0_scratch &= ~ATOM_S0_DFP1;
4258 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
4259 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
4260 }
4261 }
4262 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
4263 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
4264 if (connected) {
4265 DRM_DEBUG_KMS("DFP2 connected\n");
4266 bios_0_scratch |= ATOM_S0_DFP2;
4267 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
4268 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
4269 } else {
4270 DRM_DEBUG_KMS("DFP2 disconnected\n");
4271 bios_0_scratch &= ~ATOM_S0_DFP2;
4272 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
4273 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
4274 }
4275 }
4276 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
4277 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
4278 if (connected) {
4279 DRM_DEBUG_KMS("DFP3 connected\n");
4280 bios_0_scratch |= ATOM_S0_DFP3;
4281 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
4282 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
4283 } else {
4284 DRM_DEBUG_KMS("DFP3 disconnected\n");
4285 bios_0_scratch &= ~ATOM_S0_DFP3;
4286 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
4287 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
4288 }
4289 }
4290 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
4291 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
4292 if (connected) {
4293 DRM_DEBUG_KMS("DFP4 connected\n");
4294 bios_0_scratch |= ATOM_S0_DFP4;
4295 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
4296 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
4297 } else {
4298 DRM_DEBUG_KMS("DFP4 disconnected\n");
4299 bios_0_scratch &= ~ATOM_S0_DFP4;
4300 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
4301 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
4302 }
4303 }
4304 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
4305 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
4306 if (connected) {
4307 DRM_DEBUG_KMS("DFP5 connected\n");
4308 bios_0_scratch |= ATOM_S0_DFP5;
4309 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
4310 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
4311 } else {
4312 DRM_DEBUG_KMS("DFP5 disconnected\n");
4313 bios_0_scratch &= ~ATOM_S0_DFP5;
4314 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
4315 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
4316 }
4317 }
4318 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
4319 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
4320 if (connected) {
4321 DRM_DEBUG_KMS("DFP6 connected\n");
4322 bios_0_scratch |= ATOM_S0_DFP6;
4323 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
4324 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
4325 } else {
4326 DRM_DEBUG_KMS("DFP6 disconnected\n");
4327 bios_0_scratch &= ~ATOM_S0_DFP6;
4328 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
4329 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
4330 }
4331 }
4332
4333 if (rdev->family >= CHIP_R600) {
4334 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
4335 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4336 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4337 } else {
4338 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
4339 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4340 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4341 }
4342 }
4343
4344 void
radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder * encoder,int crtc)4345 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
4346 {
4347 struct drm_device *dev = encoder->dev;
4348 struct radeon_device *rdev = dev->dev_private;
4349 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4350 uint32_t bios_3_scratch;
4351
4352 if (ASIC_IS_DCE4(rdev))
4353 return;
4354
4355 if (rdev->family >= CHIP_R600)
4356 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4357 else
4358 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4359
4360 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4361 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
4362 bios_3_scratch |= (crtc << 18);
4363 }
4364 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4365 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
4366 bios_3_scratch |= (crtc << 24);
4367 }
4368 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4369 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
4370 bios_3_scratch |= (crtc << 16);
4371 }
4372 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4373 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
4374 bios_3_scratch |= (crtc << 20);
4375 }
4376 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4377 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
4378 bios_3_scratch |= (crtc << 17);
4379 }
4380 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4381 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
4382 bios_3_scratch |= (crtc << 19);
4383 }
4384 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4385 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
4386 bios_3_scratch |= (crtc << 23);
4387 }
4388 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4389 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
4390 bios_3_scratch |= (crtc << 25);
4391 }
4392
4393 if (rdev->family >= CHIP_R600)
4394 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4395 else
4396 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4397 }
4398
4399 void
radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder * encoder,bool on)4400 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
4401 {
4402 struct drm_device *dev = encoder->dev;
4403 struct radeon_device *rdev = dev->dev_private;
4404 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4405 uint32_t bios_2_scratch;
4406
4407 if (ASIC_IS_DCE4(rdev))
4408 return;
4409
4410 if (rdev->family >= CHIP_R600)
4411 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4412 else
4413 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4414
4415 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4416 if (on)
4417 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
4418 else
4419 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
4420 }
4421 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4422 if (on)
4423 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
4424 else
4425 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
4426 }
4427 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4428 if (on)
4429 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
4430 else
4431 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
4432 }
4433 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4434 if (on)
4435 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
4436 else
4437 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
4438 }
4439 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4440 if (on)
4441 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
4442 else
4443 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
4444 }
4445 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4446 if (on)
4447 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
4448 else
4449 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
4450 }
4451 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4452 if (on)
4453 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
4454 else
4455 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
4456 }
4457 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4458 if (on)
4459 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
4460 else
4461 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
4462 }
4463 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
4464 if (on)
4465 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
4466 else
4467 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
4468 }
4469 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
4470 if (on)
4471 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
4472 else
4473 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
4474 }
4475
4476 if (rdev->family >= CHIP_R600)
4477 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4478 else
4479 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4480 }
4481