1 /*
2 * Copyright 2008 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Jerome Glisse <glisse@freedesktop.org>
26 */
27
28 #include <linux/list_sort.h>
29 #include <linux/pci.h>
30 #include <linux/uaccess.h>
31
32 #include <drm/drm_device.h>
33 #include <drm/drm_file.h>
34 #include <drm/radeon_drm.h>
35
36 #include "radeon.h"
37 #include "radeon_reg.h"
38 #include "radeon_trace.h"
39
40 #define RADEON_CS_MAX_PRIORITY 32u
41 #define RADEON_CS_NUM_BUCKETS (RADEON_CS_MAX_PRIORITY + 1)
42
43 /* This is based on the bucket sort with O(n) time complexity.
44 * An item with priority "i" is added to bucket[i]. The lists are then
45 * concatenated in descending order.
46 */
47 struct radeon_cs_buckets {
48 struct list_head bucket[RADEON_CS_NUM_BUCKETS];
49 };
50
radeon_cs_buckets_init(struct radeon_cs_buckets * b)51 static void radeon_cs_buckets_init(struct radeon_cs_buckets *b)
52 {
53 unsigned i;
54
55 for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++)
56 INIT_LIST_HEAD(&b->bucket[i]);
57 }
58
radeon_cs_buckets_add(struct radeon_cs_buckets * b,struct list_head * item,unsigned priority)59 static void radeon_cs_buckets_add(struct radeon_cs_buckets *b,
60 struct list_head *item, unsigned priority)
61 {
62 /* Since buffers which appear sooner in the relocation list are
63 * likely to be used more often than buffers which appear later
64 * in the list, the sort mustn't change the ordering of buffers
65 * with the same priority, i.e. it must be stable.
66 */
67 list_add_tail(item, &b->bucket[min(priority, RADEON_CS_MAX_PRIORITY)]);
68 }
69
radeon_cs_buckets_get_list(struct radeon_cs_buckets * b,struct list_head * out_list)70 static void radeon_cs_buckets_get_list(struct radeon_cs_buckets *b,
71 struct list_head *out_list)
72 {
73 unsigned i;
74
75 /* Connect the sorted buckets in the output list. */
76 for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++) {
77 list_splice(&b->bucket[i], out_list);
78 }
79 }
80
radeon_cs_parser_relocs(struct radeon_cs_parser * p)81 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
82 {
83 struct radeon_cs_chunk *chunk;
84 struct radeon_cs_buckets buckets;
85 unsigned i;
86 bool need_mmap_lock = false;
87 int r;
88
89 if (p->chunk_relocs == NULL) {
90 return 0;
91 }
92 chunk = p->chunk_relocs;
93 p->dma_reloc_idx = 0;
94 /* FIXME: we assume that each relocs use 4 dwords */
95 p->nrelocs = chunk->length_dw / 4;
96 p->relocs = kvcalloc(p->nrelocs, sizeof(struct radeon_bo_list),
97 GFP_KERNEL);
98 if (p->relocs == NULL) {
99 return -ENOMEM;
100 }
101
102 radeon_cs_buckets_init(&buckets);
103
104 for (i = 0; i < p->nrelocs; i++) {
105 struct drm_radeon_cs_reloc *r;
106 struct drm_gem_object *gobj;
107 unsigned priority;
108
109 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
110 gobj = drm_gem_object_lookup(p->filp, r->handle);
111 if (gobj == NULL) {
112 DRM_ERROR("gem object lookup failed 0x%x\n",
113 r->handle);
114 return -ENOENT;
115 }
116 p->relocs[i].robj = gem_to_radeon_bo(gobj);
117
118 /* The userspace buffer priorities are from 0 to 15. A higher
119 * number means the buffer is more important.
120 * Also, the buffers used for write have a higher priority than
121 * the buffers used for read only, which doubles the range
122 * to 0 to 31. 32 is reserved for the kernel driver.
123 */
124 priority = (r->flags & RADEON_RELOC_PRIO_MASK) * 2
125 + !!r->write_domain;
126
127 /* The first reloc of an UVD job is the msg and that must be in
128 * VRAM, the second reloc is the DPB and for WMV that must be in
129 * VRAM as well. Also put everything into VRAM on AGP cards and older
130 * IGP chips to avoid image corruptions
131 */
132 if (p->ring == R600_RING_TYPE_UVD_INDEX &&
133 (i <= 0 || (p->rdev->flags & RADEON_IS_AGP) ||
134 p->rdev->family == CHIP_RS780 ||
135 p->rdev->family == CHIP_RS880)) {
136
137 /* TODO: is this still needed for NI+ ? */
138 p->relocs[i].preferred_domains =
139 RADEON_GEM_DOMAIN_VRAM;
140
141 p->relocs[i].allowed_domains =
142 RADEON_GEM_DOMAIN_VRAM;
143
144 /* prioritize this over any other relocation */
145 priority = RADEON_CS_MAX_PRIORITY;
146 } else {
147 uint32_t domain = r->write_domain ?
148 r->write_domain : r->read_domains;
149
150 if (domain & RADEON_GEM_DOMAIN_CPU) {
151 DRM_ERROR("RADEON_GEM_DOMAIN_CPU is not valid "
152 "for command submission\n");
153 return -EINVAL;
154 }
155
156 p->relocs[i].preferred_domains = domain;
157 if (domain == RADEON_GEM_DOMAIN_VRAM)
158 domain |= RADEON_GEM_DOMAIN_GTT;
159 p->relocs[i].allowed_domains = domain;
160 }
161
162 if (radeon_ttm_tt_has_userptr(p->rdev, p->relocs[i].robj->tbo.ttm)) {
163 uint32_t domain = p->relocs[i].preferred_domains;
164 if (!(domain & RADEON_GEM_DOMAIN_GTT)) {
165 DRM_ERROR("Only RADEON_GEM_DOMAIN_GTT is "
166 "allowed for userptr BOs\n");
167 return -EINVAL;
168 }
169 need_mmap_lock = true;
170 domain = RADEON_GEM_DOMAIN_GTT;
171 p->relocs[i].preferred_domains = domain;
172 p->relocs[i].allowed_domains = domain;
173 }
174
175 /* Objects shared as dma-bufs cannot be moved to VRAM */
176 if (p->relocs[i].robj->prime_shared_count) {
177 p->relocs[i].allowed_domains &= ~RADEON_GEM_DOMAIN_VRAM;
178 if (!p->relocs[i].allowed_domains) {
179 DRM_ERROR("BO associated with dma-buf cannot "
180 "be moved to VRAM\n");
181 return -EINVAL;
182 }
183 }
184
185 p->relocs[i].tv.bo = &p->relocs[i].robj->tbo;
186 p->relocs[i].tv.num_shared = !r->write_domain;
187
188 radeon_cs_buckets_add(&buckets, &p->relocs[i].tv.head,
189 priority);
190 }
191
192 radeon_cs_buckets_get_list(&buckets, &p->validated);
193
194 if (p->cs_flags & RADEON_CS_USE_VM)
195 p->vm_bos = radeon_vm_get_bos(p->rdev, p->ib.vm,
196 &p->validated);
197 #ifdef notyet
198 if (need_mmap_lock)
199 mmap_read_lock(current->mm);
200 #endif
201
202 r = radeon_bo_list_validate(p->rdev, &p->ticket, &p->validated, p->ring);
203
204 #ifdef notyet
205 if (need_mmap_lock)
206 mmap_read_unlock(current->mm);
207 #endif
208
209 return r;
210 }
211
radeon_cs_get_ring(struct radeon_cs_parser * p,u32 ring,s32 priority)212 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
213 {
214 p->priority = priority;
215
216 switch (ring) {
217 default:
218 DRM_ERROR("unknown ring id: %d\n", ring);
219 return -EINVAL;
220 case RADEON_CS_RING_GFX:
221 p->ring = RADEON_RING_TYPE_GFX_INDEX;
222 break;
223 case RADEON_CS_RING_COMPUTE:
224 if (p->rdev->family >= CHIP_TAHITI) {
225 if (p->priority > 0)
226 p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
227 else
228 p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
229 } else
230 p->ring = RADEON_RING_TYPE_GFX_INDEX;
231 break;
232 case RADEON_CS_RING_DMA:
233 if (p->rdev->family >= CHIP_CAYMAN) {
234 if (p->priority > 0)
235 p->ring = R600_RING_TYPE_DMA_INDEX;
236 else
237 p->ring = CAYMAN_RING_TYPE_DMA1_INDEX;
238 } else if (p->rdev->family >= CHIP_RV770) {
239 p->ring = R600_RING_TYPE_DMA_INDEX;
240 } else {
241 return -EINVAL;
242 }
243 break;
244 case RADEON_CS_RING_UVD:
245 p->ring = R600_RING_TYPE_UVD_INDEX;
246 break;
247 case RADEON_CS_RING_VCE:
248 /* TODO: only use the low priority ring for now */
249 p->ring = TN_RING_TYPE_VCE1_INDEX;
250 break;
251 }
252 return 0;
253 }
254
radeon_cs_sync_rings(struct radeon_cs_parser * p)255 static int radeon_cs_sync_rings(struct radeon_cs_parser *p)
256 {
257 struct radeon_bo_list *reloc;
258 int r;
259
260 list_for_each_entry(reloc, &p->validated, tv.head) {
261 struct dma_resv *resv;
262
263 resv = reloc->robj->tbo.base.resv;
264 r = radeon_sync_resv(p->rdev, &p->ib.sync, resv,
265 reloc->tv.num_shared);
266 if (r)
267 return r;
268 }
269 return 0;
270 }
271
272 /* XXX: note that this is called from the legacy UMS CS ioctl as well */
radeon_cs_parser_init(struct radeon_cs_parser * p,void * data)273 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
274 {
275 struct drm_radeon_cs *cs = data;
276 uint64_t *chunk_array_ptr;
277 u64 size;
278 unsigned i;
279 u32 ring = RADEON_CS_RING_GFX;
280 s32 priority = 0;
281
282 INIT_LIST_HEAD(&p->validated);
283
284 if (!cs->num_chunks) {
285 return 0;
286 }
287
288 /* get chunks */
289 p->idx = 0;
290 p->ib.sa_bo = NULL;
291 p->const_ib.sa_bo = NULL;
292 p->chunk_ib = NULL;
293 p->chunk_relocs = NULL;
294 p->chunk_flags = NULL;
295 p->chunk_const_ib = NULL;
296 p->chunks_array = kvmalloc_array(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
297 if (p->chunks_array == NULL) {
298 return -ENOMEM;
299 }
300 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
301 if (copy_from_user(p->chunks_array, chunk_array_ptr,
302 sizeof(uint64_t)*cs->num_chunks)) {
303 return -EFAULT;
304 }
305 p->cs_flags = 0;
306 p->nchunks = cs->num_chunks;
307 p->chunks = kvcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
308 if (p->chunks == NULL) {
309 return -ENOMEM;
310 }
311 for (i = 0; i < p->nchunks; i++) {
312 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
313 struct drm_radeon_cs_chunk user_chunk;
314 uint32_t __user *cdata;
315
316 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
317 if (copy_from_user(&user_chunk, chunk_ptr,
318 sizeof(struct drm_radeon_cs_chunk))) {
319 return -EFAULT;
320 }
321 p->chunks[i].length_dw = user_chunk.length_dw;
322 if (user_chunk.chunk_id == RADEON_CHUNK_ID_RELOCS) {
323 p->chunk_relocs = &p->chunks[i];
324 }
325 if (user_chunk.chunk_id == RADEON_CHUNK_ID_IB) {
326 p->chunk_ib = &p->chunks[i];
327 /* zero length IB isn't useful */
328 if (p->chunks[i].length_dw == 0)
329 return -EINVAL;
330 }
331 if (user_chunk.chunk_id == RADEON_CHUNK_ID_CONST_IB) {
332 p->chunk_const_ib = &p->chunks[i];
333 /* zero length CONST IB isn't useful */
334 if (p->chunks[i].length_dw == 0)
335 return -EINVAL;
336 }
337 if (user_chunk.chunk_id == RADEON_CHUNK_ID_FLAGS) {
338 p->chunk_flags = &p->chunks[i];
339 /* zero length flags aren't useful */
340 if (p->chunks[i].length_dw == 0)
341 return -EINVAL;
342 }
343
344 size = p->chunks[i].length_dw;
345 cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
346 p->chunks[i].user_ptr = cdata;
347 if (user_chunk.chunk_id == RADEON_CHUNK_ID_CONST_IB)
348 continue;
349
350 if (user_chunk.chunk_id == RADEON_CHUNK_ID_IB) {
351 if (!p->rdev || !(p->rdev->flags & RADEON_IS_AGP))
352 continue;
353 }
354
355 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
356 size *= sizeof(uint32_t);
357 if (p->chunks[i].kdata == NULL) {
358 return -ENOMEM;
359 }
360 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
361 return -EFAULT;
362 }
363 if (user_chunk.chunk_id == RADEON_CHUNK_ID_FLAGS) {
364 p->cs_flags = p->chunks[i].kdata[0];
365 if (p->chunks[i].length_dw > 1)
366 ring = p->chunks[i].kdata[1];
367 if (p->chunks[i].length_dw > 2)
368 priority = (s32)p->chunks[i].kdata[2];
369 }
370 }
371
372 /* these are KMS only */
373 if (p->rdev) {
374 if ((p->cs_flags & RADEON_CS_USE_VM) &&
375 !p->rdev->vm_manager.enabled) {
376 DRM_ERROR("VM not active on asic!\n");
377 return -EINVAL;
378 }
379
380 if (radeon_cs_get_ring(p, ring, priority))
381 return -EINVAL;
382
383 /* we only support VM on some SI+ rings */
384 if ((p->cs_flags & RADEON_CS_USE_VM) == 0) {
385 if (p->rdev->asic->ring[p->ring]->cs_parse == NULL) {
386 DRM_ERROR("Ring %d requires VM!\n", p->ring);
387 return -EINVAL;
388 }
389 } else {
390 if (p->rdev->asic->ring[p->ring]->ib_parse == NULL) {
391 DRM_ERROR("VM not supported on ring %d!\n",
392 p->ring);
393 return -EINVAL;
394 }
395 }
396 }
397
398 return 0;
399 }
400
cmp_size_smaller_first(void * priv,const struct list_head * a,const struct list_head * b)401 static int cmp_size_smaller_first(void *priv, const struct list_head *a,
402 const struct list_head *b)
403 {
404 struct radeon_bo_list *la = list_entry(a, struct radeon_bo_list, tv.head);
405 struct radeon_bo_list *lb = list_entry(b, struct radeon_bo_list, tv.head);
406
407 /* Sort A before B if A is smaller. */
408 if (la->robj->tbo.base.size > lb->robj->tbo.base.size)
409 return 1;
410 if (la->robj->tbo.base.size < lb->robj->tbo.base.size)
411 return -1;
412 return 0;
413 }
414
415 /**
416 * radeon_cs_parser_fini() - clean parser states
417 * @parser: parser structure holding parsing context.
418 * @error: error number
419 * @backoff: indicator to backoff the reservation
420 *
421 * If error is set than unvalidate buffer, otherwise just free memory
422 * used by parsing context.
423 **/
radeon_cs_parser_fini(struct radeon_cs_parser * parser,int error,bool backoff)424 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error, bool backoff)
425 {
426 unsigned i;
427
428 if (!error) {
429 /* Sort the buffer list from the smallest to largest buffer,
430 * which affects the order of buffers in the LRU list.
431 * This assures that the smallest buffers are added first
432 * to the LRU list, so they are likely to be later evicted
433 * first, instead of large buffers whose eviction is more
434 * expensive.
435 *
436 * This slightly lowers the number of bytes moved by TTM
437 * per frame under memory pressure.
438 */
439 list_sort(NULL, &parser->validated, cmp_size_smaller_first);
440
441 ttm_eu_fence_buffer_objects(&parser->ticket,
442 &parser->validated,
443 &parser->ib.fence->base);
444 } else if (backoff) {
445 ttm_eu_backoff_reservation(&parser->ticket,
446 &parser->validated);
447 }
448
449 if (parser->relocs != NULL) {
450 for (i = 0; i < parser->nrelocs; i++) {
451 struct radeon_bo *bo = parser->relocs[i].robj;
452 if (bo == NULL)
453 continue;
454
455 drm_gem_object_put(&bo->tbo.base);
456 }
457 }
458 kfree(parser->track);
459 kvfree(parser->relocs);
460 kvfree(parser->vm_bos);
461 for (i = 0; i < parser->nchunks; i++)
462 kvfree(parser->chunks[i].kdata);
463 kvfree(parser->chunks);
464 kvfree(parser->chunks_array);
465 radeon_ib_free(parser->rdev, &parser->ib);
466 radeon_ib_free(parser->rdev, &parser->const_ib);
467 }
468
radeon_cs_ib_chunk(struct radeon_device * rdev,struct radeon_cs_parser * parser)469 static int radeon_cs_ib_chunk(struct radeon_device *rdev,
470 struct radeon_cs_parser *parser)
471 {
472 int r;
473
474 if (parser->chunk_ib == NULL)
475 return 0;
476
477 if (parser->cs_flags & RADEON_CS_USE_VM)
478 return 0;
479
480 r = radeon_cs_parse(rdev, parser->ring, parser);
481 if (r || parser->parser_error) {
482 DRM_ERROR("Invalid command stream !\n");
483 return r;
484 }
485
486 r = radeon_cs_sync_rings(parser);
487 if (r) {
488 if (r != -ERESTARTSYS)
489 DRM_ERROR("Failed to sync rings: %i\n", r);
490 return r;
491 }
492
493 if (parser->ring == R600_RING_TYPE_UVD_INDEX)
494 radeon_uvd_note_usage(rdev);
495 else if ((parser->ring == TN_RING_TYPE_VCE1_INDEX) ||
496 (parser->ring == TN_RING_TYPE_VCE2_INDEX))
497 radeon_vce_note_usage(rdev);
498
499 r = radeon_ib_schedule(rdev, &parser->ib, NULL, true);
500 if (r) {
501 DRM_ERROR("Failed to schedule IB !\n");
502 }
503 return r;
504 }
505
radeon_bo_vm_update_pte(struct radeon_cs_parser * p,struct radeon_vm * vm)506 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *p,
507 struct radeon_vm *vm)
508 {
509 struct radeon_device *rdev = p->rdev;
510 struct radeon_bo_va *bo_va;
511 int i, r;
512
513 r = radeon_vm_update_page_directory(rdev, vm);
514 if (r)
515 return r;
516
517 r = radeon_vm_clear_freed(rdev, vm);
518 if (r)
519 return r;
520
521 if (vm->ib_bo_va == NULL) {
522 DRM_ERROR("Tmp BO not in VM!\n");
523 return -EINVAL;
524 }
525
526 r = radeon_vm_bo_update(rdev, vm->ib_bo_va,
527 rdev->ring_tmp_bo.bo->tbo.resource);
528 if (r)
529 return r;
530
531 for (i = 0; i < p->nrelocs; i++) {
532 struct radeon_bo *bo;
533
534 bo = p->relocs[i].robj;
535 bo_va = radeon_vm_bo_find(vm, bo);
536 if (bo_va == NULL) {
537 dev_err(rdev->dev, "bo %p not in vm %p\n", bo, vm);
538 return -EINVAL;
539 }
540
541 r = radeon_vm_bo_update(rdev, bo_va, bo->tbo.resource);
542 if (r)
543 return r;
544
545 radeon_sync_fence(&p->ib.sync, bo_va->last_pt_update);
546
547 r = dma_resv_reserve_fences(bo->tbo.base.resv, 1);
548 if (r)
549 return r;
550 }
551
552 return radeon_vm_clear_invalids(rdev, vm);
553 }
554
radeon_cs_ib_vm_chunk(struct radeon_device * rdev,struct radeon_cs_parser * parser)555 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
556 struct radeon_cs_parser *parser)
557 {
558 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
559 struct radeon_vm *vm = &fpriv->vm;
560 int r;
561
562 if (parser->chunk_ib == NULL)
563 return 0;
564 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
565 return 0;
566
567 if (parser->const_ib.length_dw) {
568 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
569 if (r) {
570 return r;
571 }
572 }
573
574 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
575 if (r) {
576 return r;
577 }
578
579 if (parser->ring == R600_RING_TYPE_UVD_INDEX)
580 radeon_uvd_note_usage(rdev);
581
582 mutex_lock(&vm->mutex);
583 r = radeon_bo_vm_update_pte(parser, vm);
584 if (r) {
585 goto out;
586 }
587
588 r = radeon_cs_sync_rings(parser);
589 if (r) {
590 if (r != -ERESTARTSYS)
591 DRM_ERROR("Failed to sync rings: %i\n", r);
592 goto out;
593 }
594
595 if ((rdev->family >= CHIP_TAHITI) &&
596 (parser->chunk_const_ib != NULL)) {
597 r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib, true);
598 } else {
599 r = radeon_ib_schedule(rdev, &parser->ib, NULL, true);
600 }
601
602 out:
603 mutex_unlock(&vm->mutex);
604 return r;
605 }
606
radeon_cs_handle_lockup(struct radeon_device * rdev,int r)607 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
608 {
609 if (r == -EDEADLK) {
610 r = radeon_gpu_reset(rdev);
611 if (!r)
612 r = -EAGAIN;
613 }
614 return r;
615 }
616
radeon_cs_ib_fill(struct radeon_device * rdev,struct radeon_cs_parser * parser)617 static int radeon_cs_ib_fill(struct radeon_device *rdev, struct radeon_cs_parser *parser)
618 {
619 struct radeon_cs_chunk *ib_chunk;
620 struct radeon_vm *vm = NULL;
621 int r;
622
623 if (parser->chunk_ib == NULL)
624 return 0;
625
626 if (parser->cs_flags & RADEON_CS_USE_VM) {
627 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
628 vm = &fpriv->vm;
629
630 if ((rdev->family >= CHIP_TAHITI) &&
631 (parser->chunk_const_ib != NULL)) {
632 ib_chunk = parser->chunk_const_ib;
633 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
634 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
635 return -EINVAL;
636 }
637 r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
638 vm, ib_chunk->length_dw * 4);
639 if (r) {
640 DRM_ERROR("Failed to get const ib !\n");
641 return r;
642 }
643 parser->const_ib.is_const_ib = true;
644 parser->const_ib.length_dw = ib_chunk->length_dw;
645 if (copy_from_user(parser->const_ib.ptr,
646 ib_chunk->user_ptr,
647 ib_chunk->length_dw * 4))
648 return -EFAULT;
649 }
650
651 ib_chunk = parser->chunk_ib;
652 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
653 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
654 return -EINVAL;
655 }
656 }
657 ib_chunk = parser->chunk_ib;
658
659 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
660 vm, ib_chunk->length_dw * 4);
661 if (r) {
662 DRM_ERROR("Failed to get ib !\n");
663 return r;
664 }
665 parser->ib.length_dw = ib_chunk->length_dw;
666 if (ib_chunk->kdata)
667 memcpy(parser->ib.ptr, ib_chunk->kdata, ib_chunk->length_dw * 4);
668 else if (copy_from_user(parser->ib.ptr, ib_chunk->user_ptr, ib_chunk->length_dw * 4))
669 return -EFAULT;
670 return 0;
671 }
672
radeon_cs_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)673 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
674 {
675 struct radeon_device *rdev = dev->dev_private;
676 struct radeon_cs_parser parser;
677 int r;
678
679 down_read(&rdev->exclusive_lock);
680 if (!rdev->accel_working) {
681 up_read(&rdev->exclusive_lock);
682 return -EBUSY;
683 }
684 if (rdev->in_reset) {
685 up_read(&rdev->exclusive_lock);
686 r = radeon_gpu_reset(rdev);
687 if (!r)
688 r = -EAGAIN;
689 return r;
690 }
691 /* initialize parser */
692 memset(&parser, 0, sizeof(struct radeon_cs_parser));
693 parser.filp = filp;
694 parser.rdev = rdev;
695 parser.dev = rdev->dev;
696 parser.family = rdev->family;
697 r = radeon_cs_parser_init(&parser, data);
698 if (r) {
699 DRM_ERROR("Failed to initialize parser !\n");
700 radeon_cs_parser_fini(&parser, r, false);
701 up_read(&rdev->exclusive_lock);
702 r = radeon_cs_handle_lockup(rdev, r);
703 return r;
704 }
705
706 r = radeon_cs_ib_fill(rdev, &parser);
707 if (!r) {
708 r = radeon_cs_parser_relocs(&parser);
709 if (r && r != -ERESTARTSYS)
710 DRM_ERROR("Failed to parse relocation %d!\n", r);
711 }
712
713 if (r) {
714 radeon_cs_parser_fini(&parser, r, false);
715 up_read(&rdev->exclusive_lock);
716 r = radeon_cs_handle_lockup(rdev, r);
717 return r;
718 }
719
720 trace_radeon_cs(&parser);
721
722 r = radeon_cs_ib_chunk(rdev, &parser);
723 if (r) {
724 goto out;
725 }
726 r = radeon_cs_ib_vm_chunk(rdev, &parser);
727 if (r) {
728 goto out;
729 }
730 out:
731 radeon_cs_parser_fini(&parser, r, true);
732 up_read(&rdev->exclusive_lock);
733 r = radeon_cs_handle_lockup(rdev, r);
734 return r;
735 }
736
737 /**
738 * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet
739 * @p: parser structure holding parsing context.
740 * @pkt: where to store packet information
741 * @idx: packet index
742 *
743 * Assume that chunk_ib_index is properly set. Will return -EINVAL
744 * if packet is bigger than remaining ib size. or if packets is unknown.
745 **/
radeon_cs_packet_parse(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt,unsigned idx)746 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
747 struct radeon_cs_packet *pkt,
748 unsigned idx)
749 {
750 struct radeon_cs_chunk *ib_chunk = p->chunk_ib;
751 struct radeon_device *rdev = p->rdev;
752 uint32_t header;
753 int ret = 0, i;
754
755 if (idx >= ib_chunk->length_dw) {
756 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
757 idx, ib_chunk->length_dw);
758 return -EINVAL;
759 }
760 header = radeon_get_ib_value(p, idx);
761 pkt->idx = idx;
762 pkt->type = RADEON_CP_PACKET_GET_TYPE(header);
763 pkt->count = RADEON_CP_PACKET_GET_COUNT(header);
764 pkt->one_reg_wr = 0;
765 switch (pkt->type) {
766 case RADEON_PACKET_TYPE0:
767 if (rdev->family < CHIP_R600) {
768 pkt->reg = R100_CP_PACKET0_GET_REG(header);
769 pkt->one_reg_wr =
770 RADEON_CP_PACKET0_GET_ONE_REG_WR(header);
771 } else
772 pkt->reg = R600_CP_PACKET0_GET_REG(header);
773 break;
774 case RADEON_PACKET_TYPE3:
775 pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header);
776 break;
777 case RADEON_PACKET_TYPE2:
778 pkt->count = -1;
779 break;
780 default:
781 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
782 ret = -EINVAL;
783 goto dump_ib;
784 }
785 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
786 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
787 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
788 ret = -EINVAL;
789 goto dump_ib;
790 }
791 return 0;
792
793 dump_ib:
794 for (i = 0; i < ib_chunk->length_dw; i++) {
795 if (i == idx)
796 printk("\t0x%08x <---\n", radeon_get_ib_value(p, i));
797 else
798 printk("\t0x%08x\n", radeon_get_ib_value(p, i));
799 }
800 return ret;
801 }
802
803 /**
804 * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP
805 * @p: structure holding the parser context.
806 *
807 * Check if the next packet is NOP relocation packet3.
808 **/
radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser * p)809 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
810 {
811 struct radeon_cs_packet p3reloc;
812 int r;
813
814 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
815 if (r)
816 return false;
817 if (p3reloc.type != RADEON_PACKET_TYPE3)
818 return false;
819 if (p3reloc.opcode != RADEON_PACKET3_NOP)
820 return false;
821 return true;
822 }
823
824 /**
825 * radeon_cs_dump_packet() - dump raw packet context
826 * @p: structure holding the parser context.
827 * @pkt: structure holding the packet.
828 *
829 * Used mostly for debugging and error reporting.
830 **/
radeon_cs_dump_packet(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt)831 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
832 struct radeon_cs_packet *pkt)
833 {
834 volatile uint32_t *ib;
835 unsigned i;
836 unsigned idx;
837
838 ib = p->ib.ptr;
839 idx = pkt->idx;
840 for (i = 0; i <= (pkt->count + 1); i++, idx++)
841 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
842 }
843
844 /**
845 * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet
846 * @p: parser structure holding parsing context.
847 * @cs_reloc: reloc informations
848 * @nomm: no memory management for debugging
849 *
850 * Check if next packet is relocation packet3, do bo validation and compute
851 * GPU offset using the provided start.
852 **/
radeon_cs_packet_next_reloc(struct radeon_cs_parser * p,struct radeon_bo_list ** cs_reloc,int nomm)853 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
854 struct radeon_bo_list **cs_reloc,
855 int nomm)
856 {
857 struct radeon_cs_chunk *relocs_chunk;
858 struct radeon_cs_packet p3reloc;
859 unsigned idx;
860 int r;
861
862 if (p->chunk_relocs == NULL) {
863 DRM_ERROR("No relocation chunk !\n");
864 return -EINVAL;
865 }
866 *cs_reloc = NULL;
867 relocs_chunk = p->chunk_relocs;
868 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
869 if (r)
870 return r;
871 p->idx += p3reloc.count + 2;
872 if (p3reloc.type != RADEON_PACKET_TYPE3 ||
873 p3reloc.opcode != RADEON_PACKET3_NOP) {
874 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
875 p3reloc.idx);
876 radeon_cs_dump_packet(p, &p3reloc);
877 return -EINVAL;
878 }
879 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
880 if (idx >= relocs_chunk->length_dw) {
881 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
882 idx, relocs_chunk->length_dw);
883 radeon_cs_dump_packet(p, &p3reloc);
884 return -EINVAL;
885 }
886 /* FIXME: we assume reloc size is 4 dwords */
887 if (nomm) {
888 *cs_reloc = p->relocs;
889 (*cs_reloc)->gpu_offset =
890 (u64)relocs_chunk->kdata[idx + 3] << 32;
891 (*cs_reloc)->gpu_offset |= relocs_chunk->kdata[idx + 0];
892 } else
893 *cs_reloc = &p->relocs[(idx / 4)];
894 return 0;
895 }
896