1 /* Caprice32 - Amstrad CPC Emulator
2 (c) Copyright 1997-2004 Ulrich Doewich
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19 /* Zilog Z80A Microprocessor emulation
20 (c) Copyright 1997-2003 Ulrich Doewich
21
22 code portions and ideas taken from the Z80 emulations by:
23 Juergen Buchmueller (MAME Z80 core v3.3)
24 Marat Fayzullin
25 and my own Z80 x86 assembly code (Caprice32 up to version 2.00b2)
26
27 Oct 03, 2000 - 18:56 all un-prefixed opcodes done
28 Oct 07, 2000 - 11:04 all CB opcodes done
29 Oct 07, 2000 - 15:06 all DD opcodes done
30 Oct 07, 2000 - 15:23 all DD CB opcodes done
31 Oct 09, 2000 - 12:41 all ED, FD, and FD CB opcodes done
32 Oct 14, 2000 - 17:48 added interrupt processing to z80_getopcode
33 Oct 22, 2000 - 19:18 removed R register update from DDCB and FDCB opcode handlers
34 Oct 22, 2000 - 19:43 added break-point and trace capabilities
35 Oct 24, 2000 - 17:57 changed math based opcodes to always work with unsigned parameters
36 Oct 29, 2000 - 20:46 fixed 16 bit memory read/write opcodes (read both halves from the low byte!)
37 Oct 29, 2000 - 20:51 fixed LD L,byte; RRC r (used wrong registers - forgot to change them after copy!)
38 Nov 06, 2000 - 21:08 fixed a couple of IX/IY instructions (forgot to change a few I?h/I?l related opcodes!)
39 Nov 06, 2000 - 21:20 fixed some DDCB/FDCB instructions (one too many M cycles for BIT (I?+o) & co.)
40 Nov 07, 2000 - 18:58 complete overhaul of DDCB/FDCB instructions (offset byte handling was wrong!)
41 Jan 24, 2001 - 18:26 fixed LD (IX/IY + o), L and LD (IX/IY + o), H (uses L and H, not I?l and I?h!)
42 Feb 19, 2001 - 18:37 removed machine cycle specific code; added cycle count tables and 'wait state' routine
43 Mar 05, 2001 - 22:58 reworked all cycle count tables - verfied with the real CPC & an oscilloscope
44 Mar 29, 2001 - 19:10 fixed the timing problem (z80_wait_states was called after interrupts even if they were disabled!)
45 Apr 03, 2001 - 18:25 incorporated the changes from the MAME Z80 core v3.1 to v3.2 update
46 Apr 09, 2001 - 19:30 fixed the problem with some CPC programs crashing (offset for IX/IY instructions was unsigned!)
47 Jul 31, 2001 - 23:34 put the 'old' NOP cycle timing table back in
48 Nov 12, 2001 - 18:15 incorporated the changes from the MAME Z80 core v3.2 to v3.3 update
49 Nov 14, 2002 - 21:39 changed the length of processing an interrupt in IM2 from 28T to 76T
50 Feb 10, 2003 - 18:24 corrected the cycle count of CPI/CPIR & CPD/CPDR with the help of Richard's PlusTest
51 Feb 12, 2003 - 17:29 added the wait state adjustment on interrupts for a specific number of instructions
52 (see Richard's document on andercheran for the complete list)
53 Apr 07, 2003 - 19:10 added z80_mf2stop to emulate the NMI caused by the stop button of the MF2
54 Apr 07, 2003 - 22:48 added code to z80_execute to monitor when the MF2 finishes and has to be made 'invisible'
55 May 10, 2003 - 19:12 fixed the unofficial DDCB/FDCB RES/SET instructions: the unaltered value was
56 stored in the associated register; some minor code clean up
57 May 15, 2003 - 23:19 "Thomas the Tank Engine", "N.E.X.O.R." and "Jocky Wilson's Darts Compendium" work now:
58 DI did not clear the z80.EI_issued counter
59 */
60 //RETRO DIFF
61 #include "z80.h"
62 #include "cap32.h"
63 #include "tape.h"
64 #include "asic.h"
65
66 extern t_CPC CPC;
67 extern t_FDC FDC;
68 extern t_GateArray GateArray;
69 extern t_PSG PSG;
70 extern t_VDU VDU;
71 extern uint8_t *pbTapeImage;
72 extern uint32_t dwMF2Flags;
73 extern uint32_t dwMF2ExitAddr;
74
75 extern int iTapeCycleCount;
76
77 #ifdef DEBUG_Z80
78 extern FILE *pfoDebug;
79 unsigned int dbg_z80_lastPC, dbg_z80_diff;
80 #endif
81
82 enum opcodes {
83 nop, ld_bc_word, ld_mbc_a, inc_bc, inc_b, dec_b, ld_b_byte, rlca,
84 ex_af_af, add_hl_bc, ld_a_mbc, dec_bc, inc_c, dec_c, ld_c_byte, rrca,
85 djnz, ld_de_word, ld_mde_a, inc_de, inc_d, dec_d, ld_d_byte, rla,
86 jr, add_hl_de, ld_a_mde, dec_de, inc_e, dec_e, ld_e_byte, rra,
87 jr_nz, ld_hl_word, ld_mword_hl, inc_hl, inc_h, dec_h, ld_h_byte, daa,
88 jr_z, add_hl_hl, ld_hl_mword, dec_hl, inc_l, dec_l, ld_l_byte, cpl,
89 jr_nc, ld_sp_word, ld_mword_a, inc_sp, inc_mhl, dec_mhl, ld_mhl_byte, scf,
90 jr_c, add_hl_sp, ld_a_mword, dec_sp, inc_a, dec_a, ld_a_byte, ccf,
91 ld_b_b, ld_b_c, ld_b_d, ld_b_e, ld_b_h, ld_b_l, ld_b_mhl, ld_b_a,
92 ld_c_b, ld_c_c, ld_c_d, ld_c_e, ld_c_h, ld_c_l, ld_c_mhl, ld_c_a,
93 ld_d_b, ld_d_c, ld_d_d, ld_d_e, ld_d_h, ld_d_l, ld_d_mhl, ld_d_a,
94 ld_e_b, ld_e_c, ld_e_d, ld_e_e, ld_e_h, ld_e_l, ld_e_mhl, ld_e_a,
95 ld_h_b, ld_h_c, ld_h_d, ld_h_e, ld_h_h, ld_h_l, ld_h_mhl, ld_h_a,
96 ld_l_b, ld_l_c, ld_l_d, ld_l_e, ld_l_h, ld_l_l, ld_l_mhl, ld_l_a,
97 ld_mhl_b, ld_mhl_c, ld_mhl_d, ld_mhl_e, ld_mhl_h, ld_mhl_l, halt, ld_mhl_a,
98 ld_a_b, ld_a_c, ld_a_d, ld_a_e, ld_a_h, ld_a_l, ld_a_mhl, ld_a_a,
99 add_b, add_c, add_d, add_e, add_h, add_l, add_mhl, add_a,
100 adc_b, adc_c, adc_d, adc_e, adc_h, adc_l, adc_mhl, adc_a,
101 sub_b, sub_c, sub_d, sub_e, sub_h, sub_l, sub_mhl, sub_a,
102 sbc_b, sbc_c, sbc_d, sbc_e, sbc_h, sbc_l, sbc_mhl, sbc_a,
103 and_b, and_c, and_d, and_e, and_h, and_l, and_mhl, and_a,
104 xor_b, xor_c, xor_d, xor_e, xor_h, xor_l, xor_mhl, xor_a,
105 or_b, or_c, or_d, or_e, or_h, or_l, or_mhl, or_a,
106 cp_b, cp_c, cp_d, cp_e, cp_h, cp_l, cp_mhl, cp_a,
107 ret_nz, pop_bc, jp_nz, jp, call_nz, push_bc, add_byte, rst00,
108 ret_z, ret, jp_z, pfx_cb, call_z, call, adc_byte, rst08,
109 ret_nc, pop_de, jp_nc, outa, call_nc, push_de, sub_byte, rst10,
110 ret_c, exx, jp_c, ina, call_c, pfx_dd, sbc_byte, rst18,
111 ret_po, pop_hl, jp_po, ex_msp_hl, call_po, push_hl, and_byte, rst20,
112 ret_pe, ld_pc_hl, jp_pe, ex_de_hl, call_pe, pfx_ed, xor_byte, rst28,
113 ret_p, pop_af, jp_p, di, call_p, push_af, or_byte, rst30,
114 ret_m, ld_sp_hl, jp_m, ei, call_m, pfx_fd, cp_byte, rst38
115 };
116
117 enum CBcodes {
118 rlc_b, rlc_c, rlc_d, rlc_e, rlc_h, rlc_l, rlc_mhl, rlc_a,
119 rrc_b, rrc_c, rrc_d, rrc_e, rrc_h, rrc_l, rrc_mhl, rrc_a,
120 rl_b, rl_c, rl_d, rl_e, rl_h, rl_l, rl_mhl, rl_a,
121 rr_b, rr_c, rr_d, rr_e, rr_h, rr_l, rr_mhl, rr_a,
122 sla_b, sla_c, sla_d, sla_e, sla_h, sla_l, sla_mhl, sla_a,
123 sra_b, sra_c, sra_d, sra_e, sra_h, sra_l, sra_mhl, sra_a,
124 sll_b, sll_c, sll_d, sll_e, sll_h, sll_l, sll_mhl, sll_a,
125 srl_b, srl_c, srl_d, srl_e, srl_h, srl_l, srl_mhl, srl_a,
126 bit0_b, bit0_c, bit0_d, bit0_e, bit0_h, bit0_l, bit0_mhl, bit0_a,
127 bit1_b, bit1_c, bit1_d, bit1_e, bit1_h, bit1_l, bit1_mhl, bit1_a,
128 bit2_b, bit2_c, bit2_d, bit2_e, bit2_h, bit2_l, bit2_mhl, bit2_a,
129 bit3_b, bit3_c, bit3_d, bit3_e, bit3_h, bit3_l, bit3_mhl, bit3_a,
130 bit4_b, bit4_c, bit4_d, bit4_e, bit4_h, bit4_l, bit4_mhl, bit4_a,
131 bit5_b, bit5_c, bit5_d, bit5_e, bit5_h, bit5_l, bit5_mhl, bit5_a,
132 bit6_b, bit6_c, bit6_d, bit6_e, bit6_h, bit6_l, bit6_mhl, bit6_a,
133 bit7_b, bit7_c, bit7_d, bit7_e, bit7_h, bit7_l, bit7_mhl, bit7_a,
134 res0_b, res0_c, res0_d, res0_e, res0_h, res0_l, res0_mhl, res0_a,
135 res1_b, res1_c, res1_d, res1_e, res1_h, res1_l, res1_mhl, res1_a,
136 res2_b, res2_c, res2_d, res2_e, res2_h, res2_l, res2_mhl, res2_a,
137 res3_b, res3_c, res3_d, res3_e, res3_h, res3_l, res3_mhl, res3_a,
138 res4_b, res4_c, res4_d, res4_e, res4_h, res4_l, res4_mhl, res4_a,
139 res5_b, res5_c, res5_d, res5_e, res5_h, res5_l, res5_mhl, res5_a,
140 res6_b, res6_c, res6_d, res6_e, res6_h, res6_l, res6_mhl, res6_a,
141 res7_b, res7_c, res7_d, res7_e, res7_h, res7_l, res7_mhl, res7_a,
142 set0_b, set0_c, set0_d, set0_e, set0_h, set0_l, set0_mhl, set0_a,
143 set1_b, set1_c, set1_d, set1_e, set1_h, set1_l, set1_mhl, set1_a,
144 set2_b, set2_c, set2_d, set2_e, set2_h, set2_l, set2_mhl, set2_a,
145 set3_b, set3_c, set3_d, set3_e, set3_h, set3_l, set3_mhl, set3_a,
146 set4_b, set4_c, set4_d, set4_e, set4_h, set4_l, set4_mhl, set4_a,
147 set5_b, set5_c, set5_d, set5_e, set5_h, set5_l, set5_mhl, set5_a,
148 set6_b, set6_c, set6_d, set6_e, set6_h, set6_l, set6_mhl, set6_a,
149 set7_b, set7_c, set7_d, set7_e, set7_h, set7_l, set7_mhl, set7_a
150 };
151
152 enum EDcodes {
153 ed_00, ed_01, ed_02, ed_03, ed_04, ed_05, ed_06, ed_07,
154 ed_08, ed_09, ed_0a, ed_0b, ed_0c, ed_0d, ed_0e, ed_0f,
155 ed_10, ed_11, ed_12, ed_13, ed_14, ed_15, ed_16, ed_17,
156 ed_18, ed_19, ed_1a, ed_1b, ed_1c, ed_1d, ed_1e, ed_1f,
157 ed_20, ed_21, ed_22, ed_23, ed_24, ed_25, ed_26, ed_27,
158 ed_28, ed_29, ed_2a, ed_2b, ed_2c, ed_2d, ed_2e, ed_2f,
159 ed_30, ed_31, ed_32, ed_33, ed_34, ed_35, ed_36, ed_37,
160 ed_38, ed_39, ed_3a, ed_3b, ed_3c, ed_3d, ed_3e, ed_3f,
161 in_b_c, out_c_b, sbc_hl_bc, ld_EDmword_bc, neg, retn, im_0, ld_i_a,
162 in_c_c, out_c_c, adc_hl_bc, ld_EDbc_mword, neg_1, reti, im_0_1, ld_r_a,
163 in_d_c, out_c_d, sbc_hl_de, ld_EDmword_de, neg_2, retn_1, im_1, ld_a_i,
164 in_e_c, out_c_e, adc_hl_de, ld_EDde_mword, neg_3, reti_1, im_2, ld_a_r,
165 in_h_c, out_c_h, sbc_hl_hl, ld_EDmword_hl, neg_4, retn_2, im_0_2, rrd,
166 in_l_c, out_c_l, adc_hl_hl, ld_EDhl_mword, neg_5, reti_2, im_0_3, rld,
167 in_0_c, out_c_0, sbc_hl_sp, ld_EDmword_sp, neg_6, retn_3, im_1_1, ed_77,
168 in_a_c, out_c_a, adc_hl_sp, ld_EDsp_mword, neg_7, reti_3, im_2_1, ed_7f,
169 ed_80, ed_81, ed_82, ed_83, ed_84, ed_85, ed_86, ed_87,
170 ed_88, ed_89, ed_8a, ed_8b, ed_8c, ed_8d, ed_8e, ed_8f,
171 ed_90, ed_91, ed_92, ed_93, ed_94, ed_95, ed_96, ed_97,
172 ed_98, ed_99, ed_9a, ed_9b, ed_9c, ed_9d, ed_9e, ed_9f,
173 ldi, cpi, ini, outi, ed_a4, ed_a5, ed_a6, ed_a7,
174 ldd, cpd, ind, outd, ed_ac, ed_ad, ed_ae, ed_af,
175 ldir, cpir, inir, otir, ed_b4, ed_b5, ed_b6, ed_b7,
176 lddr, cpdr, indr, otdr, ed_bc, ed_bd, ed_be, ed_bf,
177 ed_c0, ed_c1, ed_c2, ed_c3, ed_c4, ed_c5, ed_c6, ed_c7,
178 ed_c8, ed_c9, ed_ca, ed_cb, ed_cc, ed_cd, ed_ce, ed_cf,
179 ed_d0, ed_d1, ed_d2, ed_d3, ed_d4, ed_d5, ed_d6, ed_d7,
180 ed_d8, ed_d9, ed_da, ed_db, ed_dc, ed_dd, ed_de, ed_df,
181 ed_e0, ed_e1, ed_e2, ed_e3, ed_e4, ed_e5, ed_e6, ed_e7,
182 ed_e8, ed_e9, ed_ea, ed_eb, ed_ec, ed_ed, ed_ee, ed_ef,
183 ed_f0, ed_f1, ed_f2, ed_f3, ed_f4, ed_f5, ed_f6, ed_f7,
184 ed_f8, ed_f9, ed_fa, ed_fb, ed_fc, ed_fd, ed_fe, ed_ff
185 };
186
187
188
189 t_z80regs z80;
190 int iCycleCount, iWSAdjust;
191 static uint8_t SZ[256]; // zero and sign flags
192 static uint8_t SZ_BIT[256]; // zero, sign and parity/overflow (=zero) flags for BIT opcode
193 static uint8_t SZP[256]; // zero, sign and parity flags
194 static uint8_t SZHV_inc[256]; // zero, sign, half carry and overflow flags INC r8
195 static uint8_t SZHV_dec[256]; // zero, sign, half carry and overflow flags DEC r8
196
197 #include "z80daa.h"
198
199 static uint8_t irep_tmp1[4][4] = {
200 {0, 0, 1, 0}, {0, 1, 0, 1}, {1, 0, 1, 1}, {0, 1, 1, 0}
201 };
202
203 /* tmp1 value for ind/indr/outd/otdr for [C.1-0][io.1-0] */
204 static uint8_t drep_tmp1[4][4] = {
205 {0, 1, 0, 0}, {1, 0, 0, 1}, {0, 0, 1, 0}, {0, 1, 0, 1}
206 };
207
208 /* tmp2 value for all in/out repeated opcodes for B.7-0 */
209 static uint8_t breg_tmp2[256] = {
210 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1,
211 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0,
212 1, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0,
213 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1,
214 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0,
215 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1,
216 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1,
217 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0,
218 1, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0,
219 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1,
220 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1,
221 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0,
222 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1,
223 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0,
224 1, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0,
225 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1
226 };
227
228 #define Oa 8
229 #define Oa_ 4
230 #define Ia 12
231 #define Ia_ 0
232
233 static uint8_t cc_op[256] = {
234 4, 12, 8, 8, 4, 4, 8, 4, 4, 12, 8, 8, 4, 4, 8, 4,
235 12, 12, 8, 8, 4, 4, 8, 4, 12, 12, 8, 8, 4, 4, 8, 4,
236 8, 12, 20, 8, 4, 4, 8, 4, 8, 12, 20, 8, 4, 4, 8, 4,
237 8, 12, 16, 8, 12, 12, 12, 4, 8, 12, 16, 8, 4, 4, 8, 4,
238 4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
239 4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
240 4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
241 8, 8, 8, 8, 8, 8, 4, 8, 4, 4, 4, 4, 4, 4, 8, 4,
242 4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
243 4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
244 4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
245 4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
246 8, 12, 12, 12, 12, 16, 8, 16, 8, 12, 12, 4, 12, 20, 8, 16,
247 8, 12, 12, Oa, 12, 16, 8, 16, 8, 4, 12, Ia, 12, 4, 8, 16,
248 8, 12, 12, 24, 12, 16, 8, 16, 8, 4, 12, 4, 12, 4, 8, 16,
249 8, 12, 12, 4, 12, 16, 8, 16, 8, 8, 12, 4, 12, 4, 8, 16
250 };
251
252 static uint8_t cc_cb[256] = {
253 4, 4, 4, 4, 4, 4, 12, 4, 4, 4, 4, 4, 4, 4, 12, 4,
254 4, 4, 4, 4, 4, 4, 12, 4, 4, 4, 4, 4, 4, 4, 12, 4,
255 4, 4, 4, 4, 4, 4, 12, 4, 4, 4, 4, 4, 4, 4, 12, 4,
256 4, 4, 4, 4, 4, 4, 12, 4, 4, 4, 4, 4, 4, 4, 12, 4,
257 4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
258 4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
259 4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
260 4, 4, 4, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 8, 4,
261 4, 4, 4, 4, 4, 4, 12, 4, 4, 4, 4, 4, 4, 4, 12, 4,
262 4, 4, 4, 4, 4, 4, 12, 4, 4, 4, 4, 4, 4, 4, 12, 4,
263 4, 4, 4, 4, 4, 4, 12, 4, 4, 4, 4, 4, 4, 4, 12, 4,
264 4, 4, 4, 4, 4, 4, 12, 4, 4, 4, 4, 4, 4, 4, 12, 4,
265 4, 4, 4, 4, 4, 4, 12, 4, 4, 4, 4, 4, 4, 4, 12, 4,
266 4, 4, 4, 4, 4, 4, 12, 4, 4, 4, 4, 4, 4, 4, 12, 4,
267 4, 4, 4, 4, 4, 4, 12, 4, 4, 4, 4, 4, 4, 4, 12, 4,
268 4, 4, 4, 4, 4, 4, 12, 4, 4, 4, 4, 4, 4, 4, 12, 4
269 };
270
271 #define Ox 8
272 #define Ox_ 4
273 #define Oy 12
274 #define Oy_ 4
275 #define Ix 12
276 #define Ix_ 0
277 #define Iy 16
278 #define Iy_ 0
279
280 static uint8_t cc_ed[256] = {
281 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
282 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
283 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
284 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
285 Ix, Ox, 12, 20, 4, 12, 4, 8, Ix, Ox, 12, 20, 4, 12, 4, 8,
286 Ix, Ox, 12, 20, 4, 12, 4, 8, Ix, Ox, 12, 20, 4, 12, 4, 8,
287 Ix, Ox, 12, 20, 4, 12, 4, 16, Ix, Ox, 12, 20, 4, 12, 4, 16,
288 Ix, Ox, 12, 20, 4, 12, 4, 4, Ix, Ox, 12, 20, 4, 12, 4, 4,
289 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
290 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
291 16, 12, Iy, Oy, 4, 4, 4, 4, 16, 12, Iy, Oy, 4, 4, 4, 4,
292 16, 12, Iy, Oy, 4, 4, 4, 4, 16, 12, Iy, Oy, 4, 4, 4, 4,
293 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
294 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
295 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
296 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4
297 };
298
299 static uint8_t cc_xy[256] = {
300 4, 12, 8, 8, 4, 4, 8, 4, 4, 12, 8, 8, 4, 4, 8, 4,
301 12, 12, 8, 8, 4, 4, 8, 4, 12, 12, 8, 8, 4, 4, 8, 4,
302 8, 12, 20, 8, 4, 4, 8, 4, 8, 12, 20, 8, 4, 4, 8, 4,
303 8, 12, 16, 8, 20, 20, 20, 4, 8, 12, 16, 8, 4, 4, 8, 4,
304 4, 4, 4, 4, 4, 4, 16, 4, 4, 4, 4, 4, 4, 4, 16, 4,
305 4, 4, 4, 4, 4, 4, 16, 4, 4, 4, 4, 4, 4, 4, 16, 4,
306 4, 4, 4, 4, 4, 4, 16, 4, 4, 4, 4, 4, 4, 4, 16, 4,
307 16, 16, 16, 16, 16, 16, 4, 16, 4, 4, 4, 4, 4, 4, 16, 4,
308 4, 4, 4, 4, 4, 4, 16, 4, 4, 4, 4, 4, 4, 4, 16, 4,
309 4, 4, 4, 4, 4, 4, 16, 4, 4, 4, 4, 4, 4, 4, 16, 4,
310 4, 4, 4, 4, 4, 4, 16, 4, 4, 4, 4, 4, 4, 4, 16, 4,
311 4, 4, 4, 4, 4, 4, 16, 4, 4, 4, 4, 4, 4, 4, 16, 4,
312 8, 12, 12, 12, 12, 16, 8, 16, 8, 12, 12, 4, 12, 20, 8, 16,
313 8, 12, 12, Oa, 12, 16, 8, 16, 8, 4, 12, Ia, 12, 4, 8, 16,
314 8, 12, 12, 24, 12, 16, 8, 16, 8, 4, 12, 4, 12, 4, 8, 16,
315 8, 12, 12, 4, 12, 16, 8, 16, 8, 8, 12, 4, 12, 4, 8, 16
316 };
317
318 static uint8_t cc_xycb[256] = {
319 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20,
320 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20,
321 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20,
322 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20,
323 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
324 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
325 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
326 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
327 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20,
328 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20,
329 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20,
330 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20,
331 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20,
332 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20,
333 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20,
334 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20
335 };
336
337 static uint8_t cc_ex[256] = {
338 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
339 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
340 4, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0,
341 4, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0,
342 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
343 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
344 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
345 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
346 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
347 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
348 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
349 4, 8, 4, 4, 0, 0, 0, 0, 4, 8, 4, 4, 0, 0, 0, 0,
350 8, 0, 0, 0, 8, 0, 0, 0, 8, 0, 0, 0, 8, 0, 0, 0,
351 8, 0, 0, 0, 8, 0, 0, 0, 8, 0, 0, 0, 8, 0, 0, 0,
352 8, 0, 0, 0, 8, 0, 0, 0, 8, 0, 0, 0, 8, 0, 0, 0,
353 8, 0, 0, 0, 8, 0, 0, 0, 8, 0, 0, 0, 8, 0, 0, 0
354 };
355
356
357
358 extern uint8_t *membank_read[4], *membank_write[4];
359
read_mem(uint16_t addr)360 static INLINE uint8_t read_mem(uint16_t addr)
361 {
362 if (GateArray.registerPageOn) {
363 uint8_t value;
364 if(!asic_register_page_read(addr, &value))
365 return value;
366 }
367 return (*(membank_read[addr >> 14] + (addr & 0x3fff))); // returns a byte from a 16KB memory bank
368 }
369
write_mem(uint16_t addr,uint8_t val)370 static INLINE void write_mem(uint16_t addr, uint8_t val)
371 {
372 if (GateArray.registerPageOn) {
373 if(!asic_register_page_write(addr, val))
374 return;
375 }
376 *(membank_write[addr >> 14] + (addr & 0x3fff)) = val; // writes a byte to a 16KB memory bank
377 }
378
read_ptr()379 static INLINE uint8_t read_ptr(){
380 if(!asic.locked)
381 return asic_int();
382 return 0xFF;
383 }
384
385 #define z80_wait_states \
386 { \
387 if (iCycleCount) { \
388 crtc_cycle(iCycleCount >> 2); \
389 if (CPC.snd_enabled) { \
390 PSG.cycle_count.high += iCycleCount; \
391 if (PSG.cycle_count.high >= CPC.snd_cycle_count_init.high) { \
392 PSG.cycle_count.both -= CPC.snd_cycle_count_init.both; \
393 PSG.Synthesizer(); \
394 } \
395 } \
396 if (FDC.phase == EXEC_PHASE) { \
397 FDC.timeout -= iCycleCount; \
398 if (FDC.timeout <= 0) { \
399 FDC.flags |= OVERRUN_flag; \
400 if (FDC.cmd_direction == FDC_TO_CPU) { \
401 fdc_read_data(); \
402 } \
403 else { \
404 fdc_write_data(0xff); \
405 } \
406 } \
407 } \
408 if ((CPC.tape_motor) && (CPC.tape_play_button)) { \
409 iTapeCycleCount -= iCycleCount; \
410 if (iTapeCycleCount <= 0) { \
411 Tape_UpdateLevel(); \
412 } \
413 } \
414 CPC.cycle_count -= iCycleCount; \
415 } \
416 }
417
418 #define ADC(value) \
419 { \
420 unsigned val = value; \
421 unsigned res = _A + val + (_F & Cflag); \
422 _F = SZ[res & 0xff] | ((res >> 8) & Cflag) | ((_A ^ res ^ val) & Hflag) | \
423 (((val ^ _A ^ 0x80) & (val ^ res) & 0x80) >> 5); \
424 _A = res; \
425 }
426
427 #define ADD(value) \
428 { \
429 unsigned val = value; \
430 unsigned res = _A + val; \
431 _F = SZ[(uint8_t)res] | ((res >> 8) & Cflag) | ((_A ^ res ^ val) & Hflag) | \
432 (((val ^ _A ^ 0x80) & (val ^ res) & 0x80) >> 5); \
433 _A = (uint8_t)res; \
434 }
435
436 #define ADD16(dest, src) \
437 { \
438 uint32_t res = z80.dest.d + z80.src.d; \
439 _F = (_F & (Sflag | Zflag | Vflag)) | (((z80.dest.d ^ res ^ z80.src.d) >> 8) & Hflag) | \
440 ((res >> 16) & Cflag) | ((res >> 8) & Xflags); \
441 z80.dest.w.l = (uint16_t)res; \
442 }
443
444 #define AND(val) \
445 { \
446 _A &= val; \
447 _F = SZP[_A] | Hflag; \
448 }
449
450 #define CALL \
451 { \
452 reg_pair dest; \
453 dest.b.l = read_mem(_PC++); /* subroutine address low byte */ \
454 dest.b.h = read_mem(_PC++); /* subroutine address high byte */ \
455 write_mem(--_SP, z80.PC.b.h); /* store high byte of current PC */ \
456 write_mem(--_SP, z80.PC.b.l); /* store low byte of current PC */ \
457 _PC = dest.w.l; /* continue execution at subroutine */ \
458 }
459
460 #define CP(value) \
461 { \
462 unsigned val = value; \
463 unsigned res = _A - val; \
464 _F = (SZ[res & 0xff] & (Sflag | Zflag)) | (val & Xflags) | ((res >> 8) & Cflag) | Nflag | ((_A ^ res ^ val) & Hflag) | \
465 ((((val ^ _A) & (_A ^ res)) >> 5) & Vflag); \
466 }
467
468 #define DAA \
469 { \
470 int idx = _A; \
471 if(_F & Cflag) \
472 idx |= 0x100; \
473 if(_F & Hflag) \
474 idx |= 0x200; \
475 if(_F & Nflag) \
476 idx |= 0x400; \
477 _AF = DAATable[idx]; \
478 }
479
480 #define DEC(reg) \
481 { \
482 reg--; \
483 _F = (_F & Cflag) | SZHV_dec[reg]; \
484 }
485
486 #define JR \
487 { \
488 signed char offset; \
489 offset = (signed char)(read_mem(_PC)); /* grab signed jump offset */ \
490 _PC += offset + 1; /* add offset & correct PC */ \
491 }
492
493 #define EXX \
494 { \
495 reg_pair temp; \
496 temp = z80.BCx; \
497 z80.BCx = z80.BC; \
498 z80.BC = temp; \
499 temp = z80.DEx; \
500 z80.DEx = z80.DE; \
501 z80.DE = temp; \
502 temp = z80.HLx; \
503 z80.HLx = z80.HL; \
504 z80.HL = temp; \
505 }
506
507 #define EX(op1, op2) \
508 { \
509 reg_pair temp; \
510 temp = op1; \
511 op1 = op2; \
512 op2 = temp; \
513 }
514
515 #define EX_SP(reg) \
516 { \
517 reg_pair temp; \
518 temp.b.l = read_mem(_SP++); \
519 temp.b.h = read_mem(_SP); \
520 write_mem(_SP--, z80.reg.b.h); \
521 write_mem(_SP, z80.reg.b.l); \
522 z80.reg.w.l = temp.w.l; \
523 }
524
525 #define INC(reg) \
526 { \
527 reg++; \
528 _F = (_F & Cflag) | SZHV_inc[reg]; \
529 }
530
531 #define JP \
532 { \
533 reg_pair addr; \
534 addr.b.l = read_mem(_PC++); \
535 addr.b.h = read_mem(_PC); \
536 _PC = addr.w.l; \
537 }
538
539 #define LD16_MEM(reg) \
540 { \
541 reg_pair addr; \
542 addr.b.l = read_mem(_PC++); \
543 addr.b.h = read_mem(_PC++); \
544 z80.reg.b.l = read_mem(addr.w.l); \
545 z80.reg.b.h = read_mem(addr.w.l+1); \
546 }
547
548 #define LDMEM_16(reg) \
549 { \
550 reg_pair addr; \
551 addr.b.l = read_mem(_PC++); \
552 addr.b.h = read_mem(_PC++); \
553 write_mem(addr.w.l, z80.reg.b.l); \
554 write_mem(addr.w.l+1, z80.reg.b.h); \
555 }
556
557 #define OR(val) \
558 { \
559 _A |= val; \
560 _F = SZP[_A]; \
561 }
562
563 #define POP(reg) \
564 { \
565 z80.reg.b.l = read_mem(_SP++); \
566 z80.reg.b.h = read_mem(_SP++); \
567 }
568
569 #define PUSH(reg) \
570 { \
571 write_mem(--_SP, z80.reg.b.h); \
572 write_mem(--_SP, z80.reg.b.l); \
573 }
574
575 #define RET \
576 { \
577 z80.PC.b.l = read_mem(_SP++); \
578 z80.PC.b.h = read_mem(_SP++); \
579 }
580
581 #define RLA \
582 { \
583 uint8_t res = (_A << 1) | (_F & Cflag); \
584 uint8_t carry = (_A & 0x80) ? Cflag : 0; \
585 _F = (_F & (Sflag | Zflag | Pflag)) | carry | (res & Xflags); \
586 _A = res; \
587 }
588
589 #define RLCA \
590 { \
591 _A = (_A << 1) | (_A >> 7); \
592 _F = (_F & (Sflag | Zflag | Pflag)) | (_A & (Xflags | Cflag)); \
593 }
594
595 #define RRA \
596 { \
597 uint8_t res = (_A >> 1) | (_F << 7); \
598 uint8_t carry = (_A & 0x01) ? Cflag : 0; \
599 _F = (_F & (Sflag | Zflag | Pflag)) | carry | (res & Xflags); \
600 _A = res; \
601 }
602
603 #define RRCA \
604 { \
605 _F = (_F & (Sflag | Zflag | Pflag)) | (_A & Cflag); \
606 _A = (_A >> 1) | (_A << 7); \
607 _F |= (_A & Xflags); \
608 }
609
610 #define RST(addr) \
611 { \
612 write_mem(--_SP, z80.PC.b.h); /* store high byte of current PC */ \
613 write_mem(--_SP, z80.PC.b.l); /* store low byte of current PC */ \
614 _PC = addr; /* continue execution at restart address */ \
615 }
616
617 #define SBC(value) \
618 { \
619 unsigned val = value; \
620 unsigned res = _A - val - (_F & Cflag); \
621 _F = SZ[res & 0xff] | ((res >> 8) & Cflag) | Nflag | ((_A ^ res ^ val) & Hflag) | \
622 (((val ^ _A) & (_A ^ res) & 0x80) >> 5); \
623 _A = res; \
624 }
625
626 #define SUB(value) \
627 { \
628 unsigned val = value; \
629 unsigned res = _A - val; \
630 _F = SZ[res & 0xff] | ((res >> 8) & Cflag) | Nflag | ((_A ^ res ^ val) & Hflag) | \
631 (((val ^ _A) & (_A ^ res) & 0x80) >> 5); \
632 _A = res; \
633 }
634
635 #define XOR(val) \
636 { \
637 _A ^= val; \
638 _F = SZP[_A]; \
639 }
640
641 #define BIT(bit, reg) \
642 _F = (_F & Cflag) | Hflag | SZ_BIT[reg & (1 << bit)]
643
644 #define BIT_XY BIT
645
RES(uint8_t bit,uint8_t val)646 static INLINE uint8_t RES(uint8_t bit, uint8_t val)
647 {
648 return val & ~(1 << bit);
649 }
650
RLC(uint8_t val)651 static INLINE uint8_t RLC(uint8_t val)
652 {
653 unsigned res = val;
654 unsigned carry = (res & 0x80) ? Cflag : 0;
655 res = ((res << 1) | (res >> 7)) & 0xff;
656 _F = SZP[res] | carry;
657 return res;
658 }
659
RL(uint8_t val)660 static INLINE uint8_t RL(uint8_t val)
661 {
662 unsigned res = val;
663 unsigned carry = (res & 0x80) ? Cflag : 0;
664 res = ((res << 1) | (_F & Cflag)) & 0xff;
665 _F = SZP[res] | carry;
666 return res;
667 }
668
RRC(uint8_t val)669 static INLINE uint8_t RRC(uint8_t val) {
670 unsigned res = val;
671 unsigned carry = (res & 0x01) ? Cflag : 0;
672 res = ((res >> 1) | (res << 7)) & 0xff;
673 _F = SZP[res] | carry;
674 return res;
675 }
676
RR(uint8_t val)677 static INLINE uint8_t RR(uint8_t val) {
678 unsigned res = val;
679 unsigned carry = (res & 0x01) ? Cflag : 0;
680 res = ((res >> 1) | (_F << 7)) & 0xff;
681 _F = SZP[res] | carry;
682 return res;
683 }
684
SET(uint8_t bit,uint8_t val)685 static INLINE uint8_t SET(uint8_t bit, uint8_t val) {
686 return val | (1 << bit);
687 }
688
SLA(uint8_t val)689 static INLINE uint8_t SLA(uint8_t val) {
690 unsigned res = val;
691 unsigned carry = (res & 0x80) ? Cflag : 0;
692 res = (res << 1) & 0xff;
693 _F = SZP[res] | carry;
694 return res;
695 }
696
SLL(uint8_t val)697 static INLINE uint8_t SLL(uint8_t val) {
698 unsigned res = val;
699 unsigned carry = (res & 0x80) ? Cflag : 0;
700 res = ((res << 1) | 0x01) & 0xff;
701 _F = SZP[res] | carry;
702 return res;
703 }
704
SRA(uint8_t val)705 static INLINE uint8_t SRA(uint8_t val) {
706 unsigned res = val;
707 unsigned carry = (res & 0x01) ? Cflag : 0;
708 res = ((res >> 1) | (res & 0x80)) & 0xff;
709 _F = SZP[res] | carry;
710 return res;
711 }
712
SRL(uint8_t val)713 static INLINE uint8_t SRL(uint8_t val) {
714 unsigned res = val;
715 unsigned carry = (res & 0x01) ? Cflag : 0;
716 res = (res >> 1) & 0xff;
717 _F = SZP[res] | carry;
718 return res;
719 }
720
721 #define ADC16(reg) \
722 { \
723 uint32_t res = _HLdword + z80.reg.d + (_F & Cflag); \
724 _F = (((_HLdword ^ res ^ z80.reg.d) >> 8) & Hflag) | \
725 ((res >> 16) & Cflag) | \
726 ((res >> 8) & (Sflag | Xflags)) | \
727 ((res & 0xffff) ? 0 : Zflag) | \
728 (((z80.reg.d ^ _HLdword ^ 0x8000) & (z80.reg.d ^ res) & 0x8000) >> 13); \
729 _HL = (uint16_t)res; \
730 }
731
732 #define CPD \
733 { \
734 uint8_t val = read_mem(_HL); \
735 uint8_t res = _A - val; \
736 _HL--; \
737 _BC--; \
738 _F = (_F & Cflag) | (SZ[res] & ~Xflags) | ((_A ^ val ^ res) & Hflag) | Nflag; \
739 if(_F & Hflag) res -= 1; \
740 if(res & 0x02) _F |= 0x20; \
741 if(res & 0x08) _F |= 0x08; \
742 if(_BC) _F |= Vflag; \
743 }
744
745 #define CPDR \
746 CPD; \
747 if(_BC && !(_F & Zflag)) \
748 { \
749 iCycleCount += cc_ex[bOpCode]; \
750 _PC -= 2; \
751 iWSAdjust++; \
752 }
753
754 #define CPI \
755 { \
756 uint8_t val = read_mem(_HL); \
757 uint8_t res = _A - val; \
758 _HL++; \
759 _BC--; \
760 _F = (_F & Cflag) | (SZ[res] & ~Xflags) | ((_A ^ val ^ res) & Hflag) | Nflag; \
761 if(_F & Hflag) res -= 1; \
762 if(res & 0x02) _F |= 0x20; \
763 if(res & 0x08) _F |= 0x08; \
764 if(_BC) _F |= Vflag; \
765 }
766
767 #define CPIR \
768 CPI; \
769 if(_BC && !(_F & Zflag)) \
770 { \
771 iCycleCount += cc_ex[bOpCode]; \
772 _PC -= 2; \
773 iWSAdjust++; \
774 }
775
776 #define IND \
777 { \
778 uint8_t io = z80_IN_handler(z80.BC); \
779 _B--; \
780 write_mem(_HL, io); \
781 _HL--; \
782 _F = SZ[_B]; \
783 if(io & Sflag) _F |= Nflag; \
784 if((((_C - 1) & 0xff) + io) & 0x100) _F |= Hflag | Cflag; \
785 if((drep_tmp1[_C & 3][io & 3] ^ breg_tmp2[_B] ^ (_C >> 2) ^ (io >> 2)) & 1) \
786 _F |= Pflag; \
787 }
788
789 #define INDR \
790 IND; \
791 if(_B) \
792 { \
793 iCycleCount += cc_ex[bOpCode]; \
794 _PC -= 2; \
795 }
796
797 #define INI \
798 { \
799 uint8_t io = z80_IN_handler(z80.BC); \
800 _B--; \
801 write_mem(_HL, io); \
802 _HL++; \
803 _F = SZ[_B]; \
804 if(io & Sflag) _F |= Nflag; \
805 if((((_C + 1) & 0xff) + io) & 0x100) _F |= Hflag | Cflag; \
806 if((irep_tmp1[_C & 3][io & 3] ^ breg_tmp2[_B] ^ (_C >> 2) ^ (io >> 2)) & 1) \
807 _F |= Pflag; \
808 }
809
810 #define INIR \
811 INI; \
812 if(_B) \
813 { \
814 iCycleCount += cc_ex[bOpCode]; \
815 _PC -= 2; \
816 }
817
818 #define LDD \
819 { \
820 uint8_t io = read_mem(_HL); \
821 write_mem(_DE, io); \
822 _F &= Sflag | Zflag | Cflag; \
823 if((_A + io) & 0x02) _F |= 0x20; \
824 if((_A + io) & 0x08) _F |= 0x08; \
825 _HL--; \
826 _DE--; \
827 _BC--; \
828 if(_BC) _F |= Vflag; \
829 }
830
831 #define LDDR \
832 LDD; \
833 if(_BC) \
834 { \
835 iCycleCount += cc_ex[bOpCode]; \
836 _PC -= 2; \
837 }
838
839 #define LDI \
840 { \
841 uint8_t io = read_mem(_HL); \
842 write_mem(_DE, io); \
843 _F &= Sflag | Zflag | Cflag; \
844 if((_A + io) & 0x02) _F |= 0x20; \
845 if((_A + io) & 0x08) _F |= 0x08; \
846 _HL++; \
847 _DE++; \
848 _BC--; \
849 if(_BC) _F |= Vflag; \
850 }
851
852 #define LDIR \
853 LDI; \
854 if(_BC) \
855 { \
856 iCycleCount += cc_ex[bOpCode]; \
857 _PC -= 2; \
858 }
859
860 #define NEG \
861 { \
862 uint8_t value = _A; \
863 _A = 0; \
864 SUB(value); \
865 }
866
867 #define OUTD \
868 { \
869 uint8_t io = read_mem(_HL); \
870 _B--; \
871 z80_OUT_handler(z80.BC, io); \
872 _HL--; \
873 _F = SZ[_B]; \
874 if(io & Sflag) _F |= Nflag; \
875 if((((_C - 1) & 0xff) + io) & 0x100) _F |= Hflag | Cflag; \
876 if((drep_tmp1[_C & 3][io & 3] ^ breg_tmp2[_B] ^ (_C >> 2) ^ (io >> 2)) & 1) \
877 _F |= Pflag; \
878 }
879
880 #define OTDR \
881 OUTD; \
882 if(_B) \
883 { \
884 iCycleCount += cc_ex[bOpCode]; \
885 _PC -= 2; \
886 }
887
888 #define OUTI \
889 { \
890 uint8_t io = read_mem(_HL); \
891 _B--; \
892 z80_OUT_handler(z80.BC, io); \
893 _HL++; \
894 _F = SZ[_B]; \
895 if(io & Sflag) _F |= Nflag; \
896 if((((_C + 1) & 0xff) + io) & 0x100) _F |= Hflag | Cflag; \
897 if((irep_tmp1[_C & 3][io & 3] ^ breg_tmp2[_B] ^ (_C >> 2) ^ (io >> 2)) & 1) \
898 _F |= Pflag; \
899 }
900
901 #define OTIR \
902 OUTI; \
903 if(_B) \
904 { \
905 iCycleCount += cc_ex[bOpCode]; \
906 _PC -= 2; \
907 }
908
909 #define RLD \
910 { \
911 uint8_t n = read_mem(_HL); \
912 write_mem(_HL, (n << 4) | (_A & 0x0f)); \
913 _A = (_A & 0xf0) | (n >> 4); \
914 _F = (_F & Cflag) | SZP[_A]; \
915 }
916
917 #define RRD \
918 { \
919 uint8_t n = read_mem(_HL); \
920 write_mem(_HL, (n >> 4) | (_A << 4)); \
921 _A = (_A & 0xf0) | (n & 0x0f); \
922 _F = (_F & Cflag) | SZP[_A]; \
923 }
924
925 #define SBC16(reg) \
926 { \
927 uint32_t res = _HLdword - z80.reg.d - (_F & Cflag); \
928 _F = (((_HLdword ^ res ^ z80.reg.d) >> 8) & Hflag) | Nflag | \
929 ((res >> 16) & Cflag) | \
930 ((res >> 8) & (Sflag | Xflags)) | \
931 ((res & 0xffff) ? 0 : Zflag) | \
932 (((z80.reg.d ^ _HLdword) & (_HLdword ^ res) &0x8000) >> 13); \
933 _HL = (uint16_t)res; \
934 }
935
936
937
938 #define z80_int_handler \
939 { \
940 if (_IFF1) { /* process interrupts? */ \
941 _R++; \
942 _IFF1 = _IFF2 = 0; /* clear interrupt flip-flops */ \
943 z80.int_pending = 0; \
944 GateArray.sl_count &= 0x1f; /* clear bit 5 of GA scanline counter */ \
945 if (_HALT) { /* HALT instruction active? */ \
946 _HALT = 0; /* exit HALT 'loop' */ \
947 _PC++; /* correct PC */ \
948 } \
949 if (_IM < 2) { /* interrupt mode 0 or 1? (IM0 = IM1 on the CPC) */ \
950 iCycleCount = 20; \
951 if (iWSAdjust) { \
952 iCycleCount -= 4; \
953 } \
954 RST(0x0038); \
955 z80_wait_states \
956 } \
957 else { /* interrupt mode 2 */ \
958 reg_pair addr; \
959 iCycleCount = 28; /* was 76 */ \
960 if (iWSAdjust) { \
961 iCycleCount -= 4; \
962 } \
963 write_mem(--_SP, z80.PC.b.h); /* store high byte of current PC */ \
964 write_mem(--_SP, z80.PC.b.l); /* store low byte of current PC */ \
965 addr.b.l = read_ptr(); /* assemble pointer */ \
966 addr.b.h = _I; \
967 z80.PC.b.l = read_mem(addr.w.l); /* retrieve low byte of vector */ \
968 z80.PC.b.h = read_mem(addr.w.l+1); /* retrieve high byte of vector */ \
969 z80_wait_states \
970 } \
971 } \
972 }
973
974
975
z80_init_tables(void)976 void z80_init_tables(void)
977 {
978 int i, p;
979
980 for (i = 0; i < 256; i++) {
981 p = 0;
982 if(i & 0x01) ++p;
983 if(i & 0x02) ++p;
984 if(i & 0x04) ++p;
985 if(i & 0x08) ++p;
986 if(i & 0x10) ++p;
987 if(i & 0x20) ++p;
988 if(i & 0x40) ++p;
989 if(i & 0x80) ++p;
990 SZ[i] = i ? i & Sflag : Zflag;
991 SZ[i] |= (i & Xflags);
992 SZ_BIT[i] = i ? i & Sflag : Zflag | Pflag;
993 SZ_BIT[i] |= (i & Xflags);
994 SZP[i] = SZ[i] | ((p & 1) ? 0 : Pflag);
995 SZHV_inc[i] = SZ[i];
996 if(i == 0x80) SZHV_inc[i] |= Vflag;
997 if((i & 0x0f) == 0x00) SZHV_inc[i] |= Hflag;
998 SZHV_dec[i] = SZ[i] | Nflag;
999 if(i == 0x7f) SZHV_dec[i] |= Vflag;
1000 if((i & 0x0f) == 0x0f) SZHV_dec[i] |= Hflag;
1001 }
1002 }
1003
1004
1005
z80_mf2stop(void)1006 void z80_mf2stop(void)
1007 {
1008 _R++;
1009 _IFF1 = 0;
1010 z80.EI_issued = 0;
1011 iCycleCount = 20;
1012 if (iWSAdjust) {
1013 iCycleCount -= 4;
1014 }
1015 dwMF2ExitAddr = _PCdword;
1016 RST(0x0066); // MF2 stop button causes a Z80 NMI
1017 z80_wait_states
1018 dwMF2Flags = MF2_ACTIVE | MF2_RUNNING;
1019 }
1020
1021
1022
z80_execute(void)1023 int z80_execute(void)
1024 {
1025 uint8_t bOpCode;
1026
1027 while (_PCdword != z80.break_point) { // loop until break point
1028
1029 #ifdef DEBUG_Z80
1030 dbg_z80_diff = abs(dbg_z80_lastPC - _PC);
1031 if (dbg_z80_diff > 0x100) {
1032 fprintf(pfoDebug, "\n%04x ", _PC);
1033 }
1034 // else {
1035 // fprintf(pfoDebug, "%04x ", _PC);
1036 // }
1037 dbg_z80_lastPC = _PC;
1038 #endif
1039
1040 if (dwMF2Flags & MF2_RUNNING) {
1041 if (_PCdword == dwMF2ExitAddr) { // have we returned from the MF2?
1042 dwMF2Flags = MF2_INVISIBLE; // clear running flag and make the MF2 'invisible'
1043 }
1044 }
1045
1046 bOpCode = read_mem(_PC++);
1047 iCycleCount = cc_op[bOpCode];
1048 _R++;
1049
1050
1051
1052
1053 switch(bOpCode)
1054 {
1055 case adc_a: ADC(_A); break;
1056 case adc_b: ADC(_B); break;
1057 case adc_byte: ADC(read_mem(_PC++)); break;
1058 case adc_c: ADC(_C); break;
1059 case adc_d: ADC(_D); break;
1060 case adc_e: ADC(_E); break;
1061 case adc_h: ADC(_H); break;
1062 case adc_l: ADC(_L); break;
1063 case adc_mhl: ADC(read_mem(_HL)); break;
1064 case add_a: ADD(_A); break;
1065 case add_b: ADD(_B); break;
1066 case add_byte: ADD(read_mem(_PC++)); break;
1067 case add_c: ADD(_C); break;
1068 case add_d: ADD(_D); break;
1069 case add_e: ADD(_E); break;
1070 case add_h: ADD(_H); break;
1071 case add_hl_bc: ADD16(HL, BC); break;
1072 case add_hl_de: ADD16(HL, DE); break;
1073 case add_hl_hl: ADD16(HL, HL); break;
1074 case add_hl_sp: ADD16(HL, SP); break;
1075 case add_l: ADD(_L); break;
1076 case add_mhl: ADD(read_mem(_HL)); break;
1077 case and_a: AND(_A); break;
1078 case and_b: AND(_B); break;
1079 case and_byte: AND(read_mem(_PC++)); break;
1080 case and_c: AND(_C); break;
1081 case and_d: AND(_D); break;
1082 case and_e: AND(_E); break;
1083 case and_h: AND(_H); break;
1084 case and_l: AND(_L); break;
1085 case and_mhl: AND(read_mem(_HL)); break;
1086 case call: CALL; break;
1087 case call_c: if (_F & Cflag) { iCycleCount += cc_ex[bOpCode]; CALL } else { _PC += 2; } break;
1088 case call_m: if (_F & Sflag) { iCycleCount += cc_ex[bOpCode]; CALL } else { _PC += 2; } break;
1089 case call_nc: if (!(_F & Cflag)) { iCycleCount += cc_ex[bOpCode]; CALL } else { _PC += 2; } break;
1090 case call_nz: if (!(_F & Zflag)) { iCycleCount += cc_ex[bOpCode]; CALL } else { _PC += 2; } break;
1091 case call_p: if (!(_F & Sflag)) { iCycleCount += cc_ex[bOpCode]; CALL } else { _PC += 2; } break;
1092 case call_pe: if (_F & Pflag) { iCycleCount += cc_ex[bOpCode]; CALL } else { _PC += 2; } break;
1093 case call_po: if (!(_F & Pflag)) { iCycleCount += cc_ex[bOpCode]; CALL } else { _PC += 2; } break;
1094 case call_z: if (_F & Zflag) { iCycleCount += cc_ex[bOpCode]; CALL } else { _PC += 2; } break;
1095 case ccf: _F = ((_F & (Sflag | Zflag | Pflag | Cflag)) | ((_F & CF) << 4) | (_A & Xflags)) ^ CF; break;
1096 case cpl: _A ^= 0xff; _F = (_F & (Sflag | Zflag | Pflag | Cflag)) | Hflag | Nflag | (_A & Xflags); break;
1097 case cp_a: CP(_A); break;
1098 case cp_b: CP(_B); break;
1099 case cp_byte: CP(read_mem(_PC++)); break;
1100 case cp_c: CP(_C); break;
1101 case cp_d: CP(_D); break;
1102 case cp_e: CP(_E); break;
1103 case cp_h: CP(_H); break;
1104 case cp_l: CP(_L); break;
1105 case cp_mhl: CP(read_mem(_HL)); break;
1106 case daa: DAA; break;
1107 case dec_a: DEC(_A); break;
1108 case dec_b: DEC(_B); break;
1109 case dec_bc: _BC--; iWSAdjust++; break;
1110 case dec_c: DEC(_C); break;
1111 case dec_d: DEC(_D); break;
1112 case dec_de: _DE--; iWSAdjust++; break;
1113 case dec_e: DEC(_E); break;
1114 case dec_h: DEC(_H); break;
1115 case dec_hl: _HL--; iWSAdjust++; break;
1116 case dec_l: DEC(_L); break;
1117 case dec_mhl: { uint8_t b = read_mem(_HL); DEC(b); write_mem(_HL, b); } break;
1118 case dec_sp: _SP--; iWSAdjust++; break;
1119 case di: _IFF1 = _IFF2 = 0; z80.EI_issued = 0; break;
1120 case djnz: if (--_B) { iCycleCount += cc_ex[bOpCode]; JR } else { _PC++; } break;
1121 case ei: z80.EI_issued = 2; break;
1122 case exx: EXX; break;
1123 case ex_af_af: EX(z80.AF, z80.AFx); break;
1124 case ex_de_hl: EX(z80.DE, z80.HL); break;
1125 case ex_msp_hl: EX_SP(HL); iWSAdjust++; break;
1126 case halt: _HALT = 1; _PC--; break;
1127 case ina: { z80_wait_states iCycleCount = Ia_;} { reg_pair p; p.b.l = read_mem(_PC++); p.b.h = _A; _A = z80_IN_handler(p); } break;
1128 case inc_a: INC(_A); break;
1129 case inc_b: INC(_B); break;
1130 case inc_bc: _BC++; iWSAdjust++; break;
1131 case inc_c: INC(_C); break;
1132 case inc_d: INC(_D); break;
1133 case inc_de: _DE++; iWSAdjust++; break;
1134 case inc_e: INC(_E); break;
1135 case inc_h: INC(_H); break;
1136 case inc_hl: _HL++; iWSAdjust++; break;
1137 case inc_l: INC(_L); break;
1138 case inc_mhl: { uint8_t b = read_mem(_HL); INC(b); write_mem(_HL, b); } break;
1139 case inc_sp: _SP++; iWSAdjust++; break;
1140 case jp: JP; break;
1141 case jp_c: if (_F & Cflag) { JP } else { _PC += 2; }; break;
1142 case jp_m: if (_F & Sflag) { JP } else { _PC += 2; }; break;
1143 case jp_nc: if (!(_F & Cflag)) { JP } else { _PC += 2; }; break;
1144 case jp_nz: if (!(_F & Zflag)) { JP } else { _PC += 2; }; break;
1145 case jp_p: if (!(_F & Sflag)) { JP } else { _PC += 2; }; break;
1146 case jp_pe: if (_F & Pflag) { JP } else { _PC += 2; }; break;
1147 case jp_po: if (!(_F & Pflag)) { JP } else { _PC += 2; }; break;
1148 case jp_z: if (_F & Zflag) { JP } else { _PC += 2; }; break;
1149 case jr: JR; break;
1150 case jr_c: if (_F & Cflag) { iCycleCount += cc_ex[bOpCode]; JR } else { _PC++; }; break;
1151 case jr_nc: if (!(_F & Cflag)) { iCycleCount += cc_ex[bOpCode]; JR } else { _PC++; }; break;
1152 case jr_nz: if (!(_F & Zflag)) { iCycleCount += cc_ex[bOpCode]; JR } else { _PC++; }; break;
1153 case jr_z: if (_F & Zflag) { iCycleCount += cc_ex[bOpCode]; JR } else { _PC++; }; break;
1154 case ld_a_a: break;
1155 case ld_a_b: _A = _B; break;
1156 case ld_a_byte: _A = read_mem(_PC++); break;
1157 case ld_a_c: _A = _C; break;
1158 case ld_a_d: _A = _D; break;
1159 case ld_a_e: _A = _E; break;
1160 case ld_a_h: _A = _H; break;
1161 case ld_a_l: _A = _L; break;
1162 case ld_a_mbc: _A = read_mem(_BC); break;
1163 case ld_a_mde: _A = read_mem(_DE); break;
1164 case ld_a_mhl: _A = read_mem(_HL); break;
1165 case ld_a_mword: { reg_pair addr; addr.b.l = read_mem(_PC++); addr.b.h = read_mem(_PC++); _A = read_mem(addr.w.l); } break;
1166 case ld_bc_word: z80.BC.b.l = read_mem(_PC++); z80.BC.b.h = read_mem(_PC++); break;
1167 case ld_b_a: _B = _A; break;
1168 case ld_b_b: break;
1169 case ld_b_byte: _B = read_mem(_PC++); break;
1170 case ld_b_c: _B = _C; break;
1171 case ld_b_d: _B = _D; break;
1172 case ld_b_e: _B = _E; break;
1173 case ld_b_h: _B = _H; break;
1174 case ld_b_l: _B = _L; break;
1175 case ld_b_mhl: _B = read_mem(_HL); break;
1176 case ld_c_a: _C = _A; break;
1177 case ld_c_b: _C = _B; break;
1178 case ld_c_byte: _C = read_mem(_PC++); break;
1179 case ld_c_c: break;
1180 case ld_c_d: _C = _D; break;
1181 case ld_c_e: _C = _E; break;
1182 case ld_c_h: _C = _H; break;
1183 case ld_c_l: _C = _L; break;
1184 case ld_c_mhl: _C = read_mem(_HL); break;
1185 case ld_de_word: z80.DE.b.l = read_mem(_PC++); z80.DE.b.h = read_mem(_PC++); break;
1186 case ld_d_a: _D = _A; break;
1187 case ld_d_b: _D = _B; break;
1188 case ld_d_byte: _D = read_mem(_PC++); break;
1189 case ld_d_c: _D = _C; break;
1190 case ld_d_d: break;
1191 case ld_d_e: _D = _E; break;
1192 case ld_d_h: _D = _H; break;
1193 case ld_d_l: _D = _L; break;
1194 case ld_d_mhl: _D = read_mem(_HL); break;
1195 case ld_e_a: _E = _A; break;
1196 case ld_e_b: _E = _B; break;
1197 case ld_e_byte: _E = read_mem(_PC++); break;
1198 case ld_e_c: _E = _C; break;
1199 case ld_e_d: _E = _D; break;
1200 case ld_e_e: break;
1201 case ld_e_h: _E = _H; break;
1202 case ld_e_l: _E = _L; break;
1203 case ld_e_mhl: _E = read_mem(_HL); break;
1204 case ld_hl_mword: LD16_MEM(HL); break;
1205 case ld_hl_word: z80.HL.b.l = read_mem(_PC++); z80.HL.b.h = read_mem(_PC++); break;
1206 case ld_h_a: _H = _A; break;
1207 case ld_h_b: _H = _B; break;
1208 case ld_h_byte: _H = read_mem(_PC++); break;
1209 case ld_h_c: _H = _C; break;
1210 case ld_h_d: _H = _D; break;
1211 case ld_h_e: _H = _E; break;
1212 case ld_h_h: break;
1213 case ld_h_l: _H = _L; break;
1214 case ld_h_mhl: _H = read_mem(_HL); break;
1215 case ld_l_a: _L = _A; break;
1216 case ld_l_b: _L = _B; break;
1217 case ld_l_byte: _L = read_mem(_PC++); break;
1218 case ld_l_c: _L = _C; break;
1219 case ld_l_d: _L = _D; break;
1220 case ld_l_e: _L = _E; break;
1221 case ld_l_h: _L = _H; break;
1222 case ld_l_l: break;
1223 case ld_l_mhl: _L = read_mem(_HL); break;
1224 case ld_mbc_a: write_mem(_BC, _A); break;
1225 case ld_mde_a: write_mem(_DE, _A); break;
1226 case ld_mhl_a: write_mem(_HL, _A); break;
1227 case ld_mhl_b: write_mem(_HL, _B); break;
1228 case ld_mhl_byte: { uint8_t b = read_mem(_PC++); write_mem(_HL, b); } break;
1229 case ld_mhl_c: write_mem(_HL, _C); break;
1230 case ld_mhl_d: write_mem(_HL, _D); break;
1231 case ld_mhl_e: write_mem(_HL, _E); break;
1232 case ld_mhl_h: write_mem(_HL, _H); break;
1233 case ld_mhl_l: write_mem(_HL, _L); break;
1234 case ld_mword_a: { reg_pair addr; addr.b.l = read_mem(_PC++); addr.b.h = read_mem(_PC++); write_mem(addr.w.l, _A); } break;
1235 case ld_mword_hl: LDMEM_16(HL); break;
1236 case ld_pc_hl: _PC = _HL; break;
1237 case ld_sp_hl: _SP = _HL; iWSAdjust++; break;
1238 case ld_sp_word: z80.SP.b.l = read_mem(_PC++); z80.SP.b.h = read_mem(_PC++); break;
1239 case nop: break;
1240 case or_a: OR(_A); break;
1241 case or_b: OR(_B); break;
1242 case or_byte: OR(read_mem(_PC++)); break;
1243 case or_c: OR(_C); break;
1244 case or_d: OR(_D); break;
1245 case or_e: OR(_E); break;
1246 case or_h: OR(_H); break;
1247 case or_l: OR(_L); break;
1248 case or_mhl: OR(read_mem(_HL)); break;
1249 case outa: { z80_wait_states iCycleCount = Oa_;} { reg_pair p; p.b.l = read_mem(_PC++); p.b.h = _A; z80_OUT_handler(p, _A); } break;
1250 case pfx_cb: z80_pfx_cb(); break;
1251 case pfx_dd: z80_pfx_dd(); break;
1252 case pfx_ed: z80_pfx_ed(); break;
1253 case pfx_fd: z80_pfx_fd(); break;
1254 case pop_af: POP(AF); break;
1255 case pop_bc: POP(BC); break;
1256 case pop_de: POP(DE); break;
1257 case pop_hl: POP(HL); break;
1258 case push_af: PUSH(AF); break;
1259 case push_bc: PUSH(BC); break;
1260 case push_de: PUSH(DE); break;
1261 case push_hl: PUSH(HL); break;
1262 case ret: RET; break;
1263 case ret_c: if (_F & Cflag) { iCycleCount += cc_ex[bOpCode]; RET } else { iWSAdjust++; } ; break;
1264 case ret_m: if (_F & Sflag) { iCycleCount += cc_ex[bOpCode]; RET } else { iWSAdjust++; } ; break;
1265 case ret_nc: if (!(_F & Cflag)) { iCycleCount += cc_ex[bOpCode]; RET } else { iWSAdjust++; } ; break;
1266 case ret_nz: if (!(_F & Zflag)) { iCycleCount += cc_ex[bOpCode]; RET } else { iWSAdjust++; } ; break;
1267 case ret_p: if (!(_F & Sflag)) { iCycleCount += cc_ex[bOpCode]; RET } else { iWSAdjust++; } ; break;
1268 case ret_pe: if (_F & Pflag) { iCycleCount += cc_ex[bOpCode]; RET } else { iWSAdjust++; } ; break;
1269 case ret_po: if (!(_F & Pflag)) { iCycleCount += cc_ex[bOpCode]; RET } else { iWSAdjust++; } ; break;
1270 case ret_z: if (_F & Zflag) { iCycleCount += cc_ex[bOpCode]; RET } else { iWSAdjust++; } ; break;
1271 case rla: RLA; break;
1272 case rlca: RLCA; break;
1273 case rra: RRA; break;
1274 case rrca: RRCA; break;
1275 case rst00: RST(0x0000); break;
1276 case rst08: RST(0x0008); break;
1277 case rst10: RST(0x0010); break;
1278 case rst18: RST(0x0018); break;
1279 case rst20: RST(0x0020); break;
1280 case rst28: RST(0x0028); break;
1281 case rst30: RST(0x0030); break;
1282 case rst38: RST(0x0038); break;
1283 case sbc_a: SBC(_A); break;
1284 case sbc_b: SBC(_B); break;
1285 case sbc_byte: SBC(read_mem(_PC++)); break;
1286 case sbc_c: SBC(_C); break;
1287 case sbc_d: SBC(_D); break;
1288 case sbc_e: SBC(_E); break;
1289 case sbc_h: SBC(_H); break;
1290 case sbc_l: SBC(_L); break;
1291 case sbc_mhl: SBC(read_mem(_HL)); break;
1292 case scf: _F = (_F & (Sflag | Zflag | Pflag)) | Cflag | (_A & Xflags); break;
1293 case sub_a: SUB(_A); break;
1294 case sub_b: SUB(_B); break;
1295 case sub_byte: SUB(read_mem(_PC++)); break;
1296 case sub_c: SUB(_C); break;
1297
1298 case sub_d: SUB(_D); break;
1299 case sub_e: SUB(_E); break;
1300 case sub_h: SUB(_H); break;
1301 case sub_l: SUB(_L); break;
1302 case sub_mhl: SUB(read_mem(_HL)); break;
1303 case xor_a: XOR(_A); break;
1304 case xor_b: XOR(_B); break;
1305 case xor_byte: XOR(read_mem(_PC++)); break;
1306 case xor_c: XOR(_C); break;
1307 case xor_d: XOR(_D); break;
1308 case xor_e: XOR(_E); break;
1309 case xor_h: XOR(_H); break;
1310 case xor_l: XOR(_L); break;
1311 case xor_mhl: XOR(read_mem(_HL)); break;
1312 }
1313
1314
1315
1316 z80_wait_states
1317
1318 if (z80.EI_issued) { // EI 'delay' in effect?
1319 if (--z80.EI_issued == 0) {
1320 _IFF1 = _IFF2 = Pflag; // set interrupt flip-flops
1321 if (z80.int_pending) {
1322 z80_int_handler
1323 }
1324 }
1325 }
1326 else if (z80.int_pending) { // any interrupts pending?
1327 z80_int_handler
1328 }
1329 iWSAdjust = 0;
1330
1331 if (z80.trace) { // tracing instructions?
1332 z80.trace = 0; // reset trace condition
1333 return EC_TRACE; // exit emulation loop
1334 }
1335 else if (VDU.frame_completed) { // video emulation finished building frame?
1336 VDU.frame_completed = 0;
1337 return EC_FRAME_COMPLETE; // exit emulation loop
1338 }
1339 else if (PSG.buffer_full) { // sound emulation finished filling a buffer?
1340 PSG.buffer_full = 0;
1341 return EC_SOUND_BUFFER; // exit emulation loop
1342 }
1343 else if (CPC.cycle_count <= 0) { // emulation loop ran for one frame?
1344 CPC.cycle_count += CYCLE_COUNT_INIT;
1345 return EC_CYCLE_COUNT; // exit emulation loop
1346 }
1347 }
1348 return EC_BREAKPOINT;
1349 }
1350
1351
1352
z80_pfx_cb(void)1353 void z80_pfx_cb(void)
1354 {
1355 uint8_t bOpCode;
1356
1357 bOpCode = read_mem(_PC++);
1358 iCycleCount += cc_cb[bOpCode];
1359 _R++;
1360 switch(bOpCode)
1361 {
1362 case bit0_a: BIT(0, _A); break;
1363 case bit0_b: BIT(0, _B); break;
1364 case bit0_c: BIT(0, _C); break;
1365 case bit0_d: BIT(0, _D); break;
1366 case bit0_e: BIT(0, _E); break;
1367 case bit0_h: BIT(0, _H); break;
1368 case bit0_l: BIT(0, _L); break;
1369 case bit0_mhl: BIT(0, read_mem(_HL)); break;
1370 case bit1_a: BIT(1, _A); break;
1371 case bit1_b: BIT(1, _B); break;
1372 case bit1_c: BIT(1, _C); break;
1373 case bit1_d: BIT(1, _D); break;
1374 case bit1_e: BIT(1, _E); break;
1375 case bit1_h: BIT(1, _H); break;
1376 case bit1_l: BIT(1, _L); break;
1377 case bit1_mhl: BIT(1, read_mem(_HL)); break;
1378 case bit2_a: BIT(2, _A); break;
1379 case bit2_b: BIT(2, _B); break;
1380 case bit2_c: BIT(2, _C); break;
1381 case bit2_d: BIT(2, _D); break;
1382 case bit2_e: BIT(2, _E); break;
1383 case bit2_h: BIT(2, _H); break;
1384 case bit2_l: BIT(2, _L); break;
1385 case bit2_mhl: BIT(2, read_mem(_HL)); break;
1386 case bit3_a: BIT(3, _A); break;
1387 case bit3_b: BIT(3, _B); break;
1388 case bit3_c: BIT(3, _C); break;
1389 case bit3_d: BIT(3, _D); break;
1390 case bit3_e: BIT(3, _E); break;
1391 case bit3_h: BIT(3, _H); break;
1392 case bit3_l: BIT(3, _L); break;
1393 case bit3_mhl: BIT(3, read_mem(_HL)); break;
1394 case bit4_a: BIT(4, _A); break;
1395 case bit4_b: BIT(4, _B); break;
1396 case bit4_c: BIT(4, _C); break;
1397 case bit4_d: BIT(4, _D); break;
1398 case bit4_e: BIT(4, _E); break;
1399 case bit4_h: BIT(4, _H); break;
1400 case bit4_l: BIT(4, _L); break;
1401 case bit4_mhl: BIT(4, read_mem(_HL)); break;
1402 case bit5_a: BIT(5, _A); break;
1403 case bit5_b: BIT(5, _B); break;
1404 case bit5_c: BIT(5, _C); break;
1405 case bit5_d: BIT(5, _D); break;
1406 case bit5_e: BIT(5, _E); break;
1407 case bit5_h: BIT(5, _H); break;
1408 case bit5_l: BIT(5, _L); break;
1409 case bit5_mhl: BIT(5, read_mem(_HL)); break;
1410 case bit6_a: BIT(6, _A); break;
1411 case bit6_b: BIT(6, _B); break;
1412 case bit6_c: BIT(6, _C); break;
1413 case bit6_d: BIT(6, _D); break;
1414 case bit6_e: BIT(6, _E); break;
1415 case bit6_h: BIT(6, _H); break;
1416 case bit6_l: BIT(6, _L); break;
1417 case bit6_mhl: BIT(6, read_mem(_HL)); break;
1418 case bit7_a: BIT(7, _A); break;
1419 case bit7_b: BIT(7, _B); break;
1420 case bit7_c: BIT(7, _C); break;
1421 case bit7_d: BIT(7, _D); break;
1422 case bit7_e: BIT(7, _E); break;
1423 case bit7_h: BIT(7, _H); break;
1424 case bit7_l: BIT(7, _L); break;
1425 case bit7_mhl: BIT(7, read_mem(_HL)); break;
1426 case res0_a: _A = RES(0, _A); break;
1427 case res0_b: _B = RES(0, _B); break;
1428 case res0_c: _C = RES(0, _C); break;
1429 case res0_d: _D = RES(0, _D); break;
1430 case res0_e: _E = RES(0, _E); break;
1431 case res0_h: _H = RES(0, _H); break;
1432 case res0_l: _L = RES(0, _L); break;
1433 case res0_mhl: { uint8_t b = read_mem(_HL); write_mem(_HL, RES(0, b)); } break;
1434 case res1_a: _A = RES(1, _A); break;
1435 case res1_b: _B = RES(1, _B); break;
1436 case res1_c: _C = RES(1, _C); break;
1437 case res1_d: _D = RES(1, _D); break;
1438 case res1_e: _E = RES(1, _E); break;
1439 case res1_h: _H = RES(1, _H); break;
1440 case res1_l: _L = RES(1, _L); break;
1441 case res1_mhl: { uint8_t b = read_mem(_HL); write_mem(_HL, RES(1, b)); } break;
1442 case res2_a: _A = RES(2, _A); break;
1443 case res2_b: _B = RES(2, _B); break;
1444 case res2_c: _C = RES(2, _C); break;
1445 case res2_d: _D = RES(2, _D); break;
1446 case res2_e: _E = RES(2, _E); break;
1447 case res2_h: _H = RES(2, _H); break;
1448 case res2_l: _L = RES(2, _L); break;
1449 case res2_mhl: { uint8_t b = read_mem(_HL); write_mem(_HL, RES(2, b)); } break;
1450 case res3_a: _A = RES(3, _A); break;
1451 case res3_b: _B = RES(3, _B); break;
1452 case res3_c: _C = RES(3, _C); break;
1453 case res3_d: _D = RES(3, _D); break;
1454 case res3_e: _E = RES(3, _E); break;
1455 case res3_h: _H = RES(3, _H); break;
1456 case res3_l: _L = RES(3, _L); break;
1457 case res3_mhl: { uint8_t b = read_mem(_HL); write_mem(_HL, RES(3, b)); } break;
1458 case res4_a: _A = RES(4, _A); break;
1459 case res4_b: _B = RES(4, _B); break;
1460 case res4_c: _C = RES(4, _C); break;
1461 case res4_d: _D = RES(4, _D); break;
1462 case res4_e: _E = RES(4, _E); break;
1463 case res4_h: _H = RES(4, _H); break;
1464 case res4_l: _L = RES(4, _L); break;
1465 case res4_mhl: { uint8_t b = read_mem(_HL); write_mem(_HL, RES(4, b)); } break;
1466 case res5_a: _A = RES(5, _A); break;
1467 case res5_b: _B = RES(5, _B); break;
1468 case res5_c: _C = RES(5, _C); break;
1469 case res5_d: _D = RES(5, _D); break;
1470 case res5_e: _E = RES(5, _E); break;
1471 case res5_h: _H = RES(5, _H); break;
1472 case res5_l: _L = RES(5, _L); break;
1473 case res5_mhl: { uint8_t b = read_mem(_HL); write_mem(_HL, RES(5, b)); } break;
1474 case res6_a: _A = RES(6, _A); break;
1475 case res6_b: _B = RES(6, _B); break;
1476 case res6_c: _C = RES(6, _C); break;
1477 case res6_d: _D = RES(6, _D); break;
1478 case res6_e: _E = RES(6, _E); break;
1479 case res6_h: _H = RES(6, _H); break;
1480 case res6_l: _L = RES(6, _L); break;
1481 case res6_mhl: { uint8_t b = read_mem(_HL); write_mem(_HL, RES(6, b)); } break;
1482 case res7_a: _A = RES(7, _A); break;
1483 case res7_b: _B = RES(7, _B); break;
1484 case res7_c: _C = RES(7, _C); break;
1485 case res7_d: _D = RES(7, _D); break;
1486 case res7_e: _E = RES(7, _E); break;
1487 case res7_h: _H = RES(7, _H); break;
1488 case res7_l: _L = RES(7, _L); break;
1489 case res7_mhl: { uint8_t b = read_mem(_HL); write_mem(_HL, RES(7, b)); } break;
1490 case rlc_a: _A = RLC(_A); break;
1491 case rlc_b: _B = RLC(_B); break;
1492 case rlc_c: _C = RLC(_C); break;
1493 case rlc_d: _D = RLC(_D); break;
1494 case rlc_e: _E = RLC(_E); break;
1495 case rlc_h: _H = RLC(_H); break;
1496 case rlc_l: _L = RLC(_L); break;
1497 case rlc_mhl: { uint8_t b = read_mem(_HL); write_mem(_HL, RLC(b)); } break;
1498 case rl_a: _A = RL(_A); break;
1499 case rl_b: _B = RL(_B); break;
1500 case rl_c: _C = RL(_C); break;
1501 case rl_d: _D = RL(_D); break;
1502 case rl_e: _E = RL(_E); break;
1503 case rl_h: _H = RL(_H); break;
1504 case rl_l: _L = RL(_L); break;
1505 case rl_mhl: { uint8_t b = read_mem(_HL); write_mem(_HL, RL(b)); } break;
1506 case rrc_a: _A = RRC(_A); break;
1507 case rrc_b: _B = RRC(_B); break;
1508 case rrc_c: _C = RRC(_C); break;
1509 case rrc_d: _D = RRC(_D); break;
1510 case rrc_e: _E = RRC(_E); break;
1511 case rrc_h: _H = RRC(_H); break;
1512 case rrc_l: _L = RRC(_L); break;
1513 case rrc_mhl: { uint8_t b = read_mem(_HL); write_mem(_HL, RRC(b)); } break;
1514 case rr_a: _A = RR(_A); break;
1515 case rr_b: _B = RR(_B); break;
1516 case rr_c: _C = RR(_C); break;
1517 case rr_d: _D = RR(_D); break;
1518 case rr_e: _E = RR(_E); break;
1519 case rr_h: _H = RR(_H); break;
1520 case rr_l: _L = RR(_L); break;
1521 case rr_mhl: { uint8_t b = read_mem(_HL); write_mem(_HL, RR(b)); } break;
1522 case set0_a: _A = SET(0, _A); break;
1523 case set0_b: _B = SET(0, _B); break;
1524 case set0_c: _C = SET(0, _C); break;
1525 case set0_d: _D = SET(0, _D); break;
1526 case set0_e: _E = SET(0, _E); break;
1527 case set0_h: _H = SET(0, _H); break;
1528 case set0_l: _L = SET(0, _L); break;
1529 case set0_mhl: { uint8_t b = read_mem(_HL); write_mem(_HL, SET(0, b)); } break;
1530 case set1_a: _A = SET(1, _A); break;
1531 case set1_b: _B = SET(1, _B); break;
1532 case set1_c: _C = SET(1, _C); break;
1533 case set1_d: _D = SET(1, _D); break;
1534 case set1_e: _E = SET(1, _E); break;
1535 case set1_h: _H = SET(1, _H); break;
1536 case set1_l: _L = SET(1, _L); break;
1537 case set1_mhl: { uint8_t b = read_mem(_HL); write_mem(_HL, SET(1, b)); } break;
1538 case set2_a: _A = SET(2, _A); break;
1539 case set2_b: _B = SET(2, _B); break;
1540 case set2_c: _C = SET(2, _C); break;
1541 case set2_d: _D = SET(2, _D); break;
1542 case set2_e: _E = SET(2, _E); break;
1543 case set2_h: _H = SET(2, _H); break;
1544 case set2_l: _L = SET(2, _L); break;
1545 case set2_mhl: { uint8_t b = read_mem(_HL); write_mem(_HL, SET(2, b)); } break;
1546 case set3_a: _A = SET(3, _A); break;
1547 case set3_b: _B = SET(3, _B); break;
1548 case set3_c: _C = SET(3, _C); break;
1549 case set3_d: _D = SET(3, _D); break;
1550 case set3_e: _E = SET(3, _E); break;
1551 case set3_h: _H = SET(3, _H); break;
1552 case set3_l: _L = SET(3, _L); break;
1553 case set3_mhl: { uint8_t b = read_mem(_HL); write_mem(_HL, SET(3, b)); } break;
1554 case set4_a: _A = SET(4, _A); break;
1555 case set4_b: _B = SET(4, _B); break;
1556 case set4_c: _C = SET(4, _C); break;
1557 case set4_d: _D = SET(4, _D); break;
1558 case set4_e: _E = SET(4, _E); break;
1559 case set4_h: _H = SET(4, _H); break;
1560 case set4_l: _L = SET(4, _L); break;
1561 case set4_mhl: { uint8_t b = read_mem(_HL); write_mem(_HL, SET(4, b)); } break;
1562 case set5_a: _A = SET(5, _A); break;
1563 case set5_b: _B = SET(5, _B); break;
1564 case set5_c: _C = SET(5, _C); break;
1565 case set5_d: _D = SET(5, _D); break;
1566 case set5_e: _E = SET(5, _E); break;
1567 case set5_h: _H = SET(5, _H); break;
1568 case set5_l: _L = SET(5, _L); break;
1569 case set5_mhl: { uint8_t b = read_mem(_HL); write_mem(_HL, SET(5, b)); } break;
1570 case set6_a: _A = SET(6, _A); break;
1571 case set6_b: _B = SET(6, _B); break;
1572 case set6_c: _C = SET(6, _C); break;
1573 case set6_d: _D = SET(6, _D); break;
1574 case set6_e: _E = SET(6, _E); break;
1575 case set6_h: _H = SET(6, _H); break;
1576 case set6_l: _L = SET(6, _L); break;
1577 case set6_mhl: { uint8_t b = read_mem(_HL); write_mem(_HL, SET(6, b)); } break;
1578 case set7_a: _A = SET(7, _A); break;
1579 case set7_b: _B = SET(7, _B); break;
1580 case set7_c: _C = SET(7, _C); break;
1581 case set7_d: _D = SET(7, _D); break;
1582 case set7_e: _E = SET(7, _E); break;
1583 case set7_h: _H = SET(7, _H); break;
1584 case set7_l: _L = SET(7, _L); break;
1585 case set7_mhl: { uint8_t b = read_mem(_HL); write_mem(_HL, SET(7, b)); } break;
1586 case sla_a: _A = SLA(_A); break;
1587 case sla_b: _B = SLA(_B); break;
1588 case sla_c: _C = SLA(_C); break;
1589 case sla_d: _D = SLA(_D); break;
1590 case sla_e: _E = SLA(_E); break;
1591 case sla_h: _H = SLA(_H); break;
1592 case sla_l: _L = SLA(_L); break;
1593 case sla_mhl: { uint8_t b = read_mem(_HL); write_mem(_HL, SLA(b)); } break;
1594 case sll_a: _A = SLL(_A); break;
1595 case sll_b: _B = SLL(_B); break;
1596 case sll_c: _C = SLL(_C); break;
1597 case sll_d: _D = SLL(_D); break;
1598 case sll_e: _E = SLL(_E); break;
1599 case sll_h: _H = SLL(_H); break;
1600 case sll_l: _L = SLL(_L); break;
1601 case sll_mhl: { uint8_t b = read_mem(_HL); write_mem(_HL, SLL(b)); } break;
1602 case sra_a: _A = SRA(_A); break;
1603 case sra_b: _B = SRA(_B); break;
1604 case sra_c: _C = SRA(_C); break;
1605 case sra_d: _D = SRA(_D); break;
1606 case sra_e: _E = SRA(_E); break;
1607 case sra_h: _H = SRA(_H); break;
1608 case sra_l: _L = SRA(_L); break;
1609 case sra_mhl: { uint8_t b = read_mem(_HL); write_mem(_HL, SRA(b)); } break;
1610 case srl_a: _A = SRL(_A); break;
1611 case srl_b: _B = SRL(_B); break;
1612 case srl_c: _C = SRL(_C); break;
1613 case srl_d: _D = SRL(_D); break;
1614 case srl_e: _E = SRL(_E); break;
1615 case srl_h: _H = SRL(_H); break;
1616 case srl_l: _L = SRL(_L); break;
1617 case srl_mhl: { uint8_t b = read_mem(_HL); write_mem(_HL, SRL(b)); } break;
1618 }
1619 }
1620
1621
1622
z80_pfx_dd(void)1623 void z80_pfx_dd(void)
1624 {
1625 uint8_t bOpCode;
1626
1627 bOpCode = read_mem(_PC++);
1628 iCycleCount += cc_xy[bOpCode];
1629 _R++;
1630 switch(bOpCode)
1631 {
1632 case adc_a: ADC(_A); break;
1633 case adc_b: ADC(_B); break;
1634 case adc_byte: ADC(read_mem(_PC++)); break;
1635 case adc_c: ADC(_C); break;
1636 case adc_d: ADC(_D); break;
1637 case adc_e: ADC(_E); break;
1638 case adc_h: ADC(_IXh); break;
1639 case adc_l: ADC(_IXl); break;
1640 case adc_mhl: { signed char o = read_mem(_PC++); ADC(read_mem(_IX+o)); } break;
1641 case add_a: ADD(_A); break;
1642 case add_b: ADD(_B); break;
1643 case add_byte: ADD(read_mem(_PC++)); break;
1644 case add_c: ADD(_C); break;
1645 case add_d: ADD(_D); break;
1646 case add_e: ADD(_E); break;
1647 case add_h: ADD(_IXh); break;
1648 case add_hl_bc: ADD16(IX, BC); break;
1649 case add_hl_de: ADD16(IX, DE); break;
1650 case add_hl_hl: ADD16(IX, IX); break;
1651 case add_hl_sp: ADD16(IX, SP); break;
1652 case add_l: ADD(_IXl); break;
1653 case add_mhl: { signed char o = read_mem(_PC++); ADD(read_mem(_IX+o)); } break;
1654 case and_a: AND(_A); break;
1655 case and_b: AND(_B); break;
1656 case and_byte: AND(read_mem(_PC++)); break;
1657 case and_c: AND(_C); break;
1658 case and_d: AND(_D); break;
1659 case and_e: AND(_E); break;
1660 case and_h: AND(_IXh); break;
1661 case and_l: AND(_IXl); break;
1662 case and_mhl: { signed char o = read_mem(_PC++); AND(read_mem(_IX+o)); } break;
1663 case call: CALL; break;
1664 case call_c: if (_F & Cflag) { iCycleCount += cc_ex[bOpCode]; CALL } else { _PC += 2; } break;
1665 case call_m: if (_F & Sflag) { iCycleCount += cc_ex[bOpCode]; CALL } else { _PC += 2; } break;
1666 case call_nc: if (!(_F & Cflag)) { iCycleCount += cc_ex[bOpCode]; CALL } else { _PC += 2; } break;
1667 case call_nz: if (!(_F & Zflag)) { iCycleCount += cc_ex[bOpCode]; CALL } else { _PC += 2; } break;
1668 case call_p: if (!(_F & Sflag)) { iCycleCount += cc_ex[bOpCode]; CALL } else { _PC += 2; } break;
1669 case call_pe: if (_F & Pflag) { iCycleCount += cc_ex[bOpCode]; CALL } else { _PC += 2; } break;
1670 case call_po: if (!(_F & Pflag)) { iCycleCount += cc_ex[bOpCode]; CALL } else { _PC += 2; } break;
1671 case call_z: if (_F & Zflag) { iCycleCount += cc_ex[bOpCode]; CALL } else { _PC += 2; } break;
1672 case ccf: _F = ((_F & (Sflag | Zflag | Pflag | Cflag)) | ((_F & CF) << 4) | (_A & Xflags)) ^ CF; break;
1673 case cpl: _A ^= 0xff; _F = (_F & (Sflag | Zflag | Pflag | Cflag)) | Hflag | Nflag | (_A & Xflags); break;
1674 case cp_a: CP(_A); break;
1675 case cp_b: CP(_B); break;
1676 case cp_byte: CP(read_mem(_PC++)); break;
1677 case cp_c: CP(_C); break;
1678 case cp_d: CP(_D); break;
1679 case cp_e: CP(_E); break;
1680 case cp_h: CP(_IXh); break;
1681 case cp_l: CP(_IXl); break;
1682 case cp_mhl: { signed char o = read_mem(_PC++); CP(read_mem(_IX+o)); } break;
1683 case daa: DAA; break;
1684 case dec_a: DEC(_A); break;
1685 case dec_b: DEC(_B); break;
1686 case dec_bc: _BC--; iWSAdjust++; break;
1687 case dec_c: DEC(_C); break;
1688 case dec_d: DEC(_D); break;
1689 case dec_de: _DE--; iWSAdjust++; break;
1690 case dec_e: DEC(_E); break;
1691 case dec_h: DEC(_IXh); break;
1692 case dec_hl: _IX--; iWSAdjust++; break;
1693 case dec_l: DEC(_IXl); break;
1694 case dec_mhl: { signed char o = read_mem(_PC++); uint8_t b = read_mem(_IX+o); DEC(b); write_mem(_IX+o, b); } break;
1695 case dec_sp: _SP--; iWSAdjust++; break;
1696 case di: _IFF1 = _IFF2 = 0; z80.EI_issued = 0; break;
1697 case djnz: if (--_B) { iCycleCount += cc_ex[bOpCode]; JR } else { _PC++; } break;
1698 case ei: z80.EI_issued = 2; break;
1699 case exx: EXX; break;
1700 case ex_af_af: EX(z80.AF, z80.AFx); break;
1701 case ex_de_hl: EX(z80.DE, z80.HL); break;
1702 case ex_msp_hl: EX_SP(IX); iWSAdjust++; break;
1703 case halt: _HALT = 1; _PC--; break;
1704 case ina: { z80_wait_states iCycleCount = Ia_;} { reg_pair p; p.b.l = read_mem(_PC++); p.b.h = _A; _A = z80_IN_handler(p); } break;
1705 case inc_a: INC(_A); break;
1706 case inc_b: INC(_B); break;
1707 case inc_bc: _BC++; iWSAdjust++; break;
1708 case inc_c: INC(_C); break;
1709 case inc_d: INC(_D); break;
1710 case inc_de: _DE++; iWSAdjust++; break;
1711 case inc_e: INC(_E); break;
1712 case inc_h: INC(_IXh); break;
1713 case inc_hl: _IX++; iWSAdjust++; break;
1714 case inc_l: INC(_IXl); break;
1715 case inc_mhl: { signed char o = read_mem(_PC++); uint8_t b = read_mem(_IX+o); INC(b); write_mem(_IX+o, b); } break;
1716 case inc_sp: _SP++; iWSAdjust++; break;
1717 case jp: JP; break;
1718 case jp_c: if (_F & Cflag) { JP } else { _PC += 2; }; break;
1719 case jp_m: if (_F & Sflag) { JP } else { _PC += 2; }; break;
1720 case jp_nc: if (!(_F & Cflag)) { JP } else { _PC += 2; }; break;
1721 case jp_nz: if (!(_F & Zflag)) { JP } else { _PC += 2; }; break;
1722 case jp_p: if (!(_F & Sflag)) { JP } else { _PC += 2; }; break;
1723 case jp_pe: if (_F & Pflag) { JP } else { _PC += 2; }; break;
1724 case jp_po: if (!(_F & Pflag)) { JP } else { _PC += 2; }; break;
1725 case jp_z: if (_F & Zflag) { JP } else { _PC += 2; }; break;
1726 case jr: JR; break;
1727 case jr_c: if (_F & Cflag) { iCycleCount += cc_ex[bOpCode]; JR } else { _PC++; }; break;
1728 case jr_nc: if (!(_F & Cflag)) { iCycleCount += cc_ex[bOpCode]; JR } else { _PC++; }; break;
1729 case jr_nz: if (!(_F & Zflag)) { iCycleCount += cc_ex[bOpCode]; JR } else { _PC++; }; break;
1730 case jr_z: if (_F & Zflag) { iCycleCount += cc_ex[bOpCode]; JR } else { _PC++; }; break;
1731 case ld_a_a: break;
1732 case ld_a_b: _A = _B; break;
1733 case ld_a_byte: _A = read_mem(_PC++); break;
1734 case ld_a_c: _A = _C; break;
1735 case ld_a_d: _A = _D; break;
1736 case ld_a_e: _A = _E; break;
1737 case ld_a_h: _A = _IXh; break;
1738 case ld_a_l: _A = _IXl; break;
1739 case ld_a_mbc: _A = read_mem(_BC); break;
1740 case ld_a_mde: _A = read_mem(_DE); break;
1741 case ld_a_mhl: { signed char o = read_mem(_PC++); _A = read_mem(_IX+o); } break;
1742 case ld_a_mword: { reg_pair addr; addr.b.l = read_mem(_PC++); addr.b.h = read_mem(_PC++); _A = read_mem(addr.w.l); } break;
1743 case ld_bc_word: z80.BC.b.l = read_mem(_PC++); z80.BC.b.h = read_mem(_PC++); break;
1744 case ld_b_a: _B = _A; break;
1745 case ld_b_b: break;
1746 case ld_b_byte: _B = read_mem(_PC++); break;
1747 case ld_b_c: _B = _C; break;
1748 case ld_b_d: _B = _D; break;
1749 case ld_b_e: _B = _E; break;
1750 case ld_b_h: _B = _IXh; break;
1751 case ld_b_l: _B = _IXl; break;
1752 case ld_b_mhl: { signed char o = read_mem(_PC++); _B = read_mem(_IX+o); } break;
1753 case ld_c_a: _C = _A; break;
1754 case ld_c_b: _C = _B; break;
1755 case ld_c_byte: _C = read_mem(_PC++); break;
1756 case ld_c_c: break;
1757 case ld_c_d: _C = _D; break;
1758 case ld_c_e: _C = _E; break;
1759 case ld_c_h: _C = _IXh; break;
1760 case ld_c_l: _C = _IXl; break;
1761 case ld_c_mhl: { signed char o = read_mem(_PC++); _C = read_mem(_IX+o); } break;
1762 case ld_de_word: z80.DE.b.l = read_mem(_PC++); z80.DE.b.h = read_mem(_PC++); break;
1763 case ld_d_a: _D = _A; break;
1764 case ld_d_b: _D = _B; break;
1765 case ld_d_byte: _D = read_mem(_PC++); break;
1766 case ld_d_c: _D = _C; break;
1767 case ld_d_d: break;
1768 case ld_d_e: _D = _E; break;
1769 case ld_d_h: _D = _IXh; break;
1770 case ld_d_l: _D = _IXl; break;
1771 case ld_d_mhl: { signed char o = read_mem(_PC++); _D = read_mem(_IX+o); } break;
1772 case ld_e_a: _E = _A; break;
1773 case ld_e_b: _E = _B; break;
1774 case ld_e_byte: _E = read_mem(_PC++); break;
1775 case ld_e_c: _E = _C; break;
1776 case ld_e_d: _E = _D; break;
1777 case ld_e_e: break;
1778 case ld_e_h: _E = _IXh; break;
1779 case ld_e_l: _E = _IXl; break;
1780 case ld_e_mhl: { signed char o = read_mem(_PC++); _E = read_mem(_IX+o); } break;
1781 case ld_hl_mword: LD16_MEM(IX); break;
1782 case ld_hl_word: z80.IX.b.l = read_mem(_PC++); z80.IX.b.h = read_mem(_PC++); break;
1783 case ld_h_a: _IXh = _A; break;
1784 case ld_h_b: _IXh = _B; break;
1785 case ld_h_byte: _IXh = read_mem(_PC++); break;
1786 case ld_h_c: _IXh = _C; break;
1787 case ld_h_d: _IXh = _D; break;
1788 case ld_h_e: _IXh = _E; break;
1789 case ld_h_h: break;
1790 case ld_h_l: _IXh = _IXl; break;
1791 case ld_h_mhl: { signed char o = read_mem(_PC++); _H = read_mem(_IX+o); } break;
1792 case ld_l_a: _IXl = _A; break;
1793 case ld_l_b: _IXl = _B; break;
1794 case ld_l_byte: _IXl = read_mem(_PC++); break;
1795 case ld_l_c: _IXl = _C; break;
1796 case ld_l_d: _IXl = _D; break;
1797
1798 case ld_l_e: _IXl = _E; break;
1799 case ld_l_h: _IXl = _IXh; break;
1800 case ld_l_l: break;
1801 case ld_l_mhl: { signed char o = read_mem(_PC++); _L = read_mem(_IX+o); } break;
1802 case ld_mbc_a: write_mem(_BC, _A); break;
1803 case ld_mde_a: write_mem(_DE, _A); break;
1804 case ld_mhl_a: { signed char o = read_mem(_PC++); write_mem(_IX+o, _A); } break;
1805 case ld_mhl_b: { signed char o = read_mem(_PC++); write_mem(_IX+o, _B); } break;
1806 case ld_mhl_byte: { signed char o = read_mem(_PC++); uint8_t b = read_mem(_PC++); write_mem(_IX+o, b); } break;
1807 case ld_mhl_c: { signed char o = read_mem(_PC++); write_mem(_IX+o, _C); } break;
1808 case ld_mhl_d: { signed char o = read_mem(_PC++); write_mem(_IX+o, _D); } break;
1809 case ld_mhl_e: { signed char o = read_mem(_PC++); write_mem(_IX+o, _E); } break;
1810 case ld_mhl_h: { signed char o = read_mem(_PC++); write_mem(_IX+o, _H); } break;
1811 case ld_mhl_l: { signed char o = read_mem(_PC++); write_mem(_IX+o, _L); } break;
1812 case ld_mword_a: { reg_pair addr; addr.b.l = read_mem(_PC++); addr.b.h = read_mem(_PC++); write_mem(addr.w.l, _A); } break;
1813 case ld_mword_hl: LDMEM_16(IX); break;
1814 case ld_pc_hl: _PC = _IX; break;
1815 case ld_sp_hl: _SP = _IX; iWSAdjust++; break;
1816 case ld_sp_word: z80.SP.b.l = read_mem(_PC++); z80.SP.b.h = read_mem(_PC++); break;
1817 case nop: break;
1818 case or_a: OR(_A); break;
1819 case or_b: OR(_B); break;
1820 case or_byte: OR(read_mem(_PC++)); break;
1821 case or_c: OR(_C); break;
1822 case or_d: OR(_D); break;
1823 case or_e: OR(_E); break;
1824 case or_h: OR(_IXh); break;
1825 case or_l: OR(_IXl); break;
1826 case or_mhl: { signed char o = read_mem(_PC++); OR(read_mem(_IX+o)); } break;
1827 case outa: { z80_wait_states iCycleCount = Oa_;} { reg_pair p; p.b.l = read_mem(_PC++); p.b.h = _A; z80_OUT_handler(p, _A); } break;
1828 case pfx_cb: z80_pfx_ddcb(); break;
1829 case pfx_dd: z80_pfx_dd(); break;
1830 case pfx_ed: z80_pfx_ed(); break;
1831 case pfx_fd: z80_pfx_fd(); break;
1832 case pop_af: POP(AF); break;
1833 case pop_bc: POP(BC); break;
1834 case pop_de: POP(DE); break;
1835 case pop_hl: POP(IX); break;
1836 case push_af: PUSH(AF); break;
1837 case push_bc: PUSH(BC); break;
1838 case push_de: PUSH(DE); break;
1839 case push_hl: PUSH(IX); break;
1840 case ret: RET; break;
1841 case ret_c: if (_F & Cflag) { iCycleCount += cc_ex[bOpCode]; RET } else { iWSAdjust++; } ; break;
1842 case ret_m: if (_F & Sflag) { iCycleCount += cc_ex[bOpCode]; RET } else { iWSAdjust++; } ; break;
1843 case ret_nc: if (!(_F & Cflag)) { iCycleCount += cc_ex[bOpCode]; RET } else { iWSAdjust++; } ; break;
1844 case ret_nz: if (!(_F & Zflag)) { iCycleCount += cc_ex[bOpCode]; RET } else { iWSAdjust++; } ; break;
1845 case ret_p: if (!(_F & Sflag)) { iCycleCount += cc_ex[bOpCode]; RET } else { iWSAdjust++; } ; break;
1846 case ret_pe: if (_F & Pflag) { iCycleCount += cc_ex[bOpCode]; RET } else { iWSAdjust++; } ; break;
1847 case ret_po: if (!(_F & Pflag)) { iCycleCount += cc_ex[bOpCode]; RET } else { iWSAdjust++; } ; break;
1848 case ret_z: if (_F & Zflag) { iCycleCount += cc_ex[bOpCode]; RET } else { iWSAdjust++; } ; break;
1849 case rla: RLA; break;
1850 case rlca: RLCA; break;
1851 case rra: RRA; break;
1852 case rrca: RRCA; break;
1853 case rst00: RST(0x0000); break;
1854 case rst08: RST(0x0008); break;
1855 case rst10: RST(0x0010); break;
1856 case rst18: RST(0x0018); break;
1857 case rst20: RST(0x0020); break;
1858 case rst28: RST(0x0028); break;
1859 case rst30: RST(0x0030); break;
1860 case rst38: RST(0x0038); break;
1861 case sbc_a: SBC(_A); break;
1862 case sbc_b: SBC(_B); break;
1863 case sbc_byte: SBC(read_mem(_PC++)); break;
1864 case sbc_c: SBC(_C); break;
1865 case sbc_d: SBC(_D); break;
1866 case sbc_e: SBC(_E); break;
1867 case sbc_h: SBC(_IXh); break;
1868 case sbc_l: SBC(_IXl); break;
1869 case sbc_mhl: { signed char o = read_mem(_PC++); SBC(read_mem(_IX+o)); } break;
1870 case scf: _F = (_F & (Sflag | Zflag | Pflag)) | Cflag | (_A & Xflags); break;
1871 case sub_a: SUB(_A); break;
1872 case sub_b: SUB(_B); break;
1873 case sub_byte: SUB(read_mem(_PC++)); break;
1874 case sub_c: SUB(_C); break;
1875 case sub_d: SUB(_D); break;
1876 case sub_e: SUB(_E); break;
1877 case sub_h: SUB(_IXh); break;
1878 case sub_l: SUB(_IXl); break;
1879 case sub_mhl: { signed char o = read_mem(_PC++); SUB(read_mem(_IX+o)); } break;
1880 case xor_a: XOR(_A); break;
1881 case xor_b: XOR(_B); break;
1882 case xor_byte: XOR(read_mem(_PC++)); break;
1883 case xor_c: XOR(_C); break;
1884 case xor_d: XOR(_D); break;
1885 case xor_e: XOR(_E); break;
1886 case xor_h: XOR(_IXh); break;
1887 case xor_l: XOR(_IXl); break;
1888 case xor_mhl: { signed char o = read_mem(_PC++); XOR(read_mem(_IX+o)); } break;
1889 }
1890 }
1891
1892
1893
z80_pfx_ddcb(void)1894 void z80_pfx_ddcb(void)
1895 {
1896 signed char o;
1897 uint8_t bOpCode;
1898
1899 o = read_mem(_PC++); // offset
1900 bOpCode = read_mem(_PC++);
1901 iCycleCount += cc_xycb[bOpCode];
1902 switch(bOpCode)
1903 {
1904 case bit0_a: BIT_XY(0, read_mem(_IX+o)); break;
1905 case bit0_b: BIT_XY(0, read_mem(_IX+o)); break;
1906 case bit0_c: BIT_XY(0, read_mem(_IX+o)); break;
1907 case bit0_d: BIT_XY(0, read_mem(_IX+o)); break;
1908 case bit0_e: BIT_XY(0, read_mem(_IX+o)); break;
1909 case bit0_h: BIT_XY(0, read_mem(_IX+o)); break;
1910 case bit0_l: BIT_XY(0, read_mem(_IX+o)); break;
1911 case bit0_mhl: BIT_XY(0, read_mem(_IX+o)); break;
1912 case bit1_a: BIT_XY(1, read_mem(_IX+o)); break;
1913 case bit1_b: BIT_XY(1, read_mem(_IX+o)); break;
1914 case bit1_c: BIT_XY(1, read_mem(_IX+o)); break;
1915 case bit1_d: BIT_XY(1, read_mem(_IX+o)); break;
1916 case bit1_e: BIT_XY(1, read_mem(_IX+o)); break;
1917 case bit1_h: BIT_XY(1, read_mem(_IX+o)); break;
1918 case bit1_l: BIT_XY(1, read_mem(_IX+o)); break;
1919 case bit1_mhl: BIT_XY(1, read_mem(_IX+o)); break;
1920 case bit2_a: BIT_XY(2, read_mem(_IX+o)); break;
1921 case bit2_b: BIT_XY(2, read_mem(_IX+o)); break;
1922 case bit2_c: BIT_XY(2, read_mem(_IX+o)); break;
1923 case bit2_d: BIT_XY(2, read_mem(_IX+o)); break;
1924 case bit2_e: BIT_XY(2, read_mem(_IX+o)); break;
1925 case bit2_h: BIT_XY(2, read_mem(_IX+o)); break;
1926 case bit2_l: BIT_XY(2, read_mem(_IX+o)); break;
1927 case bit2_mhl: BIT_XY(2, read_mem(_IX+o)); break;
1928 case bit3_a: BIT_XY(3, read_mem(_IX+o)); break;
1929 case bit3_b: BIT_XY(3, read_mem(_IX+o)); break;
1930 case bit3_c: BIT_XY(3, read_mem(_IX+o)); break;
1931 case bit3_d: BIT_XY(3, read_mem(_IX+o)); break;
1932 case bit3_e: BIT_XY(3, read_mem(_IX+o)); break;
1933 case bit3_h: BIT_XY(3, read_mem(_IX+o)); break;
1934 case bit3_l: BIT_XY(3, read_mem(_IX+o)); break;
1935 case bit3_mhl: BIT_XY(3, read_mem(_IX+o)); break;
1936 case bit4_a: BIT_XY(4, read_mem(_IX+o)); break;
1937 case bit4_b: BIT_XY(4, read_mem(_IX+o)); break;
1938 case bit4_c: BIT_XY(4, read_mem(_IX+o)); break;
1939 case bit4_d: BIT_XY(4, read_mem(_IX+o)); break;
1940 case bit4_e: BIT_XY(4, read_mem(_IX+o)); break;
1941 case bit4_h: BIT_XY(4, read_mem(_IX+o)); break;
1942 case bit4_l: BIT_XY(4, read_mem(_IX+o)); break;
1943 case bit4_mhl: BIT_XY(4, read_mem(_IX+o)); break;
1944 case bit5_a: BIT_XY(5, read_mem(_IX+o)); break;
1945 case bit5_b: BIT_XY(5, read_mem(_IX+o)); break;
1946 case bit5_c: BIT_XY(5, read_mem(_IX+o)); break;
1947 case bit5_d: BIT_XY(5, read_mem(_IX+o)); break;
1948 case bit5_e: BIT_XY(5, read_mem(_IX+o)); break;
1949 case bit5_h: BIT_XY(5, read_mem(_IX+o)); break;
1950 case bit5_l: BIT_XY(5, read_mem(_IX+o)); break;
1951 case bit5_mhl: BIT_XY(5, read_mem(_IX+o)); break;
1952 case bit6_a: BIT_XY(6, read_mem(_IX+o)); break;
1953 case bit6_b: BIT_XY(6, read_mem(_IX+o)); break;
1954 case bit6_c: BIT_XY(6, read_mem(_IX+o)); break;
1955 case bit6_d: BIT_XY(6, read_mem(_IX+o)); break;
1956 case bit6_e: BIT_XY(6, read_mem(_IX+o)); break;
1957 case bit6_h: BIT_XY(6, read_mem(_IX+o)); break;
1958 case bit6_l: BIT_XY(6, read_mem(_IX+o)); break;
1959 case bit6_mhl: BIT_XY(6, read_mem(_IX+o)); break;
1960 case bit7_a: BIT_XY(7, read_mem(_IX+o)); break;
1961 case bit7_b: BIT_XY(7, read_mem(_IX+o)); break;
1962 case bit7_c: BIT_XY(7, read_mem(_IX+o)); break;
1963 case bit7_d: BIT_XY(7, read_mem(_IX+o)); break;
1964 case bit7_e: BIT_XY(7, read_mem(_IX+o)); break;
1965 case bit7_h: BIT_XY(7, read_mem(_IX+o)); break;
1966 case bit7_l: BIT_XY(7, read_mem(_IX+o)); break;
1967 case bit7_mhl: BIT_XY(7, read_mem(_IX+o)); break;
1968 case res0_a: _A = read_mem(_IX+o); write_mem(_IX+o, _A = RES(0, _A)); break;
1969 case res0_b: _B = read_mem(_IX+o); write_mem(_IX+o, _B = RES(0, _B)); break;
1970 case res0_c: _C = read_mem(_IX+o); write_mem(_IX+o, _C = RES(0, _C)); break;
1971 case res0_d: _D = read_mem(_IX+o); write_mem(_IX+o, _D = RES(0, _D)); break;
1972 case res0_e: _E = read_mem(_IX+o); write_mem(_IX+o, _E = RES(0, _E)); break;
1973 case res0_h: _H = read_mem(_IX+o); write_mem(_IX+o, _H = RES(0, _H)); break;
1974 case res0_l: _L = read_mem(_IX+o); write_mem(_IX+o, _L = RES(0, _L)); break;
1975 case res0_mhl: { uint8_t b = read_mem(_IX+o); write_mem(_IX+o, RES(0, b)); } break;
1976 case res1_a: _A = read_mem(_IX+o); write_mem(_IX+o, _A = RES(1, _A)); break;
1977 case res1_b: _B = read_mem(_IX+o); write_mem(_IX+o, _B = RES(1, _B)); break;
1978 case res1_c: _C = read_mem(_IX+o); write_mem(_IX+o, _C = RES(1, _C)); break;
1979 case res1_d: _D = read_mem(_IX+o); write_mem(_IX+o, _D = RES(1, _D)); break;
1980 case res1_e: _E = read_mem(_IX+o); write_mem(_IX+o, _E = RES(1, _E)); break;
1981 case res1_h: _H = read_mem(_IX+o); write_mem(_IX+o, _H = RES(1, _H)); break;
1982 case res1_l: _L = read_mem(_IX+o); write_mem(_IX+o, _L = RES(1, _L)); break;
1983 case res1_mhl: { uint8_t b = read_mem(_IX+o); write_mem(_IX+o, RES(1, b)); } break;
1984 case res2_a: _A = read_mem(_IX+o); write_mem(_IX+o, _A = RES(2, _A)); break;
1985 case res2_b: _B = read_mem(_IX+o); write_mem(_IX+o, _B = RES(2, _B)); break;
1986 case res2_c: _C = read_mem(_IX+o); write_mem(_IX+o, _C = RES(2, _C)); break;
1987 case res2_d: _D = read_mem(_IX+o); write_mem(_IX+o, _D = RES(2, _D)); break;
1988 case res2_e: _E = read_mem(_IX+o); write_mem(_IX+o, _E = RES(2, _E)); break;
1989 case res2_h: _H = read_mem(_IX+o); write_mem(_IX+o, _H = RES(2, _H)); break;
1990 case res2_l: _L = read_mem(_IX+o); write_mem(_IX+o, _L = RES(2, _L)); break;
1991 case res2_mhl: { uint8_t b = read_mem(_IX+o); write_mem(_IX+o, RES(2, b)); } break;
1992 case res3_a: _A = read_mem(_IX+o); write_mem(_IX+o, _A = RES(3, _A)); break;
1993 case res3_b: _B = read_mem(_IX+o); write_mem(_IX+o, _B = RES(3, _B)); break;
1994 case res3_c: _C = read_mem(_IX+o); write_mem(_IX+o, _C = RES(3, _C)); break;
1995 case res3_d: _D = read_mem(_IX+o); write_mem(_IX+o, _D = RES(3, _D)); break;
1996 case res3_e: _E = read_mem(_IX+o); write_mem(_IX+o, _E = RES(3, _E)); break;
1997 case res3_h: _H = read_mem(_IX+o); write_mem(_IX+o, _H = RES(3, _H)); break;
1998 case res3_l: _L = read_mem(_IX+o); write_mem(_IX+o, _L = RES(3, _L)); break;
1999 case res3_mhl: { uint8_t b = read_mem(_IX+o); write_mem(_IX+o, RES(3, b)); } break;
2000 case res4_a: _A = read_mem(_IX+o); write_mem(_IX+o, _A = RES(4, _A)); break;
2001 case res4_b: _B = read_mem(_IX+o); write_mem(_IX+o, _B = RES(4, _B)); break;
2002 case res4_c: _C = read_mem(_IX+o); write_mem(_IX+o, _C = RES(4, _C)); break;
2003 case res4_d: _D = read_mem(_IX+o); write_mem(_IX+o, _D = RES(4, _D)); break;
2004 case res4_e: _E = read_mem(_IX+o); write_mem(_IX+o, _E = RES(4, _E)); break;
2005 case res4_h: _H = read_mem(_IX+o); write_mem(_IX+o, _H = RES(4, _H)); break;
2006 case res4_l: _L = read_mem(_IX+o); write_mem(_IX+o, _L = RES(4, _L)); break;
2007 case res4_mhl: { uint8_t b = read_mem(_IX+o); write_mem(_IX+o, RES(4, b)); } break;
2008 case res5_a: _A = read_mem(_IX+o); write_mem(_IX+o, _A = RES(5, _A)); break;
2009 case res5_b: _B = read_mem(_IX+o); write_mem(_IX+o, _B = RES(5, _B)); break;
2010 case res5_c: _C = read_mem(_IX+o); write_mem(_IX+o, _C = RES(5, _C)); break;
2011 case res5_d: _D = read_mem(_IX+o); write_mem(_IX+o, _D = RES(5, _D)); break;
2012 case res5_e: _E = read_mem(_IX+o); write_mem(_IX+o, _E = RES(5, _E)); break;
2013 case res5_h: _H = read_mem(_IX+o); write_mem(_IX+o, _H = RES(5, _H)); break;
2014 case res5_l: _L = read_mem(_IX+o); write_mem(_IX+o, _L = RES(5, _L)); break;
2015 case res5_mhl: { uint8_t b = read_mem(_IX+o); write_mem(_IX+o, RES(5, b)); } break;
2016 case res6_a: _A = read_mem(_IX+o); write_mem(_IX+o, _A = RES(6, _A)); break;
2017 case res6_b: _B = read_mem(_IX+o); write_mem(_IX+o, _B = RES(6, _B)); break;
2018 case res6_c: _C = read_mem(_IX+o); write_mem(_IX+o, _C = RES(6, _C)); break;
2019 case res6_d: _D = read_mem(_IX+o); write_mem(_IX+o, _D = RES(6, _D)); break;
2020 case res6_e: _E = read_mem(_IX+o); write_mem(_IX+o, _E = RES(6, _E)); break;
2021 case res6_h: _H = read_mem(_IX+o); write_mem(_IX+o, _H = RES(6, _H)); break;
2022 case res6_l: _L = read_mem(_IX+o); write_mem(_IX+o, _L = RES(6, _L)); break;
2023 case res6_mhl: { uint8_t b = read_mem(_IX+o); write_mem(_IX+o, RES(6, b)); } break;
2024 case res7_a: _A = read_mem(_IX+o); write_mem(_IX+o, _A = RES(7, _A)); break;
2025 case res7_b: _B = read_mem(_IX+o); write_mem(_IX+o, _B = RES(7, _B)); break;
2026 case res7_c: _C = read_mem(_IX+o); write_mem(_IX+o, _C = RES(7, _C)); break;
2027 case res7_d: _D = read_mem(_IX+o); write_mem(_IX+o, _D = RES(7, _D)); break;
2028 case res7_e: _E = read_mem(_IX+o); write_mem(_IX+o, _E = RES(7, _E)); break;
2029 case res7_h: _H = read_mem(_IX+o); write_mem(_IX+o, _H = RES(7, _H)); break;
2030 case res7_l: _L = read_mem(_IX+o); write_mem(_IX+o, _L = RES(7, _L)); break;
2031 case res7_mhl: { uint8_t b = read_mem(_IX+o); write_mem(_IX+o, RES(7, b)); } break;
2032 case rlc_a: _A = read_mem(_IX+o); _A = RLC(_A); write_mem(_IX+o, _A); break;
2033 case rlc_b: _B = read_mem(_IX+o); _B = RLC(_B); write_mem(_IX+o, _B); break;
2034 case rlc_c: _C = read_mem(_IX+o); _C = RLC(_C); write_mem(_IX+o, _C); break;
2035 case rlc_d: _D = read_mem(_IX+o); _D = RLC(_D); write_mem(_IX+o, _D); break;
2036 case rlc_e: _E = read_mem(_IX+o); _E = RLC(_E); write_mem(_IX+o, _E); break;
2037 case rlc_h: _H = read_mem(_IX+o); _H = RLC(_H); write_mem(_IX+o, _H); break;
2038 case rlc_l: _L = read_mem(_IX+o); _L = RLC(_L); write_mem(_IX+o, _L); break;
2039 case rlc_mhl: { uint8_t b = read_mem(_IX+o); write_mem(_IX+o, RLC(b)); } break;
2040 case rl_a: _A = read_mem(_IX+o); _A = RL(_A); write_mem(_IX+o, _A); break;
2041 case rl_b: _B = read_mem(_IX+o); _B = RL(_B); write_mem(_IX+o, _B); break;
2042 case rl_c: _C = read_mem(_IX+o); _C = RL(_C); write_mem(_IX+o, _C); break;
2043 case rl_d: _D = read_mem(_IX+o); _D = RL(_D); write_mem(_IX+o, _D); break;
2044 case rl_e: _E = read_mem(_IX+o); _E = RL(_E); write_mem(_IX+o, _E); break;
2045 case rl_h: _H = read_mem(_IX+o); _H = RL(_H); write_mem(_IX+o, _H); break;
2046 case rl_l: _L = read_mem(_IX+o); _L = RL(_L); write_mem(_IX+o, _L); break;
2047 case rl_mhl: { uint8_t b = read_mem(_IX+o); write_mem(_IX+o, RL(b)); } break;
2048 case rrc_a: _A = read_mem(_IX+o); _A = RRC(_A); write_mem(_IX+o, _A); break;
2049 case rrc_b: _B = read_mem(_IX+o); _B = RRC(_B); write_mem(_IX+o, _B); break;
2050 case rrc_c: _C = read_mem(_IX+o); _C = RRC(_C); write_mem(_IX+o, _C); break;
2051 case rrc_d: _D = read_mem(_IX+o); _D = RRC(_D); write_mem(_IX+o, _D); break;
2052 case rrc_e: _E = read_mem(_IX+o); _E = RRC(_E); write_mem(_IX+o, _E); break;
2053 case rrc_h: _H = read_mem(_IX+o); _H = RRC(_H); write_mem(_IX+o, _H); break;
2054 case rrc_l: _L = read_mem(_IX+o); _L = RRC(_L); write_mem(_IX+o, _L); break;
2055 case rrc_mhl: { uint8_t b = read_mem(_IX+o); write_mem(_IX+o, RRC(b)); } break;
2056 case rr_a: _A = read_mem(_IX+o); _A = RR(_A); write_mem(_IX+o, _A); break;
2057 case rr_b: _B = read_mem(_IX+o); _B = RR(_B); write_mem(_IX+o, _B); break;
2058 case rr_c: _C = read_mem(_IX+o); _C = RR(_C); write_mem(_IX+o, _C); break;
2059 case rr_d: _D = read_mem(_IX+o); _D = RR(_D); write_mem(_IX+o, _D); break;
2060 case rr_e: _E = read_mem(_IX+o); _E = RR(_E); write_mem(_IX+o, _E); break;
2061 case rr_h: _H = read_mem(_IX+o); _H = RR(_H); write_mem(_IX+o, _H); break;
2062 case rr_l: _L = read_mem(_IX+o); _L = RR(_L); write_mem(_IX+o, _L); break;
2063 case rr_mhl: { uint8_t b = read_mem(_IX+o); write_mem(_IX+o, RR(b)); } break;
2064 case set0_a: _A = read_mem(_IX+o); write_mem(_IX+o, _A = SET(0, _A)); break;
2065 case set0_b: _B = read_mem(_IX+o); write_mem(_IX+o, _B = SET(0, _B)); break;
2066 case set0_c: _C = read_mem(_IX+o); write_mem(_IX+o, _C = SET(0, _C)); break;
2067 case set0_d: _D = read_mem(_IX+o); write_mem(_IX+o, _D = SET(0, _D)); break;
2068 case set0_e: _E = read_mem(_IX+o); write_mem(_IX+o, _E = SET(0, _E)); break;
2069 case set0_h: _H = read_mem(_IX+o); write_mem(_IX+o, _H = SET(0, _H)); break;
2070 case set0_l: _L = read_mem(_IX+o); write_mem(_IX+o, _L = SET(0, _L)); break;
2071 case set0_mhl: { uint8_t b = read_mem(_IX+o); write_mem(_IX+o, SET(0, b)); } break;
2072 case set1_a: _A = read_mem(_IX+o); write_mem(_IX+o, _A = SET(1, _A)); break;
2073 case set1_b: _B = read_mem(_IX+o); write_mem(_IX+o, _B = SET(1, _B)); break;
2074 case set1_c: _C = read_mem(_IX+o); write_mem(_IX+o, _C = SET(1, _C)); break;
2075 case set1_d: _D = read_mem(_IX+o); write_mem(_IX+o, _D = SET(1, _D)); break;
2076 case set1_e: _E = read_mem(_IX+o); write_mem(_IX+o, _E = SET(1, _E)); break;
2077 case set1_h: _H = read_mem(_IX+o); write_mem(_IX+o, _H = SET(1, _H)); break;
2078 case set1_l: _L = read_mem(_IX+o); write_mem(_IX+o, _L = SET(1, _L)); break;
2079 case set1_mhl: { uint8_t b = read_mem(_IX+o); write_mem(_IX+o, SET(1, b)); } break;
2080 case set2_a: _A = read_mem(_IX+o); write_mem(_IX+o, _A = SET(2, _A)); break;
2081 case set2_b: _B = read_mem(_IX+o); write_mem(_IX+o, _B = SET(2, _B)); break;
2082 case set2_c: _C = read_mem(_IX+o); write_mem(_IX+o, _C = SET(2, _C)); break;
2083 case set2_d: _D = read_mem(_IX+o); write_mem(_IX+o, _D = SET(2, _D)); break;
2084 case set2_e: _E = read_mem(_IX+o); write_mem(_IX+o, _E = SET(2, _E)); break;
2085 case set2_h: _H = read_mem(_IX+o); write_mem(_IX+o, _H = SET(2, _H)); break;
2086 case set2_l: _L = read_mem(_IX+o); write_mem(_IX+o, _L = SET(2, _L)); break;
2087 case set2_mhl: { uint8_t b = read_mem(_IX+o); write_mem(_IX+o, SET(2, b)); } break;
2088 case set3_a: _A = read_mem(_IX+o); write_mem(_IX+o, _A = SET(3, _A)); break;
2089 case set3_b: _B = read_mem(_IX+o); write_mem(_IX+o, _B = SET(3, _B)); break;
2090 case set3_c: _C = read_mem(_IX+o); write_mem(_IX+o, _C = SET(3, _C)); break;
2091 case set3_d: _D = read_mem(_IX+o); write_mem(_IX+o, _D = SET(3, _D)); break;
2092 case set3_e: _E = read_mem(_IX+o); write_mem(_IX+o, _E = SET(3, _E)); break;
2093 case set3_h: _H = read_mem(_IX+o); write_mem(_IX+o, _H = SET(3, _H)); break;
2094 case set3_l: _L = read_mem(_IX+o); write_mem(_IX+o, _L = SET(3, _L)); break;
2095 case set3_mhl: { uint8_t b = read_mem(_IX+o); write_mem(_IX+o, SET(3, b)); } break;
2096 case set4_a: _A = read_mem(_IX+o); write_mem(_IX+o, _A = SET(4, _A)); break;
2097 case set4_b: _B = read_mem(_IX+o); write_mem(_IX+o, _B = SET(4, _B)); break;
2098 case set4_c: _C = read_mem(_IX+o); write_mem(_IX+o, _C = SET(4, _C)); break;
2099 case set4_d: _D = read_mem(_IX+o); write_mem(_IX+o, _D = SET(4, _D)); break;
2100 case set4_e: _E = read_mem(_IX+o); write_mem(_IX+o, _E = SET(4, _E)); break;
2101 case set4_h: _H = read_mem(_IX+o); write_mem(_IX+o, _H = SET(4, _H)); break;
2102 case set4_l: _L = read_mem(_IX+o); write_mem(_IX+o, _L = SET(4, _L)); break;
2103 case set4_mhl: { uint8_t b = read_mem(_IX+o); write_mem(_IX+o, SET(4, b)); } break;
2104 case set5_a: _A = read_mem(_IX+o); write_mem(_IX+o, _A = SET(5, _A)); break;
2105 case set5_b: _B = read_mem(_IX+o); write_mem(_IX+o, _B = SET(5, _B)); break;
2106 case set5_c: _C = read_mem(_IX+o); write_mem(_IX+o, _C = SET(5, _C)); break;
2107 case set5_d: _D = read_mem(_IX+o); write_mem(_IX+o, _D = SET(5, _D)); break;
2108 case set5_e: _E = read_mem(_IX+o); write_mem(_IX+o, _E = SET(5, _E)); break;
2109 case set5_h: _H = read_mem(_IX+o); write_mem(_IX+o, _H = SET(5, _H)); break;
2110 case set5_l: _L = read_mem(_IX+o); write_mem(_IX+o, _L = SET(5, _L)); break;
2111 case set5_mhl: { uint8_t b = read_mem(_IX+o); write_mem(_IX+o, SET(5, b)); } break;
2112 case set6_a: _A = read_mem(_IX+o); write_mem(_IX+o, _A = SET(6, _A)); break;
2113 case set6_b: _B = read_mem(_IX+o); write_mem(_IX+o, _B = SET(6, _B)); break;
2114 case set6_c: _C = read_mem(_IX+o); write_mem(_IX+o, _C = SET(6, _C)); break;
2115 case set6_d: _D = read_mem(_IX+o); write_mem(_IX+o, _D = SET(6, _D)); break;
2116 case set6_e: _E = read_mem(_IX+o); write_mem(_IX+o, _E = SET(6, _E)); break;
2117 case set6_h: _H = read_mem(_IX+o); write_mem(_IX+o, _H = SET(6, _H)); break;
2118 case set6_l: _L = read_mem(_IX+o); write_mem(_IX+o, _L = SET(6, _L)); break;
2119 case set6_mhl: { uint8_t b = read_mem(_IX+o); write_mem(_IX+o, SET(6, b)); } break;
2120 case set7_a: _A = read_mem(_IX+o); write_mem(_IX+o, _A = SET(7, _A)); break;
2121 case set7_b: _B = read_mem(_IX+o); write_mem(_IX+o, _B = SET(7, _B)); break;
2122 case set7_c: _C = read_mem(_IX+o); write_mem(_IX+o, _C = SET(7, _C)); break;
2123 case set7_d: _D = read_mem(_IX+o); write_mem(_IX+o, _D = SET(7, _D)); break;
2124 case set7_e: _E = read_mem(_IX+o); write_mem(_IX+o, _E = SET(7, _E)); break;
2125 case set7_h: _H = read_mem(_IX+o); write_mem(_IX+o, _H = SET(7, _H)); break;
2126 case set7_l: _L = read_mem(_IX+o); write_mem(_IX+o, _L = SET(7, _L)); break;
2127 case set7_mhl: { uint8_t b = read_mem(_IX+o); write_mem(_IX+o, SET(7, b)); } break;
2128 case sla_a: _A = read_mem(_IX+o); _A = SLA(_A); write_mem(_IX+o, _A); break;
2129 case sla_b: _B = read_mem(_IX+o); _B = SLA(_B); write_mem(_IX+o, _B); break;
2130 case sla_c: _C = read_mem(_IX+o); _C = SLA(_C); write_mem(_IX+o, _C); break;
2131 case sla_d: _D = read_mem(_IX+o); _D = SLA(_D); write_mem(_IX+o, _D); break;
2132 case sla_e: _E = read_mem(_IX+o); _E = SLA(_E); write_mem(_IX+o, _E); break;
2133 case sla_h: _H = read_mem(_IX+o); _H = SLA(_H); write_mem(_IX+o, _H); break;
2134 case sla_l: _L = read_mem(_IX+o); _L = SLA(_L); write_mem(_IX+o, _L); break;
2135 case sla_mhl: { uint8_t b = read_mem(_IX+o); write_mem(_IX+o, SLA(b)); } break;
2136 case sll_a: _A = read_mem(_IX+o); _A = SLL(_A); write_mem(_IX+o, _A); break;
2137 case sll_b: _B = read_mem(_IX+o); _B = SLL(_B); write_mem(_IX+o, _B); break;
2138 case sll_c: _C = read_mem(_IX+o); _C = SLL(_C); write_mem(_IX+o, _C); break;
2139 case sll_d: _D = read_mem(_IX+o); _D = SLL(_D); write_mem(_IX+o, _D); break;
2140 case sll_e: _E = read_mem(_IX+o); _E = SLL(_E); write_mem(_IX+o, _E); break;
2141 case sll_h: _H = read_mem(_IX+o); _H = SLL(_H); write_mem(_IX+o, _H); break;
2142 case sll_l: _L = read_mem(_IX+o); _L = SLL(_L); write_mem(_IX+o, _L); break;
2143 case sll_mhl: { uint8_t b = read_mem(_IX+o); write_mem(_IX+o, SLL(b)); } break;
2144 case sra_a: _A = read_mem(_IX+o); _A = SRA(_A); write_mem(_IX+o, _A); break;
2145 case sra_b: _B = read_mem(_IX+o); _B = SRA(_B); write_mem(_IX+o, _B); break;
2146 case sra_c: _C = read_mem(_IX+o); _C = SRA(_C); write_mem(_IX+o, _C); break;
2147 case sra_d: _D = read_mem(_IX+o); _D = SRA(_D); write_mem(_IX+o, _D); break;
2148 case sra_e: _E = read_mem(_IX+o); _E = SRA(_E); write_mem(_IX+o, _E); break;
2149 case sra_h: _H = read_mem(_IX+o); _H = SRA(_H); write_mem(_IX+o, _H); break;
2150 case sra_l: _L = read_mem(_IX+o); _L = SRA(_L); write_mem(_IX+o, _L); break;
2151 case sra_mhl: { uint8_t b = read_mem(_IX+o); write_mem(_IX+o, SRA(b)); } break;
2152 case srl_a: _A = read_mem(_IX+o); _A = SRL(_A); write_mem(_IX+o, _A); break;
2153 case srl_b: _B = read_mem(_IX+o); _B = SRL(_B); write_mem(_IX+o, _B); break;
2154 case srl_c: _C = read_mem(_IX+o); _C = SRL(_C); write_mem(_IX+o, _C); break;
2155 case srl_d: _D = read_mem(_IX+o); _D = SRL(_D); write_mem(_IX+o, _D); break;
2156 case srl_e: _E = read_mem(_IX+o); _E = SRL(_E); write_mem(_IX+o, _E); break;
2157 case srl_h: _H = read_mem(_IX+o); _H = SRL(_H); write_mem(_IX+o, _H); break;
2158 case srl_l: _L = read_mem(_IX+o); _L = SRL(_L); write_mem(_IX+o, _L); break;
2159 case srl_mhl: { uint8_t b = read_mem(_IX+o); write_mem(_IX+o, SRL(b)); } break;
2160 }
2161 }
2162
2163
2164
z80_pfx_ed(void)2165 void z80_pfx_ed(void)
2166 {
2167 uint8_t bOpCode;
2168
2169 bOpCode = read_mem(_PC++);
2170 iCycleCount += cc_ed[bOpCode];
2171 _R++;
2172 switch(bOpCode)
2173 {
2174 case adc_hl_bc: ADC16(BC); break;
2175 case adc_hl_de: ADC16(DE); break;
2176 case adc_hl_hl: ADC16(HL); break;
2177 case adc_hl_sp: ADC16(SP); break;
2178 case cpd: CPD; break;
2179 case cpdr: CPDR; break;
2180 case cpi: CPI; break;
2181 case cpir: CPIR; break;
2182 case ed_00: break;
2183 case ed_01: break;
2184 case ed_02: break;
2185 case ed_03: break;
2186 case ed_04: break;
2187 case ed_05: break;
2188 case ed_06: break;
2189 case ed_07: break;
2190 case ed_08: break;
2191 case ed_09: break;
2192 case ed_0a: break;
2193 case ed_0b: break;
2194 case ed_0c: break;
2195 case ed_0d: break;
2196 case ed_0e: break;
2197 case ed_0f: break;
2198 case ed_10: break;
2199 case ed_11: break;
2200 case ed_12: break;
2201 case ed_13: break;
2202 case ed_14: break;
2203 case ed_15: break;
2204 case ed_16: break;
2205 case ed_17: break;
2206 case ed_18: break;
2207 case ed_19: break;
2208 case ed_1a: break;
2209 case ed_1b: break;
2210 case ed_1c: break;
2211 case ed_1d: break;
2212 case ed_1e: break;
2213 case ed_1f: break;
2214 case ed_20: break;
2215 case ed_21: break;
2216 case ed_22: break;
2217 case ed_23: break;
2218 case ed_24: break;
2219 case ed_25: break;
2220 case ed_26: break;
2221 case ed_27: break;
2222 case ed_28: break;
2223 case ed_29: break;
2224 case ed_2a: break;
2225 case ed_2b: break;
2226 case ed_2c: break;
2227 case ed_2d: break;
2228 case ed_2e: break;
2229 case ed_2f: break;
2230 case ed_30: break;
2231 case ed_31: break;
2232 case ed_32: break;
2233 case ed_33: break;
2234 case ed_34: break;
2235 case ed_35: break;
2236 case ed_36: break;
2237 case ed_37: break;
2238 case ed_38: break;
2239 case ed_39: break;
2240 case ed_3a: break;
2241 case ed_3b: break;
2242 case ed_3c: break;
2243 case ed_3d: break;
2244 case ed_3e: break;
2245 case ed_3f: break;
2246 case ed_77: break;
2247 case ed_7f: break;
2248 case ed_80: break;
2249 case ed_81: break;
2250 case ed_82: break;
2251 case ed_83: break;
2252 case ed_84: break;
2253 case ed_85: break;
2254 case ed_86: break;
2255 case ed_87: break;
2256 case ed_88: break;
2257 case ed_89: break;
2258 case ed_8a: break;
2259 case ed_8b: break;
2260 case ed_8c: break;
2261 case ed_8d: break;
2262 case ed_8e: break;
2263 case ed_8f: break;
2264 case ed_90: break;
2265 case ed_91: break;
2266 case ed_92: break;
2267 case ed_93: break;
2268 case ed_94: break;
2269 case ed_95: break;
2270 case ed_96: break;
2271 case ed_97: break;
2272 case ed_98: break;
2273 case ed_99: break;
2274 case ed_9a: break;
2275 case ed_9b: break;
2276 case ed_9c: break;
2277 case ed_9d: break;
2278 case ed_9e: break;
2279 case ed_9f: break;
2280 case ed_a4: break;
2281 case ed_a5: break;
2282 case ed_a6: break;
2283 case ed_a7: break;
2284 case ed_ac: break;
2285 case ed_ad: break;
2286 case ed_ae: break;
2287 case ed_af: break;
2288 case ed_b4: break;
2289 case ed_b5: break;
2290 case ed_b6: break;
2291 case ed_b7: break;
2292 case ed_bc: break;
2293 case ed_bd: break;
2294 case ed_be: break;
2295 case ed_bf: break;
2296 case ed_c0: break;
2297 case ed_c1: break;
2298 case ed_c2: break;
2299 case ed_c3: break;
2300 case ed_c4: break;
2301 case ed_c5: break;
2302 case ed_c6: break;
2303 case ed_c7: break;
2304 case ed_c8: break;
2305 case ed_c9: break;
2306 case ed_ca: break;
2307 case ed_cb: break;
2308 case ed_cc: break;
2309 case ed_cd: break;
2310 case ed_ce: break;
2311 case ed_cf: break;
2312 case ed_d0: break;
2313 case ed_d1: break;
2314 case ed_d2: break;
2315 case ed_d3: break;
2316 case ed_d4: break;
2317 case ed_d5: break;
2318 case ed_d6: break;
2319 case ed_d7: break;
2320 case ed_d8: break;
2321 case ed_d9: break;
2322 case ed_da: break;
2323 case ed_db: break;
2324 case ed_dc: break;
2325 case ed_dd: break;
2326 case ed_de: break;
2327 case ed_df: break;
2328 case ed_e0: break;
2329 case ed_e1: break;
2330 case ed_e2: break;
2331 case ed_e3: break;
2332 case ed_e4: break;
2333 case ed_e5: break;
2334 case ed_e6: break;
2335 case ed_e7: break;
2336 case ed_e8: break;
2337 case ed_e9: break;
2338 case ed_ea: break;
2339 case ed_eb: break;
2340 case ed_ec: break;
2341 case ed_ed: break;
2342 case ed_ee: break;
2343 case ed_ef: break;
2344 case ed_f0: break;
2345 case ed_f1: break;
2346 case ed_f2: break;
2347 case ed_f3: break;
2348 case ed_f4: break;
2349 case ed_f5: break;
2350 case ed_f6: break;
2351 case ed_f7: break;
2352 case ed_f8: break;
2353 case ed_f9: break;
2354 case ed_fa: break;
2355 case ed_fb: break;
2356 case ed_fc: break;
2357 case ed_fd: break;
2358 case ed_fe: break;
2359 case ed_ff: break;
2360 case im_0: _IM = 0; break;
2361 case im_0_1: _IM = 0; break;
2362 case im_0_2: _IM = 0; break;
2363 case im_0_3: _IM = 0; break;
2364 case im_1: _IM = 1; break;
2365 case im_1_1: _IM = 1; break;
2366 case im_2: _IM = 2; break;
2367 case im_2_1: _IM = 2; break;
2368 case ind: { z80_wait_states iCycleCount = Iy_;} IND; break;
2369 case indr: { z80_wait_states iCycleCount = Iy_;} INDR; break;
2370 case ini: { z80_wait_states iCycleCount = Iy_;} INI; break;
2371 case inir: { z80_wait_states iCycleCount = Iy_;} INIR; break;
2372 case in_0_c: { z80_wait_states iCycleCount = Ix_;} { uint8_t res = z80_IN_handler(z80.BC); _F = (_F & Cflag) | SZP[res]; } break;
2373 case in_a_c: { z80_wait_states iCycleCount = Ix_;} _A = z80_IN_handler(z80.BC); _F = (_F & Cflag) | SZP[_A]; break;
2374 case in_b_c: { z80_wait_states iCycleCount = Ix_;} _B = z80_IN_handler(z80.BC); _F = (_F & Cflag) | SZP[_B]; break;
2375 case in_c_c: { z80_wait_states iCycleCount = Ix_;} _C = z80_IN_handler(z80.BC); _F = (_F & Cflag) | SZP[_C]; break;
2376 case in_d_c: { z80_wait_states iCycleCount = Ix_;} _D = z80_IN_handler(z80.BC); _F = (_F & Cflag) | SZP[_D]; break;
2377 case in_e_c: { z80_wait_states iCycleCount = Ix_;} _E = z80_IN_handler(z80.BC); _F = (_F & Cflag) | SZP[_E]; break;
2378 case in_h_c: { z80_wait_states iCycleCount = Ix_;} _H = z80_IN_handler(z80.BC); _F = (_F & Cflag) | SZP[_H]; break;
2379 case in_l_c: { z80_wait_states iCycleCount = Ix_;} _L = z80_IN_handler(z80.BC); _F = (_F & Cflag) | SZP[_L]; break;
2380 case ldd: LDD; iWSAdjust++; break;
2381 case lddr: LDDR; iWSAdjust++; break;
2382 case ldi: LDI; iWSAdjust++; break;
2383 case ldir: LDIR; iWSAdjust++; break;
2384 case ld_a_i: _A = _I; _F = (_F & Cflag) | SZ[_A] | _IFF2; iWSAdjust++; break;
2385 case ld_a_r: _A = (_R & 0x7f) | _Rb7; _F = (_F & Cflag) | SZ[_A] | _IFF2; iWSAdjust++; break;
2386 case ld_EDbc_mword: LD16_MEM(BC); break;
2387 case ld_EDde_mword: LD16_MEM(DE); break;
2388 case ld_EDhl_mword: LD16_MEM(HL); break;
2389 case ld_EDmword_bc: LDMEM_16(BC); break;
2390 case ld_EDmword_de: LDMEM_16(DE); break;
2391 case ld_EDmword_hl: LDMEM_16(HL); break;
2392 case ld_EDmword_sp: LDMEM_16(SP); break;
2393 case ld_EDsp_mword: LD16_MEM(SP); break;
2394 case ld_i_a: _I = _A; iWSAdjust++; break;
2395 case ld_r_a: _R = _A; _Rb7 = _A & 0x80; iWSAdjust++; break;
2396 case neg: NEG; break;
2397 case neg_1: NEG; break;
2398 case neg_2: NEG; break;
2399 case neg_3: NEG; break;
2400 case neg_4: NEG; break;
2401 case neg_5: NEG; break;
2402 case neg_6: NEG; break;
2403 case neg_7: NEG; break;
2404 case otdr: { z80_wait_states iCycleCount = Oy_;} OTDR; break;
2405 case otir: { z80_wait_states iCycleCount = Oy_;} OTIR; break;
2406 case outd: { z80_wait_states iCycleCount = Oy_;} OUTD; break;
2407 case outi: { z80_wait_states iCycleCount = Oy_;} OUTI; break;
2408 case out_c_0: { z80_wait_states iCycleCount = Ox_;} z80_OUT_handler(z80.BC, 0); break;
2409 case out_c_a: { z80_wait_states iCycleCount = Ox_;} z80_OUT_handler(z80.BC, _A); break;
2410 case out_c_b: { z80_wait_states iCycleCount = Ox_;} z80_OUT_handler(z80.BC, _B); break;
2411 case out_c_c: { z80_wait_states iCycleCount = Ox_;} z80_OUT_handler(z80.BC, _C); break;
2412 case out_c_d: { z80_wait_states iCycleCount = Ox_;} z80_OUT_handler(z80.BC, _D); break;
2413 case out_c_e: { z80_wait_states iCycleCount = Ox_;} z80_OUT_handler(z80.BC, _E); break;
2414 case out_c_h: { z80_wait_states iCycleCount = Ox_;} z80_OUT_handler(z80.BC, _H); break;
2415 case out_c_l: { z80_wait_states iCycleCount = Ox_;} z80_OUT_handler(z80.BC, _L); break;
2416 case reti: _IFF1 = _IFF2; RET; break;
2417 case reti_1: _IFF1 = _IFF2; RET; break;
2418 case reti_2: _IFF1 = _IFF2; RET; break;
2419 case reti_3: _IFF1 = _IFF2; RET; break;
2420 case retn: _IFF1 = _IFF2; RET; break;
2421 case retn_1: _IFF1 = _IFF2; RET; break;
2422 case retn_2: _IFF1 = _IFF2; RET; break;
2423 case retn_3: _IFF1 = _IFF2; RET; break;
2424 case rld: RLD; break;
2425 case rrd: RRD; break;
2426 case sbc_hl_bc: SBC16(BC); break;
2427 case sbc_hl_de: SBC16(DE); break;
2428 case sbc_hl_hl: SBC16(HL); break;
2429 case sbc_hl_sp: SBC16(SP); break;
2430 }
2431 }
2432
2433
2434
z80_pfx_fd(void)2435 void z80_pfx_fd(void)
2436 {
2437 uint8_t bOpCode;
2438
2439 bOpCode = read_mem(_PC++);
2440 iCycleCount += cc_xy[bOpCode];
2441 _R++;
2442 switch(bOpCode)
2443 {
2444 case adc_a: ADC(_A); break;
2445 case adc_b: ADC(_B); break;
2446 case adc_byte: ADC(read_mem(_PC++)); break;
2447 case adc_c: ADC(_C); break;
2448 case adc_d: ADC(_D); break;
2449 case adc_e: ADC(_E); break;
2450 case adc_h: ADC(_IYh); break;
2451 case adc_l: ADC(_IYl); break;
2452 case adc_mhl: { signed char o = read_mem(_PC++); ADC(read_mem(_IY+o)); } break;
2453 case add_a: ADD(_A); break;
2454 case add_b: ADD(_B); break;
2455 case add_byte: ADD(read_mem(_PC++)); break;
2456 case add_c: ADD(_C); break;
2457 case add_d: ADD(_D); break;
2458 case add_e: ADD(_E); break;
2459 case add_h: ADD(_IYh); break;
2460 case add_hl_bc: ADD16(IY, BC); break;
2461 case add_hl_de: ADD16(IY, DE); break;
2462 case add_hl_hl: ADD16(IY, IY); break;
2463 case add_hl_sp: ADD16(IY, SP); break;
2464 case add_l: ADD(_IYl); break;
2465 case add_mhl: { signed char o = read_mem(_PC++); ADD(read_mem(_IY+o)); } break;
2466 case and_a: AND(_A); break;
2467 case and_b: AND(_B); break;
2468 case and_byte: AND(read_mem(_PC++)); break;
2469 case and_c: AND(_C); break;
2470 case and_d: AND(_D); break;
2471 case and_e: AND(_E); break;
2472 case and_h: AND(_IYh); break;
2473 case and_l: AND(_IYl); break;
2474 case and_mhl: { signed char o = read_mem(_PC++); AND(read_mem(_IY+o)); } break;
2475 case call: CALL; break;
2476 case call_c: if (_F & Cflag) { iCycleCount += cc_ex[bOpCode]; CALL } else { _PC += 2; } break;
2477 case call_m: if (_F & Sflag) { iCycleCount += cc_ex[bOpCode]; CALL } else { _PC += 2; } break;
2478 case call_nc: if (!(_F & Cflag)) { iCycleCount += cc_ex[bOpCode]; CALL } else { _PC += 2; } break;
2479 case call_nz: if (!(_F & Zflag)) { iCycleCount += cc_ex[bOpCode]; CALL } else { _PC += 2; } break;
2480 case call_p: if (!(_F & Sflag)) { iCycleCount += cc_ex[bOpCode]; CALL } else { _PC += 2; } break;
2481 case call_pe: if (_F & Pflag) { iCycleCount += cc_ex[bOpCode]; CALL } else { _PC += 2; } break;
2482 case call_po: if (!(_F & Pflag)) { iCycleCount += cc_ex[bOpCode]; CALL } else { _PC += 2; } break;
2483 case call_z: if (_F & Zflag) { iCycleCount += cc_ex[bOpCode]; CALL } else { _PC += 2; } break;
2484 case ccf: _F = ((_F & (Sflag | Zflag | Pflag | Cflag)) | ((_F & CF) << 4) | (_A & Xflags)) ^ CF; break;
2485 case cpl: _A ^= 0xff; _F = (_F & (Sflag | Zflag | Pflag | Cflag)) | Hflag | Nflag | (_A & Xflags); break;
2486 case cp_a: CP(_A); break;
2487 case cp_b: CP(_B); break;
2488 case cp_byte: CP(read_mem(_PC++)); break;
2489 case cp_c: CP(_C); break;
2490 case cp_d: CP(_D); break;
2491 case cp_e: CP(_E); break;
2492 case cp_h: CP(_IYh); break;
2493 case cp_l: CP(_IYl); break;
2494 case cp_mhl: { signed char o = read_mem(_PC++); CP(read_mem(_IY+o)); } break;
2495 case daa: DAA; break;
2496 case dec_a: DEC(_A); break;
2497 case dec_b: DEC(_B); break;
2498 case dec_bc: _BC--; iWSAdjust++; break;
2499 case dec_c: DEC(_C); break;
2500 case dec_d: DEC(_D); break;
2501 case dec_de: _DE--; iWSAdjust++; break;
2502 case dec_e: DEC(_E); break;
2503 case dec_h: DEC(_IYh); break;
2504 case dec_hl: _IY--; iWSAdjust++; break;
2505 case dec_l: DEC(_IYl); break;
2506 case dec_mhl: { signed char o = read_mem(_PC++); uint8_t b = read_mem(_IY+o); DEC(b); write_mem(_IY+o, b); } break;
2507 case dec_sp: _SP--; iWSAdjust++; break;
2508 case di: _IFF1 = _IFF2 = 0; z80.EI_issued = 0; break;
2509 case djnz: if (--_B) { iCycleCount += cc_ex[bOpCode]; JR } else { _PC++; } break;
2510 case ei: z80.EI_issued = 2; break;
2511 case exx: EXX; break;
2512 case ex_af_af: EX(z80.AF, z80.AFx); break;
2513 case ex_de_hl: EX(z80.DE, z80.HL); break;
2514 case ex_msp_hl: EX_SP(IY); iWSAdjust++; break;
2515 case halt: _HALT = 1; _PC--; break;
2516 case ina: { z80_wait_states iCycleCount = Ia_;} { reg_pair p; p.b.l = read_mem(_PC++); p.b.h = _A; _A = z80_IN_handler(p); } break;
2517 case inc_a: INC(_A); break;
2518 case inc_b: INC(_B); break;
2519 case inc_bc: _BC++; iWSAdjust++; break;
2520 case inc_c: INC(_C); break;
2521 case inc_d: INC(_D); break;
2522 case inc_de: _DE++; iWSAdjust++; break;
2523 case inc_e: INC(_E); break;
2524 case inc_h: INC(_IYh); break;
2525 case inc_hl: _IY++; iWSAdjust++; break;
2526 case inc_l: INC(_IYl); break;
2527 case inc_mhl: { signed char o = read_mem(_PC++); uint8_t b = read_mem(_IY+o); INC(b); write_mem(_IY+o, b); } break;
2528 case inc_sp: _SP++; iWSAdjust++; break;
2529 case jp: JP; break;
2530 case jp_c: if (_F & Cflag) { JP } else { _PC += 2; }; break;
2531 case jp_m: if (_F & Sflag) { JP } else { _PC += 2; }; break;
2532 case jp_nc: if (!(_F & Cflag)) { JP } else { _PC += 2; }; break;
2533 case jp_nz: if (!(_F & Zflag)) { JP } else { _PC += 2; }; break;
2534 case jp_p: if (!(_F & Sflag)) { JP } else { _PC += 2; }; break;
2535 case jp_pe: if (_F & Pflag) { JP } else { _PC += 2; }; break;
2536 case jp_po: if (!(_F & Pflag)) { JP } else { _PC += 2; }; break;
2537 case jp_z: if (_F & Zflag) { JP } else { _PC += 2; }; break;
2538 case jr: JR; break;
2539 case jr_c: if (_F & Cflag) { iCycleCount += cc_ex[bOpCode]; JR } else { _PC++; }; break;
2540 case jr_nc: if (!(_F & Cflag)) { iCycleCount += cc_ex[bOpCode]; JR } else { _PC++; }; break;
2541 case jr_nz: if (!(_F & Zflag)) { iCycleCount += cc_ex[bOpCode]; JR } else { _PC++; }; break;
2542 case jr_z: if (_F & Zflag) { iCycleCount += cc_ex[bOpCode]; JR } else { _PC++; }; break;
2543 case ld_a_a: break;
2544 case ld_a_b: _A = _B; break;
2545 case ld_a_byte: _A = read_mem(_PC++); break;
2546 case ld_a_c: _A = _C; break;
2547 case ld_a_d: _A = _D; break;
2548 case ld_a_e: _A = _E; break;
2549 case ld_a_h: _A = _IYh; break;
2550 case ld_a_l: _A = _IYl; break;
2551 case ld_a_mbc: _A = read_mem(_BC); break;
2552 case ld_a_mde: _A = read_mem(_DE); break;
2553 case ld_a_mhl: { signed char o = read_mem(_PC++); _A = read_mem(_IY+o); } break;
2554 case ld_a_mword: { reg_pair addr; addr.b.l = read_mem(_PC++); addr.b.h = read_mem(_PC++); _A = read_mem(addr.w.l); } break;
2555 case ld_bc_word: z80.BC.b.l = read_mem(_PC++); z80.BC.b.h = read_mem(_PC++); break;
2556 case ld_b_a: _B = _A; break;
2557 case ld_b_b: break;
2558 case ld_b_byte: _B = read_mem(_PC++); break;
2559 case ld_b_c: _B = _C; break;
2560 case ld_b_d: _B = _D; break;
2561 case ld_b_e: _B = _E; break;
2562 case ld_b_h: _B = _IYh; break;
2563 case ld_b_l: _B = _IYl; break;
2564 case ld_b_mhl: { signed char o = read_mem(_PC++); _B = read_mem(_IY+o); } break;
2565 case ld_c_a: _C = _A; break;
2566 case ld_c_b: _C = _B; break;
2567 case ld_c_byte: _C = read_mem(_PC++); break;
2568 case ld_c_c: break;
2569 case ld_c_d: _C = _D; break;
2570 case ld_c_e: _C = _E; break;
2571 case ld_c_h: _C = _IYh; break;
2572 case ld_c_l: _C = _IYl; break;
2573 case ld_c_mhl: { signed char o = read_mem(_PC++); _C = read_mem(_IY+o); } break;
2574 case ld_de_word: z80.DE.b.l = read_mem(_PC++); z80.DE.b.h = read_mem(_PC++); break;
2575 case ld_d_a: _D = _A; break;
2576 case ld_d_b: _D = _B; break;
2577 case ld_d_byte: _D = read_mem(_PC++); break;
2578 case ld_d_c: _D = _C; break;
2579 case ld_d_d: break;
2580 case ld_d_e: _D = _E; break;
2581 case ld_d_h: _D = _IYh; break;
2582 case ld_d_l: _D = _IYl; break;
2583 case ld_d_mhl: { signed char o = read_mem(_PC++); _D = read_mem(_IY+o); } break;
2584 case ld_e_a: _E = _A; break;
2585 case ld_e_b: _E = _B; break;
2586 case ld_e_byte: _E = read_mem(_PC++); break;
2587 case ld_e_c: _E = _C; break;
2588 case ld_e_d: _E = _D; break;
2589 case ld_e_e: break;
2590 case ld_e_h: _E = _IYh; break;
2591 case ld_e_l: _E = _IYl; break;
2592 case ld_e_mhl: { signed char o = read_mem(_PC++); _E = read_mem(_IY+o); } break;
2593 case ld_hl_mword: LD16_MEM(IY); break;
2594 case ld_hl_word: z80.IY.b.l = read_mem(_PC++); z80.IY.b.h = read_mem(_PC++); break;
2595 case ld_h_a: _IYh = _A; break;
2596 case ld_h_b: _IYh = _B; break;
2597 case ld_h_byte: _IYh = read_mem(_PC++); break;
2598 case ld_h_c: _IYh = _C; break;
2599 case ld_h_d: _IYh = _D; break;
2600 case ld_h_e: _IYh = _E; break;
2601 case ld_h_h: break;
2602 case ld_h_l: _IYh = _IYl; break;
2603 case ld_h_mhl: { signed char o = read_mem(_PC++); _H = read_mem(_IY+o); } break;
2604 case ld_l_a: _IYl = _A; break;
2605 case ld_l_b: _IYl = _B; break;
2606 case ld_l_byte: _IYl = read_mem(_PC++); break;
2607 case ld_l_c: _IYl = _C; break;
2608 case ld_l_d: _IYl = _D; break;
2609 case ld_l_e: _IYl = _E; break;
2610 case ld_l_h: _IYl = _IYh; break;
2611 case ld_l_l: break;
2612 case ld_l_mhl: { signed char o = read_mem(_PC++); _L = read_mem(_IY+o); } break;
2613 case ld_mbc_a: write_mem(_BC, _A); break;
2614 case ld_mde_a: write_mem(_DE, _A); break;
2615 case ld_mhl_a: { signed char o = read_mem(_PC++); write_mem(_IY+o, _A); } break;
2616 case ld_mhl_b: { signed char o = read_mem(_PC++); write_mem(_IY+o, _B); } break;
2617 case ld_mhl_byte: { signed char o = read_mem(_PC++); uint8_t b = read_mem(_PC++); write_mem(_IY+o, b); } break;
2618 case ld_mhl_c: { signed char o = read_mem(_PC++); write_mem(_IY+o, _C); } break;
2619 case ld_mhl_d: { signed char o = read_mem(_PC++); write_mem(_IY+o, _D); } break;
2620 case ld_mhl_e: { signed char o = read_mem(_PC++); write_mem(_IY+o, _E); } break;
2621 case ld_mhl_h: { signed char o = read_mem(_PC++); write_mem(_IY+o, _H); } break;
2622 case ld_mhl_l: { signed char o = read_mem(_PC++); write_mem(_IY+o, _L); } break;
2623 case ld_mword_a: { reg_pair addr; addr.b.l = read_mem(_PC++); addr.b.h = read_mem(_PC++); write_mem(addr.w.l, _A); } break;
2624 case ld_mword_hl: LDMEM_16(IY); break;
2625 case ld_pc_hl: _PC = _IY; break;
2626 case ld_sp_hl: _SP = _IY; iWSAdjust++; break;
2627 case ld_sp_word: z80.SP.b.l = read_mem(_PC++); z80.SP.b.h = read_mem(_PC++); break;
2628 case nop: break;
2629 case or_a: OR(_A); break;
2630 case or_b: OR(_B); break;
2631 case or_byte: OR(read_mem(_PC++)); break;
2632 case or_c: OR(_C); break;
2633 case or_d: OR(_D); break;
2634 case or_e: OR(_E); break;
2635 case or_h: OR(_IYh); break;
2636 case or_l: OR(_IYl); break;
2637 case or_mhl: { signed char o = read_mem(_PC++); OR(read_mem(_IY+o)); } break;
2638 case outa: { z80_wait_states iCycleCount = Oa_;} { reg_pair p; p.b.l = read_mem(_PC++); p.b.h = _A; z80_OUT_handler(p, _A); } break;
2639 case pfx_cb: z80_pfx_fdcb(); break;
2640 case pfx_dd: z80_pfx_dd(); break;
2641 case pfx_ed: z80_pfx_ed(); break;
2642 case pfx_fd: z80_pfx_fd(); break;
2643 case pop_af: POP(AF); break;
2644 case pop_bc: POP(BC); break;
2645 case pop_de: POP(DE); break;
2646 case pop_hl: POP(IY); break;
2647 case push_af: PUSH(AF); break;
2648 case push_bc: PUSH(BC); break;
2649 case push_de: PUSH(DE); break;
2650 case push_hl: PUSH(IY); break;
2651 case ret: RET; break;
2652 case ret_c: if (_F & Cflag) { iCycleCount += cc_ex[bOpCode]; RET } else { iWSAdjust++; } ; break;
2653 case ret_m: if (_F & Sflag) { iCycleCount += cc_ex[bOpCode]; RET } else { iWSAdjust++; } ; break;
2654 case ret_nc: if (!(_F & Cflag)) { iCycleCount += cc_ex[bOpCode]; RET } else { iWSAdjust++; } ; break;
2655 case ret_nz: if (!(_F & Zflag)) { iCycleCount += cc_ex[bOpCode]; RET } else { iWSAdjust++; } ; break;
2656 case ret_p: if (!(_F & Sflag)) { iCycleCount += cc_ex[bOpCode]; RET } else { iWSAdjust++; } ; break;
2657 case ret_pe: if (_F & Pflag) { iCycleCount += cc_ex[bOpCode]; RET } else { iWSAdjust++; } ; break;
2658 case ret_po: if (!(_F & Pflag)) { iCycleCount += cc_ex[bOpCode]; RET } else { iWSAdjust++; } ; break;
2659 case ret_z: if (_F & Zflag) { iCycleCount += cc_ex[bOpCode]; RET } else { iWSAdjust++; } ; break;
2660 case rla: RLA; break;
2661 case rlca: RLCA; break;
2662 case rra: RRA; break;
2663 case rrca: RRCA; break;
2664 case rst00: RST(0x0000); break;
2665 case rst08: RST(0x0008); break;
2666 case rst10: RST(0x0010); break;
2667 case rst18: RST(0x0018); break;
2668 case rst20: RST(0x0020); break;
2669 case rst28: RST(0x0028); break;
2670 case rst30: RST(0x0030); break;
2671 case rst38: RST(0x0038); break;
2672 case sbc_a: SBC(_A); break;
2673 case sbc_b: SBC(_B); break;
2674 case sbc_byte: SBC(read_mem(_PC++)); break;
2675 case sbc_c: SBC(_C); break;
2676 case sbc_d: SBC(_D); break;
2677 case sbc_e: SBC(_E); break;
2678 case sbc_h: SBC(_IYh); break;
2679 case sbc_l: SBC(_IYl); break;
2680 case sbc_mhl: { signed char o = read_mem(_PC++); SBC(read_mem(_IY+o)); } break;
2681 case scf: _F = (_F & (Sflag | Zflag | Pflag)) | Cflag | (_A & Xflags); break;
2682 case sub_a: SUB(_A); break;
2683 case sub_b: SUB(_B); break;
2684 case sub_byte: SUB(read_mem(_PC++)); break;
2685 case sub_c: SUB(_C); break;
2686 case sub_d: SUB(_D); break;
2687 case sub_e: SUB(_E); break;
2688 case sub_h: SUB(_IYh); break;
2689 case sub_l: SUB(_IYl); break;
2690 case sub_mhl: { signed char o = read_mem(_PC++); SUB(read_mem(_IY+o)); } break;
2691 case xor_a: XOR(_A); break;
2692 case xor_b: XOR(_B); break;
2693 case xor_byte: XOR(read_mem(_PC++)); break;
2694 case xor_c: XOR(_C); break;
2695 case xor_d: XOR(_D); break;
2696 case xor_e: XOR(_E); break;
2697 case xor_h: XOR(_IYh); break;
2698 case xor_l: XOR(_IYl); break;
2699 case xor_mhl: { signed char o = read_mem(_PC++); XOR(read_mem(_IY+o)); } break;
2700 }
2701 }
2702
2703
2704
z80_pfx_fdcb(void)2705 void z80_pfx_fdcb(void)
2706 {
2707 signed char o;
2708 uint8_t bOpCode;
2709
2710 o = read_mem(_PC++); // offset
2711 bOpCode = read_mem(_PC++);
2712 iCycleCount += cc_xycb[bOpCode];
2713 switch(bOpCode)
2714 {
2715 case bit0_a: BIT_XY(0, read_mem(_IY+o)); break;
2716 case bit0_b: BIT_XY(0, read_mem(_IY+o)); break;
2717 case bit0_c: BIT_XY(0, read_mem(_IY+o)); break;
2718 case bit0_d: BIT_XY(0, read_mem(_IY+o)); break;
2719 case bit0_e: BIT_XY(0, read_mem(_IY+o)); break;
2720 case bit0_h: BIT_XY(0, read_mem(_IY+o)); break;
2721 case bit0_l: BIT_XY(0, read_mem(_IY+o)); break;
2722 case bit0_mhl: BIT_XY(0, read_mem(_IY+o)); break;
2723 case bit1_a: BIT_XY(1, read_mem(_IY+o)); break;
2724 case bit1_b: BIT_XY(1, read_mem(_IY+o)); break;
2725 case bit1_c: BIT_XY(1, read_mem(_IY+o)); break;
2726 case bit1_d: BIT_XY(1, read_mem(_IY+o)); break;
2727 case bit1_e: BIT_XY(1, read_mem(_IY+o)); break;
2728 case bit1_h: BIT_XY(1, read_mem(_IY+o)); break;
2729 case bit1_l: BIT_XY(1, read_mem(_IY+o)); break;
2730 case bit1_mhl: BIT_XY(1, read_mem(_IY+o)); break;
2731 case bit2_a: BIT_XY(2, read_mem(_IY+o)); break;
2732 case bit2_b: BIT_XY(2, read_mem(_IY+o)); break;
2733 case bit2_c: BIT_XY(2, read_mem(_IY+o)); break;
2734 case bit2_d: BIT_XY(2, read_mem(_IY+o)); break;
2735 case bit2_e: BIT_XY(2, read_mem(_IY+o)); break;
2736 case bit2_h: BIT_XY(2, read_mem(_IY+o)); break;
2737 case bit2_l: BIT_XY(2, read_mem(_IY+o)); break;
2738 case bit2_mhl: BIT_XY(2, read_mem(_IY+o)); break;
2739 case bit3_a: BIT_XY(3, read_mem(_IY+o)); break;
2740 case bit3_b: BIT_XY(3, read_mem(_IY+o)); break;
2741 case bit3_c: BIT_XY(3, read_mem(_IY+o)); break;
2742 case bit3_d: BIT_XY(3, read_mem(_IY+o)); break;
2743 case bit3_e: BIT_XY(3, read_mem(_IY+o)); break;
2744 case bit3_h: BIT_XY(3, read_mem(_IY+o)); break;
2745 case bit3_l: BIT_XY(3, read_mem(_IY+o)); break;
2746 case bit3_mhl: BIT_XY(3, read_mem(_IY+o)); break;
2747 case bit4_a: BIT_XY(4, read_mem(_IY+o)); break;
2748 case bit4_b: BIT_XY(4, read_mem(_IY+o)); break;
2749 case bit4_c: BIT_XY(4, read_mem(_IY+o)); break;
2750 case bit4_d: BIT_XY(4, read_mem(_IY+o)); break;
2751 case bit4_e: BIT_XY(4, read_mem(_IY+o)); break;
2752 case bit4_h: BIT_XY(4, read_mem(_IY+o)); break;
2753 case bit4_l: BIT_XY(4, read_mem(_IY+o)); break;
2754 case bit4_mhl: BIT_XY(4, read_mem(_IY+o)); break;
2755 case bit5_a: BIT_XY(5, read_mem(_IY+o)); break;
2756 case bit5_b: BIT_XY(5, read_mem(_IY+o)); break;
2757 case bit5_c: BIT_XY(5, read_mem(_IY+o)); break;
2758 case bit5_d: BIT_XY(5, read_mem(_IY+o)); break;
2759 case bit5_e: BIT_XY(5, read_mem(_IY+o)); break;
2760 case bit5_h: BIT_XY(5, read_mem(_IY+o)); break;
2761 case bit5_l: BIT_XY(5, read_mem(_IY+o)); break;
2762 case bit5_mhl: BIT_XY(5, read_mem(_IY+o)); break;
2763 case bit6_a: BIT_XY(6, read_mem(_IY+o)); break;
2764 case bit6_b: BIT_XY(6, read_mem(_IY+o)); break;
2765 case bit6_c: BIT_XY(6, read_mem(_IY+o)); break;
2766 case bit6_d: BIT_XY(6, read_mem(_IY+o)); break;
2767 case bit6_e: BIT_XY(6, read_mem(_IY+o)); break;
2768 case bit6_h: BIT_XY(6, read_mem(_IY+o)); break;
2769 case bit6_l: BIT_XY(6, read_mem(_IY+o)); break;
2770 case bit6_mhl: BIT_XY(6, read_mem(_IY+o)); break;
2771 case bit7_a: BIT_XY(7, read_mem(_IY+o)); break;
2772 case bit7_b: BIT_XY(7, read_mem(_IY+o)); break;
2773 case bit7_c: BIT_XY(7, read_mem(_IY+o)); break;
2774 case bit7_d: BIT_XY(7, read_mem(_IY+o)); break;
2775 case bit7_e: BIT_XY(7, read_mem(_IY+o)); break;
2776 case bit7_h: BIT_XY(7, read_mem(_IY+o)); break;
2777 case bit7_l: BIT_XY(7, read_mem(_IY+o)); break;
2778 case bit7_mhl: BIT_XY(7, read_mem(_IY+o)); break;
2779 case res0_a: _A = read_mem(_IY+o); write_mem(_IY+o, _A = RES(0, _A)); break;
2780 case res0_b: _B = read_mem(_IY+o); write_mem(_IY+o, _B = RES(0, _B)); break;
2781 case res0_c: _C = read_mem(_IY+o); write_mem(_IY+o, _C = RES(0, _C)); break;
2782 case res0_d: _D = read_mem(_IY+o); write_mem(_IY+o, _D = RES(0, _D)); break;
2783 case res0_e: _E = read_mem(_IY+o); write_mem(_IY+o, _E = RES(0, _E)); break;
2784 case res0_h: _H = read_mem(_IY+o); write_mem(_IY+o, _H = RES(0, _H)); break;
2785 case res0_l: _L = read_mem(_IY+o); write_mem(_IY+o, _L = RES(0, _L)); break;
2786 case res0_mhl: { uint8_t b = read_mem(_IY+o); write_mem(_IY+o, RES(0, b)); } break;
2787 case res1_a: _A = read_mem(_IY+o); write_mem(_IY+o, _A = RES(1, _A)); break;
2788 case res1_b: _B = read_mem(_IY+o); write_mem(_IY+o, _B = RES(1, _B)); break;
2789 case res1_c: _C = read_mem(_IY+o); write_mem(_IY+o, _C = RES(1, _C)); break;
2790 case res1_d: _D = read_mem(_IY+o); write_mem(_IY+o, _D = RES(1, _D)); break;
2791 case res1_e: _E = read_mem(_IY+o); write_mem(_IY+o, _E = RES(1, _E)); break;
2792 case res1_h: _H = read_mem(_IY+o); write_mem(_IY+o, _H = RES(1, _H)); break;
2793 case res1_l: _L = read_mem(_IY+o); write_mem(_IY+o, _L = RES(1, _L)); break;
2794 case res1_mhl: { uint8_t b = read_mem(_IY+o); write_mem(_IY+o, RES(1, b)); } break;
2795 case res2_a: _A = read_mem(_IY+o); write_mem(_IY+o, _A = RES(2, _A)); break;
2796 case res2_b: _B = read_mem(_IY+o); write_mem(_IY+o, _B = RES(2, _B)); break;
2797 case res2_c: _C = read_mem(_IY+o); write_mem(_IY+o, _C = RES(2, _C)); break;
2798 case res2_d: _D = read_mem(_IY+o); write_mem(_IY+o, _D = RES(2, _D)); break;
2799 case res2_e: _E = read_mem(_IY+o); write_mem(_IY+o, _E = RES(2, _E)); break;
2800 case res2_h: _H = read_mem(_IY+o); write_mem(_IY+o, _H = RES(2, _H)); break;
2801 case res2_l: _L = read_mem(_IY+o); write_mem(_IY+o, _L = RES(2, _L)); break;
2802 case res2_mhl: { uint8_t b = read_mem(_IY+o); write_mem(_IY+o, RES(2, b)); } break;
2803 case res3_a: _A = read_mem(_IY+o); write_mem(_IY+o, _A = RES(3, _A)); break;
2804 case res3_b: _B = read_mem(_IY+o); write_mem(_IY+o, _B = RES(3, _B)); break;
2805 case res3_c: _C = read_mem(_IY+o); write_mem(_IY+o, _C = RES(3, _C)); break;
2806 case res3_d: _D = read_mem(_IY+o); write_mem(_IY+o, _D = RES(3, _D)); break;
2807 case res3_e: _E = read_mem(_IY+o); write_mem(_IY+o, _E = RES(3, _E)); break;
2808 case res3_h: _H = read_mem(_IY+o); write_mem(_IY+o, _H = RES(3, _H)); break;
2809 case res3_l: _L = read_mem(_IY+o); write_mem(_IY+o, _L = RES(3, _L)); break;
2810 case res3_mhl: { uint8_t b = read_mem(_IY+o); write_mem(_IY+o, RES(3, b)); } break;
2811 case res4_a: _A = read_mem(_IY+o); write_mem(_IY+o, _A = RES(4, _A)); break;
2812 case res4_b: _B = read_mem(_IY+o); write_mem(_IY+o, _B = RES(4, _B)); break;
2813 case res4_c: _C = read_mem(_IY+o); write_mem(_IY+o, _C = RES(4, _C)); break;
2814 case res4_d: _D = read_mem(_IY+o); write_mem(_IY+o, _D = RES(4, _D)); break;
2815 case res4_e: _E = read_mem(_IY+o); write_mem(_IY+o, _E = RES(4, _E)); break;
2816 case res4_h: _H = read_mem(_IY+o); write_mem(_IY+o, _H = RES(4, _H)); break;
2817 case res4_l: _L = read_mem(_IY+o); write_mem(_IY+o, _L = RES(4, _L)); break;
2818 case res4_mhl: { uint8_t b = read_mem(_IY+o); write_mem(_IY+o, RES(4, b)); } break;
2819 case res5_a: _A = read_mem(_IY+o); write_mem(_IY+o, _A = RES(5, _A)); break;
2820 case res5_b: _B = read_mem(_IY+o); write_mem(_IY+o, _B = RES(5, _B)); break;
2821 case res5_c: _C = read_mem(_IY+o); write_mem(_IY+o, _C = RES(5, _C)); break;
2822 case res5_d: _D = read_mem(_IY+o); write_mem(_IY+o, _D = RES(5, _D)); break;
2823 case res5_e: _E = read_mem(_IY+o); write_mem(_IY+o, _E = RES(5, _E)); break;
2824 case res5_h: _H = read_mem(_IY+o); write_mem(_IY+o, _H = RES(5, _H)); break;
2825 case res5_l: _L = read_mem(_IY+o); write_mem(_IY+o, _L = RES(5, _L)); break;
2826 case res5_mhl: { uint8_t b = read_mem(_IY+o); write_mem(_IY+o, RES(5, b)); } break;
2827 case res6_a: _A = read_mem(_IY+o); write_mem(_IY+o, _A = RES(6, _A)); break;
2828 case res6_b: _B = read_mem(_IY+o); write_mem(_IY+o, _B = RES(6, _B)); break;
2829 case res6_c: _C = read_mem(_IY+o); write_mem(_IY+o, _C = RES(6, _C)); break;
2830 case res6_d: _D = read_mem(_IY+o); write_mem(_IY+o, _D = RES(6, _D)); break;
2831 case res6_e: _E = read_mem(_IY+o); write_mem(_IY+o, _E = RES(6, _E)); break;
2832 case res6_h: _H = read_mem(_IY+o); write_mem(_IY+o, _H = RES(6, _H)); break;
2833 case res6_l: _L = read_mem(_IY+o); write_mem(_IY+o, _L = RES(6, _L)); break;
2834 case res6_mhl: { uint8_t b = read_mem(_IY+o); write_mem(_IY+o, RES(6, b)); } break;
2835 case res7_a: _A = read_mem(_IY+o); write_mem(_IY+o, _A = RES(7, _A)); break;
2836 case res7_b: _B = read_mem(_IY+o); write_mem(_IY+o, _B = RES(7, _B)); break;
2837 case res7_c: _C = read_mem(_IY+o); write_mem(_IY+o, _C = RES(7, _C)); break;
2838 case res7_d: _D = read_mem(_IY+o); write_mem(_IY+o, _D = RES(7, _D)); break;
2839 case res7_e: _E = read_mem(_IY+o); write_mem(_IY+o, _E = RES(7, _E)); break;
2840 case res7_h: _H = read_mem(_IY+o); write_mem(_IY+o, _H = RES(7, _H)); break;
2841 case res7_l: _L = read_mem(_IY+o); write_mem(_IY+o, _L = RES(7, _L)); break;
2842 case res7_mhl: { uint8_t b = read_mem(_IY+o); write_mem(_IY+o, RES(7, b)); } break;
2843 case rlc_a: _A = read_mem(_IY+o); _A = RLC(_A); write_mem(_IY+o, _A); break;
2844 case rlc_b: _B = read_mem(_IY+o); _B = RLC(_B); write_mem(_IY+o, _B); break;
2845 case rlc_c: _C = read_mem(_IY+o); _C = RLC(_C); write_mem(_IY+o, _C); break;
2846 case rlc_d: _D = read_mem(_IY+o); _D = RLC(_D); write_mem(_IY+o, _D); break;
2847 case rlc_e: _E = read_mem(_IY+o); _E = RLC(_E); write_mem(_IY+o, _E); break;
2848 case rlc_h: _H = read_mem(_IY+o); _H = RLC(_H); write_mem(_IY+o, _H); break;
2849 case rlc_l: _L = read_mem(_IY+o); _L = RLC(_L); write_mem(_IY+o, _L); break;
2850 case rlc_mhl: { uint8_t b = read_mem(_IY+o); write_mem(_IY+o, RLC(b)); } break;
2851 case rl_a: _A = read_mem(_IY+o); _A = RL(_A); write_mem(_IY+o, _A); break;
2852 case rl_b: _B = read_mem(_IY+o); _B = RL(_B); write_mem(_IY+o, _B); break;
2853 case rl_c: _C = read_mem(_IY+o); _C = RL(_C); write_mem(_IY+o, _C); break;
2854 case rl_d: _D = read_mem(_IY+o); _D = RL(_D); write_mem(_IY+o, _D); break;
2855 case rl_e: _E = read_mem(_IY+o); _E = RL(_E); write_mem(_IY+o, _E); break;
2856 case rl_h: _H = read_mem(_IY+o); _H = RL(_H); write_mem(_IY+o, _H); break;
2857 case rl_l: _L = read_mem(_IY+o); _L = RL(_L); write_mem(_IY+o, _L); break;
2858 case rl_mhl: { uint8_t b = read_mem(_IY+o); write_mem(_IY+o, RL(b)); } break;
2859 case rrc_a: _A = read_mem(_IY+o); _A = RRC(_A); write_mem(_IY+o, _A); break;
2860 case rrc_b: _B = read_mem(_IY+o); _B = RRC(_B); write_mem(_IY+o, _B); break;
2861 case rrc_c: _C = read_mem(_IY+o); _C = RRC(_C); write_mem(_IY+o, _C); break;
2862 case rrc_d: _D = read_mem(_IY+o); _D = RRC(_D); write_mem(_IY+o, _D); break;
2863 case rrc_e: _E = read_mem(_IY+o); _E = RRC(_E); write_mem(_IY+o, _E); break;
2864 case rrc_h: _H = read_mem(_IY+o); _H = RRC(_H); write_mem(_IY+o, _H); break;
2865 case rrc_l: _L = read_mem(_IY+o); _L = RRC(_L); write_mem(_IY+o, _L); break;
2866 case rrc_mhl: { uint8_t b = read_mem(_IY+o); write_mem(_IY+o, RRC(b)); } break;
2867 case rr_a: _A = read_mem(_IY+o); _A = RR(_A); write_mem(_IY+o, _A); break;
2868 case rr_b: _B = read_mem(_IY+o); _B = RR(_B); write_mem(_IY+o, _B); break;
2869 case rr_c: _C = read_mem(_IY+o); _C = RR(_C); write_mem(_IY+o, _C); break;
2870 case rr_d: _D = read_mem(_IY+o); _D = RR(_D); write_mem(_IY+o, _D); break;
2871 case rr_e: _E = read_mem(_IY+o); _E = RR(_E); write_mem(_IY+o, _E); break;
2872 case rr_h: _H = read_mem(_IY+o); _H = RR(_H); write_mem(_IY+o, _H); break;
2873 case rr_l: _L = read_mem(_IY+o); _L = RR(_L); write_mem(_IY+o, _L); break;
2874 case rr_mhl: { uint8_t b = read_mem(_IY+o); write_mem(_IY+o, RR(b)); } break;
2875 case set0_a: _A = read_mem(_IY+o); write_mem(_IY+o, _A = SET(0, _A)); break;
2876 case set0_b: _B = read_mem(_IY+o); write_mem(_IY+o, _B = SET(0, _B)); break;
2877 case set0_c: _C = read_mem(_IY+o); write_mem(_IY+o, _C = SET(0, _C)); break;
2878 case set0_d: _D = read_mem(_IY+o); write_mem(_IY+o, _D = SET(0, _D)); break;
2879 case set0_e: _E = read_mem(_IY+o); write_mem(_IY+o, _E = SET(0, _E)); break;
2880 case set0_h: _H = read_mem(_IY+o); write_mem(_IY+o, _H = SET(0, _H)); break;
2881 case set0_l: _L = read_mem(_IY+o); write_mem(_IY+o, _L = SET(0, _L)); break;
2882 case set0_mhl: { uint8_t b = read_mem(_IY+o); write_mem(_IY+o, SET(0, b)); } break;
2883 case set1_a: _A = read_mem(_IY+o); write_mem(_IY+o, _A = SET(1, _A)); break;
2884 case set1_b: _B = read_mem(_IY+o); write_mem(_IY+o, _B = SET(1, _B)); break;
2885 case set1_c: _C = read_mem(_IY+o); write_mem(_IY+o, _C = SET(1, _C)); break;
2886 case set1_d: _D = read_mem(_IY+o); write_mem(_IY+o, _D = SET(1, _D)); break;
2887 case set1_e: _E = read_mem(_IY+o); write_mem(_IY+o, _E = SET(1, _E)); break;
2888 case set1_h: _H = read_mem(_IY+o); write_mem(_IY+o, _H = SET(1, _H)); break;
2889 case set1_l: _L = read_mem(_IY+o); write_mem(_IY+o, _L = SET(1, _L)); break;
2890 case set1_mhl: { uint8_t b = read_mem(_IY+o); write_mem(_IY+o, SET(1, b)); } break;
2891 case set2_a: _A = read_mem(_IY+o); write_mem(_IY+o, _A = SET(2, _A)); break;
2892 case set2_b: _B = read_mem(_IY+o); write_mem(_IY+o, _B = SET(2, _B)); break;
2893 case set2_c: _C = read_mem(_IY+o); write_mem(_IY+o, _C = SET(2, _C)); break;
2894 case set2_d: _D = read_mem(_IY+o); write_mem(_IY+o, _D = SET(2, _D)); break;
2895 case set2_e: _E = read_mem(_IY+o); write_mem(_IY+o, _E = SET(2, _E)); break;
2896 case set2_h: _H = read_mem(_IY+o); write_mem(_IY+o, _H = SET(2, _H)); break;
2897 case set2_l: _L = read_mem(_IY+o); write_mem(_IY+o, _L = SET(2, _L)); break;
2898 case set2_mhl: { uint8_t b = read_mem(_IY+o); write_mem(_IY+o, SET(2, b)); } break;
2899 case set3_a: _A = read_mem(_IY+o); write_mem(_IY+o, _A = SET(3, _A)); break;
2900 case set3_b: _B = read_mem(_IY+o); write_mem(_IY+o, _B = SET(3, _B)); break;
2901 case set3_c: _C = read_mem(_IY+o); write_mem(_IY+o, _C = SET(3, _C)); break;
2902 case set3_d: _D = read_mem(_IY+o); write_mem(_IY+o, _D = SET(3, _D)); break;
2903 case set3_e: _E = read_mem(_IY+o); write_mem(_IY+o, _E = SET(3, _E)); break;
2904 case set3_h: _H = read_mem(_IY+o); write_mem(_IY+o, _H = SET(3, _H)); break;
2905 case set3_l: _L = read_mem(_IY+o); write_mem(_IY+o, _L = SET(3, _L)); break;
2906 case set3_mhl: { uint8_t b = read_mem(_IY+o); write_mem(_IY+o, SET(3, b)); } break;
2907 case set4_a: _A = read_mem(_IY+o); write_mem(_IY+o, _A = SET(4, _A)); break;
2908 case set4_b: _B = read_mem(_IY+o); write_mem(_IY+o, _B = SET(4, _B)); break;
2909 case set4_c: _C = read_mem(_IY+o); write_mem(_IY+o, _C = SET(4, _C)); break;
2910 case set4_d: _D = read_mem(_IY+o); write_mem(_IY+o, _D = SET(4, _D)); break;
2911 case set4_e: _E = read_mem(_IY+o); write_mem(_IY+o, _E = SET(4, _E)); break;
2912 case set4_h: _H = read_mem(_IY+o); write_mem(_IY+o, _H = SET(4, _H)); break;
2913 case set4_l: _L = read_mem(_IY+o); write_mem(_IY+o, _L = SET(4, _L)); break;
2914 case set4_mhl: { uint8_t b = read_mem(_IY+o); write_mem(_IY+o, SET(4, b)); } break;
2915 case set5_a: _A = read_mem(_IY+o); write_mem(_IY+o, _A = SET(5, _A)); break;
2916 case set5_b: _B = read_mem(_IY+o); write_mem(_IY+o, _B = SET(5, _B)); break;
2917 case set5_c: _C = read_mem(_IY+o); write_mem(_IY+o, _C = SET(5, _C)); break;
2918 case set5_d: _D = read_mem(_IY+o); write_mem(_IY+o, _D = SET(5, _D)); break;
2919 case set5_e: _E = read_mem(_IY+o); write_mem(_IY+o, _E = SET(5, _E)); break;
2920 case set5_h: _H = read_mem(_IY+o); write_mem(_IY+o, _H = SET(5, _H)); break;
2921 case set5_l: _L = read_mem(_IY+o); write_mem(_IY+o, _L = SET(5, _L)); break;
2922 case set5_mhl: { uint8_t b = read_mem(_IY+o); write_mem(_IY+o, SET(5, b)); } break;
2923 case set6_a: _A = read_mem(_IY+o); write_mem(_IY+o, _A = SET(6, _A)); break;
2924 case set6_b: _B = read_mem(_IY+o); write_mem(_IY+o, _B = SET(6, _B)); break;
2925 case set6_c: _C = read_mem(_IY+o); write_mem(_IY+o, _C = SET(6, _C)); break;
2926 case set6_d: _D = read_mem(_IY+o); write_mem(_IY+o, _D = SET(6, _D)); break;
2927 case set6_e: _E = read_mem(_IY+o); write_mem(_IY+o, _E = SET(6, _E)); break;
2928 case set6_h: _H = read_mem(_IY+o); write_mem(_IY+o, _H = SET(6, _H)); break;
2929 case set6_l: _L = read_mem(_IY+o); write_mem(_IY+o, _L = SET(6, _L)); break;
2930 case set6_mhl: { uint8_t b = read_mem(_IY+o); write_mem(_IY+o, SET(6, b)); } break;
2931 case set7_a: _A = read_mem(_IY+o); write_mem(_IY+o, _A = SET(7, _A)); break;
2932 case set7_b: _B = read_mem(_IY+o); write_mem(_IY+o, _B = SET(7, _B)); break;
2933 case set7_c: _C = read_mem(_IY+o); write_mem(_IY+o, _C = SET(7, _C)); break;
2934 case set7_d: _D = read_mem(_IY+o); write_mem(_IY+o, _D = SET(7, _D)); break;
2935 case set7_e: _E = read_mem(_IY+o); write_mem(_IY+o, _E = SET(7, _E)); break;
2936 case set7_h: _H = read_mem(_IY+o); write_mem(_IY+o, _H = SET(7, _H)); break;
2937 case set7_l: _L = read_mem(_IY+o); write_mem(_IY+o, _L = SET(7, _L)); break;
2938 case set7_mhl: { uint8_t b = read_mem(_IY+o); write_mem(_IY+o, SET(7, b)); } break;
2939 case sla_a: _A = read_mem(_IY+o); _A = SLA(_A); write_mem(_IY+o, _A); break;
2940 case sla_b: _B = read_mem(_IY+o); _B = SLA(_B); write_mem(_IY+o, _B); break;
2941 case sla_c: _C = read_mem(_IY+o); _C = SLA(_C); write_mem(_IY+o, _C); break;
2942 case sla_d: _D = read_mem(_IY+o); _D = SLA(_D); write_mem(_IY+o, _D); break;
2943 case sla_e: _E = read_mem(_IY+o); _E = SLA(_E); write_mem(_IY+o, _E); break;
2944 case sla_h: _H = read_mem(_IY+o); _H = SLA(_H); write_mem(_IY+o, _H); break;
2945 case sla_l: _L = read_mem(_IY+o); _L = SLA(_L); write_mem(_IY+o, _L); break;
2946 case sla_mhl: { uint8_t b = read_mem(_IY+o); write_mem(_IY+o, SLA(b)); } break;
2947 case sll_a: _A = read_mem(_IY+o); _A = SLL(_A); write_mem(_IY+o, _A); break;
2948 case sll_b: _B = read_mem(_IY+o); _B = SLL(_B); write_mem(_IY+o, _B); break;
2949 case sll_c: _C = read_mem(_IY+o); _C = SLL(_C); write_mem(_IY+o, _C); break;
2950 case sll_d: _D = read_mem(_IY+o); _D = SLL(_D); write_mem(_IY+o, _D); break;
2951 case sll_e: _E = read_mem(_IY+o); _E = SLL(_E); write_mem(_IY+o, _E); break;
2952 case sll_h: _H = read_mem(_IY+o); _H = SLL(_H); write_mem(_IY+o, _H); break;
2953 case sll_l: _L = read_mem(_IY+o); _L = SLL(_L); write_mem(_IY+o, _L); break;
2954 case sll_mhl: { uint8_t b = read_mem(_IY+o); write_mem(_IY+o, SLL(b)); } break;
2955 case sra_a: _A = read_mem(_IY+o); _A = SRA(_A); write_mem(_IY+o, _A); break;
2956 case sra_b: _B = read_mem(_IY+o); _B = SRA(_B); write_mem(_IY+o, _B); break;
2957 case sra_c: _C = read_mem(_IY+o); _C = SRA(_C); write_mem(_IY+o, _C); break;
2958 case sra_d: _D = read_mem(_IY+o); _D = SRA(_D); write_mem(_IY+o, _D); break;
2959 case sra_e: _E = read_mem(_IY+o); _E = SRA(_E); write_mem(_IY+o, _E); break;
2960 case sra_h: _H = read_mem(_IY+o); _H = SRA(_H); write_mem(_IY+o, _H); break;
2961 case sra_l: _L = read_mem(_IY+o); _L = SRA(_L); write_mem(_IY+o, _L); break;
2962 case sra_mhl: { uint8_t b = read_mem(_IY+o); write_mem(_IY+o, SRA(b)); } break;
2963 case srl_a: _A = read_mem(_IY+o); _A = SRL(_A); write_mem(_IY+o, _A); break;
2964 case srl_b: _B = read_mem(_IY+o); _B = SRL(_B); write_mem(_IY+o, _B); break;
2965 case srl_c: _C = read_mem(_IY+o); _C = SRL(_C); write_mem(_IY+o, _C); break;
2966 case srl_d: _D = read_mem(_IY+o); _D = SRL(_D); write_mem(_IY+o, _D); break;
2967 case srl_e: _E = read_mem(_IY+o); _E = SRL(_E); write_mem(_IY+o, _E); break;
2968 case srl_h: _H = read_mem(_IY+o); _H = SRL(_H); write_mem(_IY+o, _H); break;
2969 case srl_l: _L = read_mem(_IY+o); _L = SRL(_L); write_mem(_IY+o, _L); break;
2970 case srl_mhl: { uint8_t b = read_mem(_IY+o); write_mem(_IY+o, SRL(b)); } break;
2971 }
2972 }
2973