1 /* 2 * Simulator of microcontrollers (stypes.h) 3 * 4 * Copyright (C) 1997,16 Drotos Daniel, Talker Bt. 5 * 6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu 7 * 8 */ 9 10 /* This file is part of microcontroller simulator: ucsim. 11 12 UCSIM is free software; you can redistribute it and/or modify 13 it under the terms of the GNU General Public License as published by 14 the Free Software Foundation; either version 2 of the License, or 15 (at your option) any later version. 16 17 UCSIM is distributed in the hope that it will be useful, 18 but WITHOUT ANY WARRANTY; without even the implied warranty of 19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 GNU General Public License for more details. 21 22 You should have received a copy of the GNU General Public License 23 along with UCSIM; see the file COPYING. If not, write to the Free 24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 25 02111-1307, USA. */ 26 /*@1@*/ 27 28 #ifndef STYPES_HEADER 29 #define STYPES_HEADER 30 31 #include "ddconfig.h" 32 33 //typedef int8_t TYPE_BYTE; 34 //typedef uint8_t TYPE_UBYTE; 35 //typedef int16_t TYPE_WORD; 36 //typedef uint16_t TYPE_UWORD; 37 //typedef int32_t TYPE_DWORD; 38 //typedef uint32_t TYPE_UDWORD; 39 40 typedef unsigned char uchar; 41 typedef unsigned int uint; 42 typedef unsigned long ulong; 43 44 typedef signed TYPE_BYTE i8_t; 45 typedef unsigned TYPE_BYTE u8_t; 46 typedef signed TYPE_WORD i16_t; 47 typedef unsigned TYPE_WORD u16_t; 48 typedef signed TYPE_DWORD i32_t; 49 typedef unsigned TYPE_DWORD u32_t; 50 typedef signed TYPE_QWORD i64_t; 51 typedef unsigned TYPE_QWORD u64_t; 52 53 typedef i64_t t_addr; /* 64 bit max */ 54 typedef u32_t t_mem; /* 32 bit max */ 55 typedef i32_t t_smem; /* signed 32 bit memory */ 56 57 #define SPECA SPEC_QWORD 58 #define SPECM SPEC_DWORD 59 60 #define AI(addr) ((int)(addr)) 61 #define AU(addr) ((unsigned int)(addr)) 62 #define AI8(addr) (AI((addr)&0xff)) 63 #define AU8(addr) (AU((addr)&0xff)) 64 #define AI16(addr) (AI((addr)&0xffff)) 65 #define AU16(addr) (AU((addr)&0xffff)) 66 #define AI32(addr) (AI((addr)&0xffffffff)) 67 #define AU32(addr) (AU((addr)&0xffffffff)) 68 69 #define MI(v) ((int)(v)) 70 #define MU(v) ((unsigned int)(v)) 71 #define MI8(v) (MI((v)&0xff)) 72 #define MU8(v) (MU((v)&0xff)) 73 #define MI32(v) (MI((v)&0xffffffff)) 74 #define MU32(v) (MU((v)&0xffffffff)) 75 76 enum { 77 max_mem_size= 0x40000000 /* 1 GB */ 78 }; 79 80 struct id_element 81 { 82 int id; 83 const char *id_string; 84 }; 85 86 enum error_type { 87 err_unknown = 0x01, 88 err_error = 0x02, 89 err_warning = 0x04 90 }; 91 92 // table of dissassembled instructions 93 struct dis_entry 94 { 95 /*uint64_t*/long long code, mask; // max 8 byte of code 96 char branch; 97 uchar length; 98 const char *mnemonic; 99 bool is_call; 100 }; 101 102 // table entry of SFR and BIT names 103 struct name_entry 104 { 105 int cpu_type; 106 t_addr addr; 107 const char *name; 108 }; 109 110 enum cpu_type { 111 CPU_NONE = 0, 112 113 CPU_51 = 0x0001, 114 CPU_31 = 0x0002, 115 CPU_52 = 0x0004, 116 CPU_32 = 0x0008, 117 CPU_51R = 0x0010, 118 CPU_89C51R = 0x0020, 119 CPU_251 = 0x0040, 120 CPU_DS320 = 0x0080, 121 CPU_DS390 = 0x0100, 122 CPU_DS390F = 0x0200, 123 CPU_C521 = 0x0400, 124 CPU_517 = 0x0800, 125 CPU_F380 = 0x1000, 126 CPU_XC88X = 0x2000, 127 128 CPU_ALL_51 = (CPU_51|CPU_31), 129 CPU_ALL_52 = (CPU_52|CPU_32|CPU_51R|CPU_89C51R|CPU_251| 130 CPU_DS320|CPU_DS390|CPU_DS390F| 131 CPU_C521|CPU_517|CPU_XC88X| 132 CPU_F380), 133 CPU_ALL_DS3X0 = (CPU_DS320|CPU_DS390|CPU_DS390F), 134 135 CPU_AVR = 0x0001, 136 CPU_ALL_AVR = (CPU_AVR), 137 138 CPU_Z80 = 0x0001, 139 CPU_Z180 = 0x0002, 140 CPU_LR35902 = 0x0004, 141 CPU_R2K = 0x0008, 142 CPU_R3KA = 0x0010, 143 CPU_EZ80 = 0x0020, 144 CPU_ALL_Z80 = (CPU_Z80|CPU_Z180|CPU_R2K|CPU_LR35902|CPU_R3KA|CPU_EZ80), 145 146 CPU_XA = 0x0001, 147 CPU_ALL_XA = (CPU_XA), 148 149 CPU_HC08 = 0x0001, 150 CPU_HCS08 = 0x0002, 151 CPU_ALL_HC08 = (CPU_HC08|CPU_HCS08), 152 153 CPU_STM8S = 0x0001, // S and AF family 154 CPU_STM8AF = 0x0001, 155 CPU_STM8SAF = 0x0001, 156 // Devices of S family 0x00 00 00 XX 157 DEV_STM8S903 = 0x00000001, 158 DEV_STM8S003 = 0x00000002, 159 DEV_STM8S005 = 0x00000004, 160 DEV_STM8S007 = 0x00000008, 161 DEV_STM8S103 = 0x00000010, 162 DEV_STM8S105 = 0x00000020, 163 DEV_STM8S207 = 0x00000040, 164 DEV_STM8S208 = 0x00000080, 165 DEV_STM8S = (DEV_STM8S903| 166 DEV_STM8S003| 167 DEV_STM8S005| 168 DEV_STM8S007| 169 DEV_STM8S103| 170 DEV_STM8S105| 171 DEV_STM8S207| 172 DEV_STM8S208), 173 // Devices of AF family 0x00 00 0X 00 174 DEV_STM8AF52 = 0x00000100, 175 DEV_STM8AF62_12 = 0x00000200, 176 DEV_STM8AF62_46 = 0x00000400, 177 DEV_STM8AF = (DEV_STM8AF52| 178 DEV_STM8AF62_12| 179 DEV_STM8AF62_46), 180 181 DEV_STM8SAF = (DEV_STM8S|DEV_STM8AF), 182 183 CPU_STM8L = 0x0002, // AL and L family 184 // Devices of AL family 0x00 0X 00 00 185 DEV_STM8AL3xE = 0x00010000, 186 DEV_STM8AL3x8 = 0x00020000, 187 DEV_STM8AL3x346 = 0x00040000, 188 DEV_STM8AL = (DEV_STM8AL3xE| 189 DEV_STM8AL3x8| 190 DEV_STM8AL3x346), 191 // Devices of L family 0xXX 00 00 00 192 DEV_STM8L051 = 0x01000000, 193 DEV_STM8L052C = 0x02000000, 194 DEV_STM8L052R = 0x04000000, 195 DEV_STM8L151x23 = 0x08000000, 196 DEV_STM8L15x46 = 0x10000000, 197 DEV_STM8L15x8 = 0x20000000, 198 DEV_STM8L162 = 0x40000000, 199 DEV_STM8L = (DEV_STM8L051| 200 DEV_STM8L052C| 201 DEV_STM8L052R| 202 DEV_STM8L151x23| 203 DEV_STM8L15x46| 204 DEV_STM8L15x8| 205 DEV_STM8L162), 206 207 DEV_STM8ALL = (DEV_STM8AL|DEV_STM8L), 208 209 CPU_STM8101 = 0x0004, // L101 family 210 CPU_STM8L101 = 0x0004, 211 // Devices of L101 family 0x00 00 X0 00 212 DEV_STM8101 = 0x00001000, 213 DEV_STM8L101 = 0x00001000, 214 215 CPU_ALL_STM8 = (CPU_STM8S|CPU_STM8L|CPU_STM8101), 216 217 CPU_ST7 = 0x0001, 218 CPU_ALL_ST7 = (CPU_ST7), 219 220 // technology 221 CPU_CMOS = 0x0001, 222 CPU_HMOS = 0x0002, 223 224 CPU_PDK13 = 0x0001, 225 CPU_PDK14 = 0x0002, 226 CPU_PDK15 = 0x0003, 227 }; 228 229 230 struct cpu_entry 231 { 232 const char *type_str; 233 enum cpu_type type; 234 int subtype; 235 const char *type_help; 236 const char *sub_help; 237 }; 238 239 /* Classes of memories, this is index on the list */ 240 enum mem_class 241 { 242 MEM_ROM= 0, 243 MEM_XRAM, 244 MEM_IRAM, 245 MEM_SFR, 246 MEM_DUMMY, 247 MEM_IXRAM, 248 MEM_TYPES 249 }; 250 251 #define MEM_SFR_ID cchars("sfr") 252 #define MEM_XRAM_ID cchars("xram") 253 #define MEM_IXRAM_ID cchars("ixram") 254 #define MEM_IRAM_ID cchars("iram") 255 256 // States of simulator 257 enum sim_state { 258 SIM_NONE = 0, 259 SIM_GO = 0x01, // Processor is running 260 SIM_QUIT = 0x02 // Program must exit 261 }; 262 263 /* States of CPU */ 264 enum cpu_state { 265 stGO = 0, /* Normal state */ 266 stIDLE = 1, /* Idle mode is active */ 267 stPD = 2 /* Power Down mode is active */ 268 }; 269 270 /* Result of instruction simulation */ 271 enum inst_result { 272 resGO = 0, /* OK, go on */ 273 resWDTRESET = 1, /* Reseted by WDT */ 274 resINTERRUPT = 2, /* Interrupt accepted */ 275 resSTOP = 100, /* Stop if result greather then this */ 276 resHALT = 101, /* Serious error, halt CPU */ 277 resINV_ADDR = 102, /* Invalid indirect address */ 278 resSTACK_OV = 103, /* Stack overflow */ 279 resBREAKPOINT = 104, /* Fetch Breakpoint */ 280 resUSER = 105, /* Stopped by user */ 281 resINV_INST = 106, /* Invalid instruction */ 282 resBITADDR = 107, /* Bit address is uninterpretable */ 283 resERROR = 108, /* Error happened during instruction exec */ 284 resSTEP = 109, /* Step command done, no more exex needed */ 285 resSIMIF = 110, /* Stopped by simulated prog itself through sim interface */ 286 resNOT_DONE = 111, /* Intruction has not simulated */ 287 resEVENTBREAK = 112, /* Event breakpoint */ 288 }; 289 290 #define BIT_MASK(bitaddr) (1 << (bitaddr & 0x07)) 291 292 293 /* Type of breakpoints */ 294 enum brk_perm 295 { 296 brkFIX, /* f */ 297 brkDYNAMIC /* d */ 298 }; 299 300 enum brk_type 301 { 302 brkFETCH, /* f */ 303 brkEVENT /* e */ 304 }; 305 306 enum brk_event 307 { 308 brkNONE, 309 brkWXRAM, /* wx */ 310 brkRXRAM, /* rx */ 311 brkRCODE, /* rc */ 312 brkWIRAM, /* wi */ 313 brkRIRAM, /* ri */ 314 brkWSFR, /* ws */ 315 brkRSFR, /* rs */ 316 brkREAD, 317 brkWRITE, 318 brkACCESS 319 }; 320 321 /* Interrupt levels */ 322 enum intr_levels { 323 //IT_NO = -1, /* not in interroupt service */ 324 IT_LOW = 1, /* low level interrupt service */ 325 IT_HIGH = 2 /* service of high priority interrupt */ 326 }; 327 328 /* cathegories of hw elements (peripherials) */ 329 enum hw_cath { 330 HW_DUMMY = 0x0000, 331 HW_TIMER = 0x0002, 332 HW_UART = 0x0004, 333 HW_PORT = 0x0008, 334 HW_PCA = 0x0010, 335 HW_INTERRUPT = 0x0020, 336 HW_WDT = 0x0040, 337 HW_SIMIF = 0x0080, 338 HW_RESET = 0x0100, 339 HW_CLOCK = 0x0200, 340 HW_CALC = 0x0400, 341 HW_FLASH = 0x0800, 342 HW_CPU = 0x1000 343 }; 344 345 // Events that can happen in peripherals 346 enum hw_event { 347 EV_OVERFLOW, 348 EV_PORT_CHANGED, 349 EV_T2_MODE_CHANGED, 350 EV_CLK_ON, 351 EV_CLK_OFF 352 }; 353 354 // flags of hw units 355 enum hw_flags { 356 HWF_NONE = 0, 357 HWF_INSIDE = 0x0001, 358 HWF_OUTSIDE = 0x0002, 359 HWF_MISC = 0x0004 360 }; 361 362 /* Letter cases */ 363 enum letter_case { 364 case_upper, /* all is upper case */ 365 case_lower, /* all is lower case */ 366 case_case /* first letter is upper, others are lower case */ 367 }; 368 369 370 #endif 371 372 /* End of stypes.h */ 373