1 /*-
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 /*
35 * RealTek 8129/8139 PCI NIC driver
36 *
37 * Supports several extremely cheap PCI 10/100 adapters based on
38 * the RealTek chipset. Datasheets can be obtained from
39 * www.realtek.com.tw.
40 *
41 * Written by Bill Paul <wpaul@ctr.columbia.edu>
42 * Electrical Engineering Department
43 * Columbia University, New York City
44 */
45 /*
46 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
47 * probably the worst PCI ethernet controller ever made, with the possible
48 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
49 * DMA, but it has a terrible interface that nullifies any performance
50 * gains that bus-master DMA usually offers.
51 *
52 * For transmission, the chip offers a series of four TX descriptor
53 * registers. Each transmit frame must be in a contiguous buffer, aligned
54 * on a longword (32-bit) boundary. This means we almost always have to
55 * do mbuf copies in order to transmit a frame, except in the unlikely
56 * case where a) the packet fits into a single mbuf, and b) the packet
57 * is 32-bit aligned within the mbuf's data area. The presence of only
58 * four descriptor registers means that we can never have more than four
59 * packets queued for transmission at any one time.
60 *
61 * Reception is not much better. The driver has to allocate a single large
62 * buffer area (up to 64K in size) into which the chip will DMA received
63 * frames. Because we don't know where within this region received packets
64 * will begin or end, we have no choice but to copy data from the buffer
65 * area into mbufs in order to pass the packets up to the higher protocol
66 * levels.
67 *
68 * It's impossible given this rotten design to really achieve decent
69 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
70 * some equally overmuscled CPU to drive it.
71 *
72 * On the bright side, the 8139 does have a built-in PHY, although
73 * rather than using an MDIO serial interface like most other NICs, the
74 * PHY registers are directly accessible through the 8139's register
75 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
76 * filter.
77 *
78 * The 8129 chip is an older version of the 8139 that uses an external PHY
79 * chip. The 8129 has a serial MDIO interface for accessing the MII where
80 * the 8139 lets you directly access the on-board PHY registers. We need
81 * to select which interface to use depending on the chip type.
82 */
83
84 #ifdef HAVE_KERNEL_OPTION_HEADERS
85 #include "opt_device_polling.h"
86 #endif
87
88 #include <sys/param.h>
89 #include <sys/endian.h>
90 #include <sys/systm.h>
91 #include <sys/sockio.h>
92 #include <sys/mbuf.h>
93 #include <sys/malloc.h>
94 #include <sys/kernel.h>
95 #include <sys/module.h>
96 #include <sys/socket.h>
97 #include <sys/sysctl.h>
98
99 #include <net/if.h>
100 #include <net/if_var.h>
101 #include <net/if_arp.h>
102 #include <net/ethernet.h>
103 #include <net/if_dl.h>
104 #include <net/if_media.h>
105 #include <net/if_types.h>
106
107 #include <net/bpf.h>
108
109 #include <machine/bus.h>
110 #include <machine/resource.h>
111 #include <sys/bus.h>
112 #include <sys/rman.h>
113
114 #include <dev/mii/mii.h>
115 #include <dev/mii/mii_bitbang.h>
116 #include <dev/mii/miivar.h>
117
118 #include <dev/pci/pcireg.h>
119 #include <dev/pci/pcivar.h>
120
121 MODULE_DEPEND(rl, pci, 1, 1, 1);
122 MODULE_DEPEND(rl, ether, 1, 1, 1);
123 MODULE_DEPEND(rl, miibus, 1, 1, 1);
124
125 /* "device miibus" required. See GENERIC if you get errors here. */
126 #include "miibus_if.h"
127
128 #include <dev/rl/if_rlreg.h>
129
130 /*
131 * Various supported device vendors/types and their names.
132 */
133 static const struct rl_type rl_devs[] = {
134 { RT_VENDORID, RT_DEVICEID_8129, RL_8129,
135 "RealTek 8129 10/100BaseTX" },
136 { RT_VENDORID, RT_DEVICEID_8139, RL_8139,
137 "RealTek 8139 10/100BaseTX" },
138 { RT_VENDORID, RT_DEVICEID_8139D, RL_8139,
139 "RealTek 8139 10/100BaseTX" },
140 { RT_VENDORID, RT_DEVICEID_8138, RL_8139,
141 "RealTek 8139 10/100BaseTX CardBus" },
142 { RT_VENDORID, RT_DEVICEID_8100, RL_8139,
143 "RealTek 8100 10/100BaseTX" },
144 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
145 "Accton MPX 5030/5038 10/100BaseTX" },
146 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139,
147 "Delta Electronics 8139 10/100BaseTX" },
148 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139,
149 "Addtron Technology 8139 10/100BaseTX" },
150 { DLINK_VENDORID, DLINK_DEVICEID_520TX_REVC1, RL_8139,
151 "D-Link DFE-520TX (rev. C1) 10/100BaseTX" },
152 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139,
153 "D-Link DFE-530TX+ 10/100BaseTX" },
154 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139,
155 "D-Link DFE-690TXD 10/100BaseTX" },
156 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
157 "Nortel Networks 10/100BaseTX" },
158 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139,
159 "Corega FEther CB-TXD" },
160 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139,
161 "Corega FEtherII CB-TXD" },
162 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139,
163 "Peppercon AG ROL-F" },
164 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3603TX, RL_8139,
165 "Planex FNW-3603-TX" },
166 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
167 "Planex FNW-3800-TX" },
168 { CP_VENDORID, RT_DEVICEID_8139, RL_8139,
169 "Compaq HNE-300" },
170 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
171 "LevelOne FPC-0106TX" },
172 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
173 "Edimax EP-4103DL CardBus" }
174 };
175
176 static int rl_attach(device_t);
177 static int rl_detach(device_t);
178 static void rl_dmamap_cb(void *, bus_dma_segment_t *, int, int);
179 static int rl_dma_alloc(struct rl_softc *);
180 static void rl_dma_free(struct rl_softc *);
181 static void rl_eeprom_putbyte(struct rl_softc *, int);
182 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
183 static int rl_encap(struct rl_softc *, struct mbuf **);
184 static int rl_list_tx_init(struct rl_softc *);
185 static int rl_list_rx_init(struct rl_softc *);
186 static int rl_ifmedia_upd(if_t);
187 static void rl_ifmedia_sts(if_t, struct ifmediareq *);
188 static int rl_ioctl(if_t, u_long, caddr_t);
189 static void rl_intr(void *);
190 static void rl_init(void *);
191 static void rl_init_locked(struct rl_softc *sc);
192 static int rl_miibus_readreg(device_t, int, int);
193 static void rl_miibus_statchg(device_t);
194 static int rl_miibus_writereg(device_t, int, int, int);
195 #ifdef DEVICE_POLLING
196 static int rl_poll(if_t ifp, enum poll_cmd cmd, int count);
197 static int rl_poll_locked(if_t ifp, enum poll_cmd cmd, int count);
198 #endif
199 static int rl_probe(device_t);
200 static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int);
201 static void rl_reset(struct rl_softc *);
202 static int rl_resume(device_t);
203 static int rl_rxeof(struct rl_softc *);
204 static void rl_rxfilter(struct rl_softc *);
205 static int rl_shutdown(device_t);
206 static void rl_start(if_t);
207 static void rl_start_locked(if_t);
208 static void rl_stop(struct rl_softc *);
209 static int rl_suspend(device_t);
210 static void rl_tick(void *);
211 static void rl_txeof(struct rl_softc *);
212 static void rl_watchdog(struct rl_softc *);
213 static void rl_setwol(struct rl_softc *);
214 static void rl_clrwol(struct rl_softc *);
215
216 /*
217 * MII bit-bang glue
218 */
219 static uint32_t rl_mii_bitbang_read(device_t);
220 static void rl_mii_bitbang_write(device_t, uint32_t);
221
222 static const struct mii_bitbang_ops rl_mii_bitbang_ops = {
223 rl_mii_bitbang_read,
224 rl_mii_bitbang_write,
225 {
226 RL_MII_DATAOUT, /* MII_BIT_MDO */
227 RL_MII_DATAIN, /* MII_BIT_MDI */
228 RL_MII_CLK, /* MII_BIT_MDC */
229 RL_MII_DIR, /* MII_BIT_DIR_HOST_PHY */
230 0, /* MII_BIT_DIR_PHY_HOST */
231 }
232 };
233
234 static device_method_t rl_methods[] = {
235 /* Device interface */
236 DEVMETHOD(device_probe, rl_probe),
237 DEVMETHOD(device_attach, rl_attach),
238 DEVMETHOD(device_detach, rl_detach),
239 DEVMETHOD(device_suspend, rl_suspend),
240 DEVMETHOD(device_resume, rl_resume),
241 DEVMETHOD(device_shutdown, rl_shutdown),
242
243 /* MII interface */
244 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
245 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
246 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
247
248 DEVMETHOD_END
249 };
250
251 static driver_t rl_driver = {
252 "rl",
253 rl_methods,
254 sizeof(struct rl_softc)
255 };
256
257 DRIVER_MODULE(rl, pci, rl_driver, 0, 0);
258 MODULE_PNP_INFO("U16:vendor;U16:device", pci, rl, rl_devs,
259 nitems(rl_devs) - 1);
260 DRIVER_MODULE(rl, cardbus, rl_driver, 0, 0);
261 DRIVER_MODULE(miibus, rl, miibus_driver, 0, 0);
262
263 #define EE_SET(x) \
264 CSR_WRITE_1(sc, RL_EECMD, \
265 CSR_READ_1(sc, RL_EECMD) | x)
266
267 #define EE_CLR(x) \
268 CSR_WRITE_1(sc, RL_EECMD, \
269 CSR_READ_1(sc, RL_EECMD) & ~x)
270
271 /*
272 * Send a read command and address to the EEPROM, check for ACK.
273 */
274 static void
rl_eeprom_putbyte(struct rl_softc * sc,int addr)275 rl_eeprom_putbyte(struct rl_softc *sc, int addr)
276 {
277 int d, i;
278
279 d = addr | sc->rl_eecmd_read;
280
281 /*
282 * Feed in each bit and strobe the clock.
283 */
284 for (i = 0x400; i; i >>= 1) {
285 if (d & i) {
286 EE_SET(RL_EE_DATAIN);
287 } else {
288 EE_CLR(RL_EE_DATAIN);
289 }
290 DELAY(100);
291 EE_SET(RL_EE_CLK);
292 DELAY(150);
293 EE_CLR(RL_EE_CLK);
294 DELAY(100);
295 }
296 }
297
298 /*
299 * Read a word of data stored in the EEPROM at address 'addr.'
300 */
301 static void
rl_eeprom_getword(struct rl_softc * sc,int addr,uint16_t * dest)302 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
303 {
304 int i;
305 uint16_t word = 0;
306
307 /* Enter EEPROM access mode. */
308 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
309
310 /*
311 * Send address of word we want to read.
312 */
313 rl_eeprom_putbyte(sc, addr);
314
315 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
316
317 /*
318 * Start reading bits from EEPROM.
319 */
320 for (i = 0x8000; i; i >>= 1) {
321 EE_SET(RL_EE_CLK);
322 DELAY(100);
323 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
324 word |= i;
325 EE_CLR(RL_EE_CLK);
326 DELAY(100);
327 }
328
329 /* Turn off EEPROM access mode. */
330 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
331
332 *dest = word;
333 }
334
335 /*
336 * Read a sequence of words from the EEPROM.
337 */
338 static void
rl_read_eeprom(struct rl_softc * sc,uint8_t * dest,int off,int cnt,int swap)339 rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap)
340 {
341 int i;
342 uint16_t word = 0, *ptr;
343
344 for (i = 0; i < cnt; i++) {
345 rl_eeprom_getword(sc, off + i, &word);
346 ptr = (uint16_t *)(dest + (i * 2));
347 if (swap)
348 *ptr = ntohs(word);
349 else
350 *ptr = word;
351 }
352 }
353
354 /*
355 * Read the MII serial port for the MII bit-bang module.
356 */
357 static uint32_t
rl_mii_bitbang_read(device_t dev)358 rl_mii_bitbang_read(device_t dev)
359 {
360 struct rl_softc *sc;
361 uint32_t val;
362
363 sc = device_get_softc(dev);
364
365 val = CSR_READ_1(sc, RL_MII);
366 CSR_BARRIER(sc, RL_MII, 1,
367 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
368
369 return (val);
370 }
371
372 /*
373 * Write the MII serial port for the MII bit-bang module.
374 */
375 static void
rl_mii_bitbang_write(device_t dev,uint32_t val)376 rl_mii_bitbang_write(device_t dev, uint32_t val)
377 {
378 struct rl_softc *sc;
379
380 sc = device_get_softc(dev);
381
382 CSR_WRITE_1(sc, RL_MII, val);
383 CSR_BARRIER(sc, RL_MII, 1,
384 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
385 }
386
387 static int
rl_miibus_readreg(device_t dev,int phy,int reg)388 rl_miibus_readreg(device_t dev, int phy, int reg)
389 {
390 struct rl_softc *sc;
391 uint16_t rl8139_reg;
392
393 sc = device_get_softc(dev);
394
395 if (sc->rl_type == RL_8139) {
396 switch (reg) {
397 case MII_BMCR:
398 rl8139_reg = RL_BMCR;
399 break;
400 case MII_BMSR:
401 rl8139_reg = RL_BMSR;
402 break;
403 case MII_ANAR:
404 rl8139_reg = RL_ANAR;
405 break;
406 case MII_ANER:
407 rl8139_reg = RL_ANER;
408 break;
409 case MII_ANLPAR:
410 rl8139_reg = RL_LPAR;
411 break;
412 case MII_PHYIDR1:
413 case MII_PHYIDR2:
414 return (0);
415 /*
416 * Allow the rlphy driver to read the media status
417 * register. If we have a link partner which does not
418 * support NWAY, this is the register which will tell
419 * us the results of parallel detection.
420 */
421 case RL_MEDIASTAT:
422 return (CSR_READ_1(sc, RL_MEDIASTAT));
423 default:
424 device_printf(sc->rl_dev, "bad phy register\n");
425 return (0);
426 }
427 return (CSR_READ_2(sc, rl8139_reg));
428 }
429
430 return (mii_bitbang_readreg(dev, &rl_mii_bitbang_ops, phy, reg));
431 }
432
433 static int
rl_miibus_writereg(device_t dev,int phy,int reg,int data)434 rl_miibus_writereg(device_t dev, int phy, int reg, int data)
435 {
436 struct rl_softc *sc;
437 uint16_t rl8139_reg;
438
439 sc = device_get_softc(dev);
440
441 if (sc->rl_type == RL_8139) {
442 switch (reg) {
443 case MII_BMCR:
444 rl8139_reg = RL_BMCR;
445 break;
446 case MII_BMSR:
447 rl8139_reg = RL_BMSR;
448 break;
449 case MII_ANAR:
450 rl8139_reg = RL_ANAR;
451 break;
452 case MII_ANER:
453 rl8139_reg = RL_ANER;
454 break;
455 case MII_ANLPAR:
456 rl8139_reg = RL_LPAR;
457 break;
458 case MII_PHYIDR1:
459 case MII_PHYIDR2:
460 return (0);
461 break;
462 default:
463 device_printf(sc->rl_dev, "bad phy register\n");
464 return (0);
465 }
466 CSR_WRITE_2(sc, rl8139_reg, data);
467 return (0);
468 }
469
470 mii_bitbang_writereg(dev, &rl_mii_bitbang_ops, phy, reg, data);
471
472 return (0);
473 }
474
475 static void
rl_miibus_statchg(device_t dev)476 rl_miibus_statchg(device_t dev)
477 {
478 struct rl_softc *sc;
479 if_t ifp;
480 struct mii_data *mii;
481
482 sc = device_get_softc(dev);
483 mii = device_get_softc(sc->rl_miibus);
484 ifp = sc->rl_ifp;
485 if (mii == NULL || ifp == NULL ||
486 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
487 return;
488
489 sc->rl_flags &= ~RL_FLAG_LINK;
490 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
491 (IFM_ACTIVE | IFM_AVALID)) {
492 switch (IFM_SUBTYPE(mii->mii_media_active)) {
493 case IFM_10_T:
494 case IFM_100_TX:
495 sc->rl_flags |= RL_FLAG_LINK;
496 break;
497 default:
498 break;
499 }
500 }
501 /*
502 * RealTek controllers do not provide any interface to
503 * Tx/Rx MACs for resolved speed, duplex and flow-control
504 * parameters.
505 */
506 }
507
508 static u_int
rl_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)509 rl_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
510 {
511 uint32_t *hashes = arg;
512 int h;
513
514 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
515 if (h < 32)
516 hashes[0] |= (1 << h);
517 else
518 hashes[1] |= (1 << (h - 32));
519
520 return (1);
521 }
522
523 /*
524 * Program the 64-bit multicast hash filter.
525 */
526 static void
rl_rxfilter(struct rl_softc * sc)527 rl_rxfilter(struct rl_softc *sc)
528 {
529 if_t ifp = sc->rl_ifp;
530 uint32_t hashes[2] = { 0, 0 };
531 uint32_t rxfilt;
532
533 RL_LOCK_ASSERT(sc);
534
535 rxfilt = CSR_READ_4(sc, RL_RXCFG);
536 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_BROAD |
537 RL_RXCFG_RX_MULTI);
538 /* Always accept frames destined for this host. */
539 rxfilt |= RL_RXCFG_RX_INDIV;
540 /* Set capture broadcast bit to capture broadcast frames. */
541 if (if_getflags(ifp) & IFF_BROADCAST)
542 rxfilt |= RL_RXCFG_RX_BROAD;
543 if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) {
544 rxfilt |= RL_RXCFG_RX_MULTI;
545 if (if_getflags(ifp) & IFF_PROMISC)
546 rxfilt |= RL_RXCFG_RX_ALLPHYS;
547 hashes[0] = 0xFFFFFFFF;
548 hashes[1] = 0xFFFFFFFF;
549 } else {
550 /* Now program new ones. */
551 if_foreach_llmaddr(ifp, rl_hash_maddr, hashes);
552 if (hashes[0] != 0 || hashes[1] != 0)
553 rxfilt |= RL_RXCFG_RX_MULTI;
554 }
555
556 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
557 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
558 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
559 }
560
561 static void
rl_reset(struct rl_softc * sc)562 rl_reset(struct rl_softc *sc)
563 {
564 int i;
565
566 RL_LOCK_ASSERT(sc);
567
568 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
569
570 for (i = 0; i < RL_TIMEOUT; i++) {
571 DELAY(10);
572 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
573 break;
574 }
575 if (i == RL_TIMEOUT)
576 device_printf(sc->rl_dev, "reset never completed!\n");
577 }
578
579 /*
580 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
581 * IDs against our list and return a device name if we find a match.
582 */
583 static int
rl_probe(device_t dev)584 rl_probe(device_t dev)
585 {
586 const struct rl_type *t;
587 uint16_t devid, revid, vendor;
588 int i;
589
590 vendor = pci_get_vendor(dev);
591 devid = pci_get_device(dev);
592 revid = pci_get_revid(dev);
593
594 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
595 if (revid == 0x20) {
596 /* 8139C+, let re(4) take care of this device. */
597 return (ENXIO);
598 }
599 }
600 t = rl_devs;
601 for (i = 0; i < nitems(rl_devs); i++, t++) {
602 if (vendor == t->rl_vid && devid == t->rl_did) {
603 device_set_desc(dev, t->rl_name);
604 return (BUS_PROBE_DEFAULT);
605 }
606 }
607
608 return (ENXIO);
609 }
610
611 struct rl_dmamap_arg {
612 bus_addr_t rl_busaddr;
613 };
614
615 static void
rl_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nsegs,int error)616 rl_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
617 {
618 struct rl_dmamap_arg *ctx;
619
620 if (error != 0)
621 return;
622
623 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
624
625 ctx = (struct rl_dmamap_arg *)arg;
626 ctx->rl_busaddr = segs[0].ds_addr;
627 }
628
629 /*
630 * Attach the interface. Allocate softc structures, do ifmedia
631 * setup and ethernet/BPF attach.
632 */
633 static int
rl_attach(device_t dev)634 rl_attach(device_t dev)
635 {
636 uint8_t eaddr[ETHER_ADDR_LEN];
637 uint16_t as[3];
638 if_t ifp;
639 struct rl_softc *sc;
640 const struct rl_type *t;
641 struct sysctl_ctx_list *ctx;
642 struct sysctl_oid_list *children;
643 int error = 0, hwrev, i, phy, pmc, rid;
644 int prefer_iomap, unit;
645 uint16_t rl_did = 0;
646 char tn[32];
647
648 sc = device_get_softc(dev);
649 unit = device_get_unit(dev);
650 sc->rl_dev = dev;
651
652 sc->rl_twister_enable = 0;
653 snprintf(tn, sizeof(tn), "dev.rl.%d.twister_enable", unit);
654 TUNABLE_INT_FETCH(tn, &sc->rl_twister_enable);
655 ctx = device_get_sysctl_ctx(sc->rl_dev);
656 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev));
657 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "twister_enable", CTLFLAG_RD,
658 &sc->rl_twister_enable, 0, "");
659
660 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
661 MTX_DEF);
662 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
663
664 pci_enable_busmaster(dev);
665
666 /*
667 * Map control/status registers.
668 * Default to using PIO access for this driver. On SMP systems,
669 * there appear to be problems with memory mapped mode: it looks
670 * like doing too many memory mapped access back to back in rapid
671 * succession can hang the bus. I'm inclined to blame this on
672 * crummy design/construction on the part of RealTek. Memory
673 * mapped mode does appear to work on uniprocessor systems though.
674 */
675 prefer_iomap = 1;
676 snprintf(tn, sizeof(tn), "dev.rl.%d.prefer_iomap", unit);
677 TUNABLE_INT_FETCH(tn, &prefer_iomap);
678 if (prefer_iomap) {
679 sc->rl_res_id = PCIR_BAR(0);
680 sc->rl_res_type = SYS_RES_IOPORT;
681 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
682 &sc->rl_res_id, RF_ACTIVE);
683 }
684 if (prefer_iomap == 0 || sc->rl_res == NULL) {
685 sc->rl_res_id = PCIR_BAR(1);
686 sc->rl_res_type = SYS_RES_MEMORY;
687 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
688 &sc->rl_res_id, RF_ACTIVE);
689 }
690 if (sc->rl_res == NULL) {
691 device_printf(dev, "couldn't map ports/memory\n");
692 error = ENXIO;
693 goto fail;
694 }
695
696 #ifdef notdef
697 /*
698 * Detect the Realtek 8139B. For some reason, this chip is very
699 * unstable when left to autoselect the media
700 * The best workaround is to set the device to the required
701 * media type or to set it to the 10 Meg speed.
702 */
703 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF)
704 device_printf(dev,
705 "Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n");
706 #endif
707
708 sc->rl_btag = rman_get_bustag(sc->rl_res);
709 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
710
711 /* Allocate interrupt */
712 rid = 0;
713 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
714 RF_SHAREABLE | RF_ACTIVE);
715
716 if (sc->rl_irq[0] == NULL) {
717 device_printf(dev, "couldn't map interrupt\n");
718 error = ENXIO;
719 goto fail;
720 }
721
722 sc->rl_cfg0 = RL_8139_CFG0;
723 sc->rl_cfg1 = RL_8139_CFG1;
724 sc->rl_cfg2 = 0;
725 sc->rl_cfg3 = RL_8139_CFG3;
726 sc->rl_cfg4 = RL_8139_CFG4;
727 sc->rl_cfg5 = RL_8139_CFG5;
728
729 /*
730 * Reset the adapter. Only take the lock here as it's needed in
731 * order to call rl_reset().
732 */
733 RL_LOCK(sc);
734 rl_reset(sc);
735 RL_UNLOCK(sc);
736
737 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
738 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
739 if (rl_did != 0x8129)
740 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
741
742 /*
743 * Get station address from the EEPROM.
744 */
745 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0);
746 for (i = 0; i < 3; i++) {
747 eaddr[(i * 2) + 0] = as[i] & 0xff;
748 eaddr[(i * 2) + 1] = as[i] >> 8;
749 }
750
751 /*
752 * Now read the exact device type from the EEPROM to find
753 * out if it's an 8129 or 8139.
754 */
755 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0);
756
757 t = rl_devs;
758 sc->rl_type = 0;
759 while(t->rl_name != NULL) {
760 if (rl_did == t->rl_did) {
761 sc->rl_type = t->rl_basetype;
762 break;
763 }
764 t++;
765 }
766
767 if (sc->rl_type == 0) {
768 device_printf(dev, "unknown device ID: %x assuming 8139\n",
769 rl_did);
770 sc->rl_type = RL_8139;
771 /*
772 * Read RL_IDR register to get ethernet address as accessing
773 * EEPROM may not extract correct address.
774 */
775 for (i = 0; i < ETHER_ADDR_LEN; i++)
776 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
777 }
778
779 if ((error = rl_dma_alloc(sc)) != 0)
780 goto fail;
781
782 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
783
784 #define RL_PHYAD_INTERNAL 0
785
786 /* Do MII setup */
787 phy = MII_PHY_ANY;
788 if (sc->rl_type == RL_8139)
789 phy = RL_PHYAD_INTERNAL;
790 error = mii_attach(dev, &sc->rl_miibus, ifp, rl_ifmedia_upd,
791 rl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
792 if (error != 0) {
793 device_printf(dev, "attaching PHYs failed\n");
794 goto fail;
795 }
796
797 if_setsoftc(ifp, sc);
798 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
799 if_setmtu(ifp, ETHERMTU);
800 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
801 if_setioctlfn(ifp, rl_ioctl);
802 if_setstartfn(ifp, rl_start);
803 if_setinitfn(ifp, rl_init);
804 if_setcapabilities(ifp, IFCAP_VLAN_MTU);
805 /* Check WOL for RTL8139B or newer controllers. */
806 if (sc->rl_type == RL_8139 &&
807 pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) {
808 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
809 switch (hwrev) {
810 case RL_HWREV_8139B:
811 case RL_HWREV_8130:
812 case RL_HWREV_8139C:
813 case RL_HWREV_8139D:
814 case RL_HWREV_8101:
815 case RL_HWREV_8100:
816 if_setcapabilitiesbit(ifp, IFCAP_WOL, 0);
817 /* Disable WOL. */
818 rl_clrwol(sc);
819 break;
820 default:
821 break;
822 }
823 }
824 if_setcapenable(ifp, if_getcapabilities(ifp));
825 if_setcapenablebit(ifp, 0, (IFCAP_WOL_UCAST | IFCAP_WOL_MCAST));
826 #ifdef DEVICE_POLLING
827 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
828 #endif
829 if_setsendqlen(ifp, ifqmaxlen);
830 if_setsendqready(ifp);
831
832 /*
833 * Call MI attach routine.
834 */
835 ether_ifattach(ifp, eaddr);
836
837 /* Hook interrupt last to avoid having to lock softc */
838 error = bus_setup_intr(dev, sc->rl_irq[0], INTR_TYPE_NET | INTR_MPSAFE,
839 NULL, rl_intr, sc, &sc->rl_intrhand[0]);
840 if (error) {
841 device_printf(sc->rl_dev, "couldn't set up irq\n");
842 ether_ifdetach(ifp);
843 }
844
845 fail:
846 if (error)
847 rl_detach(dev);
848
849 return (error);
850 }
851
852 /*
853 * Shutdown hardware and free up resources. This can be called any
854 * time after the mutex has been initialized. It is called in both
855 * the error case in attach and the normal detach case so it needs
856 * to be careful about only freeing resources that have actually been
857 * allocated.
858 */
859 static int
rl_detach(device_t dev)860 rl_detach(device_t dev)
861 {
862 struct rl_softc *sc;
863 if_t ifp;
864
865 sc = device_get_softc(dev);
866 ifp = sc->rl_ifp;
867
868 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
869
870 #ifdef DEVICE_POLLING
871 if (if_getcapenable(ifp) & IFCAP_POLLING)
872 ether_poll_deregister(ifp);
873 #endif
874 /* These should only be active if attach succeeded */
875 if (device_is_attached(dev)) {
876 RL_LOCK(sc);
877 rl_stop(sc);
878 RL_UNLOCK(sc);
879 callout_drain(&sc->rl_stat_callout);
880 ether_ifdetach(ifp);
881 }
882 #if 0
883 sc->suspended = 1;
884 #endif
885 if (sc->rl_miibus)
886 device_delete_child(dev, sc->rl_miibus);
887 bus_generic_detach(dev);
888
889 if (sc->rl_intrhand[0])
890 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
891 if (sc->rl_irq[0])
892 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]);
893 if (sc->rl_res)
894 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id,
895 sc->rl_res);
896
897 if (ifp)
898 if_free(ifp);
899
900 rl_dma_free(sc);
901
902 mtx_destroy(&sc->rl_mtx);
903
904 return (0);
905 }
906
907 static int
rl_dma_alloc(struct rl_softc * sc)908 rl_dma_alloc(struct rl_softc *sc)
909 {
910 struct rl_dmamap_arg ctx;
911 int error, i;
912
913 /*
914 * Allocate the parent bus DMA tag appropriate for PCI.
915 */
916 error = bus_dma_tag_create(bus_get_dma_tag(sc->rl_dev), /* parent */
917 1, 0, /* alignment, boundary */
918 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
919 BUS_SPACE_MAXADDR, /* highaddr */
920 NULL, NULL, /* filter, filterarg */
921 BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsize, nsegments */
922 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
923 0, /* flags */
924 NULL, NULL, /* lockfunc, lockarg */
925 &sc->rl_parent_tag);
926 if (error) {
927 device_printf(sc->rl_dev,
928 "failed to create parent DMA tag.\n");
929 goto fail;
930 }
931 /* Create DMA tag for Rx memory block. */
932 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
933 RL_RX_8139_BUF_ALIGN, 0, /* alignment, boundary */
934 BUS_SPACE_MAXADDR, /* lowaddr */
935 BUS_SPACE_MAXADDR, /* highaddr */
936 NULL, NULL, /* filter, filterarg */
937 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, 1, /* maxsize,nsegments */
938 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, /* maxsegsize */
939 0, /* flags */
940 NULL, NULL, /* lockfunc, lockarg */
941 &sc->rl_cdata.rl_rx_tag);
942 if (error) {
943 device_printf(sc->rl_dev,
944 "failed to create Rx memory block DMA tag.\n");
945 goto fail;
946 }
947 /* Create DMA tag for Tx buffer. */
948 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
949 RL_TX_8139_BUF_ALIGN, 0, /* alignment, boundary */
950 BUS_SPACE_MAXADDR, /* lowaddr */
951 BUS_SPACE_MAXADDR, /* highaddr */
952 NULL, NULL, /* filter, filterarg */
953 MCLBYTES, 1, /* maxsize, nsegments */
954 MCLBYTES, /* maxsegsize */
955 0, /* flags */
956 NULL, NULL, /* lockfunc, lockarg */
957 &sc->rl_cdata.rl_tx_tag);
958 if (error) {
959 device_printf(sc->rl_dev, "failed to create Tx DMA tag.\n");
960 goto fail;
961 }
962
963 /*
964 * Allocate DMA'able memory and load DMA map for Rx memory block.
965 */
966 error = bus_dmamem_alloc(sc->rl_cdata.rl_rx_tag,
967 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_WAITOK |
968 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->rl_cdata.rl_rx_dmamap);
969 if (error != 0) {
970 device_printf(sc->rl_dev,
971 "failed to allocate Rx DMA memory block.\n");
972 goto fail;
973 }
974 ctx.rl_busaddr = 0;
975 error = bus_dmamap_load(sc->rl_cdata.rl_rx_tag,
976 sc->rl_cdata.rl_rx_dmamap, sc->rl_cdata.rl_rx_buf,
977 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, rl_dmamap_cb, &ctx,
978 BUS_DMA_NOWAIT);
979 if (error != 0 || ctx.rl_busaddr == 0) {
980 device_printf(sc->rl_dev,
981 "could not load Rx DMA memory block.\n");
982 goto fail;
983 }
984 sc->rl_cdata.rl_rx_buf_paddr = ctx.rl_busaddr;
985
986 /* Create DMA maps for Tx buffers. */
987 for (i = 0; i < RL_TX_LIST_CNT; i++) {
988 sc->rl_cdata.rl_tx_chain[i] = NULL;
989 sc->rl_cdata.rl_tx_dmamap[i] = NULL;
990 error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag, 0,
991 &sc->rl_cdata.rl_tx_dmamap[i]);
992 if (error != 0) {
993 device_printf(sc->rl_dev,
994 "could not create Tx dmamap.\n");
995 goto fail;
996 }
997 }
998
999 /* Leave a few bytes before the start of the RX ring buffer. */
1000 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
1001 sc->rl_cdata.rl_rx_buf += RL_RX_8139_BUF_RESERVE;
1002
1003 fail:
1004 return (error);
1005 }
1006
1007 static void
rl_dma_free(struct rl_softc * sc)1008 rl_dma_free(struct rl_softc *sc)
1009 {
1010 int i;
1011
1012 /* Rx memory block. */
1013 if (sc->rl_cdata.rl_rx_tag != NULL) {
1014 if (sc->rl_cdata.rl_rx_buf_paddr != 0)
1015 bus_dmamap_unload(sc->rl_cdata.rl_rx_tag,
1016 sc->rl_cdata.rl_rx_dmamap);
1017 if (sc->rl_cdata.rl_rx_buf_ptr != NULL)
1018 bus_dmamem_free(sc->rl_cdata.rl_rx_tag,
1019 sc->rl_cdata.rl_rx_buf_ptr,
1020 sc->rl_cdata.rl_rx_dmamap);
1021 sc->rl_cdata.rl_rx_buf_ptr = NULL;
1022 sc->rl_cdata.rl_rx_buf = NULL;
1023 sc->rl_cdata.rl_rx_buf_paddr = 0;
1024 bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag);
1025 sc->rl_cdata.rl_tx_tag = NULL;
1026 }
1027
1028 /* Tx buffers. */
1029 if (sc->rl_cdata.rl_tx_tag != NULL) {
1030 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1031 if (sc->rl_cdata.rl_tx_dmamap[i] != NULL) {
1032 bus_dmamap_destroy(
1033 sc->rl_cdata.rl_tx_tag,
1034 sc->rl_cdata.rl_tx_dmamap[i]);
1035 sc->rl_cdata.rl_tx_dmamap[i] = NULL;
1036 }
1037 }
1038 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag);
1039 sc->rl_cdata.rl_tx_tag = NULL;
1040 }
1041
1042 if (sc->rl_parent_tag != NULL) {
1043 bus_dma_tag_destroy(sc->rl_parent_tag);
1044 sc->rl_parent_tag = NULL;
1045 }
1046 }
1047
1048 /*
1049 * Initialize the transmit descriptors.
1050 */
1051 static int
rl_list_tx_init(struct rl_softc * sc)1052 rl_list_tx_init(struct rl_softc *sc)
1053 {
1054 struct rl_chain_data *cd;
1055 int i;
1056
1057 RL_LOCK_ASSERT(sc);
1058
1059 cd = &sc->rl_cdata;
1060 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1061 cd->rl_tx_chain[i] = NULL;
1062 CSR_WRITE_4(sc,
1063 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
1064 }
1065
1066 sc->rl_cdata.cur_tx = 0;
1067 sc->rl_cdata.last_tx = 0;
1068
1069 return (0);
1070 }
1071
1072 static int
rl_list_rx_init(struct rl_softc * sc)1073 rl_list_rx_init(struct rl_softc *sc)
1074 {
1075
1076 RL_LOCK_ASSERT(sc);
1077
1078 bzero(sc->rl_cdata.rl_rx_buf_ptr,
1079 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ);
1080 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, sc->rl_cdata.rl_rx_dmamap,
1081 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1082
1083 return (0);
1084 }
1085
1086 /*
1087 * A frame has been uploaded: pass the resulting mbuf chain up to
1088 * the higher level protocols.
1089 *
1090 * You know there's something wrong with a PCI bus-master chip design
1091 * when you have to use m_devget().
1092 *
1093 * The receive operation is badly documented in the datasheet, so I'll
1094 * attempt to document it here. The driver provides a buffer area and
1095 * places its base address in the RX buffer start address register.
1096 * The chip then begins copying frames into the RX buffer. Each frame
1097 * is preceded by a 32-bit RX status word which specifies the length
1098 * of the frame and certain other status bits. Each frame (starting with
1099 * the status word) is also 32-bit aligned. The frame length is in the
1100 * first 16 bits of the status word; the lower 15 bits correspond with
1101 * the 'rx status register' mentioned in the datasheet.
1102 *
1103 * Note: to make the Alpha happy, the frame payload needs to be aligned
1104 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1105 * as the offset argument to m_devget().
1106 */
1107 static int
rl_rxeof(struct rl_softc * sc)1108 rl_rxeof(struct rl_softc *sc)
1109 {
1110 struct mbuf *m;
1111 if_t ifp = sc->rl_ifp;
1112 uint8_t *rxbufpos;
1113 int total_len = 0;
1114 int wrap = 0;
1115 int rx_npkts = 0;
1116 uint32_t rxstat;
1117 uint16_t cur_rx;
1118 uint16_t limit;
1119 uint16_t max_bytes, rx_bytes = 0;
1120
1121 RL_LOCK_ASSERT(sc);
1122
1123 bus_dmamap_sync(sc->rl_cdata.rl_rx_tag, sc->rl_cdata.rl_rx_dmamap,
1124 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1125
1126 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1127
1128 /* Do not try to read past this point. */
1129 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1130
1131 if (limit < cur_rx)
1132 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1133 else
1134 max_bytes = limit - cur_rx;
1135
1136 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1137 #ifdef DEVICE_POLLING
1138 if (if_getcapenable(ifp) & IFCAP_POLLING) {
1139 if (sc->rxcycles <= 0)
1140 break;
1141 sc->rxcycles--;
1142 }
1143 #endif
1144 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1145 rxstat = le32toh(*(uint32_t *)rxbufpos);
1146
1147 /*
1148 * Here's a totally undocumented fact for you. When the
1149 * RealTek chip is in the process of copying a packet into
1150 * RAM for you, the length will be 0xfff0. If you spot a
1151 * packet header with this value, you need to stop. The
1152 * datasheet makes absolutely no mention of this and
1153 * RealTek should be shot for this.
1154 */
1155 total_len = rxstat >> 16;
1156 if (total_len == RL_RXSTAT_UNFINISHED)
1157 break;
1158
1159 if (!(rxstat & RL_RXSTAT_RXOK) ||
1160 total_len < ETHER_MIN_LEN ||
1161 total_len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) {
1162 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1163 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1164 rl_init_locked(sc);
1165 return (rx_npkts);
1166 }
1167
1168 /* No errors; receive the packet. */
1169 rx_bytes += total_len + 4;
1170
1171 /*
1172 * XXX The RealTek chip includes the CRC with every
1173 * received frame, and there's no way to turn this
1174 * behavior off (at least, I can't find anything in
1175 * the manual that explains how to do it) so we have
1176 * to trim off the CRC manually.
1177 */
1178 total_len -= ETHER_CRC_LEN;
1179
1180 /*
1181 * Avoid trying to read more bytes than we know
1182 * the chip has prepared for us.
1183 */
1184 if (rx_bytes > max_bytes)
1185 break;
1186
1187 rxbufpos = sc->rl_cdata.rl_rx_buf +
1188 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
1189 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1190 rxbufpos = sc->rl_cdata.rl_rx_buf;
1191
1192 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1193 if (total_len > wrap) {
1194 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1195 NULL);
1196 if (m != NULL)
1197 m_copyback(m, wrap, total_len - wrap,
1198 sc->rl_cdata.rl_rx_buf);
1199 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1200 } else {
1201 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1202 NULL);
1203 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1204 }
1205
1206 /* Round up to 32-bit boundary. */
1207 cur_rx = (cur_rx + 3) & ~3;
1208 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1209
1210 if (m == NULL) {
1211 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1212 continue;
1213 }
1214
1215 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1216 RL_UNLOCK(sc);
1217 if_input(ifp, m);
1218 RL_LOCK(sc);
1219 rx_npkts++;
1220 }
1221
1222 /* No need to sync Rx memory block as we didn't modify it. */
1223 return (rx_npkts);
1224 }
1225
1226 /*
1227 * A frame was downloaded to the chip. It's safe for us to clean up
1228 * the list buffers.
1229 */
1230 static void
rl_txeof(struct rl_softc * sc)1231 rl_txeof(struct rl_softc *sc)
1232 {
1233 if_t ifp = sc->rl_ifp;
1234 uint32_t txstat;
1235
1236 RL_LOCK_ASSERT(sc);
1237
1238 /*
1239 * Go through our tx list and free mbufs for those
1240 * frames that have been uploaded.
1241 */
1242 do {
1243 if (RL_LAST_TXMBUF(sc) == NULL)
1244 break;
1245 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1246 if (!(txstat & (RL_TXSTAT_TX_OK|
1247 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1248 break;
1249
1250 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (txstat & RL_TXSTAT_COLLCNT) >> 24);
1251
1252 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc),
1253 BUS_DMASYNC_POSTWRITE);
1254 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc));
1255 m_freem(RL_LAST_TXMBUF(sc));
1256 RL_LAST_TXMBUF(sc) = NULL;
1257 /*
1258 * If there was a transmit underrun, bump the TX threshold.
1259 * Make sure not to overflow the 63 * 32byte we can address
1260 * with the 6 available bit.
1261 */
1262 if ((txstat & RL_TXSTAT_TX_UNDERRUN) &&
1263 (sc->rl_txthresh < 2016))
1264 sc->rl_txthresh += 32;
1265 if (txstat & RL_TXSTAT_TX_OK)
1266 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1267 else {
1268 int oldthresh;
1269 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1270 if ((txstat & RL_TXSTAT_TXABRT) ||
1271 (txstat & RL_TXSTAT_OUTOFWIN))
1272 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1273 oldthresh = sc->rl_txthresh;
1274 /* error recovery */
1275 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1276 rl_init_locked(sc);
1277 /* restore original threshold */
1278 sc->rl_txthresh = oldthresh;
1279 return;
1280 }
1281 RL_INC(sc->rl_cdata.last_tx);
1282 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1283 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1284
1285 if (RL_LAST_TXMBUF(sc) == NULL)
1286 sc->rl_watchdog_timer = 0;
1287 }
1288
1289 static void
rl_twister_update(struct rl_softc * sc)1290 rl_twister_update(struct rl_softc *sc)
1291 {
1292 uint16_t linktest;
1293 /*
1294 * Table provided by RealTek (Kinston <shangh@realtek.com.tw>) for
1295 * Linux driver. Values undocumented otherwise.
1296 */
1297 static const uint32_t param[4][4] = {
1298 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1299 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1300 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1301 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1302 };
1303
1304 /*
1305 * Tune the so-called twister registers of the RTL8139. These
1306 * are used to compensate for impedance mismatches. The
1307 * method for tuning these registers is undocumented and the
1308 * following procedure is collected from public sources.
1309 */
1310 switch (sc->rl_twister)
1311 {
1312 case CHK_LINK:
1313 /*
1314 * If we have a sufficient link, then we can proceed in
1315 * the state machine to the next stage. If not, then
1316 * disable further tuning after writing sane defaults.
1317 */
1318 if (CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_LINK_OK) {
1319 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_OFF_CMD);
1320 sc->rl_twister = FIND_ROW;
1321 } else {
1322 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_CMD);
1323 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST);
1324 CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF);
1325 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF);
1326 sc->rl_twister = DONE;
1327 }
1328 break;
1329 case FIND_ROW:
1330 /*
1331 * Read how long it took to see the echo to find the tuning
1332 * row to use.
1333 */
1334 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
1335 if (linktest == RL_CSCFG_ROW3)
1336 sc->rl_twist_row = 3;
1337 else if (linktest == RL_CSCFG_ROW2)
1338 sc->rl_twist_row = 2;
1339 else if (linktest == RL_CSCFG_ROW1)
1340 sc->rl_twist_row = 1;
1341 else
1342 sc->rl_twist_row = 0;
1343 sc->rl_twist_col = 0;
1344 sc->rl_twister = SET_PARAM;
1345 break;
1346 case SET_PARAM:
1347 if (sc->rl_twist_col == 0)
1348 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET);
1349 CSR_WRITE_4(sc, RL_PARA7C,
1350 param[sc->rl_twist_row][sc->rl_twist_col]);
1351 if (++sc->rl_twist_col == 4) {
1352 if (sc->rl_twist_row == 3)
1353 sc->rl_twister = RECHK_LONG;
1354 else
1355 sc->rl_twister = DONE;
1356 }
1357 break;
1358 case RECHK_LONG:
1359 /*
1360 * For long cables, we have to double check to make sure we
1361 * don't mistune.
1362 */
1363 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
1364 if (linktest == RL_CSCFG_ROW3)
1365 sc->rl_twister = DONE;
1366 else {
1367 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_RETUNE);
1368 sc->rl_twister = RETUNE;
1369 }
1370 break;
1371 case RETUNE:
1372 /* Retune for a shorter cable (try column 2) */
1373 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST);
1374 CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF);
1375 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF);
1376 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET);
1377 sc->rl_twist_row--;
1378 sc->rl_twist_col = 0;
1379 sc->rl_twister = SET_PARAM;
1380 break;
1381
1382 case DONE:
1383 break;
1384 }
1385
1386 }
1387
1388 static void
rl_tick(void * xsc)1389 rl_tick(void *xsc)
1390 {
1391 struct rl_softc *sc = xsc;
1392 struct mii_data *mii;
1393 int ticks;
1394
1395 RL_LOCK_ASSERT(sc);
1396 /*
1397 * If we're doing the twister cable calibration, then we need to defer
1398 * watchdog timeouts. This is a no-op in normal operations, but
1399 * can falsely trigger when the cable calibration takes a while and
1400 * there was traffic ready to go when rl was started.
1401 *
1402 * We don't defer mii_tick since that updates the mii status, which
1403 * helps the twister process, at least according to similar patches
1404 * for the Linux driver I found online while doing the fixes. Worst
1405 * case is a few extra mii reads during calibration.
1406 */
1407 mii = device_get_softc(sc->rl_miibus);
1408 mii_tick(mii);
1409 if ((sc->rl_flags & RL_FLAG_LINK) == 0)
1410 rl_miibus_statchg(sc->rl_dev);
1411 if (sc->rl_twister_enable) {
1412 if (sc->rl_twister == DONE)
1413 rl_watchdog(sc);
1414 else
1415 rl_twister_update(sc);
1416 if (sc->rl_twister == DONE)
1417 ticks = hz;
1418 else
1419 ticks = hz / 10;
1420 } else {
1421 rl_watchdog(sc);
1422 ticks = hz;
1423 }
1424
1425 callout_reset(&sc->rl_stat_callout, ticks, rl_tick, sc);
1426 }
1427
1428 #ifdef DEVICE_POLLING
1429 static int
rl_poll(if_t ifp,enum poll_cmd cmd,int count)1430 rl_poll(if_t ifp, enum poll_cmd cmd, int count)
1431 {
1432 struct rl_softc *sc = if_getsoftc(ifp);
1433 int rx_npkts = 0;
1434
1435 RL_LOCK(sc);
1436 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1437 rx_npkts = rl_poll_locked(ifp, cmd, count);
1438 RL_UNLOCK(sc);
1439 return (rx_npkts);
1440 }
1441
1442 static int
rl_poll_locked(if_t ifp,enum poll_cmd cmd,int count)1443 rl_poll_locked(if_t ifp, enum poll_cmd cmd, int count)
1444 {
1445 struct rl_softc *sc = if_getsoftc(ifp);
1446 int rx_npkts;
1447
1448 RL_LOCK_ASSERT(sc);
1449
1450 sc->rxcycles = count;
1451 rx_npkts = rl_rxeof(sc);
1452 rl_txeof(sc);
1453
1454 if (!if_sendq_empty(ifp))
1455 rl_start_locked(ifp);
1456
1457 if (cmd == POLL_AND_CHECK_STATUS) {
1458 uint16_t status;
1459
1460 /* We should also check the status register. */
1461 status = CSR_READ_2(sc, RL_ISR);
1462 if (status == 0xffff)
1463 return (rx_npkts);
1464 if (status != 0)
1465 CSR_WRITE_2(sc, RL_ISR, status);
1466
1467 /* XXX We should check behaviour on receiver stalls. */
1468
1469 if (status & RL_ISR_SYSTEM_ERR) {
1470 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1471 rl_init_locked(sc);
1472 }
1473 }
1474 return (rx_npkts);
1475 }
1476 #endif /* DEVICE_POLLING */
1477
1478 static void
rl_intr(void * arg)1479 rl_intr(void *arg)
1480 {
1481 struct rl_softc *sc = arg;
1482 if_t ifp = sc->rl_ifp;
1483 uint16_t status;
1484 int count;
1485
1486 RL_LOCK(sc);
1487
1488 if (sc->suspended)
1489 goto done_locked;
1490
1491 #ifdef DEVICE_POLLING
1492 if (if_getcapenable(ifp) & IFCAP_POLLING)
1493 goto done_locked;
1494 #endif
1495
1496 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
1497 goto done_locked2;
1498 status = CSR_READ_2(sc, RL_ISR);
1499 if (status == 0xffff || (status & RL_INTRS) == 0)
1500 goto done_locked;
1501 /*
1502 * Ours, disable further interrupts.
1503 */
1504 CSR_WRITE_2(sc, RL_IMR, 0);
1505 for (count = 16; count > 0; count--) {
1506 CSR_WRITE_2(sc, RL_ISR, status);
1507 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
1508 if (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR))
1509 rl_rxeof(sc);
1510 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR))
1511 rl_txeof(sc);
1512 if (status & RL_ISR_SYSTEM_ERR) {
1513 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1514 rl_init_locked(sc);
1515 RL_UNLOCK(sc);
1516 return;
1517 }
1518 }
1519 status = CSR_READ_2(sc, RL_ISR);
1520 /* If the card has gone away, the read returns 0xffff. */
1521 if (status == 0xffff || (status & RL_INTRS) == 0)
1522 break;
1523 }
1524
1525 if (!if_sendq_empty(ifp))
1526 rl_start_locked(ifp);
1527
1528 done_locked2:
1529 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1530 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1531 done_locked:
1532 RL_UNLOCK(sc);
1533 }
1534
1535 /*
1536 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1537 * pointers to the fragment pointers.
1538 */
1539 static int
rl_encap(struct rl_softc * sc,struct mbuf ** m_head)1540 rl_encap(struct rl_softc *sc, struct mbuf **m_head)
1541 {
1542 struct mbuf *m;
1543 bus_dma_segment_t txsegs[1];
1544 int error, nsegs, padlen;
1545
1546 RL_LOCK_ASSERT(sc);
1547
1548 m = *m_head;
1549 padlen = 0;
1550 /*
1551 * Hardware doesn't auto-pad, so we have to make sure
1552 * pad short frames out to the minimum frame length.
1553 */
1554 if (m->m_pkthdr.len < RL_MIN_FRAMELEN)
1555 padlen = RL_MIN_FRAMELEN - m->m_pkthdr.len;
1556 /*
1557 * The RealTek is brain damaged and wants longword-aligned
1558 * TX buffers, plus we can only have one fragment buffer
1559 * per packet. We have to copy pretty much all the time.
1560 */
1561 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0 ||
1562 (padlen > 0 && M_TRAILINGSPACE(m) < padlen)) {
1563 m = m_defrag(*m_head, M_NOWAIT);
1564 if (m == NULL) {
1565 m_freem(*m_head);
1566 *m_head = NULL;
1567 return (ENOMEM);
1568 }
1569 }
1570 *m_head = m;
1571
1572 if (padlen > 0) {
1573 /*
1574 * Make security-conscious people happy: zero out the
1575 * bytes in the pad area, since we don't know what
1576 * this mbuf cluster buffer's previous user might
1577 * have left in it.
1578 */
1579 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1580 m->m_pkthdr.len += padlen;
1581 m->m_len = m->m_pkthdr.len;
1582 }
1583
1584 error = bus_dmamap_load_mbuf_sg(sc->rl_cdata.rl_tx_tag,
1585 RL_CUR_DMAMAP(sc), m, txsegs, &nsegs, 0);
1586 if (error != 0)
1587 return (error);
1588 if (nsegs == 0) {
1589 m_freem(*m_head);
1590 *m_head = NULL;
1591 return (EIO);
1592 }
1593
1594 RL_CUR_TXMBUF(sc) = m;
1595 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc),
1596 BUS_DMASYNC_PREWRITE);
1597 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), RL_ADDR_LO(txsegs[0].ds_addr));
1598
1599 return (0);
1600 }
1601
1602 /*
1603 * Main transmit routine.
1604 */
1605 static void
rl_start(if_t ifp)1606 rl_start(if_t ifp)
1607 {
1608 struct rl_softc *sc = if_getsoftc(ifp);
1609
1610 RL_LOCK(sc);
1611 rl_start_locked(ifp);
1612 RL_UNLOCK(sc);
1613 }
1614
1615 static void
rl_start_locked(if_t ifp)1616 rl_start_locked(if_t ifp)
1617 {
1618 struct rl_softc *sc = if_getsoftc(ifp);
1619 struct mbuf *m_head = NULL;
1620
1621 RL_LOCK_ASSERT(sc);
1622
1623 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1624 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
1625 return;
1626
1627 while (RL_CUR_TXMBUF(sc) == NULL) {
1628 m_head = if_dequeue(ifp);
1629
1630 if (m_head == NULL)
1631 break;
1632
1633 if (rl_encap(sc, &m_head)) {
1634 if (m_head == NULL)
1635 break;
1636 if_sendq_prepend(ifp, m_head);
1637 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1638 break;
1639 }
1640
1641 /* Pass a copy of this mbuf chain to the bpf subsystem. */
1642 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1643
1644 /* Transmit the frame. */
1645 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1646 RL_TXTHRESH(sc->rl_txthresh) |
1647 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1648
1649 RL_INC(sc->rl_cdata.cur_tx);
1650
1651 /* Set a timeout in case the chip goes out to lunch. */
1652 sc->rl_watchdog_timer = 5;
1653 }
1654
1655 /*
1656 * We broke out of the loop because all our TX slots are
1657 * full. Mark the NIC as busy until it drains some of the
1658 * packets from the queue.
1659 */
1660 if (RL_CUR_TXMBUF(sc) != NULL)
1661 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1662 }
1663
1664 static void
rl_init(void * xsc)1665 rl_init(void *xsc)
1666 {
1667 struct rl_softc *sc = xsc;
1668
1669 RL_LOCK(sc);
1670 rl_init_locked(sc);
1671 RL_UNLOCK(sc);
1672 }
1673
1674 static void
rl_init_locked(struct rl_softc * sc)1675 rl_init_locked(struct rl_softc *sc)
1676 {
1677 if_t ifp = sc->rl_ifp;
1678 struct mii_data *mii;
1679 uint32_t eaddr[2];
1680
1681 RL_LOCK_ASSERT(sc);
1682
1683 mii = device_get_softc(sc->rl_miibus);
1684
1685 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1686 return;
1687
1688 /*
1689 * Cancel pending I/O and free all RX/TX buffers.
1690 */
1691 rl_stop(sc);
1692
1693 rl_reset(sc);
1694 if (sc->rl_twister_enable) {
1695 /*
1696 * Reset twister register tuning state. The twister
1697 * registers and their tuning are undocumented, but
1698 * are necessary to cope with bad links. rl_twister =
1699 * DONE here will disable this entirely.
1700 */
1701 sc->rl_twister = CHK_LINK;
1702 }
1703
1704 /*
1705 * Init our MAC address. Even though the chipset
1706 * documentation doesn't mention it, we need to enter "Config
1707 * register write enable" mode to modify the ID registers.
1708 */
1709 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1710 bzero(eaddr, sizeof(eaddr));
1711 bcopy(if_getlladdr(sc->rl_ifp), eaddr, ETHER_ADDR_LEN);
1712 CSR_WRITE_STREAM_4(sc, RL_IDR0, eaddr[0]);
1713 CSR_WRITE_STREAM_4(sc, RL_IDR4, eaddr[1]);
1714 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1715
1716 /* Init the RX memory block pointer register. */
1717 CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr +
1718 RL_RX_8139_BUF_RESERVE);
1719 /* Init TX descriptors. */
1720 rl_list_tx_init(sc);
1721 /* Init Rx memory block. */
1722 rl_list_rx_init(sc);
1723
1724 /*
1725 * Enable transmit and receive.
1726 */
1727 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1728
1729 /*
1730 * Set the initial TX and RX configuration.
1731 */
1732 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1733 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1734
1735 /* Set RX filter. */
1736 rl_rxfilter(sc);
1737
1738 #ifdef DEVICE_POLLING
1739 /* Disable interrupts if we are polling. */
1740 if (if_getcapenable(ifp) & IFCAP_POLLING)
1741 CSR_WRITE_2(sc, RL_IMR, 0);
1742 else
1743 #endif
1744 /* Enable interrupts. */
1745 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1746
1747 /* Set initial TX threshold */
1748 sc->rl_txthresh = RL_TX_THRESH_INIT;
1749
1750 /* Start RX/TX process. */
1751 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1752
1753 /* Enable receiver and transmitter. */
1754 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1755
1756 sc->rl_flags &= ~RL_FLAG_LINK;
1757 mii_mediachg(mii);
1758
1759 CSR_WRITE_1(sc, sc->rl_cfg1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1760
1761 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
1762 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1763
1764 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1765 }
1766
1767 /*
1768 * Set media options.
1769 */
1770 static int
rl_ifmedia_upd(if_t ifp)1771 rl_ifmedia_upd(if_t ifp)
1772 {
1773 struct rl_softc *sc = if_getsoftc(ifp);
1774 struct mii_data *mii;
1775
1776 mii = device_get_softc(sc->rl_miibus);
1777
1778 RL_LOCK(sc);
1779 mii_mediachg(mii);
1780 RL_UNLOCK(sc);
1781
1782 return (0);
1783 }
1784
1785 /*
1786 * Report current media status.
1787 */
1788 static void
rl_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)1789 rl_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
1790 {
1791 struct rl_softc *sc = if_getsoftc(ifp);
1792 struct mii_data *mii;
1793
1794 mii = device_get_softc(sc->rl_miibus);
1795
1796 RL_LOCK(sc);
1797 mii_pollstat(mii);
1798 ifmr->ifm_active = mii->mii_media_active;
1799 ifmr->ifm_status = mii->mii_media_status;
1800 RL_UNLOCK(sc);
1801 }
1802
1803 static int
rl_ioctl(if_t ifp,u_long command,caddr_t data)1804 rl_ioctl(if_t ifp, u_long command, caddr_t data)
1805 {
1806 struct ifreq *ifr = (struct ifreq *)data;
1807 struct mii_data *mii;
1808 struct rl_softc *sc = if_getsoftc(ifp);
1809 int error = 0, mask;
1810
1811 switch (command) {
1812 case SIOCSIFFLAGS:
1813 RL_LOCK(sc);
1814 if (if_getflags(ifp) & IFF_UP) {
1815 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
1816 ((if_getflags(ifp) ^ sc->rl_if_flags) &
1817 (IFF_PROMISC | IFF_ALLMULTI)))
1818 rl_rxfilter(sc);
1819 else
1820 rl_init_locked(sc);
1821 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1822 rl_stop(sc);
1823 sc->rl_if_flags = if_getflags(ifp);
1824 RL_UNLOCK(sc);
1825 break;
1826 case SIOCADDMULTI:
1827 case SIOCDELMULTI:
1828 RL_LOCK(sc);
1829 rl_rxfilter(sc);
1830 RL_UNLOCK(sc);
1831 break;
1832 case SIOCGIFMEDIA:
1833 case SIOCSIFMEDIA:
1834 mii = device_get_softc(sc->rl_miibus);
1835 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1836 break;
1837 case SIOCSIFCAP:
1838 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1839 #ifdef DEVICE_POLLING
1840 if (ifr->ifr_reqcap & IFCAP_POLLING &&
1841 !(if_getcapenable(ifp) & IFCAP_POLLING)) {
1842 error = ether_poll_register(rl_poll, ifp);
1843 if (error)
1844 return(error);
1845 RL_LOCK(sc);
1846 /* Disable interrupts */
1847 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1848 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
1849 RL_UNLOCK(sc);
1850 return (error);
1851
1852 }
1853 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
1854 if_getcapenable(ifp) & IFCAP_POLLING) {
1855 error = ether_poll_deregister(ifp);
1856 /* Enable interrupts. */
1857 RL_LOCK(sc);
1858 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1859 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
1860 RL_UNLOCK(sc);
1861 return (error);
1862 }
1863 #endif /* DEVICE_POLLING */
1864 if ((mask & IFCAP_WOL) != 0 &&
1865 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) {
1866 if ((mask & IFCAP_WOL_UCAST) != 0)
1867 if_togglecapenable(ifp, IFCAP_WOL_UCAST);
1868 if ((mask & IFCAP_WOL_MCAST) != 0)
1869 if_togglecapenable(ifp, IFCAP_WOL_MCAST);
1870 if ((mask & IFCAP_WOL_MAGIC) != 0)
1871 if_togglecapenable(ifp, IFCAP_WOL_MAGIC);
1872 }
1873 break;
1874 default:
1875 error = ether_ioctl(ifp, command, data);
1876 break;
1877 }
1878
1879 return (error);
1880 }
1881
1882 static void
rl_watchdog(struct rl_softc * sc)1883 rl_watchdog(struct rl_softc *sc)
1884 {
1885
1886 RL_LOCK_ASSERT(sc);
1887
1888 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer >0)
1889 return;
1890
1891 device_printf(sc->rl_dev, "watchdog timeout\n");
1892 if_inc_counter(sc->rl_ifp, IFCOUNTER_OERRORS, 1);
1893
1894 rl_txeof(sc);
1895 rl_rxeof(sc);
1896 if_setdrvflagbits(sc->rl_ifp, 0, IFF_DRV_RUNNING);
1897 rl_init_locked(sc);
1898 }
1899
1900 /*
1901 * Stop the adapter and free any mbufs allocated to the
1902 * RX and TX lists.
1903 */
1904 static void
rl_stop(struct rl_softc * sc)1905 rl_stop(struct rl_softc *sc)
1906 {
1907 int i;
1908 if_t ifp = sc->rl_ifp;
1909
1910 RL_LOCK_ASSERT(sc);
1911
1912 sc->rl_watchdog_timer = 0;
1913 callout_stop(&sc->rl_stat_callout);
1914 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
1915 sc->rl_flags &= ~RL_FLAG_LINK;
1916
1917 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1918 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1919 for (i = 0; i < RL_TIMEOUT; i++) {
1920 DELAY(10);
1921 if ((CSR_READ_1(sc, RL_COMMAND) &
1922 (RL_CMD_RX_ENB | RL_CMD_TX_ENB)) == 0)
1923 break;
1924 }
1925 if (i == RL_TIMEOUT)
1926 device_printf(sc->rl_dev, "Unable to stop Tx/Rx MAC\n");
1927
1928 /*
1929 * Free the TX list buffers.
1930 */
1931 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1932 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1933 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag,
1934 sc->rl_cdata.rl_tx_dmamap[i],
1935 BUS_DMASYNC_POSTWRITE);
1936 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag,
1937 sc->rl_cdata.rl_tx_dmamap[i]);
1938 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1939 sc->rl_cdata.rl_tx_chain[i] = NULL;
1940 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
1941 0x0000000);
1942 }
1943 }
1944 }
1945
1946 /*
1947 * Device suspend routine. Stop the interface and save some PCI
1948 * settings in case the BIOS doesn't restore them properly on
1949 * resume.
1950 */
1951 static int
rl_suspend(device_t dev)1952 rl_suspend(device_t dev)
1953 {
1954 struct rl_softc *sc;
1955
1956 sc = device_get_softc(dev);
1957
1958 RL_LOCK(sc);
1959 rl_stop(sc);
1960 rl_setwol(sc);
1961 sc->suspended = 1;
1962 RL_UNLOCK(sc);
1963
1964 return (0);
1965 }
1966
1967 /*
1968 * Device resume routine. Restore some PCI settings in case the BIOS
1969 * doesn't, re-enable busmastering, and restart the interface if
1970 * appropriate.
1971 */
1972 static int
rl_resume(device_t dev)1973 rl_resume(device_t dev)
1974 {
1975 struct rl_softc *sc;
1976 if_t ifp;
1977 int pmc;
1978 uint16_t pmstat;
1979
1980 sc = device_get_softc(dev);
1981 ifp = sc->rl_ifp;
1982
1983 RL_LOCK(sc);
1984
1985 if ((if_getcapabilities(ifp) & IFCAP_WOL) != 0 &&
1986 pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) {
1987 /* Disable PME and clear PME status. */
1988 pmstat = pci_read_config(sc->rl_dev,
1989 pmc + PCIR_POWER_STATUS, 2);
1990 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
1991 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1992 pci_write_config(sc->rl_dev,
1993 pmc + PCIR_POWER_STATUS, pmstat, 2);
1994 }
1995 /*
1996 * Clear WOL matching such that normal Rx filtering
1997 * wouldn't interfere with WOL patterns.
1998 */
1999 rl_clrwol(sc);
2000 }
2001
2002 /* reinitialize interface if necessary */
2003 if (if_getflags(ifp) & IFF_UP)
2004 rl_init_locked(sc);
2005
2006 sc->suspended = 0;
2007
2008 RL_UNLOCK(sc);
2009
2010 return (0);
2011 }
2012
2013 /*
2014 * Stop all chip I/O so that the kernel's probe routines don't
2015 * get confused by errant DMAs when rebooting.
2016 */
2017 static int
rl_shutdown(device_t dev)2018 rl_shutdown(device_t dev)
2019 {
2020 struct rl_softc *sc;
2021
2022 sc = device_get_softc(dev);
2023
2024 RL_LOCK(sc);
2025 rl_stop(sc);
2026 /*
2027 * Mark interface as down since otherwise we will panic if
2028 * interrupt comes in later on, which can happen in some
2029 * cases.
2030 */
2031 if_setflagbits(sc->rl_ifp, 0, IFF_UP);
2032 rl_setwol(sc);
2033 RL_UNLOCK(sc);
2034
2035 return (0);
2036 }
2037
2038 static void
rl_setwol(struct rl_softc * sc)2039 rl_setwol(struct rl_softc *sc)
2040 {
2041 if_t ifp;
2042 int pmc;
2043 uint16_t pmstat;
2044 uint8_t v;
2045
2046 RL_LOCK_ASSERT(sc);
2047
2048 ifp = sc->rl_ifp;
2049 if ((if_getcapabilities(ifp) & IFCAP_WOL) == 0)
2050 return;
2051 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
2052 return;
2053
2054 /* Enable config register write. */
2055 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
2056
2057 /* Enable PME. */
2058 v = CSR_READ_1(sc, sc->rl_cfg1);
2059 v &= ~RL_CFG1_PME;
2060 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
2061 v |= RL_CFG1_PME;
2062 CSR_WRITE_1(sc, sc->rl_cfg1, v);
2063
2064 v = CSR_READ_1(sc, sc->rl_cfg3);
2065 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
2066 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0)
2067 v |= RL_CFG3_WOL_MAGIC;
2068 CSR_WRITE_1(sc, sc->rl_cfg3, v);
2069
2070 v = CSR_READ_1(sc, sc->rl_cfg5);
2071 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
2072 v &= ~RL_CFG5_WOL_LANWAKE;
2073 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) != 0)
2074 v |= RL_CFG5_WOL_UCAST;
2075 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0)
2076 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST;
2077 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
2078 v |= RL_CFG5_WOL_LANWAKE;
2079 CSR_WRITE_1(sc, sc->rl_cfg5, v);
2080
2081 /* Config register write done. */
2082 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2083
2084 /* Request PME if WOL is requested. */
2085 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
2086 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2087 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
2088 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2089 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
2090 }
2091
2092 static void
rl_clrwol(struct rl_softc * sc)2093 rl_clrwol(struct rl_softc *sc)
2094 {
2095 if_t ifp;
2096 uint8_t v;
2097
2098 ifp = sc->rl_ifp;
2099 if ((if_getcapabilities(ifp) & IFCAP_WOL) == 0)
2100 return;
2101
2102 /* Enable config register write. */
2103 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
2104
2105 v = CSR_READ_1(sc, sc->rl_cfg3);
2106 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
2107 CSR_WRITE_1(sc, sc->rl_cfg3, v);
2108
2109 /* Config register write done. */
2110 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2111
2112 v = CSR_READ_1(sc, sc->rl_cfg5);
2113 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
2114 v &= ~RL_CFG5_WOL_LANWAKE;
2115 CSR_WRITE_1(sc, sc->rl_cfg5, v);
2116 }
2117